Merge tag 'ti-k3-dt-for-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/dt

+2

Documentation/devicetree/bindings/arm/ti/k3.yaml

··· 28 28 - description: K3 AM625 SoC 29 29 items: 30 30 - enum: 31 + - beagle,am625-beagleplay 31 32 - ti,am625-sk 33 + - ti,am62-lp-sk 32 34 - const: ti,am625 33 35 34 36 - description: K3 AM642 SoC

-1

Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml

··· 222 222 223 223 examples: 224 224 - | 225 - #include <dt-bindings/pinctrl/k3.h> 226 225 #include <dt-bindings/soc/ti,sci_pm_domain.h> 227 226 #include <dt-bindings/net/ti-dp83867.h> 228 227 #include <dt-bindings/interrupt-controller/irq.h>

+6 -2

arch/arm64/boot/dts/ti/Makefile

··· 9 9 # alphabetically. 10 10 11 11 # Boards with AM62x SoC 12 + dtb-$(CONFIG_ARCH_K3) += k3-am625-beagleplay.dtb 12 13 dtb-$(CONFIG_ARCH_K3) += k3-am625-sk.dtb 14 + dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk.dtb 13 15 14 16 # Boards with AM62Ax SoC 15 17 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb ··· 30 28 dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb 31 29 32 30 # Boards with J7200 SoC 33 - dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb 31 + k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo 32 + dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb 34 33 35 34 # Boards with J721e SoC 35 + k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo 36 36 dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb 37 - dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb 37 + dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb 38 38 dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb 39 39 40 40 # Boards with J721s2 SoC

+231

arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * AM62x LP SK: https://www.ti.com/tool/SK-AM62-LP 4 + * 5 + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + */ 7 + 8 + /dts-v1/; 9 + 10 + #include "k3-am62x-sk-common.dtsi" 11 + 12 + / { 13 + compatible = "ti,am62-lp-sk", "ti,am625"; 14 + model = "Texas Instruments AM62x LP SK"; 15 + 16 + vmain_pd: regulator-0 { 17 + /* TPS65988 PD CONTROLLER OUTPUT */ 18 + compatible = "regulator-fixed"; 19 + regulator-name = "vmain_pd"; 20 + regulator-min-microvolt = <5000000>; 21 + regulator-max-microvolt = <5000000>; 22 + regulator-always-on; 23 + regulator-boot-on; 24 + }; 25 + 26 + vcc_5v0: regulator-1 { 27 + /* Output of TPS630702RNMR */ 28 + compatible = "regulator-fixed"; 29 + regulator-name = "vcc_5v0"; 30 + regulator-min-microvolt = <5000000>; 31 + regulator-max-microvolt = <5000000>; 32 + vin-supply = <&vmain_pd>; 33 + regulator-always-on; 34 + regulator-boot-on; 35 + }; 36 + 37 + vcc_3v3_sys: regulator-2 { 38 + /* output of LM61460-Q1 */ 39 + compatible = "regulator-fixed"; 40 + regulator-name = "vcc_3v3_sys"; 41 + regulator-min-microvolt = <3300000>; 42 + regulator-max-microvolt = <3300000>; 43 + vin-supply = <&vmain_pd>; 44 + regulator-always-on; 45 + regulator-boot-on; 46 + }; 47 + 48 + vdd_mmc1: regulator-3 { 49 + /* TPS22918DBVR */ 50 + compatible = "regulator-fixed"; 51 + regulator-name = "vdd_mmc1"; 52 + regulator-min-microvolt = <3300000>; 53 + regulator-max-microvolt = <3300000>; 54 + regulator-boot-on; 55 + enable-active-high; 56 + vin-supply = <&vcc_3v3_sys>; 57 + gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 58 + }; 59 + 60 + vddshv_sdio: regulator-4 { 61 + compatible = "regulator-gpio"; 62 + regulator-name = "vddshv_sdio"; 63 + pinctrl-names = "default"; 64 + pinctrl-0 = <&vddshv_sdio_pins_default>; 65 + regulator-min-microvolt = <1800000>; 66 + regulator-max-microvolt = <3300000>; 67 + regulator-boot-on; 68 + vin-supply = <&ldo1_reg>; 69 + gpios = <&main_gpio0 31 GPIO_ACTIVE_HIGH>; 70 + states = <1800000 0x0>, 71 + <3300000 0x1>; 72 + }; 73 + }; 74 + 75 + &main_pmx0 { 76 + vddshv_sdio_pins_default: vddshv-sdio-pins-default { 77 + pinctrl-single,pins = < 78 + AM62X_IOPAD(0x07c, PIN_OUTPUT, 7) /* (M19) GPMC0_CLK.GPIO0_31 */ 79 + >; 80 + }; 81 + 82 + main_gpio1_ioexp_intr_pins_default: main-gpio1-ioexp-intr-pins-default { 83 + pinctrl-single,pins = < 84 + AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (C13) UART0_RTSn.GPIO1_23 */ 85 + >; 86 + }; 87 + 88 + pmic_irq_pins_default: pmic-irq-pins-default { 89 + pinctrl-single,pins = < 90 + AM62X_IOPAD(0x01f4, PIN_INPUT, 0) /* (B16) EXTINTn */ 91 + >; 92 + }; 93 + }; 94 + 95 + &main_i2c1 { 96 + exp1: gpio@22 { 97 + compatible = "ti,tca6424"; 98 + reg = <0x22>; 99 + gpio-controller; 100 + #gpio-cells = <2>; 101 + gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 102 + "PRU_DETECT", "MMC1_SD_EN", 103 + "VPP_LDO_EN", "EXP_PS_3V3_En", 104 + "EXP_PS_5V0_En", "EXP_HAT_DETECT", 105 + "GPIO_AUD_RSTn", "GPIO_eMMC_RSTn", 106 + "UART1_FET_BUF_EN", "BT_UART_WAKE_SOC", 107 + "GPIO_HDMI_RSTn", "CSI_GPIO0", 108 + "CSI_GPIO1", "GPIO_OLDI_INT", 109 + "HDMI_INTn", "TEST_GPIO2", 110 + "MCASP1_FET_EN", "MCASP1_BUF_BT_EN", 111 + "MCASP1_FET_SEL", "UART1_FET_SEL", 112 + "", "IO_EXP_TEST_LED"; 113 + 114 + interrupt-parent = <&main_gpio1>; 115 + interrupts = <23 IRQ_TYPE_EDGE_FALLING>; 116 + interrupt-controller; 117 + #interrupt-cells = <2>; 118 + 119 + pinctrl-names = "default"; 120 + pinctrl-0 = <&main_gpio1_ioexp_intr_pins_default>; 121 + }; 122 + 123 + exp2: gpio@23 { 124 + compatible = "ti,tca6424"; 125 + reg = <0x23>; 126 + gpio-controller; 127 + #gpio-cells = <2>; 128 + gpio-line-names = "", "", 129 + "", "", 130 + "", "", 131 + "", "", 132 + "WL_LT_EN", "CSI_RSTz", 133 + "", "", 134 + "", "", 135 + "", "", 136 + "SPI0_FET_SEL", "SPI0_FET_OE", 137 + "GPIO_OLDI_RSTn", "PRU_3V3_EN", 138 + "", "", 139 + "CSI_VLDO_SEL", "SOC_WLAN_SDIO_RST"; 140 + }; 141 + }; 142 + 143 + &sdhci1 { 144 + vmmc-supply = <&vdd_mmc1>; 145 + vqmmc-supply = <&vddshv_sdio>; 146 + }; 147 + 148 + &cpsw_port2 { 149 + status = "disabled"; 150 + }; 151 + 152 + &main_i2c0 { 153 + tps65219: pmic@30 { 154 + compatible = "ti,tps65219"; 155 + reg = <0x30>; 156 + buck1-supply = <&vcc_3v3_sys>; 157 + buck2-supply = <&vcc_3v3_sys>; 158 + buck3-supply = <&vcc_3v3_sys>; 159 + ldo1-supply = <&vcc_3v3_sys>; 160 + ldo2-supply = <&buck2_reg>; 161 + ldo3-supply = <&vcc_3v3_sys>; 162 + ldo4-supply = <&vcc_3v3_sys>; 163 + 164 + pinctrl-names = "default"; 165 + pinctrl-0 = <&pmic_irq_pins_default>; 166 + 167 + interrupt-parent = <&gic500>; 168 + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 169 + ti,power-button; 170 + 171 + regulators { 172 + buck1_reg: buck1 { 173 + regulator-name = "VDD_CORE"; 174 + regulator-min-microvolt = <750000>; 175 + regulator-max-microvolt = <750000>; 176 + regulator-boot-on; 177 + regulator-always-on; 178 + }; 179 + 180 + buck2_reg: buck2 { 181 + regulator-name = "VCC1V8_SYS"; 182 + regulator-min-microvolt = <1800000>; 183 + regulator-max-microvolt = <1800000>; 184 + regulator-boot-on; 185 + regulator-always-on; 186 + }; 187 + 188 + buck3_reg: buck3 { 189 + regulator-name = "VDD_LPDDR4"; 190 + regulator-min-microvolt = <1100000>; 191 + regulator-max-microvolt = <1100000>; 192 + regulator-boot-on; 193 + regulator-always-on; 194 + }; 195 + 196 + ldo1_reg: ldo1 { 197 + regulator-name = "VDDSHV_SDIO"; 198 + regulator-min-microvolt = <3300000>; 199 + regulator-max-microvolt = <3300000>; 200 + }; 201 + 202 + ldo2_reg: ldo2 { 203 + regulator-name = "VDDAR_CORE"; 204 + regulator-min-microvolt = <850000>; 205 + regulator-max-microvolt = <850000>; 206 + regulator-boot-on; 207 + regulator-always-on; 208 + }; 209 + 210 + ldo3_reg: ldo3 { 211 + regulator-name = "VDDA_1V8"; 212 + regulator-min-microvolt = <1800000>; 213 + regulator-max-microvolt = <1800000>; 214 + regulator-boot-on; 215 + regulator-always-on; 216 + }; 217 + 218 + ldo4_reg: ldo4 { 219 + regulator-name = "VDD_1V2"; 220 + regulator-min-microvolt = <1200000>; 221 + regulator-max-microvolt = <1200000>; 222 + regulator-boot-on; 223 + regulator-always-on; 224 + }; 225 + }; 226 + }; 227 + }; 228 + 229 + &tlv320aic3106 { 230 + DVDD-supply = <&buck2_reg>; 231 + };

+107 -2

arch/arm64/boot/dts/ti/k3-am62-main.dtsi

··· 461 461 <193>, <194>, <195>; 462 462 interrupt-controller; 463 463 #interrupt-cells = <2>; 464 - ti,ngpio = <87>; 464 + ti,ngpio = <92>; 465 465 ti,davinci-gpio-unbanked = <0>; 466 466 power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>; 467 467 clocks = <&k3_clks 77 0>; ··· 478 478 <183>, <184>, <185>; 479 479 interrupt-controller; 480 480 #interrupt-cells = <2>; 481 - ti,ngpio = <88>; 481 + ti,ngpio = <52>; 482 482 ti,davinci-gpio-unbanked = <0>; 483 483 power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>; 484 484 clocks = <&k3_clks 78 0>; ··· 758 758 status = "disabled"; 759 759 }; 760 760 761 + main_rti0: watchdog@e000000 { 762 + compatible = "ti,j7-rti-wdt"; 763 + reg = <0x00 0x0e000000 0x00 0x100>; 764 + clocks = <&k3_clks 125 0>; 765 + power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 766 + assigned-clocks = <&k3_clks 125 0>; 767 + assigned-clock-parents = <&k3_clks 125 2>; 768 + }; 769 + 770 + main_rti1: watchdog@e010000 { 771 + compatible = "ti,j7-rti-wdt"; 772 + reg = <0x00 0x0e010000 0x00 0x100>; 773 + clocks = <&k3_clks 126 0>; 774 + power-domains = <&k3_pds 126 TI_SCI_PD_EXCLUSIVE>; 775 + assigned-clocks = <&k3_clks 126 0>; 776 + assigned-clock-parents = <&k3_clks 126 2>; 777 + }; 778 + 779 + main_rti2: watchdog@e020000 { 780 + compatible = "ti,j7-rti-wdt"; 781 + reg = <0x00 0x0e020000 0x00 0x100>; 782 + clocks = <&k3_clks 127 0>; 783 + power-domains = <&k3_pds 127 TI_SCI_PD_EXCLUSIVE>; 784 + assigned-clocks = <&k3_clks 127 0>; 785 + assigned-clock-parents = <&k3_clks 127 2>; 786 + }; 787 + 788 + main_rti3: watchdog@e030000 { 789 + compatible = "ti,j7-rti-wdt"; 790 + reg = <0x00 0x0e030000 0x00 0x100>; 791 + clocks = <&k3_clks 128 0>; 792 + power-domains = <&k3_pds 128 TI_SCI_PD_EXCLUSIVE>; 793 + assigned-clocks = <&k3_clks 128 0>; 794 + assigned-clock-parents = <&k3_clks 128 2>; 795 + }; 796 + 797 + main_rti15: watchdog@e0f0000 { 798 + compatible = "ti,j7-rti-wdt"; 799 + reg = <0x00 0x0e0f0000 0x00 0x100>; 800 + clocks = <&k3_clks 130 0>; 801 + power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>; 802 + assigned-clocks = <&k3_clks 130 0>; 803 + assigned-clock-parents = <&k3_clks 130 2>; 804 + }; 805 + 761 806 epwm0: pwm@23000000 { 762 807 compatible = "ti,am64-epwm", "ti,am3352-ehrpwm"; 763 808 #pwm-cells = <3>; ··· 830 785 power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; 831 786 clocks = <&epwm_tbclk 2>, <&k3_clks 88 0>; 832 787 clock-names = "tbclk", "fck"; 788 + status = "disabled"; 789 + }; 790 + 791 + mcasp0: audio-controller@2b00000 { 792 + compatible = "ti,am33xx-mcasp-audio"; 793 + reg = <0x00 0x02b00000 0x00 0x2000>, 794 + <0x00 0x02b08000 0x00 0x400>; 795 + reg-names = "mpu", "dat"; 796 + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 797 + <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 798 + interrupt-names = "tx", "rx"; 799 + 800 + dmas = <&main_bcdma 0 0xc500 0>, <&main_bcdma 0 0x4500 0>; 801 + dma-names = "tx", "rx"; 802 + 803 + clocks = <&k3_clks 190 0>; 804 + clock-names = "fck"; 805 + assigned-clocks = <&k3_clks 190 0>; 806 + assigned-clock-parents = <&k3_clks 190 2>; 807 + power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>; 808 + status = "disabled"; 809 + }; 810 + 811 + mcasp1: audio-controller@2b10000 { 812 + compatible = "ti,am33xx-mcasp-audio"; 813 + reg = <0x00 0x02b10000 0x00 0x2000>, 814 + <0x00 0x02b18000 0x00 0x400>; 815 + reg-names = "mpu", "dat"; 816 + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 817 + <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; 818 + interrupt-names = "tx", "rx"; 819 + 820 + dmas = <&main_bcdma 0 0xc501 0>, <&main_bcdma 0 0x4501 0>; 821 + dma-names = "tx", "rx"; 822 + 823 + clocks = <&k3_clks 191 0>; 824 + clock-names = "fck"; 825 + assigned-clocks = <&k3_clks 191 0>; 826 + assigned-clock-parents = <&k3_clks 191 2>; 827 + power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>; 828 + status = "disabled"; 829 + }; 830 + 831 + mcasp2: audio-controller@2b20000 { 832 + compatible = "ti,am33xx-mcasp-audio"; 833 + reg = <0x00 0x02b20000 0x00 0x2000>, 834 + <0x00 0x02b28000 0x00 0x400>; 835 + reg-names = "mpu", "dat"; 836 + interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 837 + <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 838 + interrupt-names = "tx", "rx"; 839 + 840 + dmas = <&main_bcdma 0 0xc502 0>, <&main_bcdma 0 0x4502 0>; 841 + dma-names = "tx", "rx"; 842 + 843 + clocks = <&k3_clks 192 0>; 844 + clock-names = "fck"; 845 + assigned-clocks = <&k3_clks 192 0>; 846 + assigned-clock-parents = <&k3_clks 192 2>; 847 + power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>; 833 848 status = "disabled"; 834 849 }; 835 850 };

+11

arch/arm64/boot/dts/ti/k3-am62-mcu.dtsi

··· 130 130 clocks = <&k3_clks 79 0>; 131 131 clock-names = "gpio"; 132 132 }; 133 + 134 + mcu_rti0: watchdog@4880000 { 135 + compatible = "ti,j7-rti-wdt"; 136 + reg = <0x00 0x04880000 0x00 0x100>; 137 + clocks = <&k3_clks 131 0>; 138 + power-domains = <&k3_pds 131 TI_SCI_PD_EXCLUSIVE>; 139 + assigned-clocks = <&k3_clks 131 0>; 140 + assigned-clock-parents = <&k3_clks 131 2>; 141 + /* Tightly coupled to M4F */ 142 + status = "reserved"; 143 + }; 133 144 };

+21

arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi

··· 40 40 clock-names = "fck"; 41 41 status = "disabled"; 42 42 }; 43 + 44 + wkup_rtc0: rtc@2b1f0000 { 45 + compatible = "ti,am62-rtc"; 46 + reg = <0x00 0x2b1f0000 0x00 0x100>; 47 + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 48 + clocks = <&k3_clks 117 6> , <&k3_clks 117 0>; 49 + clock-names = "vbus", "osc32k"; 50 + power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; 51 + wakeup-source; 52 + }; 53 + 54 + wkup_rti0: watchdog@2b000000 { 55 + compatible = "ti,j7-rti-wdt"; 56 + reg = <0x00 0x2b000000 0x00 0x100>; 57 + clocks = <&k3_clks 132 0>; 58 + power-domains = <&k3_pds 132 TI_SCI_PD_EXCLUSIVE>; 59 + assigned-clocks = <&k3_clks 132 0>; 60 + assigned-clock-parents = <&k3_clks 132 2>; 61 + /* Used by DM firmware */ 62 + status = "reserved"; 63 + }; 43 64 };

+2 -1

arch/arm64/boot/dts/ti/k3-am62.dtsi

··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/interrupt-controller/irq.h> 10 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 - #include <dt-bindings/pinctrl/k3.h> 12 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 12 + 13 + #include "k3-pinctrl.h" 13 14 14 15 / { 15 16 model = "Texas Instruments K3 AM625 SoC";

+758

arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * https://beagleplay.org/ 4 + * 5 + * Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + * Copyright (C) 2022-2023 Robert Nelson, BeagleBoard.org Foundation 7 + */ 8 + 9 + /dts-v1/; 10 + 11 + #include <dt-bindings/leds/common.h> 12 + #include <dt-bindings/gpio/gpio.h> 13 + #include <dt-bindings/input/input.h> 14 + #include "k3-am625.dtsi" 15 + 16 + / { 17 + compatible = "beagle,am625-beagleplay", "ti,am625"; 18 + model = "BeagleBoard.org BeaglePlay"; 19 + 20 + aliases { 21 + ethernet0 = &cpsw_port1; 22 + ethernet1 = &cpsw_port2; 23 + gpio0 = &main_gpio0; 24 + gpio1 = &main_gpio1; 25 + gpio2 = &mcu_gpio0; 26 + i2c0 = &main_i2c0; 27 + i2c1 = &main_i2c1; 28 + i2c2 = &main_i2c2; 29 + i2c3 = &main_i2c3; 30 + i2c4 = &wkup_i2c0; 31 + i2c5 = &mcu_i2c0; 32 + mdio-gpio0 = &mdio0; 33 + mmc0 = &sdhci0; 34 + mmc1 = &sdhci1; 35 + mmc2 = &sdhci2; 36 + rtc0 = &rtc; 37 + serial0 = &main_uart5; 38 + serial1 = &main_uart6; 39 + serial2 = &main_uart0; 40 + usb0 = &usb0; 41 + usb1 = &usb1; 42 + }; 43 + 44 + chosen { 45 + stdout-path = "serial2:115200n8"; 46 + }; 47 + 48 + memory@80000000 { 49 + device_type = "memory"; 50 + /* 2G RAM */ 51 + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 52 + }; 53 + 54 + reserved-memory { 55 + #address-cells = <2>; 56 + #size-cells = <2>; 57 + ranges; 58 + 59 + ramoops: ramoops@9ca00000 { 60 + compatible = "ramoops"; 61 + reg = <0x00 0x9c700000 0x00 0x00100000>; 62 + record-size = <0x8000>; 63 + console-size = <0x8000>; 64 + ftrace-size = <0x00>; 65 + pmsg-size = <0x8000>; 66 + }; 67 + 68 + secure_tfa_ddr: tfa@9e780000 { 69 + reg = <0x00 0x9e780000 0x00 0x80000>; 70 + no-map; 71 + }; 72 + 73 + secure_ddr: optee@9e800000 { 74 + reg = <0x00 0x9e800000 0x00 0x01800000>; 75 + no-map; 76 + }; 77 + 78 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { 79 + compatible = "shared-dma-pool"; 80 + reg = <0x00 0x9db00000 0x00 0xc00000>; 81 + no-map; 82 + }; 83 + }; 84 + 85 + vsys_5v0: regulator-1 { 86 + compatible = "regulator-fixed"; 87 + regulator-name = "vsys_5v0"; 88 + regulator-min-microvolt = <5000000>; 89 + regulator-max-microvolt = <5000000>; 90 + regulator-always-on; 91 + regulator-boot-on; 92 + }; 93 + 94 + vdd_3v3: regulator-2 { 95 + /* output of TLV62595DMQR-U12 */ 96 + compatible = "regulator-fixed"; 97 + regulator-name = "vdd_3v3"; 98 + regulator-min-microvolt = <3300000>; 99 + regulator-max-microvolt = <3300000>; 100 + vin-supply = <&vsys_5v0>; 101 + regulator-always-on; 102 + regulator-boot-on; 103 + }; 104 + 105 + wlan_en: regulator-3 { 106 + /* OUTPUT of SN74AVC2T244DQMR */ 107 + compatible = "regulator-fixed"; 108 + regulator-name = "wlan_en"; 109 + regulator-min-microvolt = <1800000>; 110 + regulator-max-microvolt = <1800000>; 111 + enable-active-high; 112 + regulator-always-on; 113 + vin-supply = <&vdd_3v3>; 114 + gpio = <&main_gpio0 38 GPIO_ACTIVE_HIGH>; 115 + pinctrl-names = "default"; 116 + pinctrl-0 = <&wifi_en_pins_default>; 117 + }; 118 + 119 + vdd_3v3_sd: regulator-4 { 120 + /* output of TPS22918DBVR-U21 */ 121 + pinctrl-names = "default"; 122 + pinctrl-0 = <&vdd_3v3_sd_pins_default>; 123 + 124 + compatible = "regulator-fixed"; 125 + regulator-name = "vdd_3v3_sd"; 126 + regulator-min-microvolt = <3300000>; 127 + regulator-max-microvolt = <3300000>; 128 + enable-active-high; 129 + regulator-always-on; 130 + vin-supply = <&vdd_3v3>; 131 + gpio = <&main_gpio1 19 GPIO_ACTIVE_HIGH>; 132 + }; 133 + 134 + vdd_sd_dv: regulator-5 { 135 + compatible = "regulator-gpio"; 136 + regulator-name = "sd_hs200_switch"; 137 + pinctrl-names = "default"; 138 + pinctrl-0 = <&vdd_sd_dv_pins_default>; 139 + regulator-min-microvolt = <1800000>; 140 + regulator-max-microvolt = <3300000>; 141 + regulator-boot-on; 142 + vin-supply = <&ldo1_reg>; 143 + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; 144 + states = <1800000 0x0>, 145 + <3300000 0x1>; 146 + }; 147 + 148 + leds { 149 + compatible = "gpio-leds"; 150 + 151 + led-0 { 152 + gpios = <&main_gpio0 3 GPIO_ACTIVE_HIGH>; 153 + linux,default-trigger = "heartbeat"; 154 + function = LED_FUNCTION_HEARTBEAT; 155 + default-state = "off"; 156 + }; 157 + 158 + led-1 { 159 + gpios = <&main_gpio0 4 GPIO_ACTIVE_HIGH>; 160 + linux,default-trigger = "disk-activity"; 161 + function = LED_FUNCTION_DISK_ACTIVITY; 162 + default-state = "keep"; 163 + }; 164 + 165 + led-2 { 166 + gpios = <&main_gpio0 5 GPIO_ACTIVE_HIGH>; 167 + function = LED_FUNCTION_CPU; 168 + }; 169 + 170 + led-3 { 171 + gpios = <&main_gpio0 6 GPIO_ACTIVE_HIGH>; 172 + function = LED_FUNCTION_LAN; 173 + }; 174 + 175 + led-4 { 176 + gpios = <&main_gpio0 9 GPIO_ACTIVE_HIGH>; 177 + function = LED_FUNCTION_WLAN; 178 + }; 179 + }; 180 + 181 + gpio_keys: gpio-keys { 182 + compatible = "gpio-keys"; 183 + autorepeat; 184 + pinctrl-names = "default"; 185 + pinctrl-0 = <&usr_button_pins_default>; 186 + 187 + usr: button-usr { 188 + label = "User Key"; 189 + linux,code = <BTN_0>; 190 + gpios = <&main_gpio0 18 GPIO_ACTIVE_LOW>; 191 + }; 192 + 193 + }; 194 + 195 + /* Workaround for errata i2329 - just use mdio bitbang */ 196 + mdio0: mdio { 197 + compatible = "virtual,mdio-gpio"; 198 + pinctrl-names = "default"; 199 + pinctrl-0 = <&mdio0_pins_default>; 200 + gpios = <&main_gpio0 86 GPIO_ACTIVE_HIGH>, /* MDC */ 201 + <&main_gpio0 85 GPIO_ACTIVE_HIGH>; /* MDIO */ 202 + #address-cells = <1>; 203 + #size-cells = <0>; 204 + 205 + cpsw3g_phy0: ethernet-phy@0 { 206 + reg = <0>; 207 + }; 208 + 209 + cpsw3g_phy1: ethernet-phy@1 { 210 + reg = <1>; 211 + reset-gpios = <&main_gpio1 5 GPIO_ACTIVE_LOW>; 212 + reset-assert-us = <25>; 213 + reset-deassert-us = <60000>; /* T2 */ 214 + }; 215 + }; 216 + }; 217 + 218 + &main_pmx0 { 219 + gpio0_pins_default: gpio0-pins-default { 220 + pinctrl-single,pins = < 221 + AM62X_IOPAD(0x0004, PIN_INPUT, 7) /* (G25) OSPI0_LBCLKO.GPIO0_1 */ 222 + AM62X_IOPAD(0x0008, PIN_INPUT, 7) /* (J24) OSPI0_DQS.GPIO0_2 */ 223 + AM62X_IOPAD(0x000c, PIN_INPUT, 7) /* (E25) OSPI0_D0.GPIO0_3 */ 224 + AM62X_IOPAD(0x0010, PIN_INPUT, 7) /* (G24) OSPI0_D1.GPIO0_4 */ 225 + AM62X_IOPAD(0x0014, PIN_INPUT, 7) /* (F25) OSPI0_D2.GPIO0_5 */ 226 + AM62X_IOPAD(0x0018, PIN_INPUT, 7) /* (F24) OSPI0_D3.GPIO0_6 */ 227 + AM62X_IOPAD(0x0024, PIN_INPUT, 7) /* (H25) OSPI0_D6.GPIO0_9 */ 228 + AM62X_IOPAD(0x0028, PIN_INPUT, 7) /* (J22) OSPI0_D7.GPIO0_10 */ 229 + AM62X_IOPAD(0x002c, PIN_INPUT, 7) /* (F23) OSPI0_CSn0.GPIO0_11 */ 230 + AM62X_IOPAD(0x0030, PIN_INPUT, 7) /* (G21) OSPI0_CSn1.GPIO0_12 */ 231 + AM62X_IOPAD(0x0034, PIN_INPUT, 7) /* (H21) OSPI0_CSn2.GPIO0_13 */ 232 + AM62X_IOPAD(0x0038, PIN_INPUT, 7) /* (E24) OSPI0_CSn3.GPIO0_14 */ 233 + AM62X_IOPAD(0x00a4, PIN_INPUT, 7) /* (M22) GPMC0_DIR.GPIO0_40 */ 234 + AM62X_IOPAD(0x00ac, PIN_INPUT, 7) /* (L21) GPMC0_CSn1.GPIO0_42 */ 235 + >; 236 + }; 237 + 238 + vdd_sd_dv_pins_default: vdd-sd-pins-default { 239 + pinctrl-single,pins = < 240 + AM62X_IOPAD(0x0244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ 241 + >; 242 + }; 243 + 244 + usr_button_pins_default: usr-button-pins-default { 245 + pinctrl-single,pins = < 246 + AM62X_IOPAD(0x0048, PIN_INPUT, 7) /* (N25) GPMC0_AD3.GPIO0_18 */ 247 + >; 248 + }; 249 + 250 + grove_pins_default: grove-pins-default { 251 + pinctrl-single,pins = < 252 + AM62X_IOPAD(0x01e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ 253 + AM62X_IOPAD(0x01ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ 254 + >; 255 + }; 256 + 257 + local_i2c_pins_default: local-i2c-pins-default { 258 + pinctrl-single,pins = < 259 + AM62X_IOPAD(0x01e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ 260 + AM62X_IOPAD(0x01e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ 261 + >; 262 + }; 263 + 264 + i2c2_1v8_pins_default: i2c2-pins-default { 265 + pinctrl-single,pins = < 266 + AM62X_IOPAD(0x00b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ 267 + AM62X_IOPAD(0x00b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ 268 + >; 269 + }; 270 + 271 + mdio0_pins_default: mdio0-pins-default { 272 + pinctrl-single,pins = < 273 + AM62X_IOPAD(0x0160, PIN_OUTPUT, 7) /* (AD24) MDIO0_MDC.GPIO0_86 */ 274 + AM62X_IOPAD(0x015c, PIN_INPUT, 7) /* (AB22) MDIO0_MDIO.GPIO0_85 */ 275 + >; 276 + }; 277 + 278 + rgmii1_pins_default: rgmii1-pins-default { 279 + pinctrl-single,pins = < 280 + AM62X_IOPAD(0x014c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ 281 + AM62X_IOPAD(0x0150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ 282 + AM62X_IOPAD(0x0154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ 283 + AM62X_IOPAD(0x0158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ 284 + AM62X_IOPAD(0x0148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ 285 + AM62X_IOPAD(0x0144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ 286 + AM62X_IOPAD(0x0134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ 287 + AM62X_IOPAD(0x0138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ 288 + AM62X_IOPAD(0x013c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ 289 + AM62X_IOPAD(0x0140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ 290 + AM62X_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ 291 + AM62X_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ 292 + >; 293 + }; 294 + 295 + emmc_pins_default: emmc-pins-default { 296 + pinctrl-single,pins = < 297 + AM62X_IOPAD(0x0220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ 298 + AM62X_IOPAD(0x0218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ 299 + AM62X_IOPAD(0x0214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ 300 + AM62X_IOPAD(0x0210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ 301 + AM62X_IOPAD(0x020c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ 302 + AM62X_IOPAD(0x0208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ 303 + AM62X_IOPAD(0x0204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ 304 + AM62X_IOPAD(0x0200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ 305 + AM62X_IOPAD(0x01fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ 306 + AM62X_IOPAD(0x01f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ 307 + >; 308 + }; 309 + 310 + vdd_3v3_sd_pins_default: vdd-3v3-sd-pins-default { 311 + pinctrl-single,pins = < 312 + AM62X_IOPAD(0x01c4, PIN_INPUT, 7) /* (B14) SPI0_D1_GPIO1_19 */ 313 + >; 314 + }; 315 + 316 + sd_pins_default: sd-pins-default { 317 + pinctrl-single,pins = < 318 + AM62X_IOPAD(0x023c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ 319 + AM62X_IOPAD(0x0234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ 320 + AM62X_IOPAD(0x0230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ 321 + AM62X_IOPAD(0x022c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ 322 + AM62X_IOPAD(0x0228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ 323 + AM62X_IOPAD(0x0224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ 324 + AM62X_IOPAD(0x0240, PIN_INPUT, 7) /* (D17) MMC1_SDCD.GPIO1_48 */ 325 + >; 326 + }; 327 + 328 + wifi_pins_default: wifi-pins-default { 329 + pinctrl-single,pins = < 330 + AM62X_IOPAD(0x0120, PIN_INPUT, 0) /* (C24) MMC2_CMD */ 331 + AM62X_IOPAD(0x0118, PIN_INPUT, 0) /* (D25) MMC2_CLK */ 332 + AM62X_IOPAD(0x0114, PIN_INPUT, 0) /* (B24) MMC2_DAT0 */ 333 + AM62X_IOPAD(0x0110, PIN_INPUT, 0) /* (C25) MMC2_DAT1 */ 334 + AM62X_IOPAD(0x010c, PIN_INPUT, 0) /* (E23) MMC2_DAT2 */ 335 + AM62X_IOPAD(0x0108, PIN_INPUT, 0) /* (D24) MMC2_DAT3 */ 336 + AM62X_IOPAD(0x0124, PIN_INPUT, 0) /* (A23) MMC2_SDCD */ 337 + AM62X_IOPAD(0x11c, PIN_INPUT, 0) /* (#N/A) MMC2_CLKB */ 338 + >; 339 + }; 340 + 341 + wifi_en_pins_default: wifi-en-pins-default { 342 + pinctrl-single,pins = < 343 + AM62X_IOPAD(0x009c, PIN_OUTPUT, 7) /* (V25) GPMC0_WAIT1.GPIO0_38 */ 344 + >; 345 + }; 346 + 347 + wifi_wlirq_pins_default: wifi-wlirq-pins-default { 348 + pinctrl-single,pins = < 349 + AM62X_IOPAD(0x00a8, PIN_INPUT, 7) /* (M21) GPMC0_CSn0.GPIO0_41 */ 350 + >; 351 + }; 352 + 353 + spe_pins_default: spe-pins-default { 354 + pinctrl-single,pins = < 355 + AM62X_IOPAD(0x0168, PIN_INPUT, 1) /* (AE21) RGMII2_TXC.RMII2_CRS_DV */ 356 + AM62X_IOPAD(0x0180, PIN_INPUT, 1) /* (AD23) RGMII2_RXC.RMII2_REF_CLK */ 357 + AM62X_IOPAD(0x0184, PIN_INPUT, 1) /* (AE23) RGMII2_RD0.RMII2_RXD0 */ 358 + AM62X_IOPAD(0x0188, PIN_INPUT, 1) /* (AB20) RGMII2_RD1.RMII2_RXD1 */ 359 + AM62X_IOPAD(0x017c, PIN_INPUT, 1) /* (AD22) RGMII2_RX_CTL.RMII2_RX_ER */ 360 + AM62X_IOPAD(0x016c, PIN_INPUT, 1) /* (Y18) RGMII2_TD0.RMII2_TXD0 */ 361 + AM62X_IOPAD(0x0170, PIN_INPUT, 1) /* (AA18) RGMII2_TD1.RMII2_TXD1 */ 362 + AM62X_IOPAD(0x0164, PIN_INPUT, 1) /* (AA19) RGMII2_TX_CTL.RMII2_TX_EN */ 363 + AM62X_IOPAD(0x018c, PIN_OUTPUT, 7) /* (AC21) RGMII2_RD2.GPIO1_5 */ 364 + AM62X_IOPAD(0x0190, PIN_INPUT, 7) /* (AE22) RGMII2_RD3.GPIO1_6 */ 365 + AM62X_IOPAD(0x01f0, PIN_OUTPUT, 5) /* (A18) EXT_REFCLK1.CLKOUT0 */ 366 + >; 367 + }; 368 + 369 + mikrobus_i2c_pins_default: mikrobus-i2c-pins-default { 370 + pinctrl-single,pins = < 371 + AM62X_IOPAD(0x01d0, PIN_INPUT_PULLUP, 2) /* (A15) UART0_CTSn.I2C3_SCL */ 372 + AM62X_IOPAD(0x01d4, PIN_INPUT_PULLUP, 2) /* (B15) UART0_RTSn.I2C3_SDA */ 373 + >; 374 + }; 375 + 376 + mikrobus_uart_pins_default: mikrobus-uart-pins-default { 377 + pinctrl-single,pins = < 378 + AM62X_IOPAD(0x01d8, PIN_INPUT, 1) /* (C15) MCAN0_TX.UART5_RXD */ 379 + AM62X_IOPAD(0x01dc, PIN_OUTPUT, 1) /* (E15) MCAN0_RX.UART5_TXD */ 380 + >; 381 + }; 382 + 383 + mikrobus_spi_pins_default: mikrobus-spi-pins-default { 384 + pinctrl-single,pins = < 385 + AM62X_IOPAD(0x01b0, PIN_INPUT, 1) /* (A20) MCASP0_ACLKR.SPI2_CLK */ 386 + AM62X_IOPAD(0x01ac, PIN_INPUT, 1) /* (E19) MCASP0_AFSR.SPI2_CS0 */ 387 + AM62X_IOPAD(0x0194, PIN_INPUT, 1) /* (B19) MCASP0_AXR3.SPI2_D0 */ 388 + AM62X_IOPAD(0x0198, PIN_INPUT, 1) /* (A19) MCASP0_AXR2.SPI2_D1 */ 389 + >; 390 + }; 391 + 392 + mikrobus_gpio_pins_default: mikrobus-gpio-pins-default { 393 + pinctrl-single,pins = < 394 + AM62X_IOPAD(0x019c, PIN_INPUT, 7) /* (B18) MCASP0_AXR1.GPIO1_9 */ 395 + AM62X_IOPAD(0x01a0, PIN_INPUT, 7) /* (E18) MCASP0_AXR0.GPIO1_10 */ 396 + AM62X_IOPAD(0x01a8, PIN_INPUT, 7) /* (D20) MCASP0_AFSX.GPIO1_12 */ 397 + >; 398 + }; 399 + 400 + console_pins_default: console-pins-default { 401 + pinctrl-single,pins = < 402 + AM62X_IOPAD(0x01c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ 403 + AM62X_IOPAD(0x01cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ 404 + >; 405 + }; 406 + 407 + wifi_debug_uart_pins_default: wifi-debug-uart-pins-default { 408 + pinctrl-single,pins = < 409 + AM62X_IOPAD(0x001c, PIN_INPUT, 3) /* (J23) OSPI0_D4.UART6_RXD */ 410 + AM62X_IOPAD(0x0020, PIN_OUTPUT, 3) /* (J25) OSPI0_D5.UART6_TXD */ 411 + >; 412 + }; 413 + 414 + usb1_pins_default: usb1-pins-default { 415 + pinctrl-single,pins = < 416 + AM62X_IOPAD(0x0258, PIN_INPUT, 0) /* (F18) USB1_DRVVBUS */ 417 + >; 418 + }; 419 + 420 + pmic_irq_pins_default: pmic-irq-pins-default { 421 + pinctrl-single,pins = < 422 + AM62X_IOPAD(0x01f4, PIN_INPUT_PULLUP, 0) /* (D16) EXTINTn */ 423 + >; 424 + }; 425 + }; 426 + 427 + &mcu_pmx0 { 428 + i2c_qwiic_pins_default: i2c-qwiic-pins-default { 429 + pinctrl-single,pins = < 430 + AM62X_MCU_IOPAD(0x0044, PIN_INPUT, 0) /* (A8) MCU_I2C0_SCL */ 431 + AM62X_MCU_IOPAD(0x0048, PIN_INPUT, 0) /* (D10) MCU_I2C0_SDA */ 432 + >; 433 + }; 434 + 435 + gbe_pmx_obsclk: gbe-pmx-clk-default { 436 + pinctrl-single,pins = < 437 + AM62X_MCU_IOPAD(0x0004, PIN_OUTPUT, 1) /* (B8) MCU_SPI0_CS1.MCU_OBSCLK0 */ 438 + >; 439 + }; 440 + 441 + i2c_csi_pins_default: i2c-csi-pins-default { 442 + pinctrl-single,pins = < 443 + AM62X_MCU_IOPAD(0x004c, PIN_INPUT_PULLUP, 0) /* (B9) WKUP_I2C0_SCL */ 444 + AM62X_MCU_IOPAD(0x0050, PIN_INPUT_PULLUP, 0) /* (A9) WKUP_I2C0_SDA */ 445 + >; 446 + }; 447 + 448 + wifi_32k_clk: mcu-clk-out-pins-default { 449 + pinctrl-single,pins = < 450 + AM62X_MCU_IOPAD(0x0084, PIN_OUTPUT, 0) /* (A12) WKUP_CLKOUT0 */ 451 + >; 452 + }; 453 + }; 454 + 455 + &a53_opp_table { 456 + /* Requires VDD_CORE to be at 0.85V */ 457 + opp-1400000000 { 458 + opp-hz = /bits/ 64 <1400000000>; 459 + opp-supported-hw = <0x01 0x0004>; 460 + }; 461 + }; 462 + 463 + &wkup_i2c0 { 464 + pinctrl-names = "default"; 465 + pinctrl-0 = <&i2c_csi_pins_default>; 466 + clock-frequency = <400000>; 467 + /* Enable with overlay for camera sensor */ 468 + }; 469 + 470 + &mcu_i2c0 { 471 + pinctrl-names = "default"; 472 + pinctrl-0 = <&i2c_qwiic_pins_default>; 473 + clock-frequency = <100000>; 474 + status = "okay"; 475 + }; 476 + 477 + &usbss0 { 478 + ti,vbus-divider; 479 + status = "okay"; 480 + }; 481 + 482 + &usb0 { 483 + dr_mode = "peripheral"; 484 + }; 485 + 486 + &usbss1 { 487 + ti,vbus-divider; 488 + status = "okay"; 489 + }; 490 + 491 + &usb1 { 492 + dr_mode = "host"; 493 + pinctrl-names = "default"; 494 + pinctrl-0 = <&usb1_pins_default>; 495 + }; 496 + 497 + &cpsw3g { 498 + pinctrl-names = "default"; 499 + pinctrl-0 = <&rgmii1_pins_default>, <&spe_pins_default>, 500 + <&gbe_pmx_obsclk>; 501 + assigned-clocks = <&k3_clks 157 70>, <&k3_clks 157 20>; 502 + assigned-clock-parents = <&k3_clks 157 72>, <&k3_clks 157 22>; 503 + }; 504 + 505 + &cpsw_port1 { 506 + phy-mode = "rgmii-rxid"; 507 + phy-handle = <&cpsw3g_phy0>; 508 + }; 509 + 510 + &cpsw_port2 { 511 + phy-mode = "rmii"; 512 + phy-handle = <&cpsw3g_phy1>; 513 + }; 514 + 515 + &cpsw3g_mdio { 516 + /* Workaround for errata i2329 - Use mdio bitbang */ 517 + status = "disabled"; 518 + }; 519 + 520 + &main_gpio0 { 521 + pinctrl-names = "default"; 522 + pinctrl-0 = <&gpio0_pins_default>; 523 + gpio-line-names = "BL_EN_3V3", "SPE_PO_EN", "RTC_INT", /* 0-2 */ 524 + "USR0", "USR1", "USR2", "USR3", "", "", "USR4", /* 3-9 */ 525 + "EEPROM_WP", /* 10 */ 526 + "CSI2_CAMERA_GPIO1", "CSI2_CAMERA_GPIO2", /* 11-12 */ 527 + "CC1352P7_BOOT", "CC1352P7_RSTN", "", "", "", /* 13-17 */ 528 + "USR_BUTTON", "", "", "", "", "", "", "", "", /* 18-26 */ 529 + "", "", "", "", "", "", "", "", "", "HDMI_INT", /* 27-36 */ 530 + "", "VDD_WLAN_EN", "", "", "WL_IRQ", "GBE_INTN",/* 37-42 */ 531 + "", "", "", "", "", "", "", "", "", "", "", "", /* 43-54 */ 532 + "", "", "", "", "", "", "", "", "", "", "", "", /* 55-66 */ 533 + "", "", "", "", "", "", "", "", "", "", "", "", /* 67-78 */ 534 + "", "", "", "", "", "", /* 79-84 */ 535 + "BITBANG_MDIO_DATA", "BITBANG_MDIO_CLK", /* 85-86 */ 536 + "", "", "", "", ""; /* 87-91 */ 537 + }; 538 + 539 + &main_gpio1 { 540 + pinctrl-names = "default"; 541 + pinctrl-0 = <&mikrobus_gpio_pins_default>; 542 + gpio-line-names = "", "", "", "", "", /* 0-4 */ 543 + "SPE_RSTN", "SPE_INTN", "MIKROBUS_GPIO1_7", /* 5-7 */ 544 + "MIKROBUS_GPIO1_8", "MIKROBUS_GPIO1_9", /* 8-9 */ 545 + "MIKROBUS_GPIO1_10", "MIKROBUS_GPIO1_11", /* 10-11 */ 546 + "MIKROBUS_GPIO1_12", "MIKROBUS_W1_GPIO0", /* 12-13 */ 547 + "MIKROBUS_GPIO1_14", /* 14 */ 548 + "", "", "", "", "VDD_3V3_SD", "", "", /* 15-21 */ 549 + "MIKROBUS_GPIO1_22", "MIKROBUS_GPIO1_23", /* 22-23 */ 550 + "MIKROBUS_GPIO1_24", "MIKROBUS_GPIO1_25", /* 24-25 */ 551 + "", "", "", "", "", "", "", "", "", "", "", "", /* 26-37 */ 552 + "", "", "", "", "", "", "", "", "", "", /* 38-47 */ 553 + "SD_CD", "SD_VOLT_SEL", "", ""; /* 48-51 */ 554 + }; 555 + 556 + &main_i2c0 { 557 + pinctrl-names = "default"; 558 + pinctrl-0 = <&local_i2c_pins_default>; 559 + clock-frequency = <400000>; 560 + status = "okay"; 561 + 562 + eeprom@50 { 563 + compatible = "atmel,24c32"; 564 + reg = <0x50>; 565 + }; 566 + 567 + rtc: rtc@68 { 568 + compatible = "ti,bq32000"; 569 + reg = <0x68>; 570 + interrupt-parent = <&main_gpio0>; 571 + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 572 + }; 573 + 574 + tps65219: pmic@30 { 575 + compatible = "ti,tps65219"; 576 + reg = <0x30>; 577 + buck1-supply = <&vsys_5v0>; 578 + buck2-supply = <&vsys_5v0>; 579 + buck3-supply = <&vsys_5v0>; 580 + ldo1-supply = <&vdd_3v3>; 581 + ldo2-supply = <&buck2_reg>; 582 + ldo3-supply = <&vdd_3v3>; 583 + ldo4-supply = <&vdd_3v3>; 584 + 585 + pinctrl-names = "default"; 586 + pinctrl-0 = <&pmic_irq_pins_default>; 587 + interrupt-parent = <&gic500>; 588 + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 589 + interrupt-controller; 590 + #interrupt-cells = <1>; 591 + 592 + system-power-controller; 593 + ti,power-button; 594 + 595 + regulators { 596 + buck1_reg: buck1 { 597 + regulator-name = "VDD_CORE"; 598 + regulator-min-microvolt = <850000>; 599 + regulator-max-microvolt = <850000>; 600 + regulator-boot-on; 601 + regulator-always-on; 602 + }; 603 + 604 + buck2_reg: buck2 { 605 + regulator-name = "VDD_1V8"; 606 + regulator-min-microvolt = <1800000>; 607 + regulator-max-microvolt = <1800000>; 608 + regulator-boot-on; 609 + regulator-always-on; 610 + }; 611 + 612 + buck3_reg: buck3 { 613 + regulator-name = "VDD_1V2"; 614 + regulator-min-microvolt = <1200000>; 615 + regulator-max-microvolt = <1200000>; 616 + regulator-boot-on; 617 + regulator-always-on; 618 + }; 619 + 620 + ldo1_reg: ldo1 { 621 + /* 622 + * Regulator is left as is unused, vdd_sd 623 + * is controlled via GPIO with bypass config 624 + * as per the NVM configuration 625 + */ 626 + regulator-name = "VDD_SD_3V3"; 627 + regulator-min-microvolt = <3300000>; 628 + regulator-max-microvolt = <3300000>; 629 + regulator-allow-bypass; 630 + regulator-boot-on; 631 + regulator-always-on; 632 + }; 633 + 634 + ldo2_reg: ldo2 { 635 + regulator-name = "VDDA_0V85"; 636 + regulator-min-microvolt = <850000>; 637 + regulator-max-microvolt = <850000>; 638 + regulator-boot-on; 639 + regulator-always-on; 640 + }; 641 + 642 + ldo3_reg: ldo3 { 643 + regulator-name = "VDDA_1V8"; 644 + regulator-min-microvolt = <1800000>; 645 + regulator-max-microvolt = <1800000>; 646 + regulator-boot-on; 647 + regulator-always-on; 648 + }; 649 + 650 + ldo4_reg: ldo4 { 651 + regulator-name = "VDD_2V5"; 652 + regulator-min-microvolt = <2500000>; 653 + regulator-max-microvolt = <2500000>; 654 + regulator-boot-on; 655 + regulator-always-on; 656 + }; 657 + }; 658 + }; 659 + }; 660 + 661 + &main_i2c1 { 662 + pinctrl-names = "default"; 663 + pinctrl-0 = <&grove_pins_default>; 664 + clock-frequency = <100000>; 665 + status = "okay"; 666 + }; 667 + 668 + &main_i2c2 { 669 + pinctrl-names = "default"; 670 + pinctrl-0 = <&i2c2_1v8_pins_default>; 671 + clock-frequency = <100000>; 672 + status = "okay"; 673 + }; 674 + 675 + &main_i2c3 { 676 + pinctrl-names = "default"; 677 + pinctrl-0 = <&mikrobus_i2c_pins_default>; 678 + clock-frequency = <400000>; 679 + status = "okay"; 680 + }; 681 + 682 + &main_spi2 { 683 + pinctrl-names = "default"; 684 + pinctrl-0 = <&mikrobus_spi_pins_default>; 685 + status = "okay"; 686 + }; 687 + 688 + &sdhci0 { 689 + pinctrl-names = "default"; 690 + pinctrl-0 = <&emmc_pins_default>; 691 + ti,driver-strength-ohm = <50>; 692 + disable-wp; 693 + status = "okay"; 694 + }; 695 + 696 + &sdhci1 { 697 + /* SD/MMC */ 698 + pinctrl-names = "default"; 699 + pinctrl-0 = <&sd_pins_default>; 700 + 701 + vmmc-supply = <&vdd_3v3_sd>; 702 + vqmmc-supply = <&vdd_sd_dv>; 703 + ti,driver-strength-ohm = <50>; 704 + disable-wp; 705 + cd-gpios = <&main_gpio1 48 GPIO_ACTIVE_LOW>; 706 + cd-debounce-delay-ms = <100>; 707 + ti,fails-without-test-cd; 708 + status = "okay"; 709 + }; 710 + 711 + &sdhci2 { 712 + vmmc-supply = <&wlan_en>; 713 + pinctrl-names = "default"; 714 + pinctrl-0 = <&wifi_pins_default>, <&wifi_32k_clk>; 715 + bus-width = <4>; 716 + non-removable; 717 + ti,fails-without-test-cd; 718 + cap-power-off-card; 719 + keep-power-in-suspend; 720 + ti,driver-strength-ohm = <50>; 721 + assigned-clocks = <&k3_clks 157 158>; 722 + assigned-clock-parents = <&k3_clks 157 160>; 723 + #address-cells = <1>; 724 + #size-cells = <0>; 725 + status = "okay"; 726 + 727 + wlcore: wlcore@2 { 728 + compatible = "ti,wl1807"; 729 + reg = <2>; 730 + pinctrl-names = "default"; 731 + pinctrl-0 = <&wifi_wlirq_pins_default>; 732 + interrupt-parent = <&main_gpio0>; 733 + interrupts = <41 IRQ_TYPE_EDGE_FALLING>; 734 + }; 735 + }; 736 + 737 + &main_uart0 { 738 + pinctrl-names = "default"; 739 + pinctrl-0 = <&console_pins_default>; 740 + status = "okay"; 741 + }; 742 + 743 + &main_uart1 { 744 + /* Main UART1 is used by TIFS firmware */ 745 + status = "reserved"; 746 + }; 747 + 748 + &main_uart5 { 749 + pinctrl-names = "default"; 750 + pinctrl-0 = <&mikrobus_uart_pins_default>; 751 + status = "okay"; 752 + }; 753 + 754 + &main_uart6 { 755 + pinctrl-names = "default"; 756 + pinctrl-0 = <&wifi_debug_uart_pins_default>; 757 + status = "okay"; 758 + };

+12 -232

arch/arm64/boot/dts/ti/k3-am625-sk.dts

··· 7 7 8 8 /dts-v1/; 9 9 10 - #include <dt-bindings/leds/common.h> 11 - #include <dt-bindings/gpio/gpio.h> 12 - #include <dt-bindings/net/ti-dp83867.h> 13 - #include "k3-am625.dtsi" 10 + #include "k3-am62x-sk-common.dtsi" 14 11 15 12 / { 16 13 compatible = "ti,am625-sk", "ti,am625"; 17 14 model = "Texas Instruments AM625 SK"; 18 - 19 - aliases { 20 - serial2 = &main_uart0; 21 - mmc0 = &sdhci0; 22 - mmc1 = &sdhci1; 23 - mmc2 = &sdhci2; 24 - spi0 = &ospi0; 25 - ethernet0 = &cpsw_port1; 26 - ethernet1 = &cpsw_port2; 27 - usb0 = &usb0; 28 - usb1 = &usb1; 29 - }; 30 - 31 - chosen { 32 - stdout-path = "serial2:115200n8"; 33 - bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 34 - }; 35 15 36 16 opp-table { 37 17 /* Add 1.4GHz OPP for am625-sk board. Requires VDD_CORE to be at 0.85V */ ··· 27 47 /* 2G RAM */ 28 48 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 29 49 30 - }; 31 - 32 - reserved-memory { 33 - #address-cells = <2>; 34 - #size-cells = <2>; 35 - ranges; 36 - 37 - ramoops@9ca00000 { 38 - compatible = "ramoops"; 39 - reg = <0x00 0x9ca00000 0x00 0x00100000>; 40 - record-size = <0x8000>; 41 - console-size = <0x8000>; 42 - ftrace-size = <0x00>; 43 - pmsg-size = <0x8000>; 44 - }; 45 - 46 - secure_tfa_ddr: tfa@9e780000 { 47 - reg = <0x00 0x9e780000 0x00 0x80000>; 48 - alignment = <0x1000>; 49 - no-map; 50 - }; 51 - 52 - secure_ddr: optee@9e800000 { 53 - reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 54 - alignment = <0x1000>; 55 - no-map; 56 - }; 57 - 58 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { 59 - compatible = "shared-dma-pool"; 60 - reg = <0x00 0x9db00000 0x00 0xc00000>; 61 - no-map; 62 - }; 63 50 }; 64 51 65 52 vmain_pd: regulator-0 { ··· 88 141 <3300000 0x1>; 89 142 }; 90 143 91 - leds { 92 - compatible = "gpio-leds"; 93 - pinctrl-names = "default"; 94 - pinctrl-0 = <&usr_led_pins_default>; 95 - 96 - led-0 { 97 - label = "am62-sk:green:heartbeat"; 98 - gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; 99 - linux,default-trigger = "heartbeat"; 100 - function = LED_FUNCTION_HEARTBEAT; 101 - default-state = "off"; 102 - }; 144 + vcc_1v8: regulator-5 { 145 + /* output of TPS6282518DMQ */ 146 + compatible = "regulator-fixed"; 147 + regulator-name = "vcc_1v8"; 148 + regulator-min-microvolt = <1800000>; 149 + regulator-max-microvolt = <1800000>; 150 + vin-supply = <&vcc_3v3_sys>; 151 + regulator-always-on; 152 + regulator-boot-on; 103 153 }; 104 154 }; 105 155 106 156 &main_pmx0 { 107 - main_uart0_pins_default: main-uart0-pins-default { 108 - pinctrl-single,pins = < 109 - AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14) UART0_RXD */ 110 - AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14) UART0_TXD */ 111 - >; 112 - }; 113 - 114 - main_i2c0_pins_default: main-i2c0-pins-default { 115 - pinctrl-single,pins = < 116 - AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16) I2C0_SCL */ 117 - AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16) I2C0_SDA */ 118 - >; 119 - }; 120 - 121 - main_i2c1_pins_default: main-i2c1-pins-default { 122 - pinctrl-single,pins = < 123 - AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17) I2C1_SCL */ 124 - AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17) I2C1_SDA */ 125 - >; 126 - }; 127 - 128 - main_i2c2_pins_default: main-i2c2-pins-default { 129 - pinctrl-single,pins = < 130 - AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22) GPMC0_CSn2.I2C2_SCL */ 131 - AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24) GPMC0_CSn3.I2C2_SDA */ 132 - >; 133 - }; 134 - 135 - main_mmc0_pins_default: main-mmc0-pins-default { 136 - pinctrl-single,pins = < 137 - AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3) MMC0_CMD */ 138 - AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1) MMC0_CLK */ 139 - AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2) MMC0_DAT0 */ 140 - AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1) MMC0_DAT1 */ 141 - AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3) MMC0_DAT2 */ 142 - AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4) MMC0_DAT3 */ 143 - AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2) MMC0_DAT4 */ 144 - AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1) MMC0_DAT5 */ 145 - AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2) MMC0_DAT6 */ 146 - AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2) MMC0_DAT7 */ 147 - >; 148 - }; 149 - 150 - main_mmc1_pins_default: main-mmc1-pins-default { 151 - pinctrl-single,pins = < 152 - AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21) MMC1_CMD */ 153 - AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22) MMC1_CLK */ 154 - AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22) MMC1_DAT0 */ 155 - AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21) MMC1_DAT1 */ 156 - AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21) MMC1_DAT2 */ 157 - AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22) MMC1_DAT3 */ 158 - AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17) MMC1_SDCD */ 159 - >; 160 - }; 161 - 162 - usr_led_pins_default: usr-led-pins-default { 163 - pinctrl-single,pins = < 164 - AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17) MMC1_SDWP.GPIO1_49 */ 165 - >; 166 - }; 167 - 168 - main_mdio1_pins_default: main-mdio1-pins-default { 169 - pinctrl-single,pins = < 170 - AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24) MDIO0_MDC */ 171 - AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22) MDIO0_MDIO */ 172 - >; 173 - }; 174 - 175 - main_rgmii1_pins_default: main-rgmii1-pins-default { 176 - pinctrl-single,pins = < 177 - AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17) RGMII1_RD0 */ 178 - AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17) RGMII1_RD1 */ 179 - AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16) RGMII1_RD2 */ 180 - AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15) RGMII1_RD3 */ 181 - AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17) RGMII1_RXC */ 182 - AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17) RGMII1_RX_CTL */ 183 - AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20) RGMII1_TD0 */ 184 - AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20) RGMII1_TD1 */ 185 - AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18) RGMII1_TD2 */ 186 - AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18) RGMII1_TD3 */ 187 - AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19) RGMII1_TXC */ 188 - AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19) RGMII1_TX_CTL */ 189 - >; 190 - }; 191 - 192 157 main_rgmii2_pins_default: main-rgmii2-pins-default { 193 158 pinctrl-single,pins = < 194 159 AM62X_IOPAD(0x184, PIN_INPUT, 0) /* (AE23) RGMII2_RD0 */ ··· 145 286 AM62X_IOPAD(0x01d4, PIN_INPUT, 7) /* (B15) UART0_RTSn.GPIO1_23 */ 146 287 >; 147 288 }; 148 - 149 - main_usb1_pins_default: main-usb1-pins-default { 150 - pinctrl-single,pins = < 151 - AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18) USB1_DRVVBUS */ 152 - >; 153 - }; 154 - }; 155 - 156 - &wkup_uart0 { 157 - /* WKUP UART0 is used by DM firmware */ 158 - status = "reserved"; 159 - }; 160 - 161 - &main_uart0 { 162 - status = "okay"; 163 - pinctrl-names = "default"; 164 - pinctrl-0 = <&main_uart0_pins_default>; 165 - }; 166 - 167 - &main_uart1 { 168 - /* Main UART1 is used by TIFS firmware */ 169 - status = "reserved"; 170 - }; 171 - 172 - &main_i2c0 { 173 - status = "okay"; 174 - pinctrl-names = "default"; 175 - pinctrl-0 = <&main_i2c0_pins_default>; 176 - clock-frequency = <400000>; 177 289 }; 178 290 179 291 &main_i2c1 { 180 - status = "okay"; 181 - pinctrl-names = "default"; 182 - pinctrl-0 = <&main_i2c1_pins_default>; 183 - clock-frequency = <400000>; 184 - 185 292 exp1: gpio@22 { 186 293 compatible = "ti,tca6424"; 187 294 reg = <0x22>; ··· 176 351 }; 177 352 }; 178 353 179 - &sdhci0 { 180 - status = "okay"; 181 - pinctrl-names = "default"; 182 - pinctrl-0 = <&main_mmc0_pins_default>; 183 - ti,driver-strength-ohm = <50>; 184 - disable-wp; 185 - }; 186 - 187 354 &sdhci1 { 188 - /* SD/MMC */ 189 - status = "okay"; 190 355 vmmc-supply = <&vdd_mmc1>; 191 356 vqmmc-supply = <&vdd_sd_dv>; 192 - pinctrl-names = "default"; 193 - pinctrl-0 = <&main_mmc1_pins_default>; 194 - ti,driver-strength-ohm = <50>; 195 - disable-wp; 196 357 }; 197 358 198 359 &cpsw3g { ··· 187 376 &main_rgmii2_pins_default>; 188 377 }; 189 378 190 - &cpsw_port1 { 191 - phy-mode = "rgmii-rxid"; 192 - phy-handle = <&cpsw3g_phy0>; 193 - }; 194 - 195 379 &cpsw_port2 { 196 380 phy-mode = "rgmii-rxid"; 197 381 phy-handle = <&cpsw3g_phy1>; 198 382 }; 199 383 200 384 &cpsw3g_mdio { 201 - status = "okay"; 202 - pinctrl-names = "default"; 203 - pinctrl-0 = <&main_mdio1_pins_default>; 204 - 205 - cpsw3g_phy0: ethernet-phy@0 { 206 - reg = <0>; 207 - ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 208 - ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 209 - ti,min-output-impedance; 210 - }; 211 - 212 385 cpsw3g_phy1: ethernet-phy@1 { 213 386 reg = <1>; 214 387 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; ··· 268 473 }; 269 474 }; 270 475 271 - &usbss0 { 272 - status = "okay"; 273 - ti,vbus-divider; 274 - }; 275 - 276 - &usbss1 { 277 - status = "okay"; 278 - }; 279 - 280 - &usb0 { 281 - dr_mode = "peripheral"; 282 - }; 283 - 284 - &usb1 { 285 - dr_mode = "host"; 286 - pinctrl-names = "default"; 287 - pinctrl-0 = <&main_usb1_pins_default>; 476 + &tlv320aic3106 { 477 + DVDD-supply = <&vcc_1v8>; 288 478 };

+1 -1

arch/arm64/boot/dts/ti/k3-am625.dtsi

··· 148 148 compatible = "cache"; 149 149 cache-unified; 150 150 cache-level = <2>; 151 - cache-size = <0x40000>; 151 + cache-size = <0x80000>; 152 152 cache-line-size = <64>; 153 153 cache-sets = <512>; 154 154 };

+2 -1

arch/arm64/boot/dts/ti/k3-am62a.dtsi

··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/interrupt-controller/irq.h> 10 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 - #include <dt-bindings/pinctrl/k3.h> 12 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 12 + 13 + #include "k3-pinctrl.h" 13 14 14 15 / { 15 16 model = "Texas Instruments K3 AM62A SoC";

+3 -2

arch/arm64/boot/dts/ti/k3-am62a7-sk.dts

··· 27 27 28 28 memory@80000000 { 29 29 device_type = "memory"; 30 - /* 2G RAM */ 31 - reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 30 + /* 4G RAM */ 31 + reg = <0x00000000 0x80000000 0x00000000 0x80000000>, 32 + <0x00000008 0x80000000 0x00000000 0x80000000>; 32 33 }; 33 34 34 35 reserved-memory {

+1 -1

arch/arm64/boot/dts/ti/k3-am62a7.dtsi

··· 97 97 compatible = "cache"; 98 98 cache-unified; 99 99 cache-level = <2>; 100 - cache-size = <0x40000>; 100 + cache-size = <0x80000>; 101 101 cache-line-size = <64>; 102 102 cache-sets = <512>; 103 103 };

+351

arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /* 3 + * Common dtsi for AM62x SK and derivatives 4 + * 5 + * Copyright (C) 2021-2023 Texas Instruments Incorporated - https://www.ti.com/ 6 + */ 7 + 8 + #include <dt-bindings/leds/common.h> 9 + #include <dt-bindings/gpio/gpio.h> 10 + #include <dt-bindings/net/ti-dp83867.h> 11 + #include "k3-am625.dtsi" 12 + 13 + / { 14 + aliases { 15 + serial2 = &main_uart0; 16 + mmc0 = &sdhci0; 17 + mmc1 = &sdhci1; 18 + mmc2 = &sdhci2; 19 + spi0 = &ospi0; 20 + ethernet0 = &cpsw_port1; 21 + ethernet1 = &cpsw_port2; 22 + usb0 = &usb0; 23 + usb1 = &usb1; 24 + }; 25 + 26 + chosen { 27 + stdout-path = "serial2:115200n8"; 28 + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 29 + }; 30 + 31 + memory@80000000 { 32 + device_type = "memory"; 33 + /* 2G RAM */ 34 + reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 35 + 36 + }; 37 + 38 + reserved-memory { 39 + #address-cells = <2>; 40 + #size-cells = <2>; 41 + ranges; 42 + 43 + ramoops@9ca00000 { 44 + compatible = "ramoops"; 45 + reg = <0x00 0x9ca00000 0x00 0x00100000>; 46 + record-size = <0x8000>; 47 + console-size = <0x8000>; 48 + ftrace-size = <0x00>; 49 + pmsg-size = <0x8000>; 50 + }; 51 + 52 + secure_tfa_ddr: tfa@9e780000 { 53 + reg = <0x00 0x9e780000 0x00 0x80000>; 54 + alignment = <0x1000>; 55 + no-map; 56 + }; 57 + 58 + secure_ddr: optee@9e800000 { 59 + reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 60 + alignment = <0x1000>; 61 + no-map; 62 + }; 63 + 64 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { 65 + compatible = "shared-dma-pool"; 66 + reg = <0x00 0x9db00000 0x00 0xc00000>; 67 + no-map; 68 + }; 69 + }; 70 + 71 + leds { 72 + compatible = "gpio-leds"; 73 + pinctrl-names = "default"; 74 + pinctrl-0 = <&usr_led_pins_default>; 75 + 76 + led-0 { 77 + label = "am62-sk:green:heartbeat"; 78 + gpios = <&main_gpio1 49 GPIO_ACTIVE_HIGH>; 79 + linux,default-trigger = "heartbeat"; 80 + function = LED_FUNCTION_HEARTBEAT; 81 + default-state = "off"; 82 + }; 83 + }; 84 + 85 + tlv320_mclk: clk-0 { 86 + #clock-cells = <0>; 87 + compatible = "fixed-clock"; 88 + clock-frequency = <12288000>; 89 + }; 90 + 91 + codec_audio: sound { 92 + compatible = "simple-audio-card"; 93 + simple-audio-card,name = "AM62x-SKEVM"; 94 + simple-audio-card,widgets = 95 + "Headphone", "Headphone Jack", 96 + "Line", "Line In", 97 + "Microphone", "Microphone Jack"; 98 + simple-audio-card,routing = 99 + "Headphone Jack", "HPLOUT", 100 + "Headphone Jack", "HPROUT", 101 + "LINE1L", "Line In", 102 + "LINE1R", "Line In", 103 + "MIC3R", "Microphone Jack", 104 + "Microphone Jack", "Mic Bias"; 105 + simple-audio-card,format = "dsp_b"; 106 + simple-audio-card,bitclock-master = <&sound_master>; 107 + simple-audio-card,frame-master = <&sound_master>; 108 + simple-audio-card,bitclock-inversion; 109 + 110 + simple-audio-card,cpu { 111 + sound-dai = <&mcasp1>; 112 + }; 113 + 114 + sound_master: simple-audio-card,codec { 115 + sound-dai = <&tlv320aic3106>; 116 + clocks = <&tlv320_mclk>; 117 + }; 118 + }; 119 + }; 120 + 121 + &main_pmx0 { 122 + /* First pad number is ALW package and second is AMC package */ 123 + main_uart0_pins_default: main-uart0-pins-default { 124 + pinctrl-single,pins = < 125 + AM62X_IOPAD(0x1c8, PIN_INPUT, 0) /* (D14/A13) UART0_RXD */ 126 + AM62X_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (E14/E11) UART0_TXD */ 127 + >; 128 + }; 129 + 130 + main_i2c0_pins_default: main-i2c0-pins-default { 131 + pinctrl-single,pins = < 132 + AM62X_IOPAD(0x1e0, PIN_INPUT_PULLUP, 0) /* (B16/E12) I2C0_SCL */ 133 + AM62X_IOPAD(0x1e4, PIN_INPUT_PULLUP, 0) /* (A16/D14) I2C0_SDA */ 134 + >; 135 + }; 136 + 137 + main_i2c1_pins_default: main-i2c1-pins-default { 138 + pinctrl-single,pins = < 139 + AM62X_IOPAD(0x1e8, PIN_INPUT_PULLUP, 0) /* (B17/A17) I2C1_SCL */ 140 + AM62X_IOPAD(0x1ec, PIN_INPUT_PULLUP, 0) /* (A17/A16) I2C1_SDA */ 141 + >; 142 + }; 143 + 144 + main_i2c2_pins_default: main-i2c2-pins-default { 145 + pinctrl-single,pins = < 146 + AM62X_IOPAD(0x0b0, PIN_INPUT_PULLUP, 1) /* (K22/H18) GPMC0_CSn2.I2C2_SCL */ 147 + AM62X_IOPAD(0x0b4, PIN_INPUT_PULLUP, 1) /* (K24/H19) GPMC0_CSn3.I2C2_SDA */ 148 + >; 149 + }; 150 + 151 + main_mmc0_pins_default: main-mmc0-pins-default { 152 + pinctrl-single,pins = < 153 + AM62X_IOPAD(0x220, PIN_INPUT, 0) /* (Y3/V3) MMC0_CMD */ 154 + AM62X_IOPAD(0x218, PIN_INPUT, 0) /* (AB1/Y1) MMC0_CLK */ 155 + AM62X_IOPAD(0x214, PIN_INPUT, 0) /* (AA2/V2) MMC0_DAT0 */ 156 + AM62X_IOPAD(0x210, PIN_INPUT, 0) /* (AA1/V1) MMC0_DAT1 */ 157 + AM62X_IOPAD(0x20c, PIN_INPUT, 0) /* (AA3/W2) MMC0_DAT2 */ 158 + AM62X_IOPAD(0x208, PIN_INPUT, 0) /* (Y4/W1) MMC0_DAT3 */ 159 + AM62X_IOPAD(0x204, PIN_INPUT, 0) /* (AB2/Y2) MMC0_DAT4 */ 160 + AM62X_IOPAD(0x200, PIN_INPUT, 0) /* (AC1/W3) MMC0_DAT5 */ 161 + AM62X_IOPAD(0x1fc, PIN_INPUT, 0) /* (AD2/W4) MMC0_DAT6 */ 162 + AM62X_IOPAD(0x1f8, PIN_INPUT, 0) /* (AC2/V4) MMC0_DAT7 */ 163 + >; 164 + }; 165 + 166 + main_mmc1_pins_default: main-mmc1-pins-default { 167 + pinctrl-single,pins = < 168 + AM62X_IOPAD(0x23c, PIN_INPUT, 0) /* (A21/C18) MMC1_CMD */ 169 + AM62X_IOPAD(0x234, PIN_INPUT, 0) /* (B22/A20) MMC1_CLK */ 170 + AM62X_IOPAD(0x230, PIN_INPUT, 0) /* (A22/A19) MMC1_DAT0 */ 171 + AM62X_IOPAD(0x22c, PIN_INPUT, 0) /* (B21/B19) MMC1_DAT1 */ 172 + AM62X_IOPAD(0x228, PIN_INPUT, 0) /* (C21/B20) MMC1_DAT2 */ 173 + AM62X_IOPAD(0x224, PIN_INPUT, 0) /* (D22/C19) MMC1_DAT3 */ 174 + AM62X_IOPAD(0x240, PIN_INPUT, 0) /* (D17/C15) MMC1_SDCD */ 175 + >; 176 + }; 177 + 178 + usr_led_pins_default: usr-led-pins-default { 179 + pinctrl-single,pins = < 180 + AM62X_IOPAD(0x244, PIN_OUTPUT, 7) /* (C17/B15) MMC1_SDWP.GPIO1_49 */ 181 + >; 182 + }; 183 + 184 + main_mdio1_pins_default: main-mdio1-pins-default { 185 + pinctrl-single,pins = < 186 + AM62X_IOPAD(0x160, PIN_OUTPUT, 0) /* (AD24/V17) MDIO0_MDC */ 187 + AM62X_IOPAD(0x15c, PIN_INPUT, 0) /* (AB22/U16) MDIO0_MDIO */ 188 + >; 189 + }; 190 + 191 + main_rgmii1_pins_default: main-rgmii1-pins-default { 192 + pinctrl-single,pins = < 193 + AM62X_IOPAD(0x14c, PIN_INPUT, 0) /* (AB17/W15) RGMII1_RD0 */ 194 + AM62X_IOPAD(0x150, PIN_INPUT, 0) /* (AC17/Y16) RGMII1_RD1 */ 195 + AM62X_IOPAD(0x154, PIN_INPUT, 0) /* (AB16/AA17) RGMII1_RD2 */ 196 + AM62X_IOPAD(0x158, PIN_INPUT, 0) /* (AA15/Y15) RGMII1_RD3 */ 197 + AM62X_IOPAD(0x148, PIN_INPUT, 0) /* (AD17/AA16) RGMII1_RXC */ 198 + AM62X_IOPAD(0x144, PIN_INPUT, 0) /* (AE17/W14) RGMII1_RX_CTL */ 199 + AM62X_IOPAD(0x134, PIN_OUTPUT, 0) /* (AE20/U14) RGMII1_TD0 */ 200 + AM62X_IOPAD(0x138, PIN_OUTPUT, 0) /* (AD20/AA19) RGMII1_TD1 */ 201 + AM62X_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AE18/Y17) RGMII1_TD2 */ 202 + AM62X_IOPAD(0x140, PIN_OUTPUT, 0) /* (AD18/AA18) RGMII1_TD3 */ 203 + AM62X_IOPAD(0x130, PIN_OUTPUT, 0) /* (AE19/W16) RGMII1_TXC */ 204 + AM62X_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AD19/V15) RGMII1_TX_CTL */ 205 + >; 206 + }; 207 + 208 + main_usb1_pins_default: main-usb1-pins-default { 209 + pinctrl-single,pins = < 210 + AM62X_IOPAD(0x0258, PIN_OUTPUT, 0) /* (F18/E16) USB1_DRVVBUS */ 211 + >; 212 + }; 213 + 214 + main_mcasp1_pins_default: main-mcasp1-pins-default { 215 + pinctrl-single,pins = < 216 + AM62X_IOPAD(0x090, PIN_INPUT, 2) /* (M24) GPMC0_BE0N_CLE.MCASP1_ACLKX */ 217 + AM62X_IOPAD(0x098, PIN_INPUT, 2) /* (U23) GPMC0_WAIT0.MCASP1_AFSX */ 218 + AM62X_IOPAD(0x08c, PIN_OUTPUT, 2) /* (L25) GPMC0_WEN.MCASP1_AXR0 */ 219 + AM62X_IOPAD(0x084, PIN_INPUT, 2) /* (L23) GPMC0_ADVN_ALE.MCASP1_AXR2 */ 220 + >; 221 + }; 222 + }; 223 + 224 + &wkup_uart0 { 225 + /* WKUP UART0 is used by DM firmware */ 226 + status = "reserved"; 227 + }; 228 + 229 + &main_uart0 { 230 + status = "okay"; 231 + pinctrl-names = "default"; 232 + pinctrl-0 = <&main_uart0_pins_default>; 233 + }; 234 + 235 + &main_uart1 { 236 + /* Main UART1 is used by TIFS firmware */ 237 + status = "reserved"; 238 + }; 239 + 240 + &main_i2c0 { 241 + status = "okay"; 242 + pinctrl-names = "default"; 243 + pinctrl-0 = <&main_i2c0_pins_default>; 244 + clock-frequency = <400000>; 245 + }; 246 + 247 + &main_i2c1 { 248 + status = "okay"; 249 + pinctrl-names = "default"; 250 + pinctrl-0 = <&main_i2c1_pins_default>; 251 + clock-frequency = <400000>; 252 + 253 + tlv320aic3106: audio-codec@1b { 254 + #sound-dai-cells = <0>; 255 + compatible = "ti,tlv320aic3106"; 256 + reg = <0x1b>; 257 + ai3x-micbias-vg = <1>; /* 2.0V */ 258 + 259 + /* Regulators */ 260 + AVDD-supply = <&vcc_3v3_sys>; 261 + IOVDD-supply = <&vcc_3v3_sys>; 262 + DRVDD-supply = <&vcc_3v3_sys>; 263 + }; 264 + }; 265 + 266 + &sdhci0 { 267 + status = "okay"; 268 + pinctrl-names = "default"; 269 + pinctrl-0 = <&main_mmc0_pins_default>; 270 + ti,driver-strength-ohm = <50>; 271 + disable-wp; 272 + }; 273 + 274 + &sdhci1 { 275 + /* SD/MMC */ 276 + status = "okay"; 277 + pinctrl-names = "default"; 278 + pinctrl-0 = <&main_mmc1_pins_default>; 279 + ti,driver-strength-ohm = <50>; 280 + disable-wp; 281 + }; 282 + 283 + &cpsw3g { 284 + pinctrl-names = "default"; 285 + pinctrl-0 = <&main_rgmii1_pins_default>; 286 + }; 287 + 288 + &cpsw_port1 { 289 + phy-mode = "rgmii-rxid"; 290 + phy-handle = <&cpsw3g_phy0>; 291 + }; 292 + 293 + &cpsw3g_mdio { 294 + status = "okay"; 295 + pinctrl-names = "default"; 296 + pinctrl-0 = <&main_mdio1_pins_default>; 297 + 298 + cpsw3g_phy0: ethernet-phy@0 { 299 + reg = <0>; 300 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 301 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 302 + ti,min-output-impedance; 303 + }; 304 + }; 305 + 306 + &mailbox0_cluster0 { 307 + mbox_m4_0: mbox-m4-0 { 308 + ti,mbox-rx = <0 0 0>; 309 + ti,mbox-tx = <1 0 0>; 310 + }; 311 + }; 312 + 313 + &usbss0 { 314 + status = "okay"; 315 + ti,vbus-divider; 316 + }; 317 + 318 + &usbss1 { 319 + status = "okay"; 320 + ti,vbus-divider; 321 + }; 322 + 323 + &usb0 { 324 + dr_mode = "peripheral"; 325 + }; 326 + 327 + &usb1 { 328 + dr_mode = "host"; 329 + pinctrl-names = "default"; 330 + pinctrl-0 = <&main_usb1_pins_default>; 331 + }; 332 + 333 + &mcasp1 { 334 + status = "okay"; 335 + #sound-dai-cells = <0>; 336 + 337 + pinctrl-names = "default"; 338 + pinctrl-0 = <&main_mcasp1_pins_default>; 339 + 340 + op-mode = <0>; /* MCASP_IIS_MODE */ 341 + tdm-slots = <2>; 342 + 343 + serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 344 + 1 0 2 0 345 + 0 0 0 0 346 + 0 0 0 0 347 + 0 0 0 0 348 + >; 349 + tx-num-evt = <32>; 350 + rx-num-evt = <32>; 351 + };

+2 -1

arch/arm64/boot/dts/ti/k3-am64.dtsi

··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/interrupt-controller/irq.h> 10 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 - #include <dt-bindings/pinctrl/k3.h> 12 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 12 + 13 + #include "k3-pinctrl.h" 13 14 14 15 / { 15 16 model = "Texas Instruments K3 AM642 SoC";

+2 -1

arch/arm64/boot/dts/ti/k3-am65.dtsi

··· 8 8 #include <dt-bindings/gpio/gpio.h> 9 9 #include <dt-bindings/interrupt-controller/irq.h> 10 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 - #include <dt-bindings/pinctrl/k3.h> 12 11 #include <dt-bindings/soc/ti,sci_pm_domain.h> 12 + 13 + #include "k3-pinctrl.h" 13 14 14 15 / { 15 16 model = "Texas Instruments K3 AM654 SoC";

+5 -7

arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts

··· 60 60 regulator-boot-on; 61 61 enable-active-high; 62 62 vin-supply = <&vsys_3v3>; 63 - gpio = <&exp1 10 GPIO_ACTIVE_HIGH>; 63 + gpio = <&exp1 8 GPIO_ACTIVE_HIGH>; 64 64 }; 65 65 66 66 vdd_sd_dv: regulator-tlv71033 { ··· 264 264 reg = <0x21>; 265 265 gpio-controller; 266 266 #gpio-cells = <2>; 267 - gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", "HDMI_PDn", 268 - "HDMI_LS_OE", "DP0_3V3 _EN", "BOARDID_EEPROM_WP", 269 - "CAN_STB", " ", "GPIO_uSD_PWR_EN", "eDP_ENABLE", 270 - "IO_EXP_PCIe1_M.2_RTSz", "IO_EXP_MCU_RGMII_RSTz", 271 - "IO_EXP_CSI2_EXP_RSTz", " ", "CSI0_B_GPIO1", 272 - "CSI1_B_GPIO1"; 267 + gpio-line-names = " ", " ", " ", " ", " ", 268 + "BOARDID_EEPROM_WP", "CAN_STB", " ", 269 + "GPIO_uSD_PWR_EN", " ", "IO_EXP_PCIe1_M.2_RTSz", 270 + "IO_EXP_MCU_RGMII_RST#", " ", " ", " ", " "; 273 271 }; 274 272 }; 275 273

+101

arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /** 3 + * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with 4 + * J7200 board. 5 + * 6 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 7 + */ 8 + 9 + /dts-v1/; 10 + /plugin/; 11 + 12 + #include <dt-bindings/gpio/gpio.h> 13 + #include <dt-bindings/mux/ti-serdes.h> 14 + 15 + #include "k3-pinctrl.h" 16 + 17 + &{/} { 18 + aliases { 19 + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 20 + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 21 + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; 22 + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; 23 + }; 24 + }; 25 + 26 + &cpsw0 { 27 + status = "okay"; 28 + }; 29 + 30 + &cpsw0_port1 { 31 + status = "okay"; 32 + phy-handle = <&cpsw5g_phy0>; 33 + phy-mode = "qsgmii"; 34 + mac-address = [00 00 00 00 00 00]; 35 + phys = <&cpsw0_phy_gmii_sel 1>; 36 + }; 37 + 38 + &cpsw0_port2 { 39 + status = "okay"; 40 + phy-handle = <&cpsw5g_phy1>; 41 + phy-mode = "qsgmii"; 42 + mac-address = [00 00 00 00 00 00]; 43 + phys = <&cpsw0_phy_gmii_sel 2>; 44 + }; 45 + 46 + &cpsw0_port3 { 47 + status = "okay"; 48 + phy-handle = <&cpsw5g_phy2>; 49 + phy-mode = "qsgmii"; 50 + mac-address = [00 00 00 00 00 00]; 51 + phys = <&cpsw0_phy_gmii_sel 3>; 52 + }; 53 + 54 + &cpsw0_port4 { 55 + status = "okay"; 56 + phy-handle = <&cpsw5g_phy3>; 57 + phy-mode = "qsgmii"; 58 + mac-address = [00 00 00 00 00 00]; 59 + phys = <&cpsw0_phy_gmii_sel 4>; 60 + }; 61 + 62 + &cpsw5g_mdio { 63 + status = "okay"; 64 + pinctrl-names = "default"; 65 + pinctrl-0 = <&mdio0_pins_default>; 66 + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; 67 + reset-post-delay-us = <120000>; 68 + #address-cells = <1>; 69 + #size-cells = <0>; 70 + 71 + cpsw5g_phy0: ethernet-phy@16 { 72 + reg = <16>; 73 + }; 74 + cpsw5g_phy1: ethernet-phy@17 { 75 + reg = <17>; 76 + }; 77 + cpsw5g_phy2: ethernet-phy@18 { 78 + reg = <18>; 79 + }; 80 + cpsw5g_phy3: ethernet-phy@19 { 81 + reg = <19>; 82 + }; 83 + }; 84 + 85 + &exp2 { 86 + qsgmii-line-hog { 87 + gpio-hog; 88 + gpios = <16 GPIO_ACTIVE_HIGH>; 89 + output-low; 90 + line-name = "qsgmii-pwrdn-line"; 91 + }; 92 + }; 93 + 94 + &main_pmx0 { 95 + mdio0_pins_default: mdio0-pins-default { 96 + pinctrl-single,pins = < 97 + J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ 98 + J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ 99 + >; 100 + }; 101 + };

+176

arch/arm64/boot/dts/ti/k3-j7200-main.dtsi

··· 39 39 <0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */ 40 40 }; 41 41 42 + cpsw0_phy_gmii_sel: phy@4044 { 43 + compatible = "ti,j7200-cpsw5g-phy-gmii-sel"; 44 + ti,qsgmii-main-ports = <1>; 45 + reg = <0x4044 0x10>; 46 + #phy-cells = <1>; 47 + }; 48 + 42 49 usb_serdes_mux: mux-controller@4000 { 43 50 compatible = "mmio-mux"; 44 51 #mux-control-cells = <1>; ··· 308 301 interrupt-names = "cpts"; 309 302 ti,cpts-periodic-outputs = <6>; 310 303 ti,cpts-ext-ts-inputs = <8>; 304 + }; 305 + }; 306 + 307 + cpsw0: ethernet@c000000 { 308 + compatible = "ti,j7200-cpswxg-nuss"; 309 + #address-cells = <2>; 310 + #size-cells = <2>; 311 + reg = <0x00 0xc000000 0x00 0x200000>; 312 + reg-names = "cpsw_nuss"; 313 + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; 314 + clocks = <&k3_clks 19 33>; 315 + clock-names = "fck"; 316 + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 317 + 318 + dmas = <&main_udmap 0xca00>, 319 + <&main_udmap 0xca01>, 320 + <&main_udmap 0xca02>, 321 + <&main_udmap 0xca03>, 322 + <&main_udmap 0xca04>, 323 + <&main_udmap 0xca05>, 324 + <&main_udmap 0xca06>, 325 + <&main_udmap 0xca07>, 326 + <&main_udmap 0x4a00>; 327 + dma-names = "tx0", "tx1", "tx2", "tx3", 328 + "tx4", "tx5", "tx6", "tx7", 329 + "rx"; 330 + 331 + status = "disabled"; 332 + 333 + ethernet-ports { 334 + #address-cells = <1>; 335 + #size-cells = <0>; 336 + cpsw0_port1: port@1 { 337 + reg = <1>; 338 + ti,mac-only; 339 + label = "port1"; 340 + status = "disabled"; 341 + }; 342 + 343 + cpsw0_port2: port@2 { 344 + reg = <2>; 345 + ti,mac-only; 346 + label = "port2"; 347 + status = "disabled"; 348 + }; 349 + 350 + cpsw0_port3: port@3 { 351 + reg = <3>; 352 + ti,mac-only; 353 + label = "port3"; 354 + status = "disabled"; 355 + }; 356 + 357 + cpsw0_port4: port@4 { 358 + reg = <4>; 359 + ti,mac-only; 360 + label = "port4"; 361 + status = "disabled"; 362 + }; 363 + }; 364 + 365 + cpsw5g_mdio: mdio@f00 { 366 + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 367 + reg = <0x00 0xf00 0x00 0x100>; 368 + #address-cells = <1>; 369 + #size-cells = <0>; 370 + clocks = <&k3_clks 19 33>; 371 + clock-names = "fck"; 372 + bus_freq = <1000000>; 373 + status = "disabled"; 374 + }; 375 + 376 + cpts@3d000 { 377 + compatible = "ti,j721e-cpts"; 378 + reg = <0x00 0x3d000 0x00 0x400>; 379 + clocks = <&k3_clks 19 16>; 380 + clock-names = "cpts"; 381 + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 382 + interrupt-names = "cpts"; 383 + ti,cpts-ext-ts-inputs = <4>; 384 + ti,cpts-periodic-outputs = <2>; 311 385 }; 312 386 }; 313 387 ··· 863 775 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 864 776 clocks = <&k3_clks 111 0>; 865 777 clock-names = "gpio"; 778 + }; 779 + 780 + main_spi0: spi@2100000 { 781 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 782 + reg = <0x00 0x02100000 0x00 0x400>; 783 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 784 + #address-cells = <1>; 785 + #size-cells = <0>; 786 + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 787 + clocks = <&k3_clks 266 1>; 788 + status = "disabled"; 789 + }; 790 + 791 + main_spi1: spi@2110000 { 792 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 793 + reg = <0x00 0x02110000 0x00 0x400>; 794 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 795 + #address-cells = <1>; 796 + #size-cells = <0>; 797 + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 798 + clocks = <&k3_clks 267 1>; 799 + status = "disabled"; 800 + }; 801 + 802 + main_spi2: spi@2120000 { 803 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 804 + reg = <0x00 0x02120000 0x00 0x400>; 805 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 806 + #address-cells = <1>; 807 + #size-cells = <0>; 808 + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 809 + clocks = <&k3_clks 268 1>; 810 + status = "disabled"; 811 + }; 812 + 813 + main_spi3: spi@2130000 { 814 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 815 + reg = <0x00 0x02130000 0x00 0x400>; 816 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 817 + #address-cells = <1>; 818 + #size-cells = <0>; 819 + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 820 + clocks = <&k3_clks 269 1>; 821 + status = "disabled"; 822 + }; 823 + 824 + main_spi4: spi@2140000 { 825 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 826 + reg = <0x00 0x02140000 0x00 0x400>; 827 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 828 + #address-cells = <1>; 829 + #size-cells = <0>; 830 + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 831 + clocks = <&k3_clks 270 1>; 832 + status = "disabled"; 833 + }; 834 + 835 + main_spi5: spi@2150000 { 836 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 837 + reg = <0x00 0x02150000 0x00 0x400>; 838 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 839 + #address-cells = <1>; 840 + #size-cells = <0>; 841 + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 842 + clocks = <&k3_clks 271 1>; 843 + status = "disabled"; 844 + }; 845 + 846 + main_spi6: spi@2160000 { 847 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 848 + reg = <0x00 0x02160000 0x00 0x400>; 849 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 850 + #address-cells = <1>; 851 + #size-cells = <0>; 852 + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 853 + clocks = <&k3_clks 272 1>; 854 + status = "disabled"; 855 + }; 856 + 857 + main_spi7: spi@2170000 { 858 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 859 + reg = <0x00 0x02170000 0x00 0x400>; 860 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 861 + #address-cells = <1>; 862 + #size-cells = <0>; 863 + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 864 + clocks = <&k3_clks 273 1>; 865 + status = "disabled"; 866 866 }; 867 867 868 868 watchdog0: watchdog@2200000 {

+33

arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi

··· 305 305 status = "disabled"; 306 306 }; 307 307 308 + mcu_spi0: spi@40300000 { 309 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 310 + reg = <0x00 0x040300000 0x00 0x400>; 311 + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 312 + #address-cells = <1>; 313 + #size-cells = <0>; 314 + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 315 + clocks = <&k3_clks 274 0>; 316 + status = "disabled"; 317 + }; 318 + 319 + mcu_spi1: spi@40310000 { 320 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 321 + reg = <0x00 0x040310000 0x00 0x400>; 322 + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 323 + #address-cells = <1>; 324 + #size-cells = <0>; 325 + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 326 + clocks = <&k3_clks 275 0>; 327 + status = "disabled"; 328 + }; 329 + 330 + mcu_spi2: spi@40320000 { 331 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 332 + reg = <0x00 0x040320000 0x00 0x400>; 333 + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 334 + #address-cells = <1>; 335 + #size-cells = <0>; 336 + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 337 + clocks = <&k3_clks 276 0>; 338 + status = "disabled"; 339 + }; 340 + 308 341 fss: syscon@47000000 { 309 342 compatible = "syscon", "simple-mfd"; 310 343 reg = <0x00 0x47000000 0x00 0x100>;

+2 -1

arch/arm64/boot/dts/ti/k3-j7200.dtsi

··· 7 7 8 8 #include <dt-bindings/interrupt-controller/irq.h> 9 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 - #include <dt-bindings/pinctrl/k3.h> 11 10 #include <dt-bindings/soc/ti,sci_pm_domain.h> 11 + 12 + #include "k3-pinctrl.h" 12 13 13 14 / { 14 15 model = "Texas Instruments K3 J7200 SoC";

+133

arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso

··· 1 + // SPDX-License-Identifier: GPL-2.0 2 + /** 3 + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with 4 + * J721E board. 5 + * 6 + * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/ 7 + */ 8 + 9 + /dts-v1/; 10 + /plugin/; 11 + 12 + #include <dt-bindings/gpio/gpio.h> 13 + #include <dt-bindings/mux/ti-serdes.h> 14 + #include <dt-bindings/phy/phy.h> 15 + #include <dt-bindings/phy/phy-cadence.h> 16 + 17 + #include "k3-pinctrl.h" 18 + 19 + &{/} { 20 + aliases { 21 + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1"; 22 + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2"; 23 + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3"; 24 + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4"; 25 + }; 26 + }; 27 + 28 + &cpsw0 { 29 + status = "okay"; 30 + }; 31 + 32 + &cpsw0_port1 { 33 + status = "okay"; 34 + phy-handle = <&cpsw9g_phy0>; 35 + phy-mode = "qsgmii"; 36 + mac-address = [00 00 00 00 00 00]; 37 + phys = <&cpsw0_phy_gmii_sel 1>; 38 + }; 39 + 40 + &cpsw0_port2 { 41 + status = "okay"; 42 + phy-handle = <&cpsw9g_phy1>; 43 + phy-mode = "qsgmii"; 44 + mac-address = [00 00 00 00 00 00]; 45 + phys = <&cpsw0_phy_gmii_sel 2>; 46 + }; 47 + 48 + &cpsw0_port3 { 49 + status = "okay"; 50 + phy-handle = <&cpsw9g_phy2>; 51 + phy-mode = "qsgmii"; 52 + mac-address = [00 00 00 00 00 00]; 53 + phys = <&cpsw0_phy_gmii_sel 3>; 54 + }; 55 + 56 + &cpsw0_port4 { 57 + status = "okay"; 58 + phy-handle = <&cpsw9g_phy3>; 59 + phy-mode = "qsgmii"; 60 + mac-address = [00 00 00 00 00 00]; 61 + phys = <&cpsw0_phy_gmii_sel 4>; 62 + }; 63 + 64 + &cpsw9g_mdio { 65 + status = "okay"; 66 + pinctrl-names = "default"; 67 + pinctrl-0 = <&mdio0_pins_default>; 68 + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; 69 + reset-post-delay-us = <120000>; 70 + #address-cells = <1>; 71 + #size-cells = <0>; 72 + 73 + cpsw9g_phy0: ethernet-phy@17 { 74 + reg = <17>; 75 + }; 76 + cpsw9g_phy1: ethernet-phy@16 { 77 + reg = <16>; 78 + }; 79 + cpsw9g_phy2: ethernet-phy@18 { 80 + reg = <18>; 81 + }; 82 + cpsw9g_phy3: ethernet-phy@19 { 83 + reg = <19>; 84 + }; 85 + }; 86 + 87 + &exp2 { 88 + qsgmii-line-hog { 89 + gpio-hog; 90 + gpios = <16 GPIO_ACTIVE_HIGH>; 91 + output-low; 92 + line-name = "qsgmii-pwrdn-line"; 93 + }; 94 + }; 95 + 96 + &main_pmx0 { 97 + mdio0_pins_default: mdio0-pins-default { 98 + pinctrl-single,pins = < 99 + J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */ 100 + J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */ 101 + >; 102 + }; 103 + }; 104 + 105 + &serdes_ln_ctrl { 106 + idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>, 107 + <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>, 108 + <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>, 109 + <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>, 110 + <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>, 111 + <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 112 + }; 113 + 114 + &serdes_wiz0 { 115 + status = "okay"; 116 + }; 117 + 118 + &serdes0 { 119 + status = "okay"; 120 + 121 + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>; 122 + assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>; 123 + #address-cells = <1>; 124 + #size-cells = <0>; 125 + 126 + serdes0_qsgmii_link: phy@1 { 127 + reg = <1>; 128 + cdns,num-lanes = <1>; 129 + #phy-cells = <0>; 130 + cdns,phy-type = <PHY_TYPE_QSGMII>; 131 + resets = <&serdes_wiz0 2>; 132 + }; 133 + };

+204 -1

arch/arm64/boot/dts/ti/k3-j721e-main.dtsi

··· 61 61 <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>; 62 62 }; 63 63 64 + cpsw0_phy_gmii_sel: phy@4044 { 65 + compatible = "ti,j721e-cpsw9g-phy-gmii-sel"; 66 + ti,qsgmii-main-ports = <2>, <2>; 67 + reg = <0x4044 0x20>; 68 + #phy-cells = <1>; 69 + }; 70 + 64 71 usb_serdes_mux: mux-controller@4000 { 65 72 compatible = "mmio-mux"; 66 73 #mux-control-cells = <1>; ··· 408 401 interrupt-names = "cpts"; 409 402 ti,cpts-periodic-outputs = <6>; 410 403 ti,cpts-ext-ts-inputs = <8>; 404 + }; 405 + }; 406 + 407 + cpsw0: ethernet@c000000 { 408 + compatible = "ti,j721e-cpswxg-nuss"; 409 + #address-cells = <2>; 410 + #size-cells = <2>; 411 + reg = <0x0 0xc000000 0x0 0x200000>; 412 + reg-names = "cpsw_nuss"; 413 + ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>; 414 + clocks = <&k3_clks 19 89>; 415 + clock-names = "fck"; 416 + power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>; 417 + 418 + dmas = <&main_udmap 0xca00>, 419 + <&main_udmap 0xca01>, 420 + <&main_udmap 0xca02>, 421 + <&main_udmap 0xca03>, 422 + <&main_udmap 0xca04>, 423 + <&main_udmap 0xca05>, 424 + <&main_udmap 0xca06>, 425 + <&main_udmap 0xca07>, 426 + <&main_udmap 0x4a00>; 427 + dma-names = "tx0", "tx1", "tx2", "tx3", 428 + "tx4", "tx5", "tx6", "tx7", 429 + "rx"; 430 + 431 + status = "disabled"; 432 + 433 + ethernet-ports { 434 + #address-cells = <1>; 435 + #size-cells = <0>; 436 + cpsw0_port1: port@1 { 437 + reg = <1>; 438 + ti,mac-only; 439 + label = "port1"; 440 + status = "disabled"; 441 + }; 442 + 443 + cpsw0_port2: port@2 { 444 + reg = <2>; 445 + ti,mac-only; 446 + label = "port2"; 447 + status = "disabled"; 448 + }; 449 + 450 + cpsw0_port3: port@3 { 451 + reg = <3>; 452 + ti,mac-only; 453 + label = "port3"; 454 + status = "disabled"; 455 + }; 456 + 457 + cpsw0_port4: port@4 { 458 + reg = <4>; 459 + ti,mac-only; 460 + label = "port4"; 461 + status = "disabled"; 462 + }; 463 + 464 + cpsw0_port5: port@5 { 465 + reg = <5>; 466 + ti,mac-only; 467 + label = "port5"; 468 + status = "disabled"; 469 + }; 470 + 471 + cpsw0_port6: port@6 { 472 + reg = <6>; 473 + ti,mac-only; 474 + label = "port6"; 475 + status = "disabled"; 476 + }; 477 + 478 + cpsw0_port7: port@7 { 479 + reg = <7>; 480 + ti,mac-only; 481 + label = "port7"; 482 + status = "disabled"; 483 + }; 484 + 485 + cpsw0_port8: port@8 { 486 + reg = <8>; 487 + ti,mac-only; 488 + label = "port8"; 489 + status = "disabled"; 490 + }; 491 + }; 492 + 493 + cpsw9g_mdio: mdio@f00 { 494 + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 495 + reg = <0x0 0xf00 0x0 0x100>; 496 + #address-cells = <1>; 497 + #size-cells = <0>; 498 + clocks = <&k3_clks 19 89>; 499 + clock-names = "fck"; 500 + bus_freq = <1000000>; 501 + status = "disabled"; 502 + }; 503 + 504 + cpts@3d000 { 505 + compatible = "ti,j721e-cpts"; 506 + reg = <0x0 0x3d000 0x0 0x400>; 507 + clocks = <&k3_clks 19 16>; 508 + clock-names = "cpts"; 509 + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 510 + interrupt-names = "cpts"; 511 + ti,cpts-ext-ts-inputs = <4>; 512 + ti,cpts-periodic-outputs = <2>; 411 513 }; 412 514 }; 413 515 ··· 1296 1180 ti,itap-del-sel-mmc-hs = <0xa>; 1297 1181 ti,itap-del-sel-ddr52 = <0x3>; 1298 1182 ti,trm-icp = <0x8>; 1299 - ti,strobe-sel = <0x77>; 1300 1183 dma-coherent; 1301 1184 }; 1302 1185 ··· 2442 2327 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 2443 2328 interrupt-names = "int0", "int1"; 2444 2329 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 2330 + status = "disabled"; 2331 + }; 2332 + 2333 + main_spi0: spi@2100000 { 2334 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2335 + reg = <0x00 0x02100000 0x00 0x400>; 2336 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 2337 + #address-cells = <1>; 2338 + #size-cells = <0>; 2339 + power-domains = <&k3_pds 266 TI_SCI_PD_EXCLUSIVE>; 2340 + clocks = <&k3_clks 266 1>; 2341 + status = "disabled"; 2342 + }; 2343 + 2344 + main_spi1: spi@2110000 { 2345 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2346 + reg = <0x00 0x02110000 0x00 0x400>; 2347 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 2348 + #address-cells = <1>; 2349 + #size-cells = <0>; 2350 + power-domains = <&k3_pds 267 TI_SCI_PD_EXCLUSIVE>; 2351 + clocks = <&k3_clks 267 1>; 2352 + status = "disabled"; 2353 + }; 2354 + 2355 + main_spi2: spi@2120000 { 2356 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2357 + reg = <0x00 0x02120000 0x00 0x400>; 2358 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 2359 + #address-cells = <1>; 2360 + #size-cells = <0>; 2361 + power-domains = <&k3_pds 268 TI_SCI_PD_EXCLUSIVE>; 2362 + clocks = <&k3_clks 268 1>; 2363 + status = "disabled"; 2364 + }; 2365 + 2366 + main_spi3: spi@2130000 { 2367 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2368 + reg = <0x00 0x02130000 0x00 0x400>; 2369 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 2370 + #address-cells = <1>; 2371 + #size-cells = <0>; 2372 + power-domains = <&k3_pds 269 TI_SCI_PD_EXCLUSIVE>; 2373 + clocks = <&k3_clks 269 1>; 2374 + status = "disabled"; 2375 + }; 2376 + 2377 + main_spi4: spi@2140000 { 2378 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2379 + reg = <0x00 0x02140000 0x00 0x400>; 2380 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 2381 + #address-cells = <1>; 2382 + #size-cells = <0>; 2383 + power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 2384 + clocks = <&k3_clks 270 1>; 2385 + status = "disabled"; 2386 + }; 2387 + 2388 + main_spi5: spi@2150000 { 2389 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2390 + reg = <0x00 0x02150000 0x00 0x400>; 2391 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 2392 + #address-cells = <1>; 2393 + #size-cells = <0>; 2394 + power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 2395 + clocks = <&k3_clks 271 1>; 2396 + status = "disabled"; 2397 + }; 2398 + 2399 + main_spi6: spi@2160000 { 2400 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2401 + reg = <0x00 0x02160000 0x00 0x400>; 2402 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 2403 + #address-cells = <1>; 2404 + #size-cells = <0>; 2405 + power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 2406 + clocks = <&k3_clks 272 1>; 2407 + status = "disabled"; 2408 + }; 2409 + 2410 + main_spi7: spi@2170000 { 2411 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 2412 + reg = <0x00 0x02170000 0x00 0x400>; 2413 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 2414 + #address-cells = <1>; 2415 + #size-cells = <0>; 2416 + power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 2417 + clocks = <&k3_clks 273 1>; 2445 2418 status = "disabled"; 2446 2419 }; 2447 2420 };

+33

arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi

··· 425 425 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 426 426 status = "disabled"; 427 427 }; 428 + 429 + mcu_spi0: spi@40300000 { 430 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 431 + reg = <0x00 0x040300000 0x00 0x400>; 432 + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 433 + #address-cells = <1>; 434 + #size-cells = <0>; 435 + power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 436 + clocks = <&k3_clks 274 0>; 437 + status = "disabled"; 438 + }; 439 + 440 + mcu_spi1: spi@40310000 { 441 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 442 + reg = <0x00 0x040310000 0x00 0x400>; 443 + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 444 + #address-cells = <1>; 445 + #size-cells = <0>; 446 + power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 447 + clocks = <&k3_clks 275 0>; 448 + status = "disabled"; 449 + }; 450 + 451 + mcu_spi2: spi@40320000 { 452 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 453 + reg = <0x00 0x040320000 0x00 0x400>; 454 + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 455 + #address-cells = <1>; 456 + #size-cells = <0>; 457 + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 458 + clocks = <&k3_clks 276 0>; 459 + status = "disabled"; 460 + }; 428 461 };

-4

arch/arm64/boot/dts/ti/k3-j721e-sk.dts

··· 687 687 status = "disabled"; 688 688 }; 689 689 690 - &main_r5fss0_core0{ 691 - firmware-name = "pdk-ipc/ipc_echo_test_mcu2_0_release_strip.xer5f"; 692 - }; 693 - 694 690 &usb_serdes_mux { 695 691 idle-states = <1>, <1>; /* USB0 to SERDES3, USB1 to SERDES2 */ 696 692 };

+3 -1

arch/arm64/boot/dts/ti/k3-j721e.dtsi

··· 7 7 8 8 #include <dt-bindings/interrupt-controller/irq.h> 9 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 - #include <dt-bindings/pinctrl/k3.h> 11 10 #include <dt-bindings/soc/ti,sci_pm_domain.h> 11 + 12 + #include "k3-pinctrl.h" 12 13 13 14 / { 14 15 model = "Texas Instruments K3 J721E SoC"; ··· 136 135 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */ 137 136 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */ 138 137 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */ 138 + <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */ 139 139 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 140 140 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/ 141 141 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/

+44

arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts

··· 197 197 J721S2_WKUP_IOPAD(0x0c8, PIN_INPUT, 7) /* (C28) WKUP_GPIO0_2 */ 198 198 >; 199 199 }; 200 + 201 + mcu_adc0_pins_default: mcu-adc0-pins-default { 202 + pinctrl-single,pins = < 203 + J721S2_WKUP_IOPAD(0x134, PIN_INPUT, 0) /* (L25) MCU_ADC0_AIN0 */ 204 + J721S2_WKUP_IOPAD(0x138, PIN_INPUT, 0) /* (K25) MCU_ADC0_AIN1 */ 205 + J721S2_WKUP_IOPAD(0x13c, PIN_INPUT, 0) /* (M24) MCU_ADC0_AIN2 */ 206 + J721S2_WKUP_IOPAD(0x140, PIN_INPUT, 0) /* (L24) MCU_ADC0_AIN3 */ 207 + J721S2_WKUP_IOPAD(0x144, PIN_INPUT, 0) /* (L27) MCU_ADC0_AIN4 */ 208 + J721S2_WKUP_IOPAD(0x148, PIN_INPUT, 0) /* (K24) MCU_ADC0_AIN5 */ 209 + J721S2_WKUP_IOPAD(0x14c, PIN_INPUT, 0) /* (M27) MCU_ADC0_AIN6 */ 210 + J721S2_WKUP_IOPAD(0x150, PIN_INPUT, 0) /* (M26) MCU_ADC0_AIN7 */ 211 + >; 212 + }; 213 + 214 + mcu_adc1_pins_default: mcu-adc1-pins-default { 215 + pinctrl-single,pins = < 216 + J721S2_WKUP_IOPAD(0x154, PIN_INPUT, 0) /* (P25) MCU_ADC1_AIN0 */ 217 + J721S2_WKUP_IOPAD(0x158, PIN_INPUT, 0) /* (R25) MCU_ADC1_AIN1 */ 218 + J721S2_WKUP_IOPAD(0x15c, PIN_INPUT, 0) /* (P28) MCU_ADC1_AIN2 */ 219 + J721S2_WKUP_IOPAD(0x160, PIN_INPUT, 0) /* (P27) MCU_ADC1_AIN3 */ 220 + J721S2_WKUP_IOPAD(0x164, PIN_INPUT, 0) /* (N25) MCU_ADC1_AIN4 */ 221 + J721S2_WKUP_IOPAD(0x168, PIN_INPUT, 0) /* (P26) MCU_ADC1_AIN5 */ 222 + J721S2_WKUP_IOPAD(0x16c, PIN_INPUT, 0) /* (N26) MCU_ADC1_AIN6 */ 223 + J721S2_WKUP_IOPAD(0x170, PIN_INPUT, 0) /* (N27) MCU_ADC1_AIN7 */ 224 + >; 225 + }; 200 226 }; 201 227 202 228 &main_gpio2 { ··· 334 308 pinctrl-names = "default"; 335 309 pinctrl-0 = <&mcu_mcan1_pins_default>; 336 310 phys = <&transceiver2>; 311 + }; 312 + 313 + &tscadc0 { 314 + pinctrl-0 = <&mcu_adc0_pins_default>; 315 + pinctrl-names = "default"; 316 + status = "okay"; 317 + adc { 318 + ti,adc-channels = <0 1 2 3 4 5 6 7>; 319 + }; 320 + }; 321 + 322 + &tscadc1 { 323 + pinctrl-0 = <&mcu_adc1_pins_default>; 324 + pinctrl-names = "default"; 325 + status = "okay"; 326 + adc { 327 + ti,adc-channels = <0 1 2 3 4 5 6 7>; 328 + }; 337 329 };

+88

arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

··· 1014 1014 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>; 1015 1015 status = "disabled"; 1016 1016 }; 1017 + 1018 + main_spi0: spi@2100000 { 1019 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1020 + reg = <0x00 0x02100000 0x00 0x400>; 1021 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1022 + #address-cells = <1>; 1023 + #size-cells = <0>; 1024 + power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>; 1025 + clocks = <&k3_clks 339 1>; 1026 + status = "disabled"; 1027 + }; 1028 + 1029 + main_spi1: spi@2110000 { 1030 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1031 + reg = <0x00 0x02110000 0x00 0x400>; 1032 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1033 + #address-cells = <1>; 1034 + #size-cells = <0>; 1035 + power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>; 1036 + clocks = <&k3_clks 340 1>; 1037 + status = "disabled"; 1038 + }; 1039 + 1040 + main_spi2: spi@2120000 { 1041 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1042 + reg = <0x00 0x02120000 0x00 0x400>; 1043 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1044 + #address-cells = <1>; 1045 + #size-cells = <0>; 1046 + power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>; 1047 + clocks = <&k3_clks 341 1>; 1048 + status = "disabled"; 1049 + }; 1050 + 1051 + main_spi3: spi@2130000 { 1052 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1053 + reg = <0x00 0x02130000 0x00 0x400>; 1054 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1055 + #address-cells = <1>; 1056 + #size-cells = <0>; 1057 + power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>; 1058 + clocks = <&k3_clks 342 1>; 1059 + status = "disabled"; 1060 + }; 1061 + 1062 + main_spi4: spi@2140000 { 1063 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1064 + reg = <0x00 0x02140000 0x00 0x400>; 1065 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1066 + #address-cells = <1>; 1067 + #size-cells = <0>; 1068 + power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>; 1069 + clocks = <&k3_clks 343 1>; 1070 + status = "disabled"; 1071 + }; 1072 + 1073 + main_spi5: spi@2150000 { 1074 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1075 + reg = <0x00 0x02150000 0x00 0x400>; 1076 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1077 + #address-cells = <1>; 1078 + #size-cells = <0>; 1079 + power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>; 1080 + clocks = <&k3_clks 344 1>; 1081 + status = "disabled"; 1082 + }; 1083 + 1084 + main_spi6: spi@2160000 { 1085 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1086 + reg = <0x00 0x02160000 0x00 0x400>; 1087 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1088 + #address-cells = <1>; 1089 + #size-cells = <0>; 1090 + power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 1091 + clocks = <&k3_clks 345 1>; 1092 + status = "disabled"; 1093 + }; 1094 + 1095 + main_spi7: spi@2170000 { 1096 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1097 + reg = <0x00 0x02170000 0x00 0x400>; 1098 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1099 + #address-cells = <1>; 1100 + #size-cells = <0>; 1101 + power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>; 1102 + clocks = <&k3_clks 346 1>; 1103 + status = "disabled"; 1104 + }; 1017 1105 };

+73

arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi

··· 203 203 status = "disabled"; 204 204 }; 205 205 206 + mcu_spi0: spi@40300000 { 207 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 208 + reg = <0x00 0x040300000 0x00 0x400>; 209 + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 210 + #address-cells = <1>; 211 + #size-cells = <0>; 212 + power-domains = <&k3_pds 347 TI_SCI_PD_EXCLUSIVE>; 213 + clocks = <&k3_clks 347 0>; 214 + status = "disabled"; 215 + }; 216 + 217 + mcu_spi1: spi@40310000 { 218 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 219 + reg = <0x00 0x040310000 0x00 0x400>; 220 + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 221 + #address-cells = <1>; 222 + #size-cells = <0>; 223 + power-domains = <&k3_pds 348 TI_SCI_PD_EXCLUSIVE>; 224 + clocks = <&k3_clks 348 0>; 225 + status = "disabled"; 226 + }; 227 + 228 + mcu_spi2: spi@40320000 { 229 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 230 + reg = <0x00 0x040320000 0x00 0x400>; 231 + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 232 + #address-cells = <1>; 233 + #size-cells = <0>; 234 + power-domains = <&k3_pds 349 TI_SCI_PD_EXCLUSIVE>; 235 + clocks = <&k3_clks 349 0>; 236 + status = "disabled"; 237 + }; 238 + 206 239 mcu_navss: bus@28380000{ 207 240 compatible = "simple-mfd"; 208 241 #address-cells = <2>; ··· 337 304 interrupt-names = "cpts"; 338 305 ti,cpts-ext-ts-inputs = <4>; 339 306 ti,cpts-periodic-outputs = <2>; 307 + }; 308 + }; 309 + 310 + tscadc0: tscadc@40200000 { 311 + compatible = "ti,am3359-tscadc"; 312 + reg = <0x00 0x40200000 0x00 0x1000>; 313 + interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 314 + power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 315 + clocks = <&k3_clks 0 0>; 316 + assigned-clocks = <&k3_clks 0 2>; 317 + assigned-clock-rates = <60000000>; 318 + clock-names = "fck"; 319 + dmas = <&main_udmap 0x7400>, 320 + <&main_udmap 0x7401>; 321 + dma-names = "fifo0", "fifo1"; 322 + status = "disabled"; 323 + 324 + adc { 325 + #io-channel-cells = <1>; 326 + compatible = "ti,am3359-adc"; 327 + }; 328 + }; 329 + 330 + tscadc1: tscadc@40210000 { 331 + compatible = "ti,am3359-tscadc"; 332 + reg = <0x00 0x40210000 0x00 0x1000>; 333 + interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 334 + power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 335 + clocks = <&k3_clks 1 0>; 336 + assigned-clocks = <&k3_clks 1 2>; 337 + assigned-clock-rates = <60000000>; 338 + clock-names = "fck"; 339 + dmas = <&main_udmap 0x7402>, 340 + <&main_udmap 0x7403>; 341 + dma-names = "fifo0", "fifo1"; 342 + status = "disabled"; 343 + 344 + adc { 345 + #io-channel-cells = <1>; 346 + compatible = "ti,am3359-adc"; 340 347 }; 341 348 }; 342 349 };

+2 -1

arch/arm64/boot/dts/ti/k3-j721s2.dtsi

··· 10 10 11 11 #include <dt-bindings/interrupt-controller/irq.h> 12 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 - #include <dt-bindings/pinctrl/k3.h> 14 13 #include <dt-bindings/soc/ti,sci_pm_domain.h> 14 + 15 + #include "k3-pinctrl.h" 15 16 16 17 / { 17 18

+59

arch/arm64/boot/dts/ti/k3-j784s4-evm.dts

··· 21 21 22 22 aliases { 23 23 serial2 = &main_uart8; 24 + mmc0 = &main_sdhci0; 24 25 mmc1 = &main_sdhci1; 25 26 i2c0 = &main_i2c0; 26 27 }; ··· 141 140 }; 142 141 }; 143 142 143 + &wkup_pmx0 { 144 + mcu_cpsw_pins_default: mcu-cpsw-pins-default { 145 + pinctrl-single,pins = < 146 + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 147 + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 148 + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 149 + J784S4_WKUP_IOPAD(0x088, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 150 + J784S4_WKUP_IOPAD(0x084, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 151 + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 152 + J784S4_WKUP_IOPAD(0x07c, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 153 + J784S4_WKUP_IOPAD(0x078, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 154 + J784S4_WKUP_IOPAD(0x074, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 155 + J784S4_WKUP_IOPAD(0x070, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 156 + J784S4_WKUP_IOPAD(0x080, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 157 + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 158 + >; 159 + }; 160 + 161 + mcu_mdio_pins_default: mcu-mdio-pins-default { 162 + pinctrl-single,pins = < 163 + J784S4_WKUP_IOPAD(0x09c, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 164 + J784S4_WKUP_IOPAD(0x098, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 165 + >; 166 + }; 167 + }; 168 + 144 169 &main_uart8 { 145 170 status = "okay"; 146 171 pinctrl-names = "default"; ··· 208 181 }; 209 182 }; 210 183 184 + &main_sdhci0 { 185 + /* eMMC */ 186 + status = "okay"; 187 + non-removable; 188 + ti,driver-strength-ohm = <50>; 189 + disable-wp; 190 + }; 191 + 211 192 &main_sdhci1 { 212 193 /* SD card */ 213 194 status = "okay"; ··· 228 193 229 194 &main_gpio0 { 230 195 status = "okay"; 196 + }; 197 + 198 + &mcu_cpsw { 199 + status = "okay"; 200 + pinctrl-names = "default"; 201 + pinctrl-0 = <&mcu_cpsw_pins_default>; 202 + }; 203 + 204 + &davinci_mdio { 205 + pinctrl-names = "default"; 206 + pinctrl-0 = <&mcu_mdio_pins_default>; 207 + 208 + mcu_phy0: ethernet-phy@0 { 209 + reg = <0>; 210 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 211 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 212 + ti,min-output-impedance; 213 + }; 214 + }; 215 + 216 + &mcu_cpsw_port1 { 217 + status = "okay"; 218 + phy-mode = "rgmii-rxid"; 219 + phy-handle = <&mcu_phy0>; 231 220 };

+108

arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi

··· 72 72 pinctrl-single,function-mask = <0xffffffff>; 73 73 }; 74 74 75 + main_crypto: crypto@4e00000 { 76 + compatible = "ti,j721e-sa2ul"; 77 + reg = <0x00 0x4e00000 0x00 0x1200>; 78 + power-domains = <&k3_pds 369 TI_SCI_PD_EXCLUSIVE>; 79 + #address-cells = <2>; 80 + #size-cells = <2>; 81 + ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>; 82 + 83 + dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>, 84 + <&main_udmap 0x4a41>; 85 + dma-names = "tx", "rx1", "rx2"; 86 + 87 + rng: rng@4e10000 { 88 + compatible = "inside-secure,safexcel-eip76"; 89 + reg = <0x00 0x4e10000 0x00 0x7d>; 90 + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 91 + }; 92 + }; 93 + 75 94 main_uart0: serial@2800000 { 76 95 compatible = "ti,j721e-uart", "ti,am654-uart"; 77 96 reg = <0x00 0x02800000 0x00 0x200>; ··· 417 398 #address-cells = <2>; 418 399 #size-cells = <2>; 419 400 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 401 + ti,sci-dev-id = <280>; 420 402 dma-coherent; 421 403 dma-ranges; 422 404 ··· 1022 1002 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1023 1003 interrupt-names = "int0", "int1"; 1024 1004 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1005 + status = "disabled"; 1006 + }; 1007 + 1008 + main_spi0: spi@2100000 { 1009 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1010 + reg = <0x00 0x02100000 0x00 0x400>; 1011 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1012 + #address-cells = <1>; 1013 + #size-cells = <0>; 1014 + power-domains = <&k3_pds 376 TI_SCI_PD_EXCLUSIVE>; 1015 + clocks = <&k3_clks 376 1>; 1016 + status = "disabled"; 1017 + }; 1018 + 1019 + main_spi1: spi@2110000 { 1020 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1021 + reg = <0x00 0x02110000 0x00 0x400>; 1022 + interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1023 + #address-cells = <1>; 1024 + #size-cells = <0>; 1025 + power-domains = <&k3_pds 377 TI_SCI_PD_EXCLUSIVE>; 1026 + clocks = <&k3_clks 377 1>; 1027 + status = "disabled"; 1028 + }; 1029 + 1030 + main_spi2: spi@2120000 { 1031 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1032 + reg = <0x00 0x02120000 0x00 0x400>; 1033 + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1034 + #address-cells = <1>; 1035 + #size-cells = <0>; 1036 + power-domains = <&k3_pds 378 TI_SCI_PD_EXCLUSIVE>; 1037 + clocks = <&k3_clks 378 1>; 1038 + status = "disabled"; 1039 + }; 1040 + 1041 + main_spi3: spi@2130000 { 1042 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1043 + reg = <0x00 0x02130000 0x00 0x400>; 1044 + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1045 + #address-cells = <1>; 1046 + #size-cells = <0>; 1047 + power-domains = <&k3_pds 379 TI_SCI_PD_EXCLUSIVE>; 1048 + clocks = <&k3_clks 379 1>; 1049 + status = "disabled"; 1050 + }; 1051 + 1052 + main_spi4: spi@2140000 { 1053 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1054 + reg = <0x00 0x02140000 0x00 0x400>; 1055 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1056 + #address-cells = <1>; 1057 + #size-cells = <0>; 1058 + power-domains = <&k3_pds 380 TI_SCI_PD_EXCLUSIVE>; 1059 + clocks = <&k3_clks 380 1>; 1060 + status = "disabled"; 1061 + }; 1062 + 1063 + main_spi5: spi@2150000 { 1064 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1065 + reg = <0x00 0x02150000 0x00 0x400>; 1066 + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 1067 + #address-cells = <1>; 1068 + #size-cells = <0>; 1069 + power-domains = <&k3_pds 381 TI_SCI_PD_EXCLUSIVE>; 1070 + clocks = <&k3_clks 381 1>; 1071 + status = "disabled"; 1072 + }; 1073 + 1074 + main_spi6: spi@2160000 { 1075 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1076 + reg = <0x00 0x02160000 0x00 0x400>; 1077 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1078 + #address-cells = <1>; 1079 + #size-cells = <0>; 1080 + power-domains = <&k3_pds 382 TI_SCI_PD_EXCLUSIVE>; 1081 + clocks = <&k3_clks 382 1>; 1082 + status = "disabled"; 1083 + }; 1084 + 1085 + main_spi7: spi@2170000 { 1086 + compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 1087 + reg = <0x00 0x02170000 0x00 0x400>; 1088 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1089 + #address-cells = <1>; 1090 + #size-cells = <0>; 1091 + power-domains = <&k3_pds 383 TI_SCI_PD_EXCLUSIVE>; 1092 + clocks = <&k3_clks 383 1>; 1025 1093 status = "disabled"; 1026 1094 }; 1027 1095 };

+34

arch/arm64/boot/dts/ti/k3-j784s4-mcu-wakeup.dtsi

··· 204 204 status = "disabled"; 205 205 }; 206 206 207 + mcu_spi0: spi@40300000 { 208 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 209 + reg = <0x00 0x040300000 0x00 0x400>; 210 + interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 211 + #address-cells = <1>; 212 + #size-cells = <0>; 213 + power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; 214 + clocks = <&k3_clks 384 0>; 215 + status = "disabled"; 216 + }; 217 + 218 + mcu_spi1: spi@40310000 { 219 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 220 + reg = <0x00 0x040310000 0x00 0x400>; 221 + interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 222 + #address-cells = <1>; 223 + #size-cells = <0>; 224 + power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; 225 + clocks = <&k3_clks 385 0>; 226 + status = "disabled"; 227 + }; 228 + 229 + mcu_spi2: spi@40320000 { 230 + compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 231 + reg = <0x00 0x040320000 0x00 0x400>; 232 + interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 233 + #address-cells = <1>; 234 + #size-cells = <0>; 235 + power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; 236 + clocks = <&k3_clks 386 0>; 237 + status = "disabled"; 238 + }; 239 + 207 240 mcu_navss: bus@28380000{ 208 241 compatible = "simple-bus"; 209 242 #address-cells = <2>; 210 243 #size-cells = <2>; 211 244 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 245 + ti,sci-dev-id = <323>; 212 246 dma-coherent; 213 247 dma-ranges; 214 248

+2 -1

arch/arm64/boot/dts/ti/k3-j784s4.dtsi

··· 10 10 11 11 #include <dt-bindings/interrupt-controller/irq.h> 12 12 #include <dt-bindings/interrupt-controller/arm-gic.h> 13 - #include <dt-bindings/pinctrl/k3.h> 14 13 #include <dt-bindings/soc/ti,sci_pm_domain.h> 14 + 15 + #include "k3-pinctrl.h" 15 16 16 17 / { 17 18 model = "Texas Instruments K3 J784S4 SoC";

+53

arch/arm64/boot/dts/ti/k3-pinctrl.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0 */ 2 + /* 3 + * This header provides constants for pinctrl bindings for TI's K3 SoC 4 + * family. 5 + * 6 + * Copyright (C) 2018-2023 Texas Instruments Incorporated - https://www.ti.com/ 7 + */ 8 + #ifndef DTS_ARM64_TI_K3_PINCTRL_H 9 + #define DTS_ARM64_TI_K3_PINCTRL_H 10 + 11 + #define PULLUDEN_SHIFT (16) 12 + #define PULLTYPESEL_SHIFT (17) 13 + #define RXACTIVE_SHIFT (18) 14 + 15 + #define PULL_DISABLE (1 << PULLUDEN_SHIFT) 16 + #define PULL_ENABLE (0 << PULLUDEN_SHIFT) 17 + 18 + #define PULL_UP (1 << PULLTYPESEL_SHIFT | PULL_ENABLE) 19 + #define PULL_DOWN (0 << PULLTYPESEL_SHIFT | PULL_ENABLE) 20 + 21 + #define INPUT_EN (1 << RXACTIVE_SHIFT) 22 + #define INPUT_DISABLE (0 << RXACTIVE_SHIFT) 23 + 24 + /* Only these macros are expected be used directly in device tree files */ 25 + #define PIN_OUTPUT (INPUT_DISABLE | PULL_DISABLE) 26 + #define PIN_OUTPUT_PULLUP (INPUT_DISABLE | PULL_UP) 27 + #define PIN_OUTPUT_PULLDOWN (INPUT_DISABLE | PULL_DOWN) 28 + #define PIN_INPUT (INPUT_EN | PULL_DISABLE) 29 + #define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP) 30 + #define PIN_INPUT_PULLDOWN (INPUT_EN | PULL_DOWN) 31 + 32 + #define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 33 + #define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 34 + 35 + #define AM62X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 36 + #define AM62X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 37 + 38 + #define AM64X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 39 + #define AM64X_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 40 + 41 + #define AM65X_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 42 + #define AM65X_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 43 + 44 + #define J721E_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 45 + #define J721E_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 46 + 47 + #define J721S2_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 48 + #define J721S2_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 49 + 50 + #define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 51 + #define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode)) 52 + 53 + #endif

+7

include/dt-bindings/pinctrl/k3.h

··· 8 8 #ifndef _DT_BINDINGS_PINCTRL_TI_K3_H 9 9 #define _DT_BINDINGS_PINCTRL_TI_K3_H 10 10 11 + /* 12 + * These bindings are deprecated, because they do not match the actual 13 + * concept of bindings but rather contain pure register values. 14 + * Instead include the header in the DTS source directory. 15 + */ 16 + #warning "These bindings are deprecated. Instead, use the header in the DTS source directory." 17 + 11 18 #define PULLUDEN_SHIFT (16) 12 19 #define PULLTYPESEL_SHIFT (17) 13 20 #define RXACTIVE_SHIFT (18)

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