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dt-bindings: devfreq: rk3399_dmc: Add more disable-freq properties

DDR DVFS tuning has found that several power-saving features don't have
good tradeoffs at higher frequencies -- at higher frequencies, we'll see
glitches or other errors. Provide tuning controls so these can be
disabled at higher OPPs, and left active only at the lower ones.

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>

authored by

Brian Norris and committed by
Chanwoo Choi a86fb6a9 77c18808

+37
+37
Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
··· 313 313 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated 314 314 if bus is idle for standby_idle nanoseconds. 315 315 316 + rockchip,pd-idle-dis-freq-hz: 317 + description: 318 + Defines the power-down idle disable frequency in Hz. When the DDR 319 + frequency is greater than pd-idle-dis-freq, power-down idle is disabled. 320 + See also rockchip,pd-idle-ns. 321 + 322 + rockchip,sr-idle-dis-freq-hz: 323 + description: 324 + Defines the self-refresh idle disable frequency in Hz. When the DDR 325 + frequency is greater than sr-idle-dis-freq, self-refresh idle is 326 + disabled. See also rockchip,sr-idle-ns. 327 + 328 + rockchip,sr-mc-gate-idle-dis-freq-hz: 329 + description: 330 + Defines the self-refresh and memory-controller clock gating disable 331 + frequency in Hz. When the DDR frequency is greater than 332 + sr-mc-gate-idle-dis-freq, the clock will not be gated when idle. See also 333 + rockchip,sr-mc-gate-idle-ns. 334 + 335 + rockchip,srpd-lite-idle-dis-freq-hz: 336 + description: 337 + Defines the self-refresh power down idle disable frequency in Hz. When 338 + the DDR frequency is greater than srpd-lite-idle-dis-freq, memory will 339 + not be placed into self-refresh power down mode when idle. See also 340 + rockchip,srpd-lite-idle-ns. 341 + 342 + rockchip,standby-idle-dis-freq-hz: 343 + description: 344 + Defines the standby idle disable frequency in Hz. When the DDR frequency 345 + is greater than standby-idle-dis-freq, standby idle is disabled. See also 346 + rockchip,standby-idle-ns. 347 + 316 348 required: 317 349 - compatible 318 350 - devfreq-events ··· 376 344 rockchip,ddr3_odt_dis_freq = <333000000>; 377 345 rockchip,lpddr3_odt_dis_freq = <333000000>; 378 346 rockchip,lpddr4_odt_dis_freq = <333000000>; 347 + rockchip,pd-idle-dis-freq-hz = <1000000000>; 348 + rockchip,sr-idle-dis-freq-hz = <1000000000>; 349 + rockchip,sr-mc-gate-idle-dis-freq-hz = <1000000000>; 350 + rockchip,srpd-lite-idle-dis-freq-hz = <0>; 351 + rockchip,standby-idle-dis-freq-hz = <928000000>; 379 352 };