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clk: qcom: videocc-sm8550: Move PLL & clk configuration to really probe

Video PLLs on SM8550/SM8650 require both MMCX and MXC rails to be kept ON
to configure the PLLs properly. Hence move runtime power management, PLL
configuration and enable critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-8-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Jagadeesh Kona and committed by
Bjorn Andersson a9dc2cc7 512af5bf

+33 -33
+33 -33
drivers/clk/qcom/videocc-sm8550.c
··· 7 7 #include <linux/mod_devicetable.h> 8 8 #include <linux/module.h> 9 9 #include <linux/platform_device.h> 10 - #include <linux/pm_runtime.h> 11 10 #include <linux/regmap.h> 12 11 13 12 #include <dt-bindings/clock/qcom,sm8650-videocc.h> ··· 50 51 51 52 static struct clk_alpha_pll video_cc_pll0 = { 52 53 .offset = 0x0, 54 + .config = &video_cc_pll0_config, 53 55 .vco_table = lucid_ole_vco, 54 56 .num_vco = ARRAY_SIZE(lucid_ole_vco), 55 57 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], ··· 82 82 83 83 static struct clk_alpha_pll video_cc_pll1 = { 84 84 .offset = 0x1000, 85 + .config = &video_cc_pll1_config, 85 86 .vco_table = lucid_ole_vco, 86 87 .num_vco = ARRAY_SIZE(lucid_ole_vco), 87 88 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], ··· 512 511 [VIDEO_CC_XO_CLK_ARES] = { .reg = 0x8124, .bit = 2, .udelay = 100 }, 513 512 }; 514 513 514 + static struct clk_alpha_pll *video_cc_sm8550_plls[] = { 515 + &video_cc_pll0, 516 + &video_cc_pll1, 517 + }; 518 + 519 + static u32 video_cc_sm8550_critical_cbcrs[] = { 520 + 0x80f4, /* VIDEO_CC_AHB_CLK */ 521 + 0x8124, /* VIDEO_CC_XO_CLK */ 522 + 0x8140, /* VIDEO_CC_SLEEP_CLK */ 523 + }; 524 + 525 + static u32 video_cc_sm8650_critical_cbcrs[] = { 526 + 0x80f4, /* VIDEO_CC_AHB_CLK */ 527 + 0x8124, /* VIDEO_CC_XO_CLK */ 528 + 0x8150, /* VIDEO_CC_SLEEP_CLK */ 529 + }; 530 + 515 531 static const struct regmap_config video_cc_sm8550_regmap_config = { 516 532 .reg_bits = 32, 517 533 .reg_stride = 4, 518 534 .val_bits = 32, 519 535 .max_register = 0x9f4c, 520 536 .fast_io = true, 537 + }; 538 + 539 + static struct qcom_cc_driver_data video_cc_sm8550_driver_data = { 540 + .alpha_plls = video_cc_sm8550_plls, 541 + .num_alpha_plls = ARRAY_SIZE(video_cc_sm8550_plls), 542 + .clk_cbcrs = video_cc_sm8550_critical_cbcrs, 543 + .num_clk_cbcrs = ARRAY_SIZE(video_cc_sm8550_critical_cbcrs), 521 544 }; 522 545 523 546 static const struct qcom_cc_desc video_cc_sm8550_desc = { ··· 552 527 .num_resets = ARRAY_SIZE(video_cc_sm8550_resets), 553 528 .gdscs = video_cc_sm8550_gdscs, 554 529 .num_gdscs = ARRAY_SIZE(video_cc_sm8550_gdscs), 530 + .use_rpm = true, 531 + .driver_data = &video_cc_sm8550_driver_data, 555 532 }; 556 533 557 534 static const struct of_device_id video_cc_sm8550_match_table[] = { ··· 565 538 566 539 static int video_cc_sm8550_probe(struct platform_device *pdev) 567 540 { 568 - struct regmap *regmap; 569 - int ret; 570 - u32 sleep_clk_offset = 0x8140; 571 - 572 - ret = devm_pm_runtime_enable(&pdev->dev); 573 - if (ret) 574 - return ret; 575 - 576 - ret = pm_runtime_resume_and_get(&pdev->dev); 577 - if (ret) 578 - return ret; 579 - 580 - regmap = qcom_cc_map(pdev, &video_cc_sm8550_desc); 581 - if (IS_ERR(regmap)) { 582 - pm_runtime_put(&pdev->dev); 583 - return PTR_ERR(regmap); 584 - } 585 - 586 541 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) { 587 - sleep_clk_offset = 0x8150; 588 542 video_cc_pll0_config.l = 0x1e; 589 543 video_cc_pll0_config.alpha = 0xa000; 590 544 video_cc_pll1_config.l = 0x2b; ··· 577 569 video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr; 578 570 video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr; 579 571 video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr; 572 + 573 + video_cc_sm8550_driver_data.clk_cbcrs = video_cc_sm8650_critical_cbcrs; 574 + video_cc_sm8550_driver_data.num_clk_cbcrs = 575 + ARRAY_SIZE(video_cc_sm8650_critical_cbcrs); 580 576 } 581 577 582 - clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 583 - clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 584 - 585 - /* Keep some clocks always-on */ 586 - qcom_branch_set_clk_en(regmap, 0x80f4); /* VIDEO_CC_AHB_CLK */ 587 - qcom_branch_set_clk_en(regmap, sleep_clk_offset); /* VIDEO_CC_SLEEP_CLK */ 588 - qcom_branch_set_clk_en(regmap, 0x8124); /* VIDEO_CC_XO_CLK */ 589 - 590 - ret = qcom_cc_really_probe(&pdev->dev, &video_cc_sm8550_desc, regmap); 591 - 592 - pm_runtime_put(&pdev->dev); 593 - 594 - return ret; 578 + return qcom_cc_probe(pdev, &video_cc_sm8550_desc); 595 579 } 596 580 597 581 static struct platform_driver video_cc_sm8550_driver = {