tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel os linux
1
fork

Configure Feed

Select the types of activity you want to include in your feed.

drm/amdgpu: Rework MES initialization on GFX 12.1

Currently, only SPX mode works on GFX 12.1. This patch reworks
the MES initialization to get other non-SPX modes working. For example,
for CPX mode, coop_enable bit needs to be set to 0. The shared command
buffer initialization is also not needed in CPX mode.
The shared command buffer initialization needs further improvements which
will be handled in later patches.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Reviewed-by: Alex Sierra <alex.sierra@amd.com>
Reviewed-by: Michael Chen <michael.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Mukul Joshi and committed by
Alex Deucher aa0f09f9 b7c4040d

+46 -10
+46 -10
drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
··· 591 591 mes_v12_1_get_rrmt(input->wrm_reg.reg1, 592 592 GET_INST(GC, input->xcc_id), 593 593 &misc_pkt.wait_reg_mem.rrmt_opt2); 594 + 594 595 if (misc_pkt.wait_reg_mem.rrmt_opt1.mode != MES_RRMT_MODE_REMOTE_MID) { 595 596 misc_pkt.wait_reg_mem.reg_offset1 = 596 597 NORMALIZE_XCC_REG_OFFSET(misc_pkt.wait_reg_mem.reg_offset1); ··· 1509 1508 struct amdgpu_device *adev = ip_block->adev; 1510 1509 int pipe, r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1511 1510 1512 - if (adev->enable_uni_mes && num_xcc > 1) 1513 - adev->mes.enable_coop_mode = true; 1514 - 1515 1511 adev->mes.funcs = &mes_v12_1_funcs; 1516 1512 adev->mes.kiq_hw_init = &mes_v12_1_kiq_hw_init; 1517 1513 adev->mes.kiq_hw_fini = &mes_v12_1_kiq_hw_fini; ··· 1539 1541 if (r) 1540 1542 return r; 1541 1543 1542 - if (adev->mes.enable_coop_mode) { 1544 + if (adev->enable_uni_mes && num_xcc > 1) { 1543 1545 r = mes_v12_1_allocate_shared_cmd_buf(adev, 1544 1546 pipe, xcc_id); 1545 1547 if (r) ··· 1739 1741 return 0; 1740 1742 } 1741 1743 1744 + static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id) 1745 + { 1746 + u32 num_xcc_per_xcp, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1747 + int r = 0; 1748 + 1749 + if (num_xcc == 1) 1750 + return r; 1751 + 1752 + if (adev->gfx.funcs && 1753 + adev->gfx.funcs->get_xccs_per_xcp) 1754 + num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 1755 + else 1756 + return -EINVAL; 1757 + 1758 + switch (adev->xcp_mgr->mode) { 1759 + case AMDGPU_SPX_PARTITION_MODE: 1760 + adev->mes.enable_coop_mode = 1; 1761 + adev->mes.master_xcc_ids[xcc_id] = 0; 1762 + break; 1763 + case AMDGPU_DPX_PARTITION_MODE: 1764 + adev->mes.enable_coop_mode = 1; 1765 + adev->mes.master_xcc_ids[xcc_id] = 1766 + (xcc_id/num_xcc_per_xcp) * (num_xcc / 2); 1767 + break; 1768 + case AMDGPU_QPX_PARTITION_MODE: 1769 + adev->mes.enable_coop_mode = 1; 1770 + adev->mes.master_xcc_ids[xcc_id] = 1771 + (xcc_id/num_xcc_per_xcp) * (num_xcc / 4); 1772 + break; 1773 + case AMDGPU_CPX_PARTITION_MODE: 1774 + adev->mes.enable_coop_mode = 0; 1775 + break; 1776 + default: 1777 + r = -EINVAL; 1778 + break; 1779 + } 1780 + return r; 1781 + } 1782 + 1742 1783 static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id) 1743 1784 { 1744 1785 int r; ··· 1818 1781 if (r) 1819 1782 goto failure; 1820 1783 1821 - if (adev->enable_uni_mes) 1784 + if (adev->enable_uni_mes) { 1785 + r = mes_v12_1_setup_coop_mode(adev, xcc_id); 1786 + if (r) 1787 + goto failure; 1822 1788 mes_v12_1_set_hw_resources_1(&adev->mes, 1823 1789 AMDGPU_MES_SCHED_PIPE, xcc_id); 1824 - 1790 + } 1825 1791 mes_v12_1_init_aggregated_doorbell(&adev->mes, xcc_id); 1826 1792 1827 1793 r = mes_v12_1_query_sched_status(&adev->mes, ··· 1856 1816 int r, xcc_id, num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1857 1817 1858 1818 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1859 - /* for SPX mode, all master xcc ids are set to 0 */ 1860 - if (adev->mes.enable_coop_mode) 1861 - adev->mes.master_xcc_ids[xcc_id] = 0; 1862 - 1863 1819 r = mes_v12_1_xcc_hw_init(ip_block, xcc_id); 1864 1820 if (r) 1865 1821 return r;