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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'sti-dt-for-v6.18-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt
STi dt fixes:
- Remove unused stih407-clock.dtsi file
* tag 'sti-dt-for-v6.18-round2' of git://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: dts: sti: remove dangling stih407-clock file
Link: https://lore.kernel.org/r/4a710c05-aeeb-4421-b3a1-5bfb8230d51d@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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arch/arm/boot/dts/st/stih407-clock.dtsi
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arch/arm/boot/dts/st/stih407-clock.dtsi
···
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2014 STMicroelectronics R&D Limited
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*/
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#include <dt-bindings/clock/stih407-clks.h>
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/ {
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/*
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* Fixed 30MHz oscillator inputs to SoC
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*/
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clk_sysin: clk-sysin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <30000000>;
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};
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-
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clk_tmdsout_hdmi: clk-tmdsout-hdmi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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-
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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-
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/*
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* A9 PLL.
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*/
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clockgen-a9@92b0000 {
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compatible = "st,clkgen-c32";
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reg = <0x92b0000 0x10000>;
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-
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clockgen_a9_pll: clockgen-a9-pll {
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#clock-cells = <1>;
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compatible = "st,stih407-clkgen-plla9";
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-
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clocks = <&clk_sysin>;
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};
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-
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clk_m_a9: clk-m-a9 {
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#clock-cells = <0>;
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compatible = "st,stih407-clkgen-a9-mux";
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-
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clocks = <&clockgen_a9_pll 0>,
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<&clockgen_a9_pll 0>,
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<&clk_s_c0_flexgen 13>,
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<&clk_m_a9_ext2f_div2>;
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-
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/*
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* ARM Peripheral clock for timers
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*/
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arm_periph_clk: clk-m-a9-periphs {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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-
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clocks = <&clk_m_a9>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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-
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clockgen-a@90ff000 {
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compatible = "st,clkgen-c32";
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reg = <0x90ff000 0x1000>;
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-
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clk_s_a0_pll: clk-s-a0-pll {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0-a0";
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-
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clocks = <&clk_sysin>;
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};
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-
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clk_s_a0_flexgen: clk-s-a0-flexgen {
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compatible = "st,flexgen", "st,flexgen-stih407-a0";
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-
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#clock-cells = <1>;
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-
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clocks = <&clk_s_a0_pll 0>,
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<&clk_sysin>;
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};
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};
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clk_s_c0: clockgen-c@9103000 {
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compatible = "st,clkgen-c32";
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reg = <0x9103000 0x1000>;
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-
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clk_s_c0_pll0: clk-s-c0-pll0 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll0-c0";
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-
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clocks = <&clk_sysin>;
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};
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-
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clk_s_c0_pll1: clk-s-c0-pll1 {
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#clock-cells = <1>;
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compatible = "st,clkgen-pll1-c0";
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-
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clocks = <&clk_sysin>;
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};
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-
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clk_s_c0_quadfs: clk-s-c0-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-pll";
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-
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clocks = <&clk_sysin>;
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};
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-
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clk_s_c0_flexgen: clk-s-c0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-c0";
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-
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clocks = <&clk_s_c0_pll0 0>,
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<&clk_s_c0_pll1 0>,
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<&clk_s_c0_quadfs 0>,
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<&clk_s_c0_quadfs 1>,
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<&clk_s_c0_quadfs 2>,
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<&clk_s_c0_quadfs 3>,
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<&clk_sysin>;
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/*
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* ARM Peripheral clock for timers
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*/
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clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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-
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clocks = <&clk_s_c0_flexgen 13>;
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-
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clock-output-names = "clk-m-a9-ext2f-div2";
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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};
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clockgen-d0@9104000 {
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compatible = "st,clkgen-c32";
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reg = <0x9104000 0x1000>;
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-
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clk_s_d0_quadfs: clk-s-d0-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-d0";
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-
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clocks = <&clk_sysin>;
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};
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clk_s_d0_flexgen: clk-s-d0-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-d0";
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-
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clocks = <&clk_s_d0_quadfs 0>,
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<&clk_s_d0_quadfs 1>,
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<&clk_s_d0_quadfs 2>,
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<&clk_s_d0_quadfs 3>,
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<&clk_sysin>;
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};
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};
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clockgen-d2@9106000 {
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compatible = "st,clkgen-c32";
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reg = <0x9106000 0x1000>;
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-
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clk_s_d2_quadfs: clk-s-d2-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-d2";
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clocks = <&clk_sysin>;
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};
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clk_s_d2_flexgen: clk-s-d2-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-d2";
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-
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clocks = <&clk_s_d2_quadfs 0>,
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<&clk_s_d2_quadfs 1>,
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<&clk_s_d2_quadfs 2>,
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<&clk_s_d2_quadfs 3>,
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<&clk_sysin>,
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<&clk_sysin>,
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<&clk_tmdsout_hdmi>;
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};
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};
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clockgen-d3@9107000 {
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compatible = "st,clkgen-c32";
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reg = <0x9107000 0x1000>;
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clk_s_d3_quadfs: clk-s-d3-quadfs {
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#clock-cells = <1>;
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compatible = "st,quadfs-d3";
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clocks = <&clk_sysin>;
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};
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clk_s_d3_flexgen: clk-s-d3-flexgen {
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#clock-cells = <1>;
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compatible = "st,flexgen", "st,flexgen-stih407-d3";
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clocks = <&clk_s_d3_quadfs 0>,
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<&clk_s_d3_quadfs 1>,
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<&clk_s_d3_quadfs 2>,
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<&clk_s_d3_quadfs 3>,
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<&clk_sysin>;
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};
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};
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};
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};