Merge tag 'i2c-for-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux

+5

Documentation/devicetree/bindings/eeprom/at24.yaml

··· 134 134 - const: atmel,24c64 135 135 - items: 136 136 - enum: 137 + - giantec,gt24p128f 137 138 - renesas,r1ex24128 138 139 - samsung,s524ad0xd1 139 140 - const: atmel,24c128 141 + - items: 142 + - enum: 143 + - puya,p24c256c 144 + - const: atmel,24c256 140 145 - items: 141 146 - const: microchip,24aa025e48 142 147 - items:

+1

Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml

··· 25 25 - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420 26 26 - samsung,exynos5260-hsi2c # Exynos5260 27 27 - samsung,exynos7-hsi2c # Exynos7 28 + - samsung,exynos8895-hsi2c 28 29 - samsung,exynosautov9-hsi2c 29 30 - items: 30 31 - enum:

+2

Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml

··· 34 34 - qcom,sm8450-cci 35 35 - qcom,sm8550-cci 36 36 - qcom,sm8650-cci 37 + - qcom,x1e80100-cci 37 38 - const: qcom,msm8996-cci # CCI v2 38 39 39 40 "#address-cells": ··· 225 224 enum: 226 225 - qcom,sm8550-cci 227 226 - qcom,sm8650-cci 227 + - qcom,x1e80100-cci 228 228 then: 229 229 properties: 230 230 clocks:

+4 -1

Documentation/devicetree/bindings/i2c/renesas,riic.yaml

··· 26 26 - const: renesas,riic-rz # RZ/A or RZ/G2L 27 27 28 28 - items: 29 - - const: renesas,riic-r9a08g045 # RZ/G3S 29 + - enum: 30 + - renesas,riic-r9a08g045 # RZ/G3S 31 + - renesas,riic-r9a09g047 # RZ/G3E 30 32 - const: renesas,riic-r9a09g057 # RZ/V2H(P) 31 33 32 34 - const: renesas,riic-r9a09g057 # RZ/V2H(P) ··· 91 89 - renesas,riic-r9a07g043 92 90 - renesas,riic-r9a07g044 93 91 - renesas,riic-r9a07g054 92 + - renesas,riic-r9a09g057 94 93 then: 95 94 required: 96 95 - resets

+2

Documentation/devicetree/bindings/vendor-prefixes.yaml

··· 1204 1204 description: PulsedLight, Inc 1205 1205 "^purism,.*": 1206 1206 description: Purism, SPC 1207 + "^puya,.*": 1208 + description: Puya Semiconductor (Shanghai) Co., Ltd. 1207 1209 "^qca,.*": 1208 1210 description: Qualcomm Atheros, Inc. 1209 1211 "^qcom,.*":

+2 -2

drivers/i2c/busses/Kconfig

··· 503 503 tristate "BRCM Settop/DSL I2C controller" 504 504 depends on ARCH_BCM2835 || ARCH_BCMBCA || ARCH_BRCMSTB || \ 505 505 BMIPS_GENERIC || COMPILE_TEST 506 - default y 506 + default ARCH_BCM2835 || ARCH_BCMBCA || ARCH_BRCMSTB || BMIPS_GENERIC 507 507 help 508 508 If you say yes to this option, support will be included for the 509 509 I2C interface on the Broadcom Settop/DSL SoCs. ··· 910 910 911 911 config I2C_NOMADIK 912 912 tristate "ST-Ericsson Nomadik/Ux500 I2C Controller" 913 - depends on ARM_AMBA 913 + depends on ARM_AMBA || COMPILE_TEST 914 914 help 915 915 If you say yes to this option, support will be included for the 916 916 I2C interface from ST-Ericsson's Nomadik and Ux500 architectures,

+2 -2

drivers/i2c/busses/i2c-amd756.c

··· 211 211 SMB_HOST_ADDRESS); 212 212 outb_p(command, SMB_HOST_COMMAND); 213 213 if (read_write == I2C_SMBUS_WRITE) 214 - outw_p(data->word, SMB_HOST_DATA); /* TODO: endian???? */ 214 + outw_p(data->word, SMB_HOST_DATA); 215 215 size = AMD756_WORD_DATA; 216 216 break; 217 217 case I2C_SMBUS_BLOCK_DATA: ··· 256 256 data->byte = inw_p(SMB_HOST_DATA); 257 257 break; 258 258 case AMD756_WORD_DATA: 259 - data->word = inw_p(SMB_HOST_DATA); /* TODO: endian???? */ 259 + data->word = inw_p(SMB_HOST_DATA); 260 260 break; 261 261 case AMD756_BLOCK_DATA: 262 262 data->block[0] = inw_p(SMB_HOST_DATA) & 0x3f;

+32 -78

drivers/i2c/busses/i2c-davinci.c

··· 11 11 * 12 12 * ---------------------------------------------------------------------------- 13 13 */ 14 + 15 + #include <linux/clk.h> 16 + #include <linux/cpufreq.h> 17 + #include <linux/delay.h> 18 + #include <linux/err.h> 19 + #include <linux/errno.h> 20 + #include <linux/gpio/consumer.h> 21 + #include <linux/i2c.h> 22 + #include <linux/interrupt.h> 23 + #include <linux/io.h> 14 24 #include <linux/kernel.h> 15 25 #include <linux/module.h> 16 - #include <linux/delay.h> 17 - #include <linux/i2c.h> 18 - #include <linux/clk.h> 19 - #include <linux/errno.h> 20 - #include <linux/sched.h> 21 - #include <linux/err.h> 22 - #include <linux/interrupt.h> 23 26 #include <linux/platform_device.h> 24 - #include <linux/io.h> 25 - #include <linux/slab.h> 26 - #include <linux/cpufreq.h> 27 - #include <linux/gpio/consumer.h> 28 - #include <linux/of.h> 29 - #include <linux/platform_data/i2c-davinci.h> 30 27 #include <linux/pm_runtime.h> 28 + #include <linux/property.h> 29 + #include <linux/sched.h> 30 + #include <linux/slab.h> 31 31 32 32 /* ----- global defines ----------------------------------------------- */ 33 33 ··· 117 117 /* timeout for pm runtime autosuspend */ 118 118 #define DAVINCI_I2C_PM_TIMEOUT 1000 /* ms */ 119 119 120 + #define DAVINCI_I2C_DEFAULT_BUS_FREQ 100 121 + 120 122 struct davinci_i2c_dev { 121 123 struct device *dev; 122 124 void __iomem *base; ··· 134 132 #ifdef CONFIG_CPU_FREQ 135 133 struct notifier_block freq_transition; 136 134 #endif 137 - struct davinci_i2c_platform_data *pdata; 138 - }; 139 - 140 - /* default platform data to use if not supplied in the platform_device */ 141 - static struct davinci_i2c_platform_data davinci_i2c_platform_data_default = { 142 - .bus_freq = 100, 143 - .bus_delay = 0, 135 + /* standard bus frequency (kHz) */ 136 + unsigned int bus_freq; 137 + /* Chip has a ICPFUNC register */ 138 + bool has_pfunc; 144 139 }; 145 140 146 141 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev, ··· 167 168 168 169 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev) 169 170 { 170 - struct davinci_i2c_platform_data *pdata = dev->pdata; 171 171 u16 psc; 172 172 u32 clk; 173 173 u32 d; 174 174 u32 clkh; 175 175 u32 clkl; 176 176 u32 input_clock = clk_get_rate(dev->clk); 177 - struct device_node *of_node = dev->dev->of_node; 178 177 179 178 /* NOTE: I2C Clock divider programming info 180 179 * As per I2C specs the following formulas provide prescaler ··· 206 209 psc++; /* better to run under spec than over */ 207 210 d = (psc >= 2) ? 5 : 7 - psc; 208 211 209 - if (of_node && of_device_is_compatible(of_node, "ti,keystone-i2c")) 212 + if (device_is_compatible(dev->dev, "ti,keystone-i2c")) 210 213 d = 6; 211 214 212 - clk = ((input_clock / (psc + 1)) / (pdata->bus_freq * 1000)); 215 + clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)); 213 216 /* Avoid driving the bus too fast because of rounding errors above */ 214 - if (input_clock / (psc + 1) / clk > pdata->bus_freq * 1000) 217 + if (input_clock / (psc + 1) / clk > dev->bus_freq * 1000) 215 218 clk++; 216 219 /* 217 220 * According to I2C-BUS Spec 2.1, in FAST-MODE LOW period should be at 218 221 * least 1.3uS, which is not the case with 50% duty cycle. Driving HIGH 219 222 * to LOW ratio as 1 to 2 is more safe. 220 223 */ 221 - if (pdata->bus_freq > 100) 224 + if (dev->bus_freq > 100) 222 225 clkl = (clk << 1) / 3; 223 226 else 224 227 clkl = (clk >> 1); ··· 252 255 */ 253 256 static int i2c_davinci_init(struct davinci_i2c_dev *dev) 254 257 { 255 - struct davinci_i2c_platform_data *pdata = dev->pdata; 256 - 257 258 /* put I2C into reset */ 258 259 davinci_i2c_reset_ctrl(dev, 0); 259 260 ··· 269 274 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG)); 270 275 dev_dbg(dev->dev, "CLKH = %d\n", 271 276 davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG)); 272 - dev_dbg(dev->dev, "bus_freq = %dkHz, bus_delay = %d\n", 273 - pdata->bus_freq, pdata->bus_delay); 277 + dev_dbg(dev->dev, "bus_freq = %dkHz\n", dev->bus_freq); 274 278 275 279 276 280 /* Take the I2C module out of reset: */ ··· 302 308 303 309 i2c_davinci_init(dev); 304 310 } 305 - 306 - static struct i2c_bus_recovery_info davinci_i2c_gpio_recovery_info = { 307 - .recover_bus = i2c_generic_scl_recovery, 308 - .prepare_recovery = davinci_i2c_prepare_recovery, 309 - .unprepare_recovery = davinci_i2c_unprepare_recovery, 310 - }; 311 311 312 312 static void davinci_i2c_set_scl(struct i2c_adapter *adap, int val) 313 313 { ··· 402 414 i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop) 403 415 { 404 416 struct davinci_i2c_dev *dev = i2c_get_adapdata(adap); 405 - struct davinci_i2c_platform_data *pdata = dev->pdata; 406 417 u32 flag; 407 418 u16 w; 408 419 unsigned long time_left; ··· 410 423 dev_warn(dev->dev, "transfer to own address aborted\n"); 411 424 return -EADDRNOTAVAIL; 412 425 } 413 - 414 - /* Introduce a delay, required for some boards (e.g Davinci EVM) */ 415 - if (pdata->bus_delay) 416 - udelay(pdata->bus_delay); 417 426 418 427 /* set the target address */ 419 428 davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr); ··· 741 758 { 742 759 struct davinci_i2c_dev *dev; 743 760 struct i2c_adapter *adap; 744 - struct i2c_bus_recovery_info *rinfo; 745 761 int r, irq; 762 + u32 prop; 746 763 747 764 irq = platform_get_irq(pdev, 0); 748 765 if (irq < 0) ··· 756 773 757 774 dev->dev = &pdev->dev; 758 775 dev->irq = irq; 759 - dev->pdata = dev_get_platdata(&pdev->dev); 760 776 platform_set_drvdata(pdev, dev); 761 777 762 - if (!dev->pdata && pdev->dev.of_node) { 763 - u32 prop; 778 + r = device_property_read_u32(&pdev->dev, "clock-frequency", &prop); 779 + if (r) 780 + prop = DAVINCI_I2C_DEFAULT_BUS_FREQ; 764 781 765 - dev->pdata = devm_kzalloc(&pdev->dev, 766 - sizeof(struct davinci_i2c_platform_data), GFP_KERNEL); 767 - if (!dev->pdata) 768 - return -ENOMEM; 782 + dev->bus_freq = prop / 1000; 769 783 770 - memcpy(dev->pdata, &davinci_i2c_platform_data_default, 771 - sizeof(struct davinci_i2c_platform_data)); 772 - if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency", 773 - &prop)) 774 - dev->pdata->bus_freq = prop / 1000; 775 - 776 - dev->pdata->has_pfunc = 777 - of_property_read_bool(pdev->dev.of_node, 778 - "ti,has-pfunc"); 779 - } else if (!dev->pdata) { 780 - dev->pdata = &davinci_i2c_platform_data_default; 781 - } 784 + dev->has_pfunc = device_property_present(&pdev->dev, "ti,has-pfunc"); 782 785 783 786 dev->clk = devm_clk_get(&pdev->dev, NULL); 784 787 if (IS_ERR(dev->clk)) ··· 810 841 adap->algo = &i2c_davinci_algo; 811 842 adap->dev.parent = &pdev->dev; 812 843 adap->timeout = DAVINCI_I2C_TIMEOUT; 813 - adap->dev.of_node = pdev->dev.of_node; 844 + adap->dev.of_node = dev_of_node(&pdev->dev); 814 845 815 - if (dev->pdata->has_pfunc) 846 + if (dev->has_pfunc) 816 847 adap->bus_recovery_info = &davinci_i2c_scl_recovery_info; 817 - else if (dev->pdata->gpio_recovery) { 818 - rinfo = &davinci_i2c_gpio_recovery_info; 819 - adap->bus_recovery_info = rinfo; 820 - rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", 821 - GPIOD_OUT_HIGH_OPEN_DRAIN); 822 - if (IS_ERR(rinfo->scl_gpiod)) { 823 - r = PTR_ERR(rinfo->scl_gpiod); 824 - goto err_unuse_clocks; 825 - } 826 - rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 827 - if (IS_ERR(rinfo->sda_gpiod)) { 828 - r = PTR_ERR(rinfo->sda_gpiod); 829 - goto err_unuse_clocks; 830 - } 831 - } 832 848 833 849 adap->nr = pdev->id; 834 850 r = i2c_add_numbered_adapter(adap);

+3 -2

drivers/i2c/busses/i2c-designware-common.c

··· 8 8 * Copyright (C) 2007 MontaVista Software Inc. 9 9 * Copyright (C) 2009 Provigent Ltd. 10 10 */ 11 + 12 + #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON" 13 + 11 14 #include <linux/acpi.h> 12 15 #include <linux/clk.h> 13 16 #include <linux/delay.h> ··· 31 28 #include <linux/swab.h> 32 29 #include <linux/types.h> 33 30 #include <linux/units.h> 34 - 35 - #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW_COMMON" 36 31 37 32 #include "i2c-designware-core.h" 38 33

+3 -2

drivers/i2c/busses/i2c-designware-master.c

··· 8 8 * Copyright (C) 2007 MontaVista Software Inc. 9 9 * Copyright (C) 2009 Provigent Ltd. 10 10 */ 11 + 12 + #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW" 13 + 11 14 #include <linux/delay.h> 12 15 #include <linux/err.h> 13 16 #include <linux/errno.h> ··· 24 21 #include <linux/pm_runtime.h> 25 22 #include <linux/regmap.h> 26 23 #include <linux/reset.h> 27 - 28 - #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW" 29 24 30 25 #include "i2c-designware-core.h" 31 26

+3 -2

drivers/i2c/busses/i2c-designware-slave.c

··· 6 6 * 7 7 * Copyright (C) 2016 Synopsys Inc. 8 8 */ 9 + 10 + #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW" 11 + 9 12 #include <linux/delay.h> 10 13 #include <linux/err.h> 11 14 #include <linux/errno.h> ··· 18 15 #include <linux/module.h> 19 16 #include <linux/pm_runtime.h> 20 17 #include <linux/regmap.h> 21 - 22 - #define DEFAULT_SYMBOL_NAMESPACE "I2C_DW" 23 18 24 19 #include "i2c-designware-core.h" 25 20

+31 -4

drivers/i2c/busses/i2c-exynos5.c

··· 168 168 I2C_TYPE_EXYNOS5, 169 169 I2C_TYPE_EXYNOS7, 170 170 I2C_TYPE_EXYNOSAUTOV9, 171 + I2C_TYPE_EXYNOS8895, 171 172 }; 172 173 173 174 struct exynos5_i2c { ··· 241 240 .hw = I2C_TYPE_EXYNOSAUTOV9, 242 241 }; 243 242 243 + static const struct exynos_hsi2c_variant exynos8895_hsi2c_data = { 244 + .fifo_depth = 64, 245 + .hw = I2C_TYPE_EXYNOS8895, 246 + }; 247 + 244 248 static const struct of_device_id exynos5_i2c_match[] = { 245 249 { 246 250 .compatible = "samsung,exynos5-hsi2c", ··· 262 256 }, { 263 257 .compatible = "samsung,exynosautov9-hsi2c", 264 258 .data = &exynosautov9_hsi2c_data 259 + }, { 260 + .compatible = "samsung,exynos8895-hsi2c", 261 + .data = &exynos8895_hsi2c_data 265 262 }, {}, 266 263 }; 267 264 MODULE_DEVICE_TABLE(of, exynos5_i2c_match); ··· 340 331 * clk_cycle := TSCLK_L + TSCLK_H 341 332 * temp := (CLK_DIV + 1) * (clk_cycle + 2) 342 333 * 334 + * In case of HSI2C controllers in Exynos8895 335 + * FPCLK / FI2C = 336 + * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 337 + * 2 * ((FLT_CYCLE + 3) - (FLT_CYCLE + 3) % (CLK_DIV + 1)) 338 + * 339 + * clk_cycle := TSCLK_L + TSCLK_H 340 + * temp := (FPCLK / FI2C) - (FLT_CYCLE + 3) * 2 341 + * 343 342 * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510 344 343 * 345 344 * To split SCL clock into low, high periods appropriately, one ··· 369 352 * 370 353 */ 371 354 t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7; 372 - temp = clkin / op_clk - 8 - t_ftl_cycle; 373 - if (i2c->variant->hw != I2C_TYPE_EXYNOS7) 374 - temp -= t_ftl_cycle; 355 + if (i2c->variant->hw == I2C_TYPE_EXYNOS8895) 356 + temp = clkin / op_clk - (t_ftl_cycle + 3) * 2; 357 + else if (i2c->variant->hw == I2C_TYPE_EXYNOS7) 358 + temp = clkin / op_clk - 8 - t_ftl_cycle; 359 + else 360 + temp = clkin / op_clk - 8 - (t_ftl_cycle * 2); 375 361 div = temp / 512; 376 - clk_cycle = temp / (div + 1) - 2; 362 + 363 + if (i2c->variant->hw == I2C_TYPE_EXYNOS8895) 364 + clk_cycle = (temp + ((t_ftl_cycle + 3) % (div + 1)) * 2) / 365 + (div + 1) - 2; 366 + else 367 + clk_cycle = temp / (div + 1) - 2; 377 368 if (temp < 4 || div >= 256 || clk_cycle < 2) { 378 369 dev_err(i2c->dev, "%s clock set-up failed\n", 379 370 hs_timings ? "HS" : "FS"); ··· 515 490 /* handle interrupt related to the transfer status */ 516 491 switch (i2c->variant->hw) { 517 492 case I2C_TYPE_EXYNOSAUTOV9: 493 + fallthrough; 494 + case I2C_TYPE_EXYNOS8895: 518 495 fallthrough; 519 496 case I2C_TYPE_EXYNOS7: 520 497 if (int_status & HSI2C_INT_TRANS_DONE) {

+6 -2

drivers/i2c/busses/i2c-i801.c

··· 1252 1252 */ 1253 1253 { "Latitude 5480", 0x29 }, 1254 1254 { "Precision 3540", 0x29 }, 1255 + { "Precision M6800", 0x29 }, 1255 1256 { "Vostro V131", 0x1d }, 1256 1257 { "Vostro 5568", 0x29 }, 1257 1258 { "XPS 15 7590", 0x29 }, ··· 1683 1682 if (!(priv->features & FEATURE_BLOCK_BUFFER)) 1684 1683 priv->features &= ~FEATURE_BLOCK_PROC; 1685 1684 1686 - err = pcim_enable_device(dev); 1685 + /* 1686 + * Do not call pcim_enable_device(), because the device has to remain 1687 + * enabled on driver detach. See i801_remove() for the reasoning. 1688 + */ 1689 + err = pci_enable_device(dev); 1687 1690 if (err) { 1688 1691 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1689 1692 err); 1690 1693 return err; 1691 1694 } 1692 - pcim_pin_device(dev); 1693 1695 1694 1696 /* Determine the address of the SMBus area */ 1695 1697 priv->smba = pci_resource_start(dev, SMBBAR);

+799 -12

drivers/i2c/busses/i2c-imx-lpi2c.c

··· 8 8 #include <linux/clk.h> 9 9 #include <linux/completion.h> 10 10 #include <linux/delay.h> 11 + #include <linux/dma-mapping.h> 12 + #include <linux/dmaengine.h> 11 13 #include <linux/err.h> 12 14 #include <linux/errno.h> 13 15 #include <linux/i2c.h> ··· 31 29 #define LPI2C_MCR 0x10 /* i2c contrl register */ 32 30 #define LPI2C_MSR 0x14 /* i2c status register */ 33 31 #define LPI2C_MIER 0x18 /* i2c interrupt enable */ 32 + #define LPI2C_MDER 0x1C /* i2c DMA enable */ 34 33 #define LPI2C_MCFGR0 0x20 /* i2c master configuration */ 35 34 #define LPI2C_MCFGR1 0x24 /* i2c master configuration */ 36 35 #define LPI2C_MCFGR2 0x28 /* i2c master configuration */ ··· 42 39 #define LPI2C_MFSR 0x5C /* i2c master FIFO status */ 43 40 #define LPI2C_MTDR 0x60 /* i2c master TX data register */ 44 41 #define LPI2C_MRDR 0x70 /* i2c master RX data register */ 42 + 43 + #define LPI2C_SCR 0x110 /* i2c target control register */ 44 + #define LPI2C_SSR 0x114 /* i2c target status register */ 45 + #define LPI2C_SIER 0x118 /* i2c target interrupt enable */ 46 + #define LPI2C_SDER 0x11C /* i2c target DMA enable */ 47 + #define LPI2C_SCFGR0 0x120 /* i2c target configuration */ 48 + #define LPI2C_SCFGR1 0x124 /* i2c target configuration */ 49 + #define LPI2C_SCFGR2 0x128 /* i2c target configuration */ 50 + #define LPI2C_SAMR 0x140 /* i2c target address match */ 51 + #define LPI2C_SASR 0x150 /* i2c target address status */ 52 + #define LPI2C_STAR 0x154 /* i2c target transmit ACK */ 53 + #define LPI2C_STDR 0x160 /* i2c target transmit data */ 54 + #define LPI2C_SRDR 0x170 /* i2c target receive data */ 55 + #define LPI2C_SRDROR 0x178 /* i2c target receive data read only */ 45 56 46 57 /* i2c command */ 47 58 #define TRAN_DATA 0X00 ··· 87 70 #define MCFGR1_AUTOSTOP BIT(8) 88 71 #define MCFGR1_IGNACK BIT(9) 89 72 #define MRDR_RXEMPTY BIT(14) 73 + #define MDER_TDDE BIT(0) 74 + #define MDER_RDDE BIT(1) 75 + 76 + #define SCR_SEN BIT(0) 77 + #define SCR_RST BIT(1) 78 + #define SCR_FILTEN BIT(4) 79 + #define SCR_RTF BIT(8) 80 + #define SCR_RRF BIT(9) 81 + #define SSR_TDF BIT(0) 82 + #define SSR_RDF BIT(1) 83 + #define SSR_AVF BIT(2) 84 + #define SSR_TAF BIT(3) 85 + #define SSR_RSF BIT(8) 86 + #define SSR_SDF BIT(9) 87 + #define SSR_BEF BIT(10) 88 + #define SSR_FEF BIT(11) 89 + #define SSR_SBF BIT(24) 90 + #define SSR_BBF BIT(25) 91 + #define SSR_CLEAR_BITS (SSR_RSF | SSR_SDF | SSR_BEF | SSR_FEF) 92 + #define SIER_TDIE BIT(0) 93 + #define SIER_RDIE BIT(1) 94 + #define SIER_AVIE BIT(2) 95 + #define SIER_TAIE BIT(3) 96 + #define SIER_RSIE BIT(8) 97 + #define SIER_SDIE BIT(9) 98 + #define SIER_BEIE BIT(10) 99 + #define SIER_FEIE BIT(11) 100 + #define SIER_AM0F BIT(12) 101 + #define SCFGR1_RXSTALL BIT(1) 102 + #define SCFGR1_TXDSTALL BIT(2) 103 + #define SCFGR2_FILTSDA_SHIFT 24 104 + #define SCFGR2_FILTSCL_SHIFT 16 105 + #define SCFGR2_CLKHOLD(x) (x) 106 + #define SCFGR2_FILTSDA(x) ((x) << SCFGR2_FILTSDA_SHIFT) 107 + #define SCFGR2_FILTSCL(x) ((x) << SCFGR2_FILTSCL_SHIFT) 108 + #define SASR_READ_REQ 0x1 109 + #define SLAVE_INT_FLAG (SIER_TDIE | SIER_RDIE | SIER_AVIE | \ 110 + SIER_SDIE | SIER_BEIE) 90 111 91 112 #define I2C_CLK_RATIO 2 92 113 #define CHUNK_DATA 256 93 114 94 115 #define I2C_PM_TIMEOUT 10 /* ms */ 116 + #define I2C_DMA_THRESHOLD 8 /* bytes */ 95 117 96 118 enum lpi2c_imx_mode { 97 119 STANDARD, /* 100+Kbps */ ··· 145 89 TWO_PIN_OO, 146 90 TWO_PIN_PP, 147 91 FOUR_PIN_PP, 92 + }; 93 + 94 + struct lpi2c_imx_dma { 95 + bool using_pio_mode; 96 + u8 rx_cmd_buf_len; 97 + u8 *dma_buf; 98 + u16 *rx_cmd_buf; 99 + unsigned int dma_len; 100 + unsigned int tx_burst_num; 101 + unsigned int rx_burst_num; 102 + unsigned long dma_msg_flag; 103 + resource_size_t phy_addr; 104 + dma_addr_t dma_tx_addr; 105 + dma_addr_t dma_addr; 106 + enum dma_data_direction dma_data_dir; 107 + enum dma_transfer_direction dma_transfer_dir; 108 + struct dma_chan *chan_tx; 109 + struct dma_chan *chan_rx; 148 110 }; 149 111 150 112 struct lpi2c_imx_struct { ··· 182 108 unsigned int rxfifosize; 183 109 enum lpi2c_imx_mode mode; 184 110 struct i2c_bus_recovery_info rinfo; 111 + bool can_use_dma; 112 + struct lpi2c_imx_dma *dma; 113 + struct i2c_client *target; 185 114 }; 186 115 187 116 static void lpi2c_imx_intctrl(struct lpi2c_imx_struct *lpi2c_imx, ··· 382 305 return 0; 383 306 } 384 307 385 - static int lpi2c_imx_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) 308 + static int lpi2c_imx_pio_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) 386 309 { 387 310 unsigned long time_left; 388 311 ··· 528 451 lpi2c_imx_intctrl(lpi2c_imx, MIER_RDIE | MIER_NDIE); 529 452 } 530 453 454 + static bool is_use_dma(struct lpi2c_imx_struct *lpi2c_imx, struct i2c_msg *msg) 455 + { 456 + if (!lpi2c_imx->can_use_dma) 457 + return false; 458 + 459 + /* 460 + * When the length of data is less than I2C_DMA_THRESHOLD, 461 + * cpu mode is used directly to avoid low performance. 462 + */ 463 + return !(msg->len < I2C_DMA_THRESHOLD); 464 + } 465 + 466 + static int lpi2c_imx_pio_xfer(struct lpi2c_imx_struct *lpi2c_imx, 467 + struct i2c_msg *msg) 468 + { 469 + reinit_completion(&lpi2c_imx->complete); 470 + 471 + if (msg->flags & I2C_M_RD) 472 + lpi2c_imx_read(lpi2c_imx, msg); 473 + else 474 + lpi2c_imx_write(lpi2c_imx, msg); 475 + 476 + return lpi2c_imx_pio_msg_complete(lpi2c_imx); 477 + } 478 + 479 + static int lpi2c_imx_dma_timeout_calculate(struct lpi2c_imx_struct *lpi2c_imx) 480 + { 481 + unsigned long time = 0; 482 + 483 + time = 8 * lpi2c_imx->dma->dma_len * 1000 / lpi2c_imx->bitrate; 484 + 485 + /* Add extra second for scheduler related activities */ 486 + time += 1; 487 + 488 + /* Double calculated time */ 489 + return msecs_to_jiffies(time * MSEC_PER_SEC); 490 + } 491 + 492 + static int lpi2c_imx_alloc_rx_cmd_buf(struct lpi2c_imx_struct *lpi2c_imx) 493 + { 494 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 495 + u16 rx_remain = dma->dma_len; 496 + int cmd_num; 497 + u16 temp; 498 + 499 + /* 500 + * Calculate the number of rx command words via the DMA TX channel 501 + * writing into command register based on the i2c msg len, and build 502 + * the rx command words buffer. 503 + */ 504 + cmd_num = DIV_ROUND_UP(rx_remain, CHUNK_DATA); 505 + dma->rx_cmd_buf = kcalloc(cmd_num, sizeof(u16), GFP_KERNEL); 506 + dma->rx_cmd_buf_len = cmd_num * sizeof(u16); 507 + 508 + if (!dma->rx_cmd_buf) { 509 + dev_err(&lpi2c_imx->adapter.dev, "Alloc RX cmd buffer failed\n"); 510 + return -ENOMEM; 511 + } 512 + 513 + for (int i = 0; i < cmd_num ; i++) { 514 + temp = rx_remain > CHUNK_DATA ? CHUNK_DATA - 1 : rx_remain - 1; 515 + temp |= (RECV_DATA << 8); 516 + rx_remain -= CHUNK_DATA; 517 + dma->rx_cmd_buf[i] = temp; 518 + } 519 + 520 + return 0; 521 + } 522 + 523 + static int lpi2c_imx_dma_msg_complete(struct lpi2c_imx_struct *lpi2c_imx) 524 + { 525 + unsigned long time_left, time; 526 + 527 + time = lpi2c_imx_dma_timeout_calculate(lpi2c_imx); 528 + time_left = wait_for_completion_timeout(&lpi2c_imx->complete, time); 529 + if (time_left == 0) { 530 + dev_err(&lpi2c_imx->adapter.dev, "I/O Error in DMA Data Transfer\n"); 531 + return -ETIMEDOUT; 532 + } 533 + 534 + return 0; 535 + } 536 + 537 + static void lpi2c_dma_unmap(struct lpi2c_imx_dma *dma) 538 + { 539 + struct dma_chan *chan = dma->dma_data_dir == DMA_FROM_DEVICE 540 + ? dma->chan_rx : dma->chan_tx; 541 + 542 + dma_unmap_single(chan->device->dev, dma->dma_addr, 543 + dma->dma_len, dma->dma_data_dir); 544 + 545 + dma->dma_data_dir = DMA_NONE; 546 + } 547 + 548 + static void lpi2c_cleanup_rx_cmd_dma(struct lpi2c_imx_dma *dma) 549 + { 550 + dmaengine_terminate_sync(dma->chan_tx); 551 + dma_unmap_single(dma->chan_tx->device->dev, dma->dma_tx_addr, 552 + dma->rx_cmd_buf_len, DMA_TO_DEVICE); 553 + } 554 + 555 + static void lpi2c_cleanup_dma(struct lpi2c_imx_dma *dma) 556 + { 557 + if (dma->dma_data_dir == DMA_FROM_DEVICE) 558 + dmaengine_terminate_sync(dma->chan_rx); 559 + else if (dma->dma_data_dir == DMA_TO_DEVICE) 560 + dmaengine_terminate_sync(dma->chan_tx); 561 + 562 + lpi2c_dma_unmap(dma); 563 + } 564 + 565 + static void lpi2c_dma_callback(void *data) 566 + { 567 + struct lpi2c_imx_struct *lpi2c_imx = (struct lpi2c_imx_struct *)data; 568 + 569 + complete(&lpi2c_imx->complete); 570 + } 571 + 572 + static int lpi2c_dma_rx_cmd_submit(struct lpi2c_imx_struct *lpi2c_imx) 573 + { 574 + struct dma_async_tx_descriptor *rx_cmd_desc; 575 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 576 + struct dma_chan *txchan = dma->chan_tx; 577 + dma_cookie_t cookie; 578 + 579 + dma->dma_tx_addr = dma_map_single(txchan->device->dev, 580 + dma->rx_cmd_buf, dma->rx_cmd_buf_len, 581 + DMA_TO_DEVICE); 582 + if (dma_mapping_error(txchan->device->dev, dma->dma_tx_addr)) { 583 + dev_err(&lpi2c_imx->adapter.dev, "DMA map failed, use pio\n"); 584 + return -EINVAL; 585 + } 586 + 587 + rx_cmd_desc = dmaengine_prep_slave_single(txchan, dma->dma_tx_addr, 588 + dma->rx_cmd_buf_len, DMA_MEM_TO_DEV, 589 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 590 + if (!rx_cmd_desc) { 591 + dev_err(&lpi2c_imx->adapter.dev, "DMA prep slave sg failed, use pio\n"); 592 + goto desc_prepare_err_exit; 593 + } 594 + 595 + cookie = dmaengine_submit(rx_cmd_desc); 596 + if (dma_submit_error(cookie)) { 597 + dev_err(&lpi2c_imx->adapter.dev, "submitting DMA failed, use pio\n"); 598 + goto submit_err_exit; 599 + } 600 + 601 + dma_async_issue_pending(txchan); 602 + 603 + return 0; 604 + 605 + desc_prepare_err_exit: 606 + dma_unmap_single(txchan->device->dev, dma->dma_tx_addr, 607 + dma->rx_cmd_buf_len, DMA_TO_DEVICE); 608 + return -EINVAL; 609 + 610 + submit_err_exit: 611 + dma_unmap_single(txchan->device->dev, dma->dma_tx_addr, 612 + dma->rx_cmd_buf_len, DMA_TO_DEVICE); 613 + dmaengine_desc_free(rx_cmd_desc); 614 + return -EINVAL; 615 + } 616 + 617 + static int lpi2c_dma_submit(struct lpi2c_imx_struct *lpi2c_imx) 618 + { 619 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 620 + struct dma_async_tx_descriptor *desc; 621 + struct dma_chan *chan; 622 + dma_cookie_t cookie; 623 + 624 + if (dma->dma_msg_flag & I2C_M_RD) { 625 + chan = dma->chan_rx; 626 + dma->dma_data_dir = DMA_FROM_DEVICE; 627 + dma->dma_transfer_dir = DMA_DEV_TO_MEM; 628 + } else { 629 + chan = dma->chan_tx; 630 + dma->dma_data_dir = DMA_TO_DEVICE; 631 + dma->dma_transfer_dir = DMA_MEM_TO_DEV; 632 + } 633 + 634 + dma->dma_addr = dma_map_single(chan->device->dev, 635 + dma->dma_buf, dma->dma_len, dma->dma_data_dir); 636 + if (dma_mapping_error(chan->device->dev, dma->dma_addr)) { 637 + dev_err(&lpi2c_imx->adapter.dev, "DMA map failed, use pio\n"); 638 + return -EINVAL; 639 + } 640 + 641 + desc = dmaengine_prep_slave_single(chan, dma->dma_addr, 642 + dma->dma_len, dma->dma_transfer_dir, 643 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 644 + if (!desc) { 645 + dev_err(&lpi2c_imx->adapter.dev, "DMA prep slave sg failed, use pio\n"); 646 + goto desc_prepare_err_exit; 647 + } 648 + 649 + reinit_completion(&lpi2c_imx->complete); 650 + desc->callback = lpi2c_dma_callback; 651 + desc->callback_param = lpi2c_imx; 652 + 653 + cookie = dmaengine_submit(desc); 654 + if (dma_submit_error(cookie)) { 655 + dev_err(&lpi2c_imx->adapter.dev, "submitting DMA failed, use pio\n"); 656 + goto submit_err_exit; 657 + } 658 + 659 + /* Can't switch to PIO mode when DMA have started transfer */ 660 + dma->using_pio_mode = false; 661 + 662 + dma_async_issue_pending(chan); 663 + 664 + return 0; 665 + 666 + desc_prepare_err_exit: 667 + lpi2c_dma_unmap(dma); 668 + return -EINVAL; 669 + 670 + submit_err_exit: 671 + lpi2c_dma_unmap(dma); 672 + dmaengine_desc_free(desc); 673 + return -EINVAL; 674 + } 675 + 676 + static int lpi2c_imx_find_max_burst_num(unsigned int fifosize, unsigned int len) 677 + { 678 + unsigned int i; 679 + 680 + for (i = fifosize / 2; i > 0; i--) 681 + if (!(len % i)) 682 + break; 683 + 684 + return i; 685 + } 686 + 687 + /* 688 + * For a highest DMA efficiency, tx/rx burst number should be calculated according 689 + * to the FIFO depth. 690 + */ 691 + static void lpi2c_imx_dma_burst_num_calculate(struct lpi2c_imx_struct *lpi2c_imx) 692 + { 693 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 694 + unsigned int cmd_num; 695 + 696 + if (dma->dma_msg_flag & I2C_M_RD) { 697 + /* 698 + * One RX cmd word can trigger DMA receive no more than 256 bytes. 699 + * The number of RX cmd words should be calculated based on the data 700 + * length. 701 + */ 702 + cmd_num = DIV_ROUND_UP(dma->dma_len, CHUNK_DATA); 703 + dma->tx_burst_num = lpi2c_imx_find_max_burst_num(lpi2c_imx->txfifosize, 704 + cmd_num); 705 + dma->rx_burst_num = lpi2c_imx_find_max_burst_num(lpi2c_imx->rxfifosize, 706 + dma->dma_len); 707 + } else { 708 + dma->tx_burst_num = lpi2c_imx_find_max_burst_num(lpi2c_imx->txfifosize, 709 + dma->dma_len); 710 + } 711 + } 712 + 713 + static int lpi2c_dma_config(struct lpi2c_imx_struct *lpi2c_imx) 714 + { 715 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 716 + struct dma_slave_config rx = {}, tx = {}; 717 + int ret; 718 + 719 + lpi2c_imx_dma_burst_num_calculate(lpi2c_imx); 720 + 721 + if (dma->dma_msg_flag & I2C_M_RD) { 722 + tx.dst_addr = dma->phy_addr + LPI2C_MTDR; 723 + tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 724 + tx.dst_maxburst = dma->tx_burst_num; 725 + tx.direction = DMA_MEM_TO_DEV; 726 + ret = dmaengine_slave_config(dma->chan_tx, &tx); 727 + if (ret < 0) 728 + return ret; 729 + 730 + rx.src_addr = dma->phy_addr + LPI2C_MRDR; 731 + rx.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 732 + rx.src_maxburst = dma->rx_burst_num; 733 + rx.direction = DMA_DEV_TO_MEM; 734 + ret = dmaengine_slave_config(dma->chan_rx, &rx); 735 + if (ret < 0) 736 + return ret; 737 + } else { 738 + tx.dst_addr = dma->phy_addr + LPI2C_MTDR; 739 + tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 740 + tx.dst_maxburst = dma->tx_burst_num; 741 + tx.direction = DMA_MEM_TO_DEV; 742 + ret = dmaengine_slave_config(dma->chan_tx, &tx); 743 + if (ret < 0) 744 + return ret; 745 + } 746 + 747 + return 0; 748 + } 749 + 750 + static void lpi2c_dma_enable(struct lpi2c_imx_struct *lpi2c_imx) 751 + { 752 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 753 + /* 754 + * TX interrupt will be triggered when the number of words in 755 + * the transmit FIFO is equal or less than TX watermark. 756 + * RX interrupt will be triggered when the number of words in 757 + * the receive FIFO is greater than RX watermark. 758 + * In order to trigger the DMA interrupt, TX watermark should be 759 + * set equal to the DMA TX burst number but RX watermark should 760 + * be set less than the DMA RX burst number. 761 + */ 762 + if (dma->dma_msg_flag & I2C_M_RD) { 763 + /* Set I2C TX/RX watermark */ 764 + writel(dma->tx_burst_num | (dma->rx_burst_num - 1) << 16, 765 + lpi2c_imx->base + LPI2C_MFCR); 766 + /* Enable I2C DMA TX/RX function */ 767 + writel(MDER_TDDE | MDER_RDDE, lpi2c_imx->base + LPI2C_MDER); 768 + } else { 769 + /* Set I2C TX watermark */ 770 + writel(dma->tx_burst_num, lpi2c_imx->base + LPI2C_MFCR); 771 + /* Enable I2C DMA TX function */ 772 + writel(MDER_TDDE, lpi2c_imx->base + LPI2C_MDER); 773 + } 774 + 775 + /* Enable NACK detected */ 776 + lpi2c_imx_intctrl(lpi2c_imx, MIER_NDIE); 777 + }; 778 + 779 + /* 780 + * When lpi2c is in TX DMA mode we can use one DMA TX channel to write 781 + * data word into TXFIFO, but in RX DMA mode it is different. 782 + * 783 + * The LPI2C MTDR register is a command data and transmit data register. 784 + * Bits 8-10 are the command data field and Bits 0-7 are the transmit 785 + * data field. When the LPI2C master needs to read data, the number of 786 + * bytes to read should be set in the command field and RECV_DATA should 787 + * be set into the command data field to receive (DATA[7:0] + 1) bytes. 788 + * The recv data command word is made of RECV_DATA in the command data 789 + * field and the number of bytes to read in transmit data field. When the 790 + * length of data to be read exceeds 256 bytes, recv data command word 791 + * needs to be written to TXFIFO multiple times. 792 + * 793 + * So when in RX DMA mode, the TX channel also must to be configured to 794 + * send RX command words and the RX command word must be set in advance 795 + * before transmitting. 796 + */ 797 + static int lpi2c_imx_dma_xfer(struct lpi2c_imx_struct *lpi2c_imx, 798 + struct i2c_msg *msg) 799 + { 800 + struct lpi2c_imx_dma *dma = lpi2c_imx->dma; 801 + int ret; 802 + 803 + /* When DMA mode fails before transferring, CPU mode can be used. */ 804 + dma->using_pio_mode = true; 805 + 806 + dma->dma_len = msg->len; 807 + dma->dma_msg_flag = msg->flags; 808 + dma->dma_buf = i2c_get_dma_safe_msg_buf(msg, I2C_DMA_THRESHOLD); 809 + if (!dma->dma_buf) 810 + return -ENOMEM; 811 + 812 + ret = lpi2c_dma_config(lpi2c_imx); 813 + if (ret) { 814 + dev_err(&lpi2c_imx->adapter.dev, "Failed to configure DMA (%d)\n", ret); 815 + goto disable_dma; 816 + } 817 + 818 + lpi2c_dma_enable(lpi2c_imx); 819 + 820 + ret = lpi2c_dma_submit(lpi2c_imx); 821 + if (ret) { 822 + dev_err(&lpi2c_imx->adapter.dev, "DMA submission failed (%d)\n", ret); 823 + goto disable_dma; 824 + } 825 + 826 + if (dma->dma_msg_flag & I2C_M_RD) { 827 + ret = lpi2c_imx_alloc_rx_cmd_buf(lpi2c_imx); 828 + if (ret) 829 + goto disable_cleanup_data_dma; 830 + 831 + ret = lpi2c_dma_rx_cmd_submit(lpi2c_imx); 832 + if (ret) 833 + goto disable_cleanup_data_dma; 834 + } 835 + 836 + ret = lpi2c_imx_dma_msg_complete(lpi2c_imx); 837 + if (ret) 838 + goto disable_cleanup_all_dma; 839 + 840 + /* When encountering NACK in transfer, clean up all DMA transfers */ 841 + if ((readl(lpi2c_imx->base + LPI2C_MSR) & MSR_NDF) && !ret) { 842 + ret = -EIO; 843 + goto disable_cleanup_all_dma; 844 + } 845 + 846 + if (dma->dma_msg_flag & I2C_M_RD) 847 + dma_unmap_single(dma->chan_tx->device->dev, dma->dma_tx_addr, 848 + dma->rx_cmd_buf_len, DMA_TO_DEVICE); 849 + lpi2c_dma_unmap(dma); 850 + 851 + goto disable_dma; 852 + 853 + disable_cleanup_all_dma: 854 + if (dma->dma_msg_flag & I2C_M_RD) 855 + lpi2c_cleanup_rx_cmd_dma(dma); 856 + disable_cleanup_data_dma: 857 + lpi2c_cleanup_dma(dma); 858 + disable_dma: 859 + /* Disable I2C DMA function */ 860 + writel(0, lpi2c_imx->base + LPI2C_MDER); 861 + 862 + if (dma->dma_msg_flag & I2C_M_RD) 863 + kfree(dma->rx_cmd_buf); 864 + 865 + if (ret) 866 + i2c_put_dma_safe_msg_buf(dma->dma_buf, msg, false); 867 + else 868 + i2c_put_dma_safe_msg_buf(dma->dma_buf, msg, true); 869 + 870 + return ret; 871 + } 872 + 531 873 static int lpi2c_imx_xfer(struct i2c_adapter *adapter, 532 874 struct i2c_msg *msgs, int num) 533 875 { ··· 973 477 lpi2c_imx->msglen = msgs[i].len; 974 478 init_completion(&lpi2c_imx->complete); 975 479 976 - if (msgs[i].flags & I2C_M_RD) 977 - lpi2c_imx_read(lpi2c_imx, &msgs[i]); 978 - else 979 - lpi2c_imx_write(lpi2c_imx, &msgs[i]); 480 + if (is_use_dma(lpi2c_imx, &msgs[i])) { 481 + result = lpi2c_imx_dma_xfer(lpi2c_imx, &msgs[i]); 482 + if (result && lpi2c_imx->dma->using_pio_mode) 483 + result = lpi2c_imx_pio_xfer(lpi2c_imx, &msgs[i]); 484 + } else { 485 + result = lpi2c_imx_pio_xfer(lpi2c_imx, &msgs[i]); 486 + } 980 487 981 - result = lpi2c_imx_msg_complete(lpi2c_imx); 982 488 if (result) 983 489 goto stop; 984 490 ··· 1008 510 return (result < 0) ? result : num; 1009 511 } 1010 512 1011 - static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) 513 + static irqreturn_t lpi2c_imx_target_isr(struct lpi2c_imx_struct *lpi2c_imx, 514 + u32 ssr, u32 sier_filter) 1012 515 { 1013 - struct lpi2c_imx_struct *lpi2c_imx = dev_id; 516 + u8 value; 517 + u32 sasr; 518 + 519 + /* Arbitration lost */ 520 + if (sier_filter & SSR_BEF) { 521 + writel(0, lpi2c_imx->base + LPI2C_SIER); 522 + return IRQ_HANDLED; 523 + } 524 + 525 + /* Address detected */ 526 + if (sier_filter & SSR_AVF) { 527 + sasr = readl(lpi2c_imx->base + LPI2C_SASR); 528 + if (SASR_READ_REQ & sasr) { 529 + /* Read request */ 530 + i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_READ_REQUESTED, &value); 531 + writel(value, lpi2c_imx->base + LPI2C_STDR); 532 + goto ret; 533 + } else { 534 + /* Write request */ 535 + i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_WRITE_REQUESTED, &value); 536 + } 537 + } 538 + 539 + if (sier_filter & SSR_SDF) 540 + /* STOP */ 541 + i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_STOP, &value); 542 + 543 + if (sier_filter & SSR_TDF) { 544 + /* Target send data */ 545 + i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_READ_PROCESSED, &value); 546 + writel(value, lpi2c_imx->base + LPI2C_STDR); 547 + } 548 + 549 + if (sier_filter & SSR_RDF) { 550 + /* Target receive data */ 551 + value = readl(lpi2c_imx->base + LPI2C_SRDR); 552 + i2c_slave_event(lpi2c_imx->target, I2C_SLAVE_WRITE_RECEIVED, &value); 553 + } 554 + 555 + ret: 556 + /* Clear SSR */ 557 + writel(ssr & SSR_CLEAR_BITS, lpi2c_imx->base + LPI2C_SSR); 558 + return IRQ_HANDLED; 559 + } 560 + 561 + static irqreturn_t lpi2c_imx_master_isr(struct lpi2c_imx_struct *lpi2c_imx) 562 + { 1014 563 unsigned int enabled; 1015 564 unsigned int temp; 1016 565 ··· 1077 532 return IRQ_HANDLED; 1078 533 } 1079 534 535 + static irqreturn_t lpi2c_imx_isr(int irq, void *dev_id) 536 + { 537 + struct lpi2c_imx_struct *lpi2c_imx = dev_id; 538 + 539 + if (lpi2c_imx->target) { 540 + u32 scr = readl(lpi2c_imx->base + LPI2C_SCR); 541 + u32 ssr = readl(lpi2c_imx->base + LPI2C_SSR); 542 + u32 sier_filter = ssr & readl(lpi2c_imx->base + LPI2C_SIER); 543 + 544 + /* 545 + * The target is enabled and an interrupt has been triggered. 546 + * Enter the target's irq handler. 547 + */ 548 + if ((scr & SCR_SEN) && sier_filter) 549 + return lpi2c_imx_target_isr(lpi2c_imx, ssr, sier_filter); 550 + } 551 + 552 + /* 553 + * Otherwise the interrupt has been triggered by the master. 554 + * Enter the master's irq handler. 555 + */ 556 + return lpi2c_imx_master_isr(lpi2c_imx); 557 + } 558 + 559 + static void lpi2c_imx_target_init(struct lpi2c_imx_struct *lpi2c_imx) 560 + { 561 + u32 temp; 562 + 563 + /* reset target module */ 564 + writel(SCR_RST, lpi2c_imx->base + LPI2C_SCR); 565 + writel(0, lpi2c_imx->base + LPI2C_SCR); 566 + 567 + /* Set target address */ 568 + writel((lpi2c_imx->target->addr << 1), lpi2c_imx->base + LPI2C_SAMR); 569 + 570 + writel(SCFGR1_RXSTALL | SCFGR1_TXDSTALL, lpi2c_imx->base + LPI2C_SCFGR1); 571 + 572 + /* 573 + * set SCFGR2: FILTSDA, FILTSCL and CLKHOLD 574 + * 575 + * FILTSCL/FILTSDA can eliminate signal skew. It should generally be 576 + * set to the same value and should be set >= 50ns. 577 + * 578 + * CLKHOLD is only used when clock stretching is enabled, but it will 579 + * extend the clock stretching to ensure there is an additional delay 580 + * between the target driving SDA and the target releasing the SCL pin. 581 + * 582 + * CLKHOLD setting is crucial for lpi2c target. When master read data 583 + * from target, if there is a delay caused by cpu idle, excessive load, 584 + * or other delays between two bytes in one message transmission, it 585 + * will cause a short interval time between the driving SDA signal and 586 + * releasing SCL signal. The lpi2c master will mistakenly think it is a stop 587 + * signal resulting in an arbitration failure. This issue can be avoided 588 + * by setting CLKHOLD. 589 + * 590 + * In order to ensure lpi2c function normally when the lpi2c speed is as 591 + * low as 100kHz, CLKHOLD should be set to 3 and it is also compatible with 592 + * higher clock frequency like 400kHz and 1MHz. 593 + */ 594 + temp = SCFGR2_FILTSDA(2) | SCFGR2_FILTSCL(2) | SCFGR2_CLKHOLD(3); 595 + writel(temp, lpi2c_imx->base + LPI2C_SCFGR2); 596 + 597 + /* 598 + * Enable module: 599 + * SCR_FILTEN can enable digital filter and output delay counter for LPI2C 600 + * target mode. So SCR_FILTEN need be asserted when enable SDA/SCL FILTER 601 + * and CLKHOLD. 602 + */ 603 + writel(SCR_SEN | SCR_FILTEN, lpi2c_imx->base + LPI2C_SCR); 604 + 605 + /* Enable interrupt from i2c module */ 606 + writel(SLAVE_INT_FLAG, lpi2c_imx->base + LPI2C_SIER); 607 + } 608 + 609 + static int lpi2c_imx_register_target(struct i2c_client *client) 610 + { 611 + struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(client->adapter); 612 + int ret; 613 + 614 + if (lpi2c_imx->target) 615 + return -EBUSY; 616 + 617 + lpi2c_imx->target = client; 618 + 619 + ret = pm_runtime_resume_and_get(lpi2c_imx->adapter.dev.parent); 620 + if (ret < 0) { 621 + dev_err(&lpi2c_imx->adapter.dev, "failed to resume i2c controller"); 622 + return ret; 623 + } 624 + 625 + lpi2c_imx_target_init(lpi2c_imx); 626 + 627 + return 0; 628 + } 629 + 630 + static int lpi2c_imx_unregister_target(struct i2c_client *client) 631 + { 632 + struct lpi2c_imx_struct *lpi2c_imx = i2c_get_adapdata(client->adapter); 633 + int ret; 634 + 635 + if (!lpi2c_imx->target) 636 + return -EINVAL; 637 + 638 + /* Reset target address. */ 639 + writel(0, lpi2c_imx->base + LPI2C_SAMR); 640 + 641 + writel(SCR_RST, lpi2c_imx->base + LPI2C_SCR); 642 + writel(0, lpi2c_imx->base + LPI2C_SCR); 643 + 644 + lpi2c_imx->target = NULL; 645 + 646 + ret = pm_runtime_put_sync(lpi2c_imx->adapter.dev.parent); 647 + if (ret < 0) 648 + dev_err(&lpi2c_imx->adapter.dev, "failed to suspend i2c controller"); 649 + 650 + return ret; 651 + } 652 + 1080 653 static int lpi2c_imx_init_recovery_info(struct lpi2c_imx_struct *lpi2c_imx, 1081 654 struct platform_device *pdev) 1082 655 { ··· 1209 546 return 0; 1210 547 } 1211 548 549 + static void dma_exit(struct device *dev, struct lpi2c_imx_dma *dma) 550 + { 551 + if (dma->chan_rx) 552 + dma_release_channel(dma->chan_rx); 553 + 554 + if (dma->chan_tx) 555 + dma_release_channel(dma->chan_tx); 556 + 557 + devm_kfree(dev, dma); 558 + } 559 + 560 + static int lpi2c_dma_init(struct device *dev, dma_addr_t phy_addr) 561 + { 562 + struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 563 + struct lpi2c_imx_dma *dma; 564 + int ret; 565 + 566 + dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 567 + if (!dma) 568 + return -ENOMEM; 569 + 570 + dma->phy_addr = phy_addr; 571 + 572 + /* Prepare for TX DMA: */ 573 + dma->chan_tx = dma_request_chan(dev, "tx"); 574 + if (IS_ERR(dma->chan_tx)) { 575 + ret = PTR_ERR(dma->chan_tx); 576 + if (ret != -ENODEV && ret != -EPROBE_DEFER) 577 + dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 578 + dma->chan_tx = NULL; 579 + goto dma_exit; 580 + } 581 + 582 + /* Prepare for RX DMA: */ 583 + dma->chan_rx = dma_request_chan(dev, "rx"); 584 + if (IS_ERR(dma->chan_rx)) { 585 + ret = PTR_ERR(dma->chan_rx); 586 + if (ret != -ENODEV && ret != -EPROBE_DEFER) 587 + dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 588 + dma->chan_rx = NULL; 589 + goto dma_exit; 590 + } 591 + 592 + lpi2c_imx->can_use_dma = true; 593 + lpi2c_imx->dma = dma; 594 + return 0; 595 + 596 + dma_exit: 597 + dma_exit(dev, dma); 598 + return ret; 599 + } 600 + 1212 601 static u32 lpi2c_imx_func(struct i2c_adapter *adapter) 1213 602 { 1214 603 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | ··· 1270 555 static const struct i2c_algorithm lpi2c_imx_algo = { 1271 556 .master_xfer = lpi2c_imx_xfer, 1272 557 .functionality = lpi2c_imx_func, 558 + .reg_target = lpi2c_imx_register_target, 559 + .unreg_target = lpi2c_imx_unregister_target, 1273 560 }; 1274 561 1275 562 static const struct of_device_id lpi2c_imx_of_match[] = { ··· 1283 566 static int lpi2c_imx_probe(struct platform_device *pdev) 1284 567 { 1285 568 struct lpi2c_imx_struct *lpi2c_imx; 569 + struct resource *res; 570 + dma_addr_t phy_addr; 1286 571 unsigned int temp; 1287 572 int irq, ret; 1288 573 ··· 1292 573 if (!lpi2c_imx) 1293 574 return -ENOMEM; 1294 575 1295 - lpi2c_imx->base = devm_platform_ioremap_resource(pdev, 0); 576 + lpi2c_imx->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1296 577 if (IS_ERR(lpi2c_imx->base)) 1297 578 return PTR_ERR(lpi2c_imx->base); 1298 579 ··· 1306 587 lpi2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1307 588 strscpy(lpi2c_imx->adapter.name, pdev->name, 1308 589 sizeof(lpi2c_imx->adapter.name)); 590 + phy_addr = (dma_addr_t)res->start; 1309 591 1310 592 ret = devm_clk_bulk_get_all(&pdev->dev, &lpi2c_imx->clks); 1311 593 if (ret < 0) ··· 1318 598 if (ret) 1319 599 lpi2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1320 600 1321 - ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, 0, 601 + ret = devm_request_irq(&pdev->dev, irq, lpi2c_imx_isr, IRQF_NO_SUSPEND, 1322 602 pdev->name, lpi2c_imx); 1323 603 if (ret) 1324 604 return dev_err_probe(&pdev->dev, ret, "can't claim irq %d\n", irq); ··· 1359 639 /* Give it another chance if pinctrl used is not ready yet */ 1360 640 if (ret == -EPROBE_DEFER) 1361 641 goto rpm_disable; 642 + 643 + /* Init DMA */ 644 + ret = lpi2c_dma_init(&pdev->dev, phy_addr); 645 + if (ret) { 646 + if (ret == -EPROBE_DEFER) 647 + goto rpm_disable; 648 + dev_info(&pdev->dev, "use pio mode\n"); 649 + } 1362 650 1363 651 ret = i2c_add_adapter(&lpi2c_imx->adapter); 1364 652 if (ret) ··· 1422 694 return 0; 1423 695 } 1424 696 697 + static int __maybe_unused lpi2c_suspend_noirq(struct device *dev) 698 + { 699 + return pm_runtime_force_suspend(dev); 700 + } 701 + 702 + static int __maybe_unused lpi2c_resume_noirq(struct device *dev) 703 + { 704 + struct lpi2c_imx_struct *lpi2c_imx = dev_get_drvdata(dev); 705 + int ret; 706 + 707 + ret = pm_runtime_force_resume(dev); 708 + if (ret) 709 + return ret; 710 + 711 + /* 712 + * If the I2C module powers down during system suspend, 713 + * the register values will be lost. Therefore, reinitialize 714 + * the target when the system resumes. 715 + */ 716 + if (lpi2c_imx->target) 717 + lpi2c_imx_target_init(lpi2c_imx); 718 + 719 + return 0; 720 + } 721 + 722 + static int lpi2c_suspend(struct device *dev) 723 + { 724 + /* 725 + * Some I2C devices may need the I2C controller to remain active 726 + * during resume_noirq() or suspend_noirq(). If the controller is 727 + * autosuspended, there is no way to wake it up once runtime PM is 728 + * disabled (in suspend_late()). 729 + * 730 + * During system resume, the I2C controller will be available only 731 + * after runtime PM is re-enabled (in resume_early()). However, this 732 + * may be too late for some devices. 733 + * 734 + * Wake up the controller in the suspend() callback while runtime PM 735 + * is still enabled. The I2C controller will remain available until 736 + * the suspend_noirq() callback (pm_runtime_force_suspend()) is 737 + * called. During resume, the I2C controller can be restored by the 738 + * resume_noirq() callback (pm_runtime_force_resume()). 739 + * 740 + * Finally, the resume() callback re-enables autosuspend, ensuring 741 + * the I2C controller remains available until the system enters 742 + * suspend_noirq() and from resume_noirq(). 743 + */ 744 + return pm_runtime_resume_and_get(dev); 745 + } 746 + 747 + static int lpi2c_resume(struct device *dev) 748 + { 749 + pm_runtime_mark_last_busy(dev); 750 + pm_runtime_put_autosuspend(dev); 751 + 752 + return 0; 753 + } 754 + 1425 755 static const struct dev_pm_ops lpi2c_pm_ops = { 1426 - SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1427 - pm_runtime_force_resume) 756 + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(lpi2c_suspend_noirq, 757 + lpi2c_resume_noirq) 758 + SYSTEM_SLEEP_PM_OPS(lpi2c_suspend, lpi2c_resume) 1428 759 SET_RUNTIME_PM_OPS(lpi2c_runtime_suspend, 1429 760 lpi2c_runtime_resume, NULL) 1430 761 };

+82 -17

drivers/i2c/busses/i2c-imx.c

··· 397 397 } 398 398 399 399 /* Functions for DMA support */ 400 - static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 401 - dma_addr_t phy_addr) 400 + static int i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, dma_addr_t phy_addr) 402 401 { 403 402 struct imx_i2c_dma *dma; 404 403 struct dma_slave_config dma_sconfig; 405 - struct device *dev = &i2c_imx->adapter.dev; 404 + struct device *dev = i2c_imx->adapter.dev.parent; 406 405 int ret; 407 406 408 407 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 409 408 if (!dma) 410 - return; 409 + return -ENOMEM; 411 410 412 411 dma->chan_tx = dma_request_chan(dev, "tx"); 413 412 if (IS_ERR(dma->chan_tx)) { ··· 451 452 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 452 453 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 453 454 454 - return; 455 + return 0; 455 456 456 457 fail_rx: 457 458 dma_release_channel(dma->chan_rx); ··· 459 460 dma_release_channel(dma->chan_tx); 460 461 fail_al: 461 462 devm_kfree(dev, dma); 463 + 464 + return ret; 462 465 } 463 466 464 467 static void i2c_imx_dma_callback(void *arg) ··· 622 621 return 0; 623 622 } 624 623 625 - static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 626 - unsigned int i2c_clk_rate) 624 + static int i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 625 + unsigned int i2c_clk_rate) 627 626 { 628 627 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 629 628 unsigned int div; ··· 638 637 639 638 /* Divider value calculation */ 640 639 if (i2c_imx->cur_clk == i2c_clk_rate) 641 - return; 640 + return 0; 641 + 642 + /* Keep the denominator of the following program always NOT equal to 0. */ 643 + if (!(i2c_clk_rate / 2)) 644 + return -EINVAL; 642 645 643 646 i2c_imx->cur_clk = i2c_clk_rate; 644 647 ··· 673 668 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 674 669 i2c_clk_div[i].val, i2c_clk_div[i].div); 675 670 #endif 671 + 672 + return 0; 676 673 } 677 674 678 675 static int i2c_imx_clk_notifier_call(struct notifier_block *nb, ··· 684 677 struct imx_i2c_struct *i2c_imx = container_of(nb, 685 678 struct imx_i2c_struct, 686 679 clk_change_nb); 680 + int ret = 0; 687 681 688 682 if (action & POST_RATE_CHANGE) 689 - i2c_imx_set_clk(i2c_imx, ndata->new_rate); 683 + ret = i2c_imx_set_clk(i2c_imx, ndata->new_rate); 690 684 691 - return NOTIFY_OK; 685 + return notifier_from_errno(ret); 692 686 } 693 687 694 688 static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) ··· 1768 1760 goto rpm_disable; 1769 1761 1770 1762 /* Request IRQ */ 1771 - ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED, pdev->name, i2c_imx); 1763 + ret = request_irq(irq, i2c_imx_isr, IRQF_SHARED | IRQF_NO_SUSPEND, 1764 + pdev->name, i2c_imx); 1772 1765 if (ret) { 1773 1766 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1774 1767 goto rpm_disable; ··· 1789 1780 i2c_imx->bitrate = pdata->bitrate; 1790 1781 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1791 1782 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1792 - i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1783 + ret = i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1784 + if (ret < 0) { 1785 + dev_err(&pdev->dev, "can't get I2C clock\n"); 1786 + goto clk_notifier_unregister; 1787 + } 1793 1788 1794 1789 i2c_imx_reset_regs(i2c_imx); 1795 1790 ··· 1802 1789 /* Give it another chance if pinctrl used is not ready yet */ 1803 1790 if (ret == -EPROBE_DEFER) 1804 1791 goto clk_notifier_unregister; 1792 + 1793 + /* 1794 + * DMA mode should be optional for I2C, when encountering DMA errors, 1795 + * no need to exit I2C probe. Only print warning to show DMA error and 1796 + * use PIO mode directly to ensure I2C bus available as much as possible. 1797 + */ 1798 + ret = i2c_imx_dma_request(i2c_imx, phy_addr); 1799 + if (ret) { 1800 + if (ret == -EPROBE_DEFER) 1801 + goto clk_notifier_unregister; 1802 + else if (ret == -ENODEV) 1803 + dev_dbg(&pdev->dev, "Only use PIO mode\n"); 1804 + else 1805 + dev_warn(&pdev->dev, "Failed to setup DMA (%pe), only use PIO mode\n", 1806 + ERR_PTR(ret)); 1807 + } 1805 1808 1806 1809 /* Add I2C adapter */ 1807 1810 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); ··· 1832 1803 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1833 1804 i2c_imx->adapter.name); 1834 1805 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1835 - 1836 - /* Init DMA config if supported */ 1837 - i2c_imx_dma_request(i2c_imx, phy_addr); 1838 1806 1839 1807 return 0; /* Return OK */ 1840 1808 ··· 1884 1858 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1885 1859 1886 1860 clk_disable(i2c_imx->clk); 1887 - 1888 - return 0; 1861 + return pinctrl_pm_select_sleep_state(dev); 1889 1862 } 1890 1863 1891 1864 static int i2c_imx_runtime_resume(struct device *dev) 1892 1865 { 1893 1866 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1894 1867 int ret; 1868 + 1869 + ret = pinctrl_pm_select_default_state(dev); 1870 + if (ret) 1871 + return ret; 1895 1872 1896 1873 ret = clk_enable(i2c_imx->clk); 1897 1874 if (ret) ··· 1903 1874 return ret; 1904 1875 } 1905 1876 1877 + static int i2c_imx_suspend(struct device *dev) 1878 + { 1879 + /* 1880 + * Some I2C devices may need the I2C controller to remain active 1881 + * during resume_noirq() or suspend_noirq(). If the controller is 1882 + * autosuspended, there is no way to wake it up once runtime PM is 1883 + * disabled (in suspend_late()). 1884 + * 1885 + * During system resume, the I2C controller will be available only 1886 + * after runtime PM is re-enabled (in resume_early()). However, this 1887 + * may be too late for some devices. 1888 + * 1889 + * Wake up the controller in the suspend() callback while runtime PM 1890 + * is still enabled. The I2C controller will remain available until 1891 + * the suspend_noirq() callback (pm_runtime_force_suspend()) is 1892 + * called. During resume, the I2C controller can be restored by the 1893 + * resume_noirq() callback (pm_runtime_force_resume()). 1894 + * 1895 + * Finally, the resume() callback re-enables autosuspend, ensuring 1896 + * the I2C controller remains available until the system enters 1897 + * suspend_noirq() and from resume_noirq(). 1898 + */ 1899 + return pm_runtime_resume_and_get(dev); 1900 + } 1901 + 1902 + static int i2c_imx_resume(struct device *dev) 1903 + { 1904 + pm_runtime_mark_last_busy(dev); 1905 + pm_runtime_put_autosuspend(dev); 1906 + 1907 + return 0; 1908 + } 1909 + 1906 1910 static const struct dev_pm_ops i2c_imx_pm_ops = { 1911 + NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1912 + pm_runtime_force_resume) 1913 + SYSTEM_SLEEP_PM_OPS(i2c_imx_suspend, i2c_imx_resume) 1907 1914 RUNTIME_PM_OPS(i2c_imx_runtime_suspend, i2c_imx_runtime_resume, NULL) 1908 1915 }; 1909 1916

+3 -3

drivers/i2c/busses/i2c-isch.c

··· 291 291 292 292 /* Set up the sysfs linkage to our parent device */ 293 293 priv->adapter.dev.parent = dev; 294 - priv->adapter.owner = THIS_MODULE, 295 - priv->adapter.class = I2C_CLASS_HWMON, 296 - priv->adapter.algo = &smbus_algorithm, 294 + priv->adapter.owner = THIS_MODULE; 295 + priv->adapter.class = I2C_CLASS_HWMON; 296 + priv->adapter.algo = &smbus_algorithm; 297 297 298 298 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 299 299 "SMBus SCH adapter at %04x", (unsigned short)res->start);

+2 -6

drivers/i2c/busses/i2c-keba.c

··· 464 464 { 465 465 int i; 466 466 467 - for (i = 0; i < ki2c->client_size; i++) { 468 - struct i2c_client *client = ki2c->client[i]; 469 - 470 - if (client) 471 - i2c_unregister_device(client); 472 - } 467 + for (i = 0; i < ki2c->client_size; i++) 468 + i2c_unregister_device(ki2c->client[i]); 473 469 } 474 470 475 471 static int ki2c_register_devices(struct ki2c *ki2c)

+326 -101

drivers/i2c/busses/i2c-npcm7xx.c

··· 263 263 #define I2C_FREQ_MIN_HZ 10000 264 264 #define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ 265 265 266 + struct smb_timing_t { 267 + u32 core_clk; 268 + u8 hldt; 269 + u8 dbcnt; 270 + u16 sclfrq; 271 + u8 scllt; 272 + u8 sclht; 273 + bool fast_mode; 274 + }; 275 + 276 + static struct smb_timing_t smb_timing_100khz[] = { 277 + { 278 + .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x4, 279 + .sclfrq = 0xFB, .scllt = 0x0, .sclht = 0x0, 280 + .fast_mode = false, 281 + }, 282 + { 283 + .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x1, 284 + .sclfrq = 0x9D, .scllt = 0x0, .sclht = 0x0, 285 + .fast_mode = false, 286 + }, 287 + { 288 + .core_clk = 50000000, .hldt = 0x2A, .dbcnt = 0x1, 289 + .sclfrq = 0x7E, .scllt = 0x0, .sclht = 0x0, 290 + .fast_mode = false, 291 + }, 292 + { 293 + .core_clk = 48000000, .hldt = 0x2A, .dbcnt = 0x1, 294 + .sclfrq = 0x79, .scllt = 0x0, .sclht = 0x0, 295 + .fast_mode = false, 296 + }, 297 + { 298 + .core_clk = 40000000, .hldt = 0x2A, .dbcnt = 0x1, 299 + .sclfrq = 0x65, .scllt = 0x0, .sclht = 0x0, 300 + .fast_mode = false, 301 + }, 302 + { 303 + .core_clk = 30000000, .hldt = 0x2A, .dbcnt = 0x1, 304 + .sclfrq = 0x4C, .scllt = 0x0, .sclht = 0x0, 305 + .fast_mode = false, 306 + }, 307 + { 308 + .core_clk = 29000000, .hldt = 0x2A, .dbcnt = 0x1, 309 + .sclfrq = 0x49, .scllt = 0x0, .sclht = 0x0, 310 + .fast_mode = false, 311 + }, 312 + { 313 + .core_clk = 26000000, .hldt = 0x2A, .dbcnt = 0x1, 314 + .sclfrq = 0x42, .scllt = 0x0, .sclht = 0x0, 315 + .fast_mode = false, 316 + }, 317 + { 318 + .core_clk = 25000000, .hldt = 0x2A, .dbcnt = 0x1, 319 + .sclfrq = 0x3F, .scllt = 0x0, .sclht = 0x0, 320 + .fast_mode = false, 321 + }, 322 + { 323 + .core_clk = 24000000, .hldt = 0x2A, .dbcnt = 0x1, 324 + .sclfrq = 0x3D, .scllt = 0x0, .sclht = 0x0, 325 + .fast_mode = false, 326 + }, 327 + { 328 + .core_clk = 20000000, .hldt = 0x2A, .dbcnt = 0x1, 329 + .sclfrq = 0x33, .scllt = 0x0, .sclht = 0x0, 330 + .fast_mode = false, 331 + }, 332 + { 333 + .core_clk = 16180000, .hldt = 0x2A, .dbcnt = 0x1, 334 + .sclfrq = 0x29, .scllt = 0x0, .sclht = 0x0, 335 + .fast_mode = false, 336 + }, 337 + { 338 + .core_clk = 15000000, .hldt = 0x23, .dbcnt = 0x1, 339 + .sclfrq = 0x26, .scllt = 0x0, .sclht = 0x0, 340 + .fast_mode = false, 341 + }, 342 + { 343 + .core_clk = 13000000, .hldt = 0x1D, .dbcnt = 0x1, 344 + .sclfrq = 0x21, .scllt = 0x0, .sclht = 0x0, 345 + .fast_mode = false, 346 + }, 347 + { 348 + .core_clk = 12000000, .hldt = 0x1B, .dbcnt = 0x1, 349 + .sclfrq = 0x1F, .scllt = 0x0, .sclht = 0x0, 350 + .fast_mode = false, 351 + }, 352 + { 353 + .core_clk = 10000000, .hldt = 0x18, .dbcnt = 0x1, 354 + .sclfrq = 0x1A, .scllt = 0x0, .sclht = 0x0, 355 + .fast_mode = false, 356 + }, 357 + { 358 + .core_clk = 9000000, .hldt = 0x16, .dbcnt = 0x1, 359 + .sclfrq = 0x17, .scllt = 0x0, .sclht = 0x0, 360 + .fast_mode = false, 361 + }, 362 + { 363 + .core_clk = 8090000, .hldt = 0x14, .dbcnt = 0x1, 364 + .sclfrq = 0x15, .scllt = 0x0, .sclht = 0x0, 365 + .fast_mode = false, 366 + }, 367 + { 368 + .core_clk = 7500000, .hldt = 0x7, .dbcnt = 0x1, 369 + .sclfrq = 0x13, .scllt = 0x0, .sclht = 0x0, 370 + .fast_mode = false, 371 + }, 372 + { 373 + .core_clk = 6500000, .hldt = 0xE, .dbcnt = 0x1, 374 + .sclfrq = 0x11, .scllt = 0x0, .sclht = 0x0, 375 + .fast_mode = false, 376 + }, 377 + { 378 + .core_clk = 4000000, .hldt = 0x9, .dbcnt = 0x1, 379 + .sclfrq = 0xB, .scllt = 0x0, .sclht = 0x0, 380 + .fast_mode = false, 381 + }, 382 + }; 383 + 384 + static struct smb_timing_t smb_timing_400khz[] = { 385 + { 386 + .core_clk = 100000000, .hldt = 0x2A, .dbcnt = 0x3, 387 + .sclfrq = 0x0, .scllt = 0x47, .sclht = 0x35, 388 + .fast_mode = true, 389 + }, 390 + { 391 + .core_clk = 62500000, .hldt = 0x2A, .dbcnt = 0x2, 392 + .sclfrq = 0x0, .scllt = 0x2C, .sclht = 0x22, 393 + .fast_mode = true, 394 + }, 395 + { 396 + .core_clk = 50000000, .hldt = 0x21, .dbcnt = 0x1, 397 + .sclfrq = 0x0, .scllt = 0x24, .sclht = 0x1B, 398 + .fast_mode = true, 399 + }, 400 + { 401 + .core_clk = 48000000, .hldt = 0x1E, .dbcnt = 0x1, 402 + .sclfrq = 0x0, .scllt = 0x24, .sclht = 0x19, 403 + .fast_mode = true, 404 + }, 405 + { 406 + .core_clk = 40000000, .hldt = 0x1B, .dbcnt = 0x1, 407 + .sclfrq = 0x0, .scllt = 0x1E, .sclht = 0x14, 408 + .fast_mode = true, 409 + }, 410 + { 411 + .core_clk = 33000000, .hldt = 0x15, .dbcnt = 0x1, 412 + .sclfrq = 0x0, .scllt = 0x19, .sclht = 0x11, 413 + .fast_mode = true, 414 + }, 415 + { 416 + .core_clk = 30000000, .hldt = 0x15, .dbcnt = 0x1, 417 + .sclfrq = 0x0, .scllt = 0x19, .sclht = 0xD, 418 + .fast_mode = true, 419 + }, 420 + { 421 + .core_clk = 29000000, .hldt = 0x11, .dbcnt = 0x1, 422 + .sclfrq = 0x0, .scllt = 0x15, .sclht = 0x10, 423 + .fast_mode = true, 424 + }, 425 + { 426 + .core_clk = 26000000, .hldt = 0x10, .dbcnt = 0x1, 427 + .sclfrq = 0x0, .scllt = 0x13, .sclht = 0xE, 428 + .fast_mode = true, 429 + }, 430 + { 431 + .core_clk = 25000000, .hldt = 0xF, .dbcnt = 0x1, 432 + .sclfrq = 0x0, .scllt = 0x13, .sclht = 0xD, 433 + .fast_mode = true, 434 + }, 435 + { 436 + .core_clk = 24000000, .hldt = 0xD, .dbcnt = 0x1, 437 + .sclfrq = 0x0, .scllt = 0x12, .sclht = 0xD, 438 + .fast_mode = true, 439 + }, 440 + { 441 + .core_clk = 20000000, .hldt = 0xB, .dbcnt = 0x1, 442 + .sclfrq = 0x0, .scllt = 0xF, .sclht = 0xA, 443 + .fast_mode = true, 444 + }, 445 + { 446 + .core_clk = 16180000, .hldt = 0xA, .dbcnt = 0x1, 447 + .sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9, 448 + .fast_mode = true, 449 + }, 450 + { 451 + .core_clk = 15000000, .hldt = 0x9, .dbcnt = 0x1, 452 + .sclfrq = 0x0, .scllt = 0xB, .sclht = 0x8, 453 + .fast_mode = true, 454 + }, 455 + { 456 + .core_clk = 13000000, .hldt = 0x7, .dbcnt = 0x1, 457 + .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7, 458 + .fast_mode = true, 459 + }, 460 + { 461 + .core_clk = 12000000, .hldt = 0x7, .dbcnt = 0x1, 462 + .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x6, 463 + .fast_mode = true, 464 + }, 465 + { 466 + .core_clk = 10000000, .hldt = 0x6, .dbcnt = 0x1, 467 + .sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5, 468 + .fast_mode = true, 469 + }, 470 + }; 471 + 472 + static struct smb_timing_t smb_timing_1000khz[] = { 473 + { 474 + .core_clk = 100000000, .hldt = 0x15, .dbcnt = 0x4, 475 + .sclfrq = 0x0, .scllt = 0x1C, .sclht = 0x15, 476 + .fast_mode = true, 477 + }, 478 + { 479 + .core_clk = 62500000, .hldt = 0xF, .dbcnt = 0x3, 480 + .sclfrq = 0x0, .scllt = 0x11, .sclht = 0xE, 481 + .fast_mode = true, 482 + }, 483 + { 484 + .core_clk = 50000000, .hldt = 0xA, .dbcnt = 0x2, 485 + .sclfrq = 0x0, .scllt = 0xE, .sclht = 0xB, 486 + .fast_mode = true, 487 + }, 488 + { 489 + .core_clk = 48000000, .hldt = 0x9, .dbcnt = 0x2, 490 + .sclfrq = 0x0, .scllt = 0xD, .sclht = 0xB, 491 + .fast_mode = true, 492 + }, 493 + { 494 + .core_clk = 41000000, .hldt = 0x9, .dbcnt = 0x2, 495 + .sclfrq = 0x0, .scllt = 0xC, .sclht = 0x9, 496 + .fast_mode = true, 497 + }, 498 + { 499 + .core_clk = 40000000, .hldt = 0x8, .dbcnt = 0x2, 500 + .sclfrq = 0x0, .scllt = 0xB, .sclht = 0x9, 501 + .fast_mode = true, 502 + }, 503 + { 504 + .core_clk = 33000000, .hldt = 0x7, .dbcnt = 0x1, 505 + .sclfrq = 0x0, .scllt = 0xA, .sclht = 0x7, 506 + .fast_mode = true, 507 + }, 508 + { 509 + .core_clk = 25000000, .hldt = 0x4, .dbcnt = 0x1, 510 + .sclfrq = 0x0, .scllt = 0x7, .sclht = 0x6, 511 + .fast_mode = true, 512 + }, 513 + { 514 + .core_clk = 24000000, .hldt = 0x7, .dbcnt = 0x1, 515 + .sclfrq = 0x0, .scllt = 0x8, .sclht = 0x5, 516 + .fast_mode = true, 517 + }, 518 + { 519 + .core_clk = 20000000, .hldt = 0x4, .dbcnt = 0x1, 520 + .sclfrq = 0x0, .scllt = 0x6, .sclht = 0x4, 521 + .fast_mode = true, 522 + }, 523 + }; 524 + 266 525 struct npcm_i2c_data { 267 526 u8 fifo_size; 268 527 u32 segctl_init_val; ··· 1925 1666 (FIELD_GET(NPCM_I2CCST3_EO_BUSY, 1926 1667 ioread8(bus->reg + NPCM_I2CCST3)))) { 1927 1668 npcm_i2c_irq_handle_eob(bus); 1669 + #if IS_ENABLED(CONFIG_I2C_SLAVE) 1670 + /* reenable slave if it was enabled */ 1671 + if (bus->slave) 1672 + iowrite8(bus->slave->addr | NPCM_I2CADDR_SAEN, 1673 + bus->reg + NPCM_I2CADDR1); 1674 + #endif 1928 1675 return 0; 1929 1676 } 1930 1677 ··· 2070 1805 */ 2071 1806 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) 2072 1807 { 2073 - u32 k1 = 0; 2074 - u32 k2 = 0; 2075 - u8 dbnct = 0; 2076 - u32 sclfrq = 0; 2077 - u8 hldt = 7; 1808 + struct smb_timing_t *smb_timing; 1809 + u8 scl_table_cnt = 0, table_size = 0; 2078 1810 u8 fast_mode = 0; 2079 - u32 src_clk_khz; 2080 - u32 bus_freq_khz; 2081 1811 2082 - src_clk_khz = bus->apb_clk / 1000; 2083 - bus_freq_khz = bus_freq_hz / 1000; 2084 1812 bus->bus_freq = bus_freq_hz; 2085 1813 2086 - /* 100KHz and below: */ 2087 - if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) { 2088 - sclfrq = src_clk_khz / (bus_freq_khz * 4); 2089 - 2090 - if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) 2091 - return -EDOM; 2092 - 2093 - if (src_clk_khz >= 40000) 2094 - hldt = 17; 2095 - else if (src_clk_khz >= 12500) 2096 - hldt = 15; 2097 - else 2098 - hldt = 7; 2099 - } 2100 - 2101 - /* 400KHz: */ 2102 - else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) { 2103 - sclfrq = 0; 1814 + switch (bus_freq_hz) { 1815 + case I2C_MAX_STANDARD_MODE_FREQ: 1816 + smb_timing = smb_timing_100khz; 1817 + table_size = ARRAY_SIZE(smb_timing_100khz); 1818 + break; 1819 + case I2C_MAX_FAST_MODE_FREQ: 1820 + smb_timing = smb_timing_400khz; 1821 + table_size = ARRAY_SIZE(smb_timing_400khz); 2104 1822 fast_mode = I2CCTL3_400K_MODE; 2105 - 2106 - if (src_clk_khz < 7500) 2107 - /* 400KHZ cannot be supported for core clock < 7.5MHz */ 2108 - return -EDOM; 2109 - 2110 - else if (src_clk_khz >= 50000) { 2111 - k1 = 80; 2112 - k2 = 48; 2113 - hldt = 12; 2114 - dbnct = 7; 2115 - } 2116 - 2117 - /* Master or Slave with frequency > 25MHz */ 2118 - else if (src_clk_khz > 25000) { 2119 - hldt = clk_coef(src_clk_khz, 300) + 7; 2120 - k1 = clk_coef(src_clk_khz, 1600); 2121 - k2 = clk_coef(src_clk_khz, 900); 2122 - } 2123 - } 2124 - 2125 - /* 1MHz: */ 2126 - else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) { 2127 - sclfrq = 0; 1823 + break; 1824 + case I2C_MAX_FAST_MODE_PLUS_FREQ: 1825 + smb_timing = smb_timing_1000khz; 1826 + table_size = ARRAY_SIZE(smb_timing_1000khz); 2128 1827 fast_mode = I2CCTL3_400K_MODE; 2129 - 2130 - /* 1MHZ cannot be supported for core clock < 24 MHz */ 2131 - if (src_clk_khz < 24000) 2132 - return -EDOM; 2133 - 2134 - k1 = clk_coef(src_clk_khz, 620); 2135 - k2 = clk_coef(src_clk_khz, 380); 2136 - 2137 - /* Core clk > 40 MHz */ 2138 - if (src_clk_khz > 40000) { 2139 - /* 2140 - * Set HLDT: 2141 - * SDA hold time: (HLDT-7) * T(CLK) >= 120 2142 - * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7 2143 - */ 2144 - hldt = clk_coef(src_clk_khz, 120) + 7; 2145 - } else { 2146 - hldt = 7; 2147 - dbnct = 2; 2148 - } 1828 + break; 1829 + default: 1830 + return -EINVAL; 2149 1831 } 2150 1832 2151 - /* Frequency larger than 1 MHz is not supported */ 2152 - else 1833 + for (scl_table_cnt = 0; scl_table_cnt < table_size; scl_table_cnt++) 1834 + if (bus->apb_clk >= smb_timing[scl_table_cnt].core_clk) 1835 + break; 1836 + 1837 + if (scl_table_cnt == table_size) 2153 1838 return -EINVAL; 2154 1839 2155 - if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 2156 - k1 = round_up(k1, 2); 2157 - k2 = round_up(k2 + 1, 2); 2158 - if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || 2159 - k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) 2160 - return -EDOM; 2161 - } 2162 - 2163 1840 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ 2164 - iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F), 1841 + iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, smb_timing[scl_table_cnt].sclfrq & 0x7F), 2165 1842 bus->reg + NPCM_I2CCTL2); 2166 1843 2167 1844 /* bits [8:7] are in I2CCTL3 reg */ 2168 - iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), 1845 + iowrite8(FIELD_PREP(I2CCTL3_SCLFRQ8_7, (smb_timing[scl_table_cnt].sclfrq >> 7) & 0x3) | 1846 + fast_mode, 2169 1847 bus->reg + NPCM_I2CCTL3); 2170 1848 2171 1849 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ ··· 2120 1912 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 2121 1913 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 2122 1914 */ 2123 - iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT); 2124 - iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT); 1915 + iowrite8(smb_timing[scl_table_cnt].scllt, bus->reg + NPCM_I2CSCLLT); 1916 + iowrite8(smb_timing[scl_table_cnt].sclht, bus->reg + NPCM_I2CSCLHT); 2125 1917 2126 - iowrite8(dbnct, bus->reg + NPCM_I2CCTL5); 1918 + iowrite8(smb_timing[scl_table_cnt].dbcnt, bus->reg + NPCM_I2CCTL5); 2127 1919 } 2128 1920 2129 - iowrite8(hldt, bus->reg + NPCM_I2CCTL4); 1921 + iowrite8(smb_timing[scl_table_cnt].hldt, bus->reg + NPCM_I2CCTL4); 2130 1922 2131 1923 /* Return to Bank 1, and stay there by default: */ 2132 1924 npcm_i2c_select_bank(bus, I2C_BANK_1); ··· 2243 2035 } 2244 2036 2245 2037 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus, 2246 - u8 slave_addr, u16 nwrite, u16 nread, 2038 + u16 nwrite, u16 nread, 2247 2039 u8 *write_data, u8 *read_data, 2248 2040 bool use_PEC, bool use_read_block) 2249 2041 { ··· 2251 2043 bus->cmd_err = -EBUSY; 2252 2044 return false; 2253 2045 } 2254 - bus->dest_addr = slave_addr << 1; 2255 2046 bus->wr_buf = write_data; 2256 2047 bus->wr_size = nwrite; 2257 2048 bus->wr_ind = 0; ··· 2293 2086 unsigned long time_left, flags; 2294 2087 u16 nwrite, nread; 2295 2088 u8 *write_data, *read_data; 2296 - u8 slave_addr; 2297 2089 unsigned long timeout; 2298 2090 bool read_block = false; 2299 2091 bool read_PEC = false; ··· 2305 2099 } 2306 2100 2307 2101 msg0 = &msgs[0]; 2308 - slave_addr = msg0->addr; 2309 2102 if (msg0->flags & I2C_M_RD) { /* read */ 2310 2103 nwrite = 0; 2311 2104 write_data = NULL; ··· 2337 2132 } 2338 2133 } 2339 2134 2340 - /* 2341 - * Adaptive TimeOut: estimated time in usec + 100% margin: 2342 - * 2: double the timeout for clock stretching case 2343 - * 9: bits per transaction (including the ack/nack) 2344 - */ 2345 - timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite); 2346 - timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec)); 2347 2135 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) { 2348 2136 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num); 2349 2137 return -EINVAL; 2350 2138 } 2351 2139 2352 - time_left = jiffies + timeout + 1; 2140 + time_left = jiffies + bus->adap.timeout / bus->adap.retries + 1; 2353 2141 do { 2354 2142 /* 2355 2143 * we must clear slave address immediately when the bus is not ··· 2361 2163 } while (time_is_after_jiffies(time_left) && bus_busy); 2362 2164 2363 2165 /* 2166 + * Store the address early in a global position to ensure it is 2167 + * accessible for a potential call to i2c_recover_bus(). 2168 + * 2169 + * Since the transfer might be a read operation, remove the I2C_M_RD flag 2170 + * from the bus->dest_addr for the i2c_recover_bus() call later. 2171 + * 2172 + * The i2c_recover_bus() uses the address in a write direction to recover 2173 + * the i2c bus if some error condition occurs. 2174 + * 2175 + * Remove the I2C_M_RD flag from the address since npcm_i2c_master_start_xmit() 2176 + * handles the read/write operation internally. 2177 + */ 2178 + bus->dest_addr = i2c_8bit_addr_from_msg(msg0) & ~I2C_M_RD; 2179 + 2180 + /* 2364 2181 * Check the BER (bus error) state, when ber_state is true, it means that the module 2365 2182 * detects the bus error which is caused by some factor like that the electricity 2366 2183 * noise occurs on the bus. Under this condition, the module is reset and the bus ··· 2392 2179 } 2393 2180 2394 2181 npcm_i2c_init_params(bus); 2395 - bus->dest_addr = slave_addr; 2396 2182 bus->msgs = msgs; 2397 2183 bus->msgs_num = num; 2398 2184 bus->cmd_err = 0; ··· 2401 2189 2402 2190 npcm_i2c_int_enable(bus, true); 2403 2191 2404 - if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread, 2192 + if (npcm_i2c_master_start_xmit(bus, nwrite, nread, 2405 2193 write_data, read_data, read_PEC, 2406 2194 read_block)) { 2195 + /* 2196 + * Adaptive TimeOut: estimated time in usec + 100% margin: 2197 + * 2: double the timeout for clock stretching case 2198 + * 9: bits per transaction (including the ack/nack) 2199 + */ 2200 + timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite); 2201 + timeout = max_t(unsigned long, bus->adap.timeout / bus->adap.retries, 2202 + usecs_to_jiffies(timeout_usec)); 2407 2203 time_left = wait_for_completion_timeout(&bus->cmd_complete, 2408 2204 timeout); 2409 2205 ··· 2537 2317 adap = &bus->adap; 2538 2318 adap->owner = THIS_MODULE; 2539 2319 adap->retries = 3; 2540 - adap->timeout = msecs_to_jiffies(35); 2320 + /* 2321 + * The users want to connect a lot of masters on the same bus. 2322 + * This timeout is used to determine the time it takes to take bus ownership. 2323 + * The transactions are very long, so waiting 35ms is not enough. 2324 + */ 2325 + adap->timeout = 2 * HZ; 2541 2326 adap->algo = &npcm_i2c_algo; 2542 2327 adap->quirks = &npcm_i2c_quirks; 2543 2328 adap->algo_data = bus;

+27 -29

drivers/i2c/busses/i2c-qcom-geni.c

··· 823 823 return gi2c->irq; 824 824 825 825 ret = geni_i2c_clk_map_idx(gi2c); 826 - if (ret) { 827 - dev_err(dev, "Invalid clk frequency %d Hz: %d\n", 828 - gi2c->clk_freq_out, ret); 829 - return ret; 830 - } 826 + if (ret) 827 + return dev_err_probe(dev, ret, "Invalid clk frequency %d Hz\n", 828 + gi2c->clk_freq_out); 831 829 832 830 gi2c->adap.algo = &geni_i2c_algo; 833 831 init_completion(&gi2c->done); ··· 835 837 /* Keep interrupts disabled initially to allow for low-power modes */ 836 838 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, IRQF_NO_AUTOEN, 837 839 dev_name(dev), gi2c); 838 - if (ret) { 839 - dev_err(dev, "Request_irq failed:%d: err:%d\n", 840 - gi2c->irq, ret); 841 - return ret; 842 - } 840 + if (ret) 841 + return dev_err_probe(dev, ret, 842 + "Request_irq failed: %d\n", gi2c->irq); 843 + 843 844 i2c_set_adapdata(&gi2c->adap, gi2c); 844 845 gi2c->adap.dev.parent = dev; 845 846 gi2c->adap.dev.of_node = dev->of_node; ··· 867 870 868 871 ret = geni_se_resources_on(&gi2c->se); 869 872 if (ret) { 870 - dev_err(dev, "Error turning on resources %d\n", ret); 871 - clk_disable_unprepare(gi2c->core_clk); 872 - return ret; 873 + dev_err_probe(dev, ret, "Error turning on resources\n"); 874 + goto err_clk; 873 875 } 874 876 proto = geni_se_read_proto(&gi2c->se); 875 877 if (proto != GENI_SE_I2C) { 876 - dev_err(dev, "Invalid proto %d\n", proto); 877 - geni_se_resources_off(&gi2c->se); 878 - clk_disable_unprepare(gi2c->core_clk); 879 - return -ENXIO; 878 + ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto); 879 + goto err_resources; 880 880 } 881 881 882 882 if (desc && desc->no_dma_support) ··· 885 891 /* FIFO is disabled, so we can only use GPI DMA */ 886 892 gi2c->gpi_mode = true; 887 893 ret = setup_gpi_dma(gi2c); 888 - if (ret) { 889 - geni_se_resources_off(&gi2c->se); 890 - clk_disable_unprepare(gi2c->core_clk); 891 - return dev_err_probe(dev, ret, "Failed to setup GPI DMA mode\n"); 892 - } 894 + if (ret) 895 + goto err_resources; 893 896 894 897 dev_dbg(dev, "Using GPI DMA mode for I2C\n"); 895 898 } else { ··· 898 907 tx_depth = desc->tx_fifo_depth; 899 908 900 909 if (!tx_depth) { 901 - dev_err(dev, "Invalid TX FIFO depth\n"); 902 - geni_se_resources_off(&gi2c->se); 903 - clk_disable_unprepare(gi2c->core_clk); 904 - return -EINVAL; 910 + ret = dev_err_probe(dev, -EINVAL, 911 + "Invalid TX FIFO depth\n"); 912 + goto err_resources; 905 913 } 906 914 907 915 gi2c->tx_wm = tx_depth - 1; ··· 914 924 clk_disable_unprepare(gi2c->core_clk); 915 925 ret = geni_se_resources_off(&gi2c->se); 916 926 if (ret) { 917 - dev_err(dev, "Error turning off resources %d\n", ret); 927 + dev_err_probe(dev, ret, "Error turning off resources\n"); 918 928 goto err_dma; 919 929 } 920 930 ··· 930 940 931 941 ret = i2c_add_adapter(&gi2c->adap); 932 942 if (ret) { 933 - dev_err(dev, "Error adding i2c adapter %d\n", ret); 943 + dev_err_probe(dev, ret, "Error adding i2c adapter\n"); 934 944 pm_runtime_disable(gi2c->se.dev); 935 945 goto err_dma; 936 946 } 937 947 938 948 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 939 949 940 - return 0; 950 + return ret; 951 + 952 + err_resources: 953 + geni_se_resources_off(&gi2c->se); 954 + err_clk: 955 + clk_disable_unprepare(gi2c->core_clk); 956 + 957 + return ret; 941 958 942 959 err_dma: 943 960 release_gpi_dma(gi2c); 961 + 944 962 return ret; 945 963 } 946 964

+72 -62

drivers/i2c/busses/i2c-riic.c

··· 34 34 * Also check the comments in the interrupt routines for some gory details. 35 35 */ 36 36 37 + #include <linux/bits.h> 37 38 #include <linux/clk.h> 38 39 #include <linux/completion.h> 39 40 #include <linux/err.h> 40 41 #include <linux/i2c.h> 41 42 #include <linux/interrupt.h> 42 43 #include <linux/io.h> 44 + #include <linux/iopoll.h> 43 45 #include <linux/module.h> 44 46 #include <linux/of.h> 45 47 #include <linux/platform_device.h> 46 48 #include <linux/pm_runtime.h> 47 49 #include <linux/reset.h> 50 + #include <linux/time.h> 48 51 49 - #define ICCR1_ICE 0x80 50 - #define ICCR1_IICRST 0x40 51 - #define ICCR1_SOWP 0x10 52 + #define ICCR1_ICE BIT(7) 53 + #define ICCR1_IICRST BIT(6) 54 + #define ICCR1_SOWP BIT(4) 55 + #define ICCR1_SCLI BIT(1) 56 + #define ICCR1_SDAI BIT(0) 52 57 53 - #define ICCR2_BBSY 0x80 54 - #define ICCR2_SP 0x08 55 - #define ICCR2_RS 0x04 56 - #define ICCR2_ST 0x02 58 + #define ICCR2_BBSY BIT(7) 59 + #define ICCR2_SP BIT(3) 60 + #define ICCR2_RS BIT(2) 61 + #define ICCR2_ST BIT(1) 57 62 58 - #define ICMR1_CKS_MASK 0x70 59 - #define ICMR1_BCWP 0x08 63 + #define ICMR1_CKS_MASK GENMASK(6, 4) 64 + #define ICMR1_BCWP BIT(3) 60 65 #define ICMR1_CKS(_x) ((((_x) << 4) & ICMR1_CKS_MASK) | ICMR1_BCWP) 61 66 62 - #define ICMR3_RDRFS 0x20 63 - #define ICMR3_ACKWP 0x10 64 - #define ICMR3_ACKBT 0x08 67 + #define ICMR3_RDRFS BIT(5) 68 + #define ICMR3_ACKWP BIT(4) 69 + #define ICMR3_ACKBT BIT(3) 65 70 66 - #define ICFER_FMPE 0x80 71 + #define ICFER_FMPE BIT(7) 67 72 68 - #define ICIER_TIE 0x80 69 - #define ICIER_TEIE 0x40 70 - #define ICIER_RIE 0x20 71 - #define ICIER_NAKIE 0x10 72 - #define ICIER_SPIE 0x08 73 + #define ICIER_TIE BIT(7) 74 + #define ICIER_TEIE BIT(6) 75 + #define ICIER_RIE BIT(5) 76 + #define ICIER_NAKIE BIT(4) 77 + #define ICIER_SPIE BIT(3) 73 78 74 - #define ICSR2_NACKF 0x10 79 + #define ICSR2_NACKF BIT(4) 75 80 76 - #define ICBR_RESERVED 0xe0 /* Should be 1 on writes */ 81 + #define ICBR_RESERVED GENMASK(7, 5) /* Should be 1 on writes */ 77 82 78 83 #define RIIC_INIT_MSG -1 79 84 ··· 139 134 riic_writeb(riic, (riic_readb(riic, reg) & ~clear) | set, reg); 140 135 } 141 136 137 + static int riic_bus_barrier(struct riic_dev *riic) 138 + { 139 + int ret; 140 + u8 val; 141 + 142 + /* 143 + * The SDA line can still be low even when BBSY = 0. Therefore, after checking 144 + * the BBSY flag, also verify that the SDA and SCL lines are not being held low. 145 + */ 146 + ret = readb_poll_timeout(riic->base + riic->info->regs[RIIC_ICCR2], val, 147 + !(val & ICCR2_BBSY), 10, riic->adapter.timeout); 148 + if (ret) 149 + return ret; 150 + 151 + if ((riic_readb(riic, RIIC_ICCR1) & (ICCR1_SDAI | ICCR1_SCLI)) != 152 + (ICCR1_SDAI | ICCR1_SCLI)) 153 + return -EBUSY; 154 + 155 + return 0; 156 + } 157 + 142 158 static int riic_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) 143 159 { 144 160 struct riic_dev *riic = i2c_get_adapdata(adap); ··· 172 146 if (ret) 173 147 return ret; 174 148 175 - if (riic_readb(riic, RIIC_ICCR2) & ICCR2_BBSY) { 176 - riic->err = -EBUSY; 149 + riic->err = riic_bus_barrier(riic); 150 + if (riic->err) 177 151 goto out; 178 - } 179 152 180 153 reinit_completion(&riic->msg_done); 181 - riic->err = 0; 182 154 183 155 riic_writeb(riic, 0, RIIC_ICSR2); 184 156 ··· 336 312 { 337 313 int ret; 338 314 unsigned long rate; 315 + unsigned long ns_per_tick; 339 316 int total_ticks, cks, brl, brh; 340 317 struct i2c_timings *t = &riic->i2c_t; 341 318 struct device *dev = riic->adapter.dev.parent; ··· 345 320 : I2C_MAX_FAST_MODE_FREQ; 346 321 347 322 if (t->bus_freq_hz > max_freq) 348 - return dev_err_probe(&riic->adapter.dev, -EINVAL, 323 + return dev_err_probe(dev, -EINVAL, 349 324 "unsupported bus speed %uHz (%u max)\n", 350 325 t->bus_freq_hz, max_freq); 351 326 ··· 381 356 rate /= 2; 382 357 } 383 358 384 - if (brl > (0x1F + 3)) { 385 - dev_err(&riic->adapter.dev, "invalid speed (%lu). Too slow.\n", 386 - (unsigned long)t->bus_freq_hz); 387 - return -EINVAL; 388 - } 359 + if (brl > (0x1F + 3)) 360 + return dev_err_probe(dev, -EINVAL, "invalid speed (%uHz). Too slow.\n", 361 + t->bus_freq_hz); 389 362 390 363 brh = total_ticks - brl; 391 364 ··· 400 377 * Remove clock ticks for rise and fall times. Convert ns to clock 401 378 * ticks. 402 379 */ 403 - brl -= t->scl_fall_ns / (1000000000 / rate); 404 - brh -= t->scl_rise_ns / (1000000000 / rate); 380 + ns_per_tick = NSEC_PER_SEC / rate; 381 + brl -= t->scl_fall_ns / ns_per_tick; 382 + brh -= t->scl_rise_ns / ns_per_tick; 405 383 406 384 /* Adjust for min register values for when SCLE=1 and NFE=1 */ 407 385 if (brl < 1) ··· 412 388 413 389 pr_debug("i2c-riic: freq=%lu, duty=%d, fall=%lu, rise=%lu, cks=%d, brl=%d, brh=%d\n", 414 390 rate / total_ticks, ((brl + 3) * 100) / (brl + brh + 6), 415 - t->scl_fall_ns / (1000000000 / rate), 416 - t->scl_rise_ns / (1000000000 / rate), cks, brl, brh); 391 + t->scl_fall_ns / ns_per_tick, t->scl_rise_ns / ns_per_tick, cks, brl, brh); 417 392 418 393 ret = pm_runtime_resume_and_get(dev); 419 394 if (ret) ··· 439 416 return 0; 440 417 } 441 418 442 - static struct riic_irq_desc riic_irqs[] = { 419 + static const struct riic_irq_desc riic_irqs[] = { 443 420 { .res_num = 0, .isr = riic_tend_isr, .name = "riic-tend" }, 444 421 { .res_num = 1, .isr = riic_rdrf_isr, .name = "riic-rdrf" }, 445 422 { .res_num = 2, .isr = riic_tdre_isr, .name = "riic-tdre" }, 446 423 { .res_num = 3, .isr = riic_stop_isr, .name = "riic-stop" }, 447 424 { .res_num = 5, .isr = riic_tend_isr, .name = "riic-nack" }, 448 425 }; 449 - 450 - static void riic_reset_control_assert(void *data) 451 - { 452 - reset_control_assert(data); 453 - } 454 426 455 427 static int riic_i2c_probe(struct platform_device *pdev) 456 428 { ··· 463 445 return PTR_ERR(riic->base); 464 446 465 447 riic->clk = devm_clk_get(dev, NULL); 466 - if (IS_ERR(riic->clk)) { 467 - dev_err(dev, "missing controller clock"); 468 - return PTR_ERR(riic->clk); 469 - } 448 + if (IS_ERR(riic->clk)) 449 + return dev_err_probe(dev, PTR_ERR(riic->clk), 450 + "missing controller clock"); 470 451 471 - riic->rstc = devm_reset_control_get_optional_exclusive(dev, NULL); 452 + riic->rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, NULL); 472 453 if (IS_ERR(riic->rstc)) 473 454 return dev_err_probe(dev, PTR_ERR(riic->rstc), 474 - "Error: missing reset ctrl\n"); 475 - 476 - ret = reset_control_deassert(riic->rstc); 477 - if (ret) 478 - return ret; 479 - 480 - ret = devm_add_action_or_reset(dev, riic_reset_control_assert, riic->rstc); 481 - if (ret) 482 - return ret; 455 + "failed to acquire deasserted reset\n"); 483 456 484 457 for (i = 0; i < ARRAY_SIZE(riic_irqs); i++) { 485 - ret = platform_get_irq(pdev, riic_irqs[i].res_num); 486 - if (ret < 0) 487 - return ret; 458 + int irq; 488 459 489 - ret = devm_request_irq(dev, ret, riic_irqs[i].isr, 460 + irq = platform_get_irq(pdev, riic_irqs[i].res_num); 461 + if (irq < 0) 462 + return irq; 463 + 464 + ret = devm_request_irq(dev, irq, riic_irqs[i].isr, 490 465 0, riic_irqs[i].name, riic); 491 - if (ret) { 492 - dev_err(dev, "failed to request irq %s\n", riic_irqs[i].name); 493 - return ret; 494 - } 466 + if (ret) 467 + return dev_err_probe(dev, ret, "failed to request irq %s\n", 468 + riic_irqs[i].name); 495 469 } 496 470 497 471 riic->info = of_device_get_match_data(dev);

+228 -55

drivers/i2c/busses/i2c-xiic.c

··· 30 30 #include <linux/of.h> 31 31 #include <linux/clk.h> 32 32 #include <linux/pm_runtime.h> 33 + #include <linux/iopoll.h> 34 + #include <linux/spinlock.h> 33 35 34 36 #define DRIVER_NAME "xiic-i2c" 35 37 #define DYNAMIC_MODE_READ_BROKEN_BIT BIT(0) ··· 76 74 * @smbus_block_read: Flag to handle block read 77 75 * @input_clk: Input clock to I2C controller 78 76 * @i2c_clk: I2C SCL frequency 77 + * @atomic: Mode of transfer 78 + * @atomic_lock: Lock for atomic transfer mode 79 + * @atomic_xfer_state: See STATE_ 79 80 */ 80 81 struct xiic_i2c { 81 82 struct device *dev; ··· 101 96 bool smbus_block_read; 102 97 unsigned long input_clk; 103 98 unsigned int i2c_clk; 99 + bool atomic; 100 + spinlock_t atomic_lock; /* Lock for atomic transfer mode */ 101 + enum xilinx_i2c_state atomic_xfer_state; 104 102 }; 105 103 106 104 struct xiic_version_data { ··· 232 224 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 233 225 /* timeout waiting for the controller finish transfers */ 234 226 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 227 + /* timeout waiting for the controller finish transfers in micro seconds */ 228 + #define XIIC_XFER_TIMEOUT_US 10000000 235 229 236 230 /* 237 231 * The following constant is used for the device global interrupt enable ··· 247 237 248 238 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 249 239 static void __xiic_start_xfer(struct xiic_i2c *i2c); 240 + 241 + static int xiic_i2c_runtime_suspend(struct device *dev) 242 + { 243 + struct xiic_i2c *i2c = dev_get_drvdata(dev); 244 + 245 + clk_disable(i2c->clk); 246 + 247 + return 0; 248 + } 249 + 250 + static int xiic_i2c_runtime_resume(struct device *dev) 251 + { 252 + struct xiic_i2c *i2c = dev_get_drvdata(dev); 253 + int ret; 254 + 255 + ret = clk_enable(i2c->clk); 256 + if (ret) { 257 + dev_err(dev, "Cannot enable clock.\n"); 258 + return ret; 259 + } 260 + 261 + return 0; 262 + } 250 263 251 264 /* 252 265 * For the register read and write functions, a little-endian and big-endian ··· 407 374 unsigned int index = 0; 408 375 u32 reg_val; 409 376 410 - dev_dbg(i2c->adap.dev.parent, 411 - "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", 412 - __func__, i2c->input_clk, i2c->i2c_clk); 377 + if (!i2c->atomic) 378 + dev_dbg(i2c->adap.dev.parent, 379 + "%s entry, i2c->input_clk: %ld, i2c->i2c_clk: %d\n", 380 + __func__, i2c->input_clk, i2c->i2c_clk); 413 381 414 382 /* If not specified in DT, do not configure in SW. Rely only on Vivado design */ 415 383 if (!i2c->i2c_clk || !i2c->input_clk) ··· 501 467 return ret; 502 468 503 469 /* Enable interrupts */ 504 - xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 470 + if (!i2c->atomic) 471 + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 505 472 506 473 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 507 474 ··· 584 549 585 550 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 586 551 587 - dev_dbg(i2c->adap.dev.parent, 588 - "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", 589 - __func__, bytes_in_fifo, xiic_rx_space(i2c), 590 - xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 591 - xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 552 + if (!i2c->atomic) 553 + dev_dbg(i2c->adap.dev.parent, 554 + "%s entry, bytes in fifo: %d, rem: %d, SR: 0x%x, CR: 0x%x\n", 555 + __func__, bytes_in_fifo, xiic_rx_space(i2c), 556 + xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 557 + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 592 558 593 559 if (bytes_in_fifo > xiic_rx_space(i2c)) 594 560 bytes_in_fifo = xiic_rx_space(i2c); ··· 648 612 } 649 613 } 650 614 615 + static bool xiic_error_check(struct xiic_i2c *i2c) 616 + { 617 + bool status = false; 618 + u32 pend, isr, ier; 619 + 620 + isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 621 + ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 622 + pend = isr & ier; 623 + 624 + if ((pend & XIIC_INTR_ARB_LOST_MASK) || 625 + ((pend & XIIC_INTR_TX_ERROR_MASK) && 626 + !(pend & XIIC_INTR_RX_FULL_MASK))) { 627 + xiic_reinit(i2c); 628 + status = true; 629 + if (i2c->tx_msg || i2c->rx_msg) 630 + i2c->atomic_xfer_state = STATE_ERROR; 631 + } 632 + return status; 633 + } 634 + 651 635 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 652 636 { 653 637 /* return the actual space left in the FIFO */ ··· 681 625 682 626 len = (len > fifo_space) ? fifo_space : len; 683 627 684 - dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 685 - __func__, len, fifo_space); 628 + if (!i2c->atomic) 629 + dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 630 + __func__, len, fifo_space); 686 631 687 632 while (len--) { 688 633 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; ··· 706 649 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 707 650 ~XIIC_CR_MSMS_MASK); 708 651 } 709 - dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 652 + if (!i2c->atomic) 653 + dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 710 654 } 711 655 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 656 + 657 + if (i2c->atomic && xiic_error_check(i2c)) 658 + return; 712 659 } 713 660 } 714 661 ··· 915 854 */ 916 855 err = xiic_bus_busy(i2c); 917 856 while (err && tries--) { 918 - msleep(1); 857 + if (i2c->atomic) 858 + udelay(1000); 859 + else 860 + usleep_range(1000, 1100); 919 861 err = xiic_bus_busy(i2c); 920 862 } 921 863 922 864 return err; 865 + } 866 + 867 + static void xiic_recv_atomic(struct xiic_i2c *i2c) 868 + { 869 + while (xiic_rx_space(i2c)) { 870 + if (xiic_getreg32(i2c, XIIC_IISR_OFFSET) & XIIC_INTR_RX_FULL_MASK) { 871 + xiic_read_rx(i2c); 872 + 873 + /* Clear Rx full and Tx error interrupts. */ 874 + xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | 875 + XIIC_INTR_TX_ERROR_MASK); 876 + } 877 + if (xiic_error_check(i2c)) 878 + return; 879 + } 880 + 881 + i2c->rx_msg = NULL; 882 + xiic_irq_clr_en(i2c, XIIC_INTR_TX_ERROR_MASK); 883 + 884 + /* send next message if this wasn't the last. */ 885 + if (i2c->nmsgs > 1) { 886 + i2c->nmsgs--; 887 + i2c->tx_msg++; 888 + __xiic_start_xfer(i2c); 889 + } 923 890 } 924 891 925 892 static void xiic_start_recv(struct xiic_i2c *i2c) ··· 956 867 u8 cr = 0, rfd_set = 0; 957 868 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 958 869 959 - dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 960 - __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 961 - xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 870 + if (!i2c->atomic) 871 + dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 872 + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 873 + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 962 874 963 875 /* Disable Tx interrupts */ 964 876 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK | XIIC_INTR_TX_EMPTY_MASK); ··· 1057 967 XIIC_CR_MSMS_MASK) 1058 968 & ~(XIIC_CR_DIR_IS_TX_MASK)); 1059 969 } 1060 - dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", 1061 - __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 1062 - xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 970 + if (!i2c->atomic) 971 + dev_dbg(i2c->adap.dev.parent, "%s end, ISR: 0x%x, CR: 0x%x\n", 972 + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 973 + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 1063 974 } 1064 975 1065 976 if (i2c->nmsgs == 1) ··· 1070 979 /* the message is tx:ed */ 1071 980 i2c->tx_pos = msg->len; 1072 981 1073 - /* Enable interrupts */ 1074 - xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 1075 - 1076 982 i2c->prev_msg_tx = false; 983 + 984 + /* Enable interrupts */ 985 + if (!i2c->atomic) 986 + xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 987 + else 988 + xiic_recv_atomic(i2c); 989 + } 990 + 991 + static void xiic_send_rem_atomic(struct xiic_i2c *i2c) 992 + { 993 + while (xiic_tx_space(i2c)) { 994 + if (xiic_tx_fifo_space(i2c)) { 995 + u16 data; 996 + 997 + data = i2c->tx_msg->buf[i2c->tx_pos]; 998 + i2c->tx_pos++; 999 + if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 1000 + /* last message in transfer -> STOP */ 1001 + if (i2c->dynamic) { 1002 + data |= XIIC_TX_DYN_STOP_MASK; 1003 + } else { 1004 + u8 cr; 1005 + int status; 1006 + 1007 + /* Wait till FIFO is empty so STOP is sent last */ 1008 + status = xiic_wait_tx_empty(i2c); 1009 + if (status) 1010 + return; 1011 + 1012 + /* Write to CR to stop */ 1013 + cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 1014 + xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & 1015 + ~XIIC_CR_MSMS_MASK); 1016 + } 1017 + } 1018 + xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 1019 + } 1020 + if (xiic_error_check(i2c)) 1021 + return; 1022 + } 1023 + 1024 + if (i2c->nmsgs > 1) { 1025 + i2c->nmsgs--; 1026 + i2c->tx_msg++; 1027 + __xiic_start_xfer(i2c); 1028 + } else { 1029 + xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 1030 + } 1077 1031 } 1078 1032 1079 1033 static void xiic_start_send(struct xiic_i2c *i2c) ··· 1127 991 u16 data; 1128 992 struct i2c_msg *msg = i2c->tx_msg; 1129 993 1130 - dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 1131 - __func__, msg, msg->len); 1132 - dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 1133 - __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 1134 - xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 994 + if (!i2c->atomic) { 995 + dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 996 + __func__, msg, msg->len); 997 + dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 998 + __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 999 + xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 1000 + } 1135 1001 1136 1002 if (i2c->dynamic) { 1137 1003 /* write the address */ ··· 1198 1060 XIIC_INTR_TX_ERROR_MASK | 1199 1061 XIIC_INTR_BNB_MASK); 1200 1062 } 1063 + 1201 1064 i2c->prev_msg_tx = true; 1065 + 1066 + if (i2c->atomic && !i2c->atomic_xfer_state) 1067 + xiic_send_rem_atomic(i2c); 1202 1068 } 1203 1069 1204 1070 static void __xiic_start_xfer(struct xiic_i2c *i2c) 1205 1071 { 1206 1072 int fifo_space = xiic_tx_fifo_space(i2c); 1207 1073 1208 - dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 1209 - __func__, i2c->tx_msg, fifo_space); 1074 + if (!i2c->atomic) 1075 + dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 1076 + __func__, i2c->tx_msg, fifo_space); 1210 1077 1211 1078 if (!i2c->tx_msg) 1079 + return; 1080 + 1081 + if (i2c->atomic && xiic_error_check(i2c)) 1212 1082 return; 1213 1083 1214 1084 i2c->rx_pos = 0; ··· 1235 1089 bool broken_read, max_read_len, smbus_blk_read; 1236 1090 int ret, count; 1237 1091 1238 - mutex_lock(&i2c->lock); 1092 + if (i2c->atomic) 1093 + spin_lock(&i2c->atomic_lock); 1094 + else 1095 + mutex_lock(&i2c->lock); 1239 1096 1240 1097 if (i2c->tx_msg || i2c->rx_msg) { 1241 1098 dev_err(i2c->adap.dev.parent, ··· 1246 1097 ret = -EBUSY; 1247 1098 goto out; 1248 1099 } 1100 + 1101 + i2c->atomic_xfer_state = STATE_DONE; 1249 1102 1250 1103 /* In single master mode bus can only be busy, when in use by this 1251 1104 * driver. If the register indicates bus being busy for some reason we ··· 1275 1124 i2c->tx_msg = msgs; 1276 1125 i2c->rx_msg = NULL; 1277 1126 i2c->nmsgs = num; 1278 - init_completion(&i2c->completion); 1127 + 1128 + if (!i2c->atomic) 1129 + init_completion(&i2c->completion); 1279 1130 1280 1131 /* Decide standard mode or Dynamic mode */ 1281 1132 i2c->dynamic = true; ··· 1312 1159 __xiic_start_xfer(i2c); 1313 1160 1314 1161 out: 1315 - mutex_unlock(&i2c->lock); 1162 + if (i2c->atomic) 1163 + spin_unlock(&i2c->atomic_lock); 1164 + else 1165 + mutex_unlock(&i2c->lock); 1316 1166 1317 1167 return ret; 1318 1168 } ··· 1354 1198 return err; 1355 1199 } 1356 1200 1201 + static int xiic_xfer_atomic(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 1202 + { 1203 + struct xiic_i2c *i2c = i2c_get_adapdata(adap); 1204 + u32 status_reg; 1205 + int err; 1206 + 1207 + err = xiic_i2c_runtime_resume(i2c->dev); 1208 + if (err) 1209 + return err; 1210 + 1211 + i2c->atomic = true; 1212 + err = xiic_start_xfer(i2c, msgs, num); 1213 + if (err < 0) 1214 + return err; 1215 + 1216 + err = readl_poll_timeout_atomic(i2c->base + XIIC_SR_REG_OFFSET, 1217 + status_reg, !(status_reg & XIIC_SR_BUS_BUSY_MASK), 1218 + 1, XIIC_XFER_TIMEOUT_US); 1219 + 1220 + if (err) /* Timeout */ 1221 + err = -ETIMEDOUT; 1222 + 1223 + spin_lock(&i2c->atomic_lock); 1224 + if (err || i2c->state) { 1225 + i2c->tx_msg = NULL; 1226 + i2c->rx_msg = NULL; 1227 + i2c->nmsgs = 0; 1228 + } 1229 + 1230 + err = (i2c->atomic_xfer_state == STATE_DONE) ? num : -EIO; 1231 + spin_unlock(&i2c->atomic_lock); 1232 + 1233 + i2c->atomic = false; 1234 + xiic_i2c_runtime_suspend(i2c->dev); 1235 + 1236 + return err; 1237 + } 1238 + 1357 1239 static u32 xiic_func(struct i2c_adapter *adap) 1358 1240 { 1359 1241 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_SMBUS_BLOCK_DATA; ··· 1399 1205 1400 1206 static const struct i2c_algorithm xiic_algorithm = { 1401 1207 .master_xfer = xiic_xfer, 1208 + .master_xfer_atomic = xiic_xfer_atomic, 1402 1209 .functionality = xiic_func, 1403 1210 }; 1404 1211 ··· 1463 1268 DRIVER_NAME " %s", pdev->name); 1464 1269 1465 1270 mutex_init(&i2c->lock); 1271 + spin_lock_init(&i2c->atomic_lock); 1466 1272 1467 1273 i2c->clk = devm_clk_get_enabled(&pdev->dev, NULL); 1468 1274 if (IS_ERR(i2c->clk)) ··· 1559 1363 pm_runtime_disable(&pdev->dev); 1560 1364 pm_runtime_set_suspended(&pdev->dev); 1561 1365 pm_runtime_dont_use_autosuspend(&pdev->dev); 1562 - } 1563 - 1564 - static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 1565 - { 1566 - struct xiic_i2c *i2c = dev_get_drvdata(dev); 1567 - 1568 - clk_disable(i2c->clk); 1569 - 1570 - return 0; 1571 - } 1572 - 1573 - static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 1574 - { 1575 - struct xiic_i2c *i2c = dev_get_drvdata(dev); 1576 - int ret; 1577 - 1578 - ret = clk_enable(i2c->clk); 1579 - if (ret) { 1580 - dev_err(dev, "Cannot enable clock.\n"); 1581 - return ret; 1582 - } 1583 - 1584 - return 0; 1585 1366 } 1586 1367 1587 1368 static const struct dev_pm_ops xiic_dev_pm_ops = {

+22

drivers/i2c/i2c-core-acpi.c

··· 355 355 {} 356 356 }; 357 357 358 + static const struct acpi_device_id i2c_acpi_force_100khz_device_ids[] = { 359 + /* 360 + * When a 400KHz freq is used on this model of ELAN touchpad in Linux, 361 + * excessive smoothing (similar to when the touchpad's firmware detects 362 + * a noisy signal) is sometimes applied. As some devices' (e.g, Lenovo 363 + * V15 G4) ACPI tables specify a 400KHz frequency for this device and 364 + * some I2C busses (e.g, Designware I2C) default to a 400KHz freq, 365 + * force the speed to 100KHz as a workaround. 366 + * 367 + * For future investigation: This problem may be related to the default 368 + * HCNT/LCNT values given by some busses' drivers, because they are not 369 + * specified in the aforementioned devices' ACPI tables, and because 370 + * the device works without issues on Windows at what is expected to be 371 + * a 400KHz frequency. The root cause of the issue is not known. 372 + */ 373 + { "ELAN06FA", 0 }, 374 + {} 375 + }; 376 + 358 377 static acpi_status i2c_acpi_lookup_speed(acpi_handle handle, u32 level, 359 378 void *data, void **return_value) 360 379 { ··· 391 372 392 373 if (acpi_match_device_ids(adev, i2c_acpi_force_400khz_device_ids) == 0) 393 374 lookup->force_speed = I2C_MAX_FAST_MODE_FREQ; 375 + 376 + if (acpi_match_device_ids(adev, i2c_acpi_force_100khz_device_ids) == 0) 377 + lookup->force_speed = I2C_MAX_STANDARD_MODE_FREQ; 394 378 395 379 return AE_OK; 396 380 }

+47 -83

drivers/i2c/i2c-core-base.c

··· 1015 1015 if (status) 1016 1016 goto out_remove_swnode; 1017 1017 1018 + client->debugfs = debugfs_create_dir(dev_name(&client->dev), adap->debugfs); 1019 + 1018 1020 dev_dbg(&adap->dev, "client [%s] registered with bus id %s\n", 1019 1021 client->name, dev_name(&client->dev)); 1020 1022 ··· 1060 1058 1061 1059 if (ACPI_COMPANION(&client->dev)) 1062 1060 acpi_device_clear_enumerated(ACPI_COMPANION(&client->dev)); 1061 + 1062 + debugfs_remove_recursive(client->debugfs); 1063 1063 device_remove_software_node(&client->dev); 1064 1064 device_unregister(&client->dev); 1065 1065 } ··· 1297 1293 info.flags |= I2C_CLIENT_SLAVE; 1298 1294 } 1299 1295 1296 + info.flags |= I2C_CLIENT_USER; 1297 + 1300 1298 client = i2c_new_client_device(adap, &info); 1301 1299 if (IS_ERR(client)) 1302 1300 return PTR_ERR(client); 1303 1301 1304 - /* Keep track of the added device */ 1305 - mutex_lock(&adap->userspace_clients_lock); 1306 - list_add_tail(&client->detected, &adap->userspace_clients); 1307 - mutex_unlock(&adap->userspace_clients_lock); 1308 1302 dev_info(dev, "%s: Instantiated device %s at 0x%02hx\n", "new_device", 1309 1303 info.type, info.addr); 1310 1304 1311 1305 return count; 1312 1306 } 1313 1307 static DEVICE_ATTR_WO(new_device); 1308 + 1309 + static int __i2c_find_user_addr(struct device *dev, void *addrp) 1310 + { 1311 + struct i2c_client *client = i2c_verify_client(dev); 1312 + unsigned short addr = *(unsigned short *)addrp; 1313 + 1314 + return client && client->flags & I2C_CLIENT_USER && 1315 + i2c_encode_flags_to_addr(client) == addr; 1316 + } 1314 1317 1315 1318 /* 1316 1319 * And of course let the users delete the devices they instantiated, if ··· 1333 1322 const char *buf, size_t count) 1334 1323 { 1335 1324 struct i2c_adapter *adap = to_i2c_adapter(dev); 1336 - struct i2c_client *client, *next; 1325 + struct device *child_dev; 1337 1326 unsigned short addr; 1338 1327 char end; 1339 1328 int res; ··· 1349 1338 return -EINVAL; 1350 1339 } 1351 1340 1341 + mutex_lock(&core_lock); 1352 1342 /* Make sure the device was added through sysfs */ 1353 - res = -ENOENT; 1354 - mutex_lock_nested(&adap->userspace_clients_lock, 1355 - i2c_adapter_depth(adap)); 1356 - list_for_each_entry_safe(client, next, &adap->userspace_clients, 1357 - detected) { 1358 - if (i2c_encode_flags_to_addr(client) == addr) { 1359 - dev_info(dev, "%s: Deleting device %s at 0x%02hx\n", 1360 - "delete_device", client->name, client->addr); 1361 - 1362 - list_del(&client->detected); 1363 - i2c_unregister_device(client); 1364 - res = count; 1365 - break; 1366 - } 1343 + child_dev = device_find_child(&adap->dev, &addr, __i2c_find_user_addr); 1344 + if (child_dev) { 1345 + i2c_unregister_device(i2c_verify_client(child_dev)); 1346 + put_device(child_dev); 1347 + } else { 1348 + dev_err(dev, "Can't find userspace-created device at %#x\n", addr); 1349 + count = -ENOENT; 1367 1350 } 1368 - mutex_unlock(&adap->userspace_clients_lock); 1351 + mutex_unlock(&core_lock); 1369 1352 1370 - if (res < 0) 1371 - dev_err(dev, "%s: Can't find device in list\n", 1372 - "delete_device"); 1373 - return res; 1353 + return count; 1374 1354 } 1375 1355 static DEVICE_ATTR_IGNORE_LOCKDEP(delete_device, S_IWUSR, NULL, 1376 1356 delete_device_store); ··· 1532 1530 adap->locked_flags = 0; 1533 1531 rt_mutex_init(&adap->bus_lock); 1534 1532 rt_mutex_init(&adap->mux_lock); 1535 - mutex_init(&adap->userspace_clients_lock); 1536 - INIT_LIST_HEAD(&adap->userspace_clients); 1537 1533 1538 1534 /* Set default timeout to 1 second if not already set */ 1539 1535 if (adap->timeout == 0) ··· 1697 1697 } 1698 1698 EXPORT_SYMBOL_GPL(i2c_add_numbered_adapter); 1699 1699 1700 - static void i2c_do_del_adapter(struct i2c_driver *driver, 1701 - struct i2c_adapter *adapter) 1702 - { 1703 - struct i2c_client *client, *_n; 1704 - 1705 - /* Remove the devices we created ourselves as the result of hardware 1706 - * probing (using a driver's detect method) */ 1707 - list_for_each_entry_safe(client, _n, &driver->clients, detected) { 1708 - if (client->adapter == adapter) { 1709 - dev_dbg(&adapter->dev, "Removing %s at 0x%x\n", 1710 - client->name, client->addr); 1711 - list_del(&client->detected); 1712 - i2c_unregister_device(client); 1713 - } 1714 - } 1715 - } 1716 - 1717 1700 static int __unregister_client(struct device *dev, void *dummy) 1718 1701 { 1719 1702 struct i2c_client *client = i2c_verify_client(dev); ··· 1712 1729 return 0; 1713 1730 } 1714 1731 1715 - static int __process_removed_adapter(struct device_driver *d, void *data) 1716 - { 1717 - i2c_do_del_adapter(to_i2c_driver(d), data); 1718 - return 0; 1719 - } 1720 - 1721 1732 /** 1722 1733 * i2c_del_adapter - unregister I2C adapter 1723 1734 * @adap: the adapter being unregistered ··· 1723 1746 void i2c_del_adapter(struct i2c_adapter *adap) 1724 1747 { 1725 1748 struct i2c_adapter *found; 1726 - struct i2c_client *client, *next; 1727 1749 1728 1750 /* First make sure that this adapter was ever added */ 1729 1751 mutex_lock(&core_lock); ··· 1734 1758 } 1735 1759 1736 1760 i2c_acpi_remove_space_handler(adap); 1737 - /* Tell drivers about this removal */ 1738 - mutex_lock(&core_lock); 1739 - bus_for_each_drv(&i2c_bus_type, NULL, adap, 1740 - __process_removed_adapter); 1741 - mutex_unlock(&core_lock); 1742 - 1743 - /* Remove devices instantiated from sysfs */ 1744 - mutex_lock_nested(&adap->userspace_clients_lock, 1745 - i2c_adapter_depth(adap)); 1746 - list_for_each_entry_safe(client, next, &adap->userspace_clients, 1747 - detected) { 1748 - dev_dbg(&adap->dev, "Removing %s at 0x%x\n", client->name, 1749 - client->addr); 1750 - list_del(&client->detected); 1751 - i2c_unregister_device(client); 1752 - } 1753 - mutex_unlock(&adap->userspace_clients_lock); 1754 1761 1755 1762 /* Detach any active clients. This can't fail, thus we do not 1756 1763 * check the returned value. This is a two-pass process, because 1757 1764 * we can't remove the dummy devices during the first pass: they 1758 1765 * could have been instantiated by real devices wishing to clean 1759 1766 * them up properly, so we give them a chance to do that first. */ 1767 + mutex_lock(&core_lock); 1760 1768 device_for_each_child(&adap->dev, NULL, __unregister_client); 1761 1769 device_for_each_child(&adap->dev, NULL, __unregister_dummy); 1770 + mutex_unlock(&core_lock); 1762 1771 1763 1772 /* device name is gone after device_unregister */ 1764 1773 dev_dbg(&adap->dev, "adapter [%s] unregistered\n", adap->name); ··· 1963 2002 /* add the driver to the list of i2c drivers in the driver core */ 1964 2003 driver->driver.owner = owner; 1965 2004 driver->driver.bus = &i2c_bus_type; 1966 - INIT_LIST_HEAD(&driver->clients); 1967 2005 1968 2006 /* When registration returns, the driver core 1969 2007 * will have called probe() for all matching-but-unbound devices. ··· 1980 2020 } 1981 2021 EXPORT_SYMBOL(i2c_register_driver); 1982 2022 1983 - static int __process_removed_driver(struct device *dev, void *data) 2023 + static int __i2c_unregister_detected_client(struct device *dev, void *argp) 1984 2024 { 1985 - if (dev->type == &i2c_adapter_type) 1986 - i2c_do_del_adapter(data, to_i2c_adapter(dev)); 2025 + struct i2c_client *client = i2c_verify_client(dev); 2026 + 2027 + if (client && client->flags & I2C_CLIENT_AUTO) 2028 + i2c_unregister_device(client); 2029 + 1987 2030 return 0; 1988 2031 } 1989 2032 ··· 1997 2034 */ 1998 2035 void i2c_del_driver(struct i2c_driver *driver) 1999 2036 { 2000 - i2c_for_each_dev(driver, __process_removed_driver); 2037 + mutex_lock(&core_lock); 2038 + /* Satisfy __must_check, function can't fail */ 2039 + if (driver_for_each_device(&driver->driver, NULL, NULL, 2040 + __i2c_unregister_detected_client)) { 2041 + } 2042 + mutex_unlock(&core_lock); 2001 2043 2002 2044 driver_unregister(&driver->driver); 2003 2045 pr_debug("driver [%s] unregistered\n", driver->driver.name); ··· 2429 2461 /* Finally call the custom detection function */ 2430 2462 memset(&info, 0, sizeof(struct i2c_board_info)); 2431 2463 info.addr = addr; 2464 + info.flags = I2C_CLIENT_AUTO; 2432 2465 err = driver->detect(temp_client, &info); 2433 2466 if (err) { 2434 2467 /* -ENODEV is returned if the detection fails. We catch it ··· 2456 2487 dev_dbg(&adapter->dev, "Creating %s at 0x%02x\n", 2457 2488 info.type, info.addr); 2458 2489 client = i2c_new_client_device(adapter, &info); 2459 - if (!IS_ERR(client)) 2460 - list_add_tail(&client->detected, &driver->clients); 2461 - else 2490 + if (IS_ERR(client)) 2462 2491 dev_err(&adapter->dev, "Failed creating %s at 0x%02x\n", 2463 2492 info.type, info.addr); 2464 2493 } ··· 2466 2499 static int i2c_detect(struct i2c_adapter *adapter, struct i2c_driver *driver) 2467 2500 { 2468 2501 const unsigned short *address_list; 2469 - struct i2c_client *temp_client; 2502 + struct i2c_client temp_client; 2470 2503 int i, err = 0; 2471 2504 2472 2505 address_list = driver->address_list; ··· 2487 2520 return 0; 2488 2521 2489 2522 /* Set up a temporary client to help detect callback */ 2490 - temp_client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL); 2491 - if (!temp_client) 2492 - return -ENOMEM; 2493 - temp_client->adapter = adapter; 2523 + memset(&temp_client, 0, sizeof(temp_client)); 2524 + temp_client.adapter = adapter; 2494 2525 2495 2526 for (i = 0; address_list[i] != I2C_CLIENT_END; i += 1) { 2496 2527 dev_dbg(&adapter->dev, 2497 2528 "found normal entry for adapter %d, addr 0x%02x\n", 2498 2529 i2c_adapter_id(adapter), address_list[i]); 2499 - temp_client->addr = address_list[i]; 2500 - err = i2c_detect_address(temp_client, driver); 2530 + temp_client.addr = address_list[i]; 2531 + err = i2c_detect_address(&temp_client, driver); 2501 2532 if (unlikely(err)) 2502 2533 break; 2503 2534 } 2504 2535 2505 - kfree(temp_client); 2506 2536 return err; 2507 2537 } 2508 2538

+4 -4

drivers/i2c/i2c-slave-eeprom.c

··· 91 91 } 92 92 93 93 static ssize_t i2c_slave_eeprom_bin_read(struct file *filp, struct kobject *kobj, 94 - struct bin_attribute *attr, char *buf, loff_t off, size_t count) 94 + const struct bin_attribute *attr, char *buf, loff_t off, size_t count) 95 95 { 96 96 struct eeprom_data *eeprom; 97 97 unsigned long flags; ··· 106 106 } 107 107 108 108 static ssize_t i2c_slave_eeprom_bin_write(struct file *filp, struct kobject *kobj, 109 - struct bin_attribute *attr, char *buf, loff_t off, size_t count) 109 + const struct bin_attribute *attr, char *buf, loff_t off, size_t count) 110 110 { 111 111 struct eeprom_data *eeprom; 112 112 unsigned long flags; ··· 165 165 sysfs_bin_attr_init(&eeprom->bin); 166 166 eeprom->bin.attr.name = "slave-eeprom"; 167 167 eeprom->bin.attr.mode = S_IRUSR | S_IWUSR; 168 - eeprom->bin.read = i2c_slave_eeprom_bin_read; 169 - eeprom->bin.write = i2c_slave_eeprom_bin_write; 168 + eeprom->bin.read_new = i2c_slave_eeprom_bin_read; 169 + eeprom->bin.write_new = i2c_slave_eeprom_bin_write; 170 170 eeprom->bin.size = size; 171 171 172 172 ret = sysfs_create_bin_file(&client->dev.kobj, &eeprom->bin);

+5 -8

include/linux/i2c.h

··· 244 244 * @id_table: List of I2C devices supported by this driver 245 245 * @detect: Callback for device detection 246 246 * @address_list: The I2C addresses to probe (for detect) 247 - * @clients: List of detected clients we created (for i2c-core use only) 248 247 * @flags: A bitmask of flags defined in &enum i2c_driver_flags 249 248 * 250 249 * The driver.owner field should be set to the module owner of this driver. ··· 298 299 /* Device detection callback for automatic device creation */ 299 300 int (*detect)(struct i2c_client *client, struct i2c_board_info *info); 300 301 const unsigned short *address_list; 301 - struct list_head clients; 302 302 303 303 u32 flags; 304 304 }; ··· 313 315 * @dev: Driver model device node for the slave. 314 316 * @init_irq: IRQ that was set at initialization 315 317 * @irq: indicates the IRQ generated by this device (if any) 316 - * @detected: member of an i2c_driver.clients list or i2c-core's 317 - * userspace_devices list 318 318 * @slave_cb: Callback when I2C slave mode of an adapter is used. The adapter 319 319 * calls it to pass on slave events to the slave driver. 320 320 * @devres_group_id: id of the devres group that will be created for resources 321 321 * acquired when probing this device. 322 + * @debugfs: pointer to the debugfs subdirectory which the I2C core created 323 + * for this client. 322 324 * 323 325 * An i2c_client identifies a single device (i.e. chip) connected to an 324 326 * i2c bus. The behaviour exposed to Linux is defined by the driver ··· 332 334 #define I2C_CLIENT_SLAVE 0x20 /* we are the slave */ 333 335 #define I2C_CLIENT_HOST_NOTIFY 0x40 /* We want to use I2C host notify */ 334 336 #define I2C_CLIENT_WAKE 0x80 /* for board_info; true iff can wake */ 337 + #define I2C_CLIENT_AUTO 0x100 /* client was auto-detected */ 338 + #define I2C_CLIENT_USER 0x200 /* client was userspace-created */ 335 339 #define I2C_CLIENT_SCCB 0x9000 /* Use Omnivision SCCB protocol */ 336 340 /* Must match I2C_M_STOP|IGNORE_NAK */ 337 341 ··· 345 345 struct device dev; /* the device structure */ 346 346 int init_irq; /* irq set at initialization */ 347 347 int irq; /* irq issued by device */ 348 - struct list_head detected; 349 348 #if IS_ENABLED(CONFIG_I2C_SLAVE) 350 349 i2c_slave_cb_t slave_cb; /* callback for slave mode */ 351 350 #endif 352 351 void *devres_group_id; /* ID of probe devres group */ 352 + struct dentry *debugfs; /* per-client debugfs dir */ 353 353 }; 354 354 #define to_i2c_client(d) container_of(d, struct i2c_client, dev) 355 355 ··· 750 750 int nr; 751 751 char name[48]; 752 752 struct completion dev_released; 753 - 754 - struct mutex userspace_clients_lock; 755 - struct list_head userspace_clients; 756 753 757 754 struct i2c_bus_recovery_info *bus_recovery_info; 758 755 const struct i2c_adapter_quirks *quirks;

-26

include/linux/platform_data/i2c-davinci.h

··· 1 - /* 2 - * DaVinci I2C controller platform_device info 3 - * 4 - * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com> 5 - * 6 - * 2007 (c) MontaVista Software, Inc. This file is licensed under 7 - * the terms of the GNU General Public License version 2. This program 8 - * is licensed "as is" without any warranty of any kind, whether express 9 - * or implied. 10 - */ 11 - 12 - #ifndef __ASM_ARCH_I2C_H 13 - #define __ASM_ARCH_I2C_H 14 - 15 - /* All frequencies are expressed in kHz */ 16 - struct davinci_i2c_platform_data { 17 - unsigned int bus_freq; /* standard bus frequency (kHz) */ 18 - unsigned int bus_delay; /* post-transaction delay (usec) */ 19 - bool gpio_recovery; /* Use GPIO recovery method */ 20 - bool has_pfunc; /* Chip has a ICPFUNC register */ 21 - }; 22 - 23 - /* for board setup code */ 24 - void davinci_init_i2c(struct davinci_i2c_platform_data *); 25 - 26 - #endif /* __ASM_ARCH_I2C_H */

+1 -6

sound/ppc/keywest.c

··· 61 61 return -ENODEV; 62 62 } 63 63 64 - /* 65 - * Let i2c-core delete that device on driver removal. 66 - * This is safe because i2c-core holds the core_lock mutex for us. 67 - */ 68 - list_add_tail(&keywest_ctx->client->detected, 69 - &to_i2c_driver(keywest_ctx->client->dev.driver)->clients); 70 64 return 0; 71 65 } 72 66 ··· 93 99 void snd_pmac_keywest_cleanup(struct pmac_keywest *i2c) 94 100 { 95 101 if (keywest_ctx && keywest_ctx == i2c) { 102 + i2c_unregister_device(keywest_ctx->client); 96 103 i2c_del_driver(&keywest_driver); 97 104 keywest_ctx = NULL; 98 105 }

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