Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'pwm/for-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux
Pull pwm updates from Uwe Kleine-König:
"This time there are very little changes for pwm. There is nothing new,
just a few maintenance cleanups.
The contributors this time around were Krzysztof Kozlowski, Mingwei
Zheng, Philipp Stanner, and Stanislav Jakubek. Thanks!"
* tag 'pwm/for-6.14-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux:
pwm: stm32: Add check for clk_enable()
dt-bindings: pwm: Correct indentation and style in DTS example
pwm: stm32-lp: Add check for clk_enable()
dt-bindings: pwm: marvell,berlin-pwm: Convert from txt to yaml
dt-bindings: pwm: sprd,ums512-pwm: convert to YAML
pwm: Replace deprecated PCI functions
+143
-86
+4
-4
Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
+4
-4
Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml
···
41
41
examples:
42
42
- |
43
43
pwm@44b00000 {
44
-
compatible = "adi,axi-pwmgen-2.00.a";
45
-
reg = <0x44b00000 0x1000>;
46
-
clocks = <&spi_clk>;
47
-
#pwm-cells = <3>;
44
+
compatible = "adi,axi-pwmgen-2.00.a";
45
+
reg = <0x44b00000 0x1000>;
46
+
clocks = <&spi_clk>;
47
+
#pwm-cells = <3>;
48
48
};
+4
-4
Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
+4
-4
Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
···
35
35
examples:
36
36
- |
37
37
pwm: pwm@f0408000 {
38
-
compatible = "brcm,bcm7038-pwm";
39
-
reg = <0xf0408000 0x28>;
40
-
#pwm-cells = <2>;
41
-
clocks = <&upg_fixed>;
38
+
compatible = "brcm,bcm7038-pwm";
39
+
reg = <0xf0408000 0x28>;
40
+
#pwm-cells = <2>;
41
+
clocks = <&upg_fixed>;
42
42
};
+4
-4
Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml
+4
-4
Documentation/devicetree/bindings/pwm/brcm,kona-pwm.yaml
···
43
43
#include <dt-bindings/clock/bcm281xx.h>
44
44
45
45
pwm@3e01a000 {
46
-
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
47
-
reg = <0x3e01a000 0xcc>;
48
-
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
49
-
#pwm-cells = <3>;
46
+
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
47
+
reg = <0x3e01a000 0xcc>;
48
+
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
49
+
#pwm-cells = <3>;
50
50
};
51
51
...
+44
Documentation/devicetree/bindings/pwm/marvell,berlin-pwm.yaml
+44
Documentation/devicetree/bindings/pwm/marvell,berlin-pwm.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pwm/marvell,berlin-pwm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Berlin PWM controller
8
+
9
+
maintainers:
10
+
- Jisheng Zhang <jszhang@kernel.org>
11
+
- Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
12
+
13
+
properties:
14
+
compatible:
15
+
const: marvell,berlin-pwm
16
+
17
+
reg:
18
+
maxItems: 1
19
+
20
+
"#pwm-cells":
21
+
const: 3
22
+
23
+
clocks:
24
+
maxItems: 1
25
+
26
+
required:
27
+
- compatible
28
+
- reg
29
+
- clocks
30
+
31
+
allOf:
32
+
- $ref: pwm.yaml#
33
+
34
+
unevaluatedProperties: false
35
+
36
+
examples:
37
+
- |
38
+
pwm@f7f20000 {
39
+
compatible = "marvell,berlin-pwm";
40
+
reg = <0xf7f20000 0x40>;
41
+
clocks = <&chip_clk 12>;
42
+
#pwm-cells = <3>;
43
+
};
44
+
-17
Documentation/devicetree/bindings/pwm/pwm-berlin.txt
-17
Documentation/devicetree/bindings/pwm/pwm-berlin.txt
···
1
-
Berlin PWM controller
2
-
3
-
Required properties:
4
-
- compatible: should be "marvell,berlin-pwm"
5
-
- reg: physical base address and length of the controller's registers
6
-
- clocks: phandle to the input clock
7
-
- #pwm-cells: should be 3. See pwm.yaml in this directory for a description of
8
-
the cells format.
9
-
10
-
Example:
11
-
12
-
pwm: pwm@f7f20000 {
13
-
compatible = "marvell,berlin-pwm";
14
-
reg = <0xf7f20000 0x40>;
15
-
clocks = <&chip_clk CLKID_CFG>;
16
-
#pwm-cells = <3>;
17
-
}
-40
Documentation/devicetree/bindings/pwm/pwm-sprd.txt
-40
Documentation/devicetree/bindings/pwm/pwm-sprd.txt
···
1
-
Spreadtrum PWM controller
2
-
3
-
Spreadtrum SoCs PWM controller provides 4 PWM channels.
4
-
5
-
Required properties:
6
-
- compatible : Should be "sprd,ums512-pwm".
7
-
- reg: Physical base address and length of the controller's registers.
8
-
- clocks: The phandle and specifier referencing the controller's clocks.
9
-
- clock-names: Should contain following entries:
10
-
"pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
11
-
"enablen": for PWM channel n enable clock (n range: 0 ~ 3).
12
-
- #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
13
-
the cells format.
14
-
15
-
Optional properties:
16
-
- assigned-clocks: Reference to the PWM clock entries.
17
-
- assigned-clock-parents: The phandle of the parent clock of PWM clock.
18
-
19
-
Example:
20
-
pwms: pwm@32260000 {
21
-
compatible = "sprd,ums512-pwm";
22
-
reg = <0 0x32260000 0 0x10000>;
23
-
clock-names = "pwm0", "enable0",
24
-
"pwm1", "enable1",
25
-
"pwm2", "enable2",
26
-
"pwm3", "enable3";
27
-
clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
28
-
<&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
29
-
<&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
30
-
<&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
31
-
assigned-clocks = <&aon_clk CLK_PWM0>,
32
-
<&aon_clk CLK_PWM1>,
33
-
<&aon_clk CLK_PWM2>,
34
-
<&aon_clk CLK_PWM3>;
35
-
assigned-clock-parents = <&ext_26m>,
36
-
<&ext_26m>,
37
-
<&ext_26m>,
38
-
<&ext_26m>;
39
-
#pwm-cells = <2>;
40
-
};
+66
Documentation/devicetree/bindings/pwm/sprd,ums512-pwm.yaml
+66
Documentation/devicetree/bindings/pwm/sprd,ums512-pwm.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/pwm/sprd,ums512-pwm.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: Spreadtrum/Unisoc UMS512 PWM Controller
8
+
9
+
maintainers:
10
+
- Orson Zhai <orsonzhai@gmail.com>
11
+
- Baolin Wang <baolin.wang@linux.alibaba.com>
12
+
- Chunyan Zhang <zhang.lyra@gmail.com>
13
+
14
+
properties:
15
+
compatible:
16
+
const: sprd,ums512-pwm
17
+
18
+
reg:
19
+
maxItems: 1
20
+
21
+
clocks:
22
+
maxItems: 8
23
+
24
+
clock-names:
25
+
items:
26
+
- const: pwm0
27
+
- const: enable0
28
+
- const: pwm1
29
+
- const: enable1
30
+
- const: pwm2
31
+
- const: enable2
32
+
- const: pwm3
33
+
- const: enable3
34
+
35
+
'#pwm-cells':
36
+
const: 2
37
+
38
+
required:
39
+
- compatible
40
+
- reg
41
+
- clocks
42
+
- clock-names
43
+
44
+
allOf:
45
+
- $ref: pwm.yaml#
46
+
47
+
unevaluatedProperties: false
48
+
49
+
examples:
50
+
- |
51
+
#include <dt-bindings/clock/sprd,ums512-clk.h>
52
+
53
+
pwm@32260000 {
54
+
compatible = "sprd,ums512-pwm";
55
+
reg = <0x32260000 0x10000>;
56
+
clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
57
+
<&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
58
+
<&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
59
+
<&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
60
+
clock-names = "pwm0", "enable0",
61
+
"pwm1", "enable1",
62
+
"pwm2", "enable2",
63
+
"pwm3", "enable3";
64
+
#pwm-cells = <2>;
65
+
};
66
+
...
+5
-9
drivers/pwm/pwm-dwc.c
+5
-9
drivers/pwm/pwm-dwc.c
···
66
66
67
67
pci_set_master(pci);
68
68
69
-
ret = pcim_iomap_regions(pci, BIT(0), pci_name(pci));
70
-
if (ret)
71
-
return dev_err_probe(dev, ret, "Failed to iomap PCI BAR\n");
72
-
73
69
info = (const struct dwc_pwm_info *)id->driver_data;
74
70
ddata = devm_kzalloc(dev, struct_size(ddata, chips, info->nr), GFP_KERNEL);
75
71
if (!ddata)
76
72
return -ENOMEM;
77
73
78
-
/*
79
-
* No need to check for pcim_iomap_table() failure,
80
-
* pcim_iomap_regions() already does it for us.
81
-
*/
82
-
ddata->io_base = pcim_iomap_table(pci)[0];
74
+
ddata->io_base = pcim_iomap_region(pci, 0, "pwm-dwc");
75
+
if (IS_ERR(ddata->io_base))
76
+
return dev_err_probe(dev, PTR_ERR(ddata->io_base),
77
+
"Failed to request / iomap PCI BAR\n");
78
+
83
79
ddata->info = info;
84
80
85
81
for (idx = 0; idx < ddata->info->nr; idx++) {
+5
-4
drivers/pwm/pwm-lpss-pci.c
+5
-4
drivers/pwm/pwm-lpss-pci.c
···
18
18
const struct pci_device_id *id)
19
19
{
20
20
const struct pwm_lpss_boardinfo *info;
21
+
void __iomem *io_base;
21
22
struct pwm_chip *chip;
22
23
int err;
23
24
···
26
25
if (err < 0)
27
26
return err;
28
27
29
-
err = pcim_iomap_regions(pdev, BIT(0), pci_name(pdev));
30
-
if (err)
31
-
return err;
28
+
io_base = pcim_iomap_region(pdev, 0, "pwm-lpss");
29
+
if (IS_ERR(io_base))
30
+
return PTR_ERR(io_base);
32
31
33
32
info = (struct pwm_lpss_boardinfo *)id->driver_data;
34
-
chip = devm_pwm_lpss_probe(&pdev->dev, pcim_iomap_table(pdev)[0], info);
33
+
chip = devm_pwm_lpss_probe(&pdev->dev, io_base, info);
35
34
if (IS_ERR(chip))
36
35
return PTR_ERR(chip);
37
36
+6
-2
drivers/pwm/pwm-stm32-lp.c
+6
-2
drivers/pwm/pwm-stm32-lp.c
···
167
167
regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
168
168
state->enabled = !!FIELD_GET(STM32_LPTIM_ENABLE, val);
169
169
/* Keep PWM counter clock refcount in sync with PWM initial state */
170
-
if (state->enabled)
171
-
clk_enable(priv->clk);
170
+
if (state->enabled) {
171
+
int ret = clk_enable(priv->clk);
172
+
173
+
if (ret)
174
+
return ret;
175
+
}
172
176
173
177
regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val);
174
178
presc = FIELD_GET(STM32_LPTIM_PRESC, val);
+5
-2
drivers/pwm/pwm-stm32.c
+5
-2
drivers/pwm/pwm-stm32.c
···
858
858
chip->ops = &stm32pwm_ops;
859
859
860
860
/* Initialize clock refcount to number of enabled PWM channels. */
861
-
for (i = 0; i < num_enabled; i++)
862
-
clk_enable(priv->clk);
861
+
for (i = 0; i < num_enabled; i++) {
862
+
ret = clk_enable(priv->clk);
863
+
if (ret)
864
+
return ret;
865
+
}
863
866
864
867
ret = devm_pwmchip_add(dev, chip);
865
868
if (ret < 0)