tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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phy: cadence-torrent: Constify struct cdns_reg_pairs

'struct cdns_reg_pairs' is not modified in this driver.

Constifying this structure moves some data to a read-only section, so
increase overall security.

On a x86_64, with allmodconfig:
Before:
======
text data bss dec hex filename
78154 20222 16 98392 18058 drivers/phy/cadence/phy-cadence-torrent.o

After:
=====
text data bss dec hex filename
85130 13214 16 98360 18038 drivers/phy/cadence/phy-cadence-torrent.o

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/803684a6f0c24d7e091dc8d285dd49c6fd31a010.1720718240.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Christophe JAILLET and committed by
Vinod Koul ad365481 b52a38ab

+84 -84
+84 -84
drivers/phy/cadence/phy-cadence-torrent.c
··· 422 422 }; 423 423 424 424 struct cdns_torrent_vals { 425 - struct cdns_reg_pairs *reg_pairs; 425 + const struct cdns_reg_pairs *reg_pairs; 426 426 u32 num_regs; 427 427 }; 428 428 ··· 2315 2315 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; 2316 2316 struct cdns_torrent_vals *phy_pma_cmn_vals; 2317 2317 struct cdns_torrent_vals *pcs_cmn_vals; 2318 - struct cdns_reg_pairs *reg_pairs; 2318 + const struct cdns_reg_pairs *reg_pairs; 2319 2319 struct regmap *regmap; 2320 2320 u32 num_regs; 2321 2321 int i, j; ··· 2471 2471 enum cdns_torrent_phy_type phy_t1, phy_t2; 2472 2472 struct cdns_torrent_vals *phy_pma_cmn_vals; 2473 2473 struct cdns_torrent_vals *pcs_cmn_vals; 2474 + const struct cdns_reg_pairs *reg_pairs; 2474 2475 int i, j, node, mlane, num_lanes, ret; 2475 - struct cdns_reg_pairs *reg_pairs; 2476 2476 enum cdns_torrent_ssc_mode ssc; 2477 2477 struct regmap *regmap; 2478 2478 u32 num_regs; ··· 3079 3079 } 3080 3080 3081 3081 /* SGMII and QSGMII link configuration */ 3082 - static struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = { 3082 + static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = { 3083 3083 {0x0002, PHY_PLL_CFG} 3084 3084 }; 3085 3085 3086 - static struct cdns_reg_pairs sgmii_qsgmii_xcvr_diag_ln_regs[] = { 3086 + static const struct cdns_reg_pairs sgmii_qsgmii_xcvr_diag_ln_regs[] = { 3087 3087 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3088 3088 {0x0113, XCVR_DIAG_PLLDRC_CTRL} 3089 3089 }; ··· 3155 3155 cdns_torrent_phy_resume_noirq); 3156 3156 3157 3157 /* USB and DP link configuration */ 3158 - static struct cdns_reg_pairs usb_dp_link_cmn_regs[] = { 3158 + static const struct cdns_reg_pairs usb_dp_link_cmn_regs[] = { 3159 3159 {0x0002, PHY_PLL_CFG}, 3160 3160 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3161 3161 }; 3162 3162 3163 - static struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = { 3163 + static const struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = { 3164 3164 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3165 3165 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3166 3166 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3167 3167 }; 3168 3168 3169 - static struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = { 3169 + static const struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = { 3170 3170 {0x0001, XCVR_DIAG_HSCLK_SEL}, 3171 3171 {0x0009, XCVR_DIAG_PLLDRC_CTRL} 3172 3172 }; ··· 3187 3187 }; 3188 3188 3189 3189 /* USXGMII and SGMII/QSGMII link configuration */ 3190 - static struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = { 3190 + static const struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = { 3191 3191 {0x0002, PHY_PLL_CFG}, 3192 3192 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3193 3193 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3194 3194 }; 3195 3195 3196 - static struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = { 3196 + static const struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = { 3197 3197 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3198 3198 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3199 3199 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3200 3200 }; 3201 3201 3202 - static struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = { 3202 + static const struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = { 3203 3203 {0x0111, XCVR_DIAG_HSCLK_SEL}, 3204 3204 {0x0103, XCVR_DIAG_HSCLK_DIV}, 3205 3205 {0x0A9B, XCVR_DIAG_PLLDRC_CTRL} ··· 3221 3221 }; 3222 3222 3223 3223 /* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */ 3224 - static struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = { 3224 + static const struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = { 3225 3225 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0}, 3226 3226 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0}, 3227 3227 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR}, ··· 3239 3239 }; 3240 3240 3241 3241 /* Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */ 3242 - static struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = { 3242 + static const struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = { 3243 3243 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3244 3244 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3245 3245 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, ··· 3254 3254 }; 3255 3255 3256 3256 /* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */ 3257 - static struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = { 3257 + static const struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = { 3258 3258 {0x0014, CMN_SSM_BIAS_TMR}, 3259 3259 {0x0028, CMN_PLLSM0_PLLPRE_TMR}, 3260 3260 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR}, ··· 3286 3286 }; 3287 3287 3288 3288 /* TI J7200, Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */ 3289 - static struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = { 3289 + static const struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = { 3290 3290 {0x0028, CMN_PLLSM1_PLLPRE_TMR}, 3291 3291 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR}, 3292 3292 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, ··· 3303 3303 }; 3304 3304 3305 3305 /* PCIe and USXGMII link configuration */ 3306 - static struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = { 3306 + static const struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = { 3307 3307 {0x0003, PHY_PLL_CFG}, 3308 3308 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3309 3309 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3310 3310 {0x0400, CMN_PDIAG_PLL1_CLK_SEL_M0} 3311 3311 }; 3312 3312 3313 - static struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = { 3313 + static const struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = { 3314 3314 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3315 3315 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3316 3316 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3317 3317 }; 3318 3318 3319 - static struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = { 3319 + static const struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = { 3320 3320 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3321 3321 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3322 3322 {0x0089, XCVR_DIAG_PLLDRC_CTRL} ··· 3340 3340 /* 3341 3341 * Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC 3342 3342 */ 3343 - static struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = { 3343 + static const struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = { 3344 3344 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3345 3345 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0}, 3346 3346 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0}, ··· 3355 3355 {0x007F, CMN_TXPDCAL_TUNE} 3356 3356 }; 3357 3357 3358 - static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3358 + static const struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3359 3359 {0x00F3, TX_PSC_A0}, 3360 3360 {0x04A2, TX_PSC_A2}, 3361 3361 {0x04A2, TX_PSC_A3 }, ··· 3363 3363 {0x0000, XCVR_DIAG_PSC_OVRD} 3364 3364 }; 3365 3365 3366 - static struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3366 + static const struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3367 3367 {0x091D, RX_PSC_A0}, 3368 3368 {0x0900, RX_PSC_A2}, 3369 3369 {0x0100, RX_PSC_A3}, ··· 3397 3397 }; 3398 3398 3399 3399 /* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */ 3400 - static struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = { 3400 + static const struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = { 3401 3401 {0x0040, PHY_PMA_CMN_CTRL1}, 3402 3402 }; 3403 3403 ··· 3407 3407 }; 3408 3408 3409 3409 /* Single USXGMII link configuration */ 3410 - static struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = { 3410 + static const struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = { 3411 3411 {0x0000, PHY_PLL_CFG}, 3412 3412 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0} 3413 3413 }; 3414 3414 3415 - static struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = { 3415 + static const struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = { 3416 3416 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3417 3417 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3418 3418 {0x0001, XCVR_DIAG_PLLDRC_CTRL} ··· 3429 3429 }; 3430 3430 3431 3431 /* Single link USXGMII, 156.25 MHz Ref clk, no SSC */ 3432 - static struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = { 3432 + static const struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = { 3433 3433 {0x0014, CMN_SSM_BIAS_TMR}, 3434 3434 {0x0028, CMN_PLLSM0_PLLPRE_TMR}, 3435 3435 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR}, ··· 3467 3467 {0x0138, CMN_PLL1_LOCK_PLLCNT_START} 3468 3468 }; 3469 3469 3470 - static struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3470 + static const struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3471 3471 {0x07A2, TX_RCVDET_ST_TMR}, 3472 3472 {0x00F3, TX_PSC_A0}, 3473 3473 {0x04A2, TX_PSC_A2}, ··· 3476 3476 {0x0000, XCVR_DIAG_PSC_OVRD} 3477 3477 }; 3478 3478 3479 - static struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3479 + static const struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3480 3480 {0x0014, RX_SDCAL0_INIT_TMR}, 3481 3481 {0x0062, RX_SDCAL0_ITER_TMR}, 3482 3482 {0x0014, RX_SDCAL1_INIT_TMR}, ··· 3514 3514 }; 3515 3515 3516 3516 /* PCIe and DP link configuration */ 3517 - static struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = { 3517 + static const struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = { 3518 3518 {0x0003, PHY_PLL_CFG}, 3519 3519 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3520 3520 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1} 3521 3521 }; 3522 3522 3523 - static struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = { 3523 + static const struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = { 3524 3524 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3525 3525 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3526 3526 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3527 3527 }; 3528 3528 3529 - static struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = { 3529 + static const struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = { 3530 3530 {0x0001, XCVR_DIAG_HSCLK_SEL}, 3531 3531 {0x0009, XCVR_DIAG_PLLDRC_CTRL} 3532 3532 }; ··· 3547 3547 }; 3548 3548 3549 3549 /* DP Multilink, 100 MHz Ref clk, no SSC */ 3550 - static struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = { 3550 + static const struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = { 3551 3551 {0x007F, CMN_TXPUCAL_TUNE}, 3552 3552 {0x007F, CMN_TXPDCAL_TUNE} 3553 3553 }; 3554 3554 3555 - static struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = { 3555 + static const struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = { 3556 3556 {0x00FB, TX_PSC_A0}, 3557 3557 {0x04AA, TX_PSC_A2}, 3558 3558 {0x04AA, TX_PSC_A3}, 3559 3559 {0x000F, XCVR_DIAG_BIDI_CTRL} 3560 3560 }; 3561 3561 3562 - static struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = { 3562 + static const struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = { 3563 3563 {0x0000, RX_PSC_A0}, 3564 3564 {0x0000, RX_PSC_A2}, 3565 3565 {0x0000, RX_PSC_A3}, ··· 3585 3585 }; 3586 3586 3587 3587 /* Single DisplayPort(DP) link configuration */ 3588 - static struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { 3588 + static const struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { 3589 3589 {0x0000, PHY_PLL_CFG}, 3590 3590 }; 3591 3591 3592 - static struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { 3592 + static const struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { 3593 3593 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3594 3594 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3595 3595 }; ··· 3605 3605 }; 3606 3606 3607 3607 /* Single DP, 19.2 MHz Ref clk, no SSC */ 3608 - static struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { 3608 + static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { 3609 3609 {0x0014, CMN_SSM_BIAS_TMR}, 3610 3610 {0x0027, CMN_PLLSM0_PLLPRE_TMR}, 3611 3611 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR}, ··· 3642 3642 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3643 3643 }; 3644 3644 3645 - static struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { 3645 + static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { 3646 3646 {0x0780, TX_RCVDET_ST_TMR}, 3647 3647 {0x00FB, TX_PSC_A0}, 3648 3648 {0x04AA, TX_PSC_A2}, ··· 3650 3650 {0x000F, XCVR_DIAG_BIDI_CTRL} 3651 3651 }; 3652 3652 3653 - static struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { 3653 + static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { 3654 3654 {0x0000, RX_PSC_A0}, 3655 3655 {0x0000, RX_PSC_A2}, 3656 3656 {0x0000, RX_PSC_A3}, ··· 3676 3676 }; 3677 3677 3678 3678 /* Single DP, 25 MHz Ref clk, no SSC */ 3679 - static struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { 3679 + static const struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { 3680 3680 {0x0019, CMN_SSM_BIAS_TMR}, 3681 3681 {0x0032, CMN_PLLSM0_PLLPRE_TMR}, 3682 3682 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR}, ··· 3713 3713 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3714 3714 }; 3715 3715 3716 - static struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { 3716 + static const struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { 3717 3717 {0x09C4, TX_RCVDET_ST_TMR}, 3718 3718 {0x00FB, TX_PSC_A0}, 3719 3719 {0x04AA, TX_PSC_A2}, ··· 3721 3721 {0x000F, XCVR_DIAG_BIDI_CTRL} 3722 3722 }; 3723 3723 3724 - static struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { 3724 + static const struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { 3725 3725 {0x0000, RX_PSC_A0}, 3726 3726 {0x0000, RX_PSC_A2}, 3727 3727 {0x0000, RX_PSC_A3}, ··· 3747 3747 }; 3748 3748 3749 3749 /* Single DP, 100 MHz Ref clk, no SSC */ 3750 - static struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { 3750 + static const struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { 3751 3751 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3752 3752 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3753 3753 }; 3754 3754 3755 - static struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { 3755 + static const struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { 3756 3756 {0x00FB, TX_PSC_A0}, 3757 3757 {0x04AA, TX_PSC_A2}, 3758 3758 {0x04AA, TX_PSC_A3}, 3759 3759 {0x000F, XCVR_DIAG_BIDI_CTRL} 3760 3760 }; 3761 3761 3762 - static struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { 3762 + static const struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { 3763 3763 {0x0000, RX_PSC_A0}, 3764 3764 {0x0000, RX_PSC_A2}, 3765 3765 {0x0000, RX_PSC_A3}, ··· 3785 3785 }; 3786 3786 3787 3787 /* USB and SGMII/QSGMII link configuration */ 3788 - static struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { 3788 + static const struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { 3789 3789 {0x0002, PHY_PLL_CFG}, 3790 3790 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3791 3791 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3792 3792 }; 3793 3793 3794 - static struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { 3794 + static const struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { 3795 3795 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3796 3796 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3797 3797 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3798 3798 }; 3799 3799 3800 - static struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { 3800 + static const struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { 3801 3801 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3802 3802 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3803 3803 {0x009B, XCVR_DIAG_PLLDRC_CTRL} ··· 3819 3819 }; 3820 3820 3821 3821 /* PCIe and USB Unique SSC link configuration */ 3822 - static struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { 3822 + static const struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { 3823 3823 {0x0003, PHY_PLL_CFG}, 3824 3824 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3825 3825 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3826 3826 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0} 3827 3827 }; 3828 3828 3829 - static struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { 3829 + static const struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { 3830 3830 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3831 3831 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3832 3832 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3833 3833 }; 3834 3834 3835 - static struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { 3835 + static const struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { 3836 3836 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3837 3837 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3838 3838 {0x00C9, XCVR_DIAG_PLLDRC_CTRL} ··· 3854 3854 }; 3855 3855 3856 3856 /* USB 100 MHz Ref clk, internal SSC */ 3857 - static struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { 3857 + static const struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { 3858 3858 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3859 3859 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 3860 3860 {0x0004, CMN_PLL1_DSM_DIAG_M0}, ··· 3913 3913 }; 3914 3914 3915 3915 /* Single USB link configuration */ 3916 - static struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { 3916 + static const struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { 3917 3917 {0x0000, PHY_PLL_CFG}, 3918 3918 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3919 3919 }; 3920 3920 3921 - static struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { 3921 + static const struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { 3922 3922 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3923 3923 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3924 3924 {0x0041, XCVR_DIAG_PLLDRC_CTRL} ··· 3935 3935 }; 3936 3936 3937 3937 /* USB PHY PCS common configuration */ 3938 - static struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { 3938 + static const struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { 3939 3939 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, 3940 3940 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, 3941 3941 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} ··· 3947 3947 }; 3948 3948 3949 3949 /* USB 100 MHz Ref clk, no SSC */ 3950 - static struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { 3950 + static const struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { 3951 3951 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3952 3952 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3953 3953 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, ··· 3962 3962 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), 3963 3963 }; 3964 3964 3965 - static struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { 3965 + static const struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { 3966 3966 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 3967 3967 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 3968 3968 {0x007F, CMN_TXPUCAL_TUNE}, 3969 3969 {0x007F, CMN_TXPDCAL_TUNE} 3970 3970 }; 3971 3971 3972 - static struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { 3972 + static const struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { 3973 3973 {0x02FF, TX_PSC_A0}, 3974 3974 {0x06AF, TX_PSC_A1}, 3975 3975 {0x06AE, TX_PSC_A2}, ··· 3979 3979 {0x0003, XCVR_DIAG_PSC_OVRD} 3980 3980 }; 3981 3981 3982 - static struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { 3982 + static const struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { 3983 3983 {0x0D1D, RX_PSC_A0}, 3984 3984 {0x0D1D, RX_PSC_A1}, 3985 3985 {0x0D00, RX_PSC_A2}, ··· 4018 4018 }; 4019 4019 4020 4020 /* Single link USB, 100 MHz Ref clk, internal SSC */ 4021 - static struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { 4021 + static const struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { 4022 4022 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4023 4023 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4024 4024 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, ··· 4065 4065 }; 4066 4066 4067 4067 /* PCIe and SGMII/QSGMII Unique SSC link configuration */ 4068 - static struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { 4068 + static const struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { 4069 4069 {0x0003, PHY_PLL_CFG}, 4070 4070 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 4071 4071 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 4072 4072 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 4073 4073 }; 4074 4074 4075 - static struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { 4075 + static const struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { 4076 4076 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4077 4077 {0x0001, XCVR_DIAG_HSCLK_DIV}, 4078 4078 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 4079 4079 }; 4080 4080 4081 - static struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { 4081 + static const struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { 4082 4082 {0x0011, XCVR_DIAG_HSCLK_SEL}, 4083 4083 {0x0003, XCVR_DIAG_HSCLK_DIV}, 4084 4084 {0x009B, XCVR_DIAG_PLLDRC_CTRL} ··· 4100 4100 }; 4101 4101 4102 4102 /* SGMII 100 MHz Ref clk, no SSC */ 4103 - static struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { 4103 + static const struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { 4104 4104 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4105 4105 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4106 4106 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, ··· 4113 4113 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), 4114 4114 }; 4115 4115 4116 - static struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { 4116 + static const struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { 4117 4117 {0x007F, CMN_TXPUCAL_TUNE}, 4118 4118 {0x007F, CMN_TXPDCAL_TUNE} 4119 4119 }; 4120 4120 4121 - static struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { 4121 + static const struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { 4122 4122 {0x00F3, TX_PSC_A0}, 4123 4123 {0x04A2, TX_PSC_A2}, 4124 4124 {0x04A2, TX_PSC_A3}, ··· 4127 4127 {0x0002, XCVR_DIAG_PSC_OVRD} 4128 4128 }; 4129 4129 4130 - static struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { 4130 + static const struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { 4131 4131 {0x00F3, TX_PSC_A0}, 4132 4132 {0x04A2, TX_PSC_A2}, 4133 4133 {0x04A2, TX_PSC_A3}, ··· 4137 4137 {0x4000, XCVR_DIAG_RXCLK_CTRL} 4138 4138 }; 4139 4139 4140 - static struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { 4140 + static const struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { 4141 4141 {0x091D, RX_PSC_A0}, 4142 4142 {0x0900, RX_PSC_A2}, 4143 4143 {0x0100, RX_PSC_A3}, ··· 4176 4176 }; 4177 4177 4178 4178 /* TI J7200, multilink SGMII */ 4179 - static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = { 4179 + static const struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = { 4180 4180 {0x07A2, TX_RCVDET_ST_TMR}, 4181 4181 {0x00F3, TX_PSC_A0}, 4182 4182 {0x04A2, TX_PSC_A2}, ··· 4192 4192 .num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_tx_ln_regs), 4193 4193 }; 4194 4194 4195 - static struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = { 4195 + static const struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = { 4196 4196 {0x0014, RX_SDCAL0_INIT_TMR}, 4197 4197 {0x0062, RX_SDCAL0_ITER_TMR}, 4198 4198 {0x0014, RX_SDCAL1_INIT_TMR}, ··· 4220 4220 }; 4221 4221 4222 4222 /* SGMII 100 MHz Ref clk, internal SSC */ 4223 - static struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { 4223 + static const struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { 4224 4224 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4225 4225 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4226 4226 {0x0004, CMN_PLL1_DSM_DIAG_M0}, ··· 4277 4277 }; 4278 4278 4279 4279 /* QSGMII 100 MHz Ref clk, no SSC */ 4280 - static struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { 4280 + static const struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { 4281 4281 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4282 4282 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4283 4283 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, ··· 4290 4290 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), 4291 4291 }; 4292 4292 4293 - static struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { 4293 + static const struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { 4294 4294 {0x007F, CMN_TXPUCAL_TUNE}, 4295 4295 {0x007F, CMN_TXPDCAL_TUNE} 4296 4296 }; 4297 4297 4298 - static struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { 4298 + static const struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { 4299 4299 {0x00F3, TX_PSC_A0}, 4300 4300 {0x04A2, TX_PSC_A2}, 4301 4301 {0x04A2, TX_PSC_A3}, ··· 4305 4305 {0x0002, XCVR_DIAG_PSC_OVRD} 4306 4306 }; 4307 4307 4308 - static struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { 4308 + static const struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { 4309 4309 {0x00F3, TX_PSC_A0}, 4310 4310 {0x04A2, TX_PSC_A2}, 4311 4311 {0x04A2, TX_PSC_A3}, ··· 4316 4316 {0x4000, XCVR_DIAG_RXCLK_CTRL} 4317 4317 }; 4318 4318 4319 - static struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { 4319 + static const struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { 4320 4320 {0x091D, RX_PSC_A0}, 4321 4321 {0x0900, RX_PSC_A2}, 4322 4322 {0x0100, RX_PSC_A3}, ··· 4355 4355 }; 4356 4356 4357 4357 /* TI J7200, multilink QSGMII */ 4358 - static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = { 4358 + static const struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = { 4359 4359 {0x07A2, TX_RCVDET_ST_TMR}, 4360 4360 {0x00F3, TX_PSC_A0}, 4361 4361 {0x04A2, TX_PSC_A2}, ··· 4372 4372 .num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_tx_ln_regs), 4373 4373 }; 4374 4374 4375 - static struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = { 4375 + static const struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = { 4376 4376 {0x0014, RX_SDCAL0_INIT_TMR}, 4377 4377 {0x0062, RX_SDCAL0_ITER_TMR}, 4378 4378 {0x0014, RX_SDCAL1_INIT_TMR}, ··· 4400 4400 }; 4401 4401 4402 4402 /* QSGMII 100 MHz Ref clk, internal SSC */ 4403 - static struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { 4403 + static const struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { 4404 4404 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4405 4405 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4406 4406 {0x0004, CMN_PLL1_DSM_DIAG_M0}, ··· 4457 4457 }; 4458 4458 4459 4459 /* Single SGMII/QSGMII link configuration */ 4460 - static struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { 4460 + static const struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { 4461 4461 {0x0000, PHY_PLL_CFG}, 4462 4462 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} 4463 4463 }; 4464 4464 4465 - static struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { 4465 + static const struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { 4466 4466 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4467 4467 {0x0003, XCVR_DIAG_HSCLK_DIV}, 4468 4468 {0x0013, XCVR_DIAG_PLLDRC_CTRL} ··· 4479 4479 }; 4480 4480 4481 4481 /* Multi link PCIe, 100 MHz Ref clk, internal SSC */ 4482 - static struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { 4482 + static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { 4483 4483 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4484 4484 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4485 4485 {0x0004, CMN_PLL1_DSM_DIAG_M0}, ··· 4534 4534 }; 4535 4535 4536 4536 /* Single link PCIe, 100 MHz Ref clk, internal SSC */ 4537 - static struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { 4537 + static const struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { 4538 4538 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4539 4539 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4540 4540 {0x0004, CMN_PLL1_DSM_DIAG_M0}, ··· 4589 4589 }; 4590 4590 4591 4591 /* PCIe, 100 MHz Ref clk, no SSC & external SSC */ 4592 - static struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { 4592 + static const struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { 4593 4593 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4594 4594 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4595 4595 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} 4596 4596 }; 4597 4597 4598 - static struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { 4598 + static const struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { 4599 4599 {0x0019, RX_REE_TAP1_CLIP}, 4600 4600 {0x0019, RX_REE_TAP2TON_CLIP}, 4601 4601 {0x0001, RX_DIAG_ACYA}