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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: camcc-sm8550: Move PLL & clk configuration to really probe
Camera PLLs on SM8550 require both MMCX and MXC rails to be kept ON to
configure the PLLs properly. Hence move runtime power management, PLL
configuration and enabling critical clocks to qcom_cc_really_probe() which
ensures all required power domains are in enabled state before configuring
the PLLs or enabling the clocks.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-10-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Jagadeesh Kona
and committed by
Bjorn Andersson
adb50c76
eb65d754
+44
-41
+44
-41
drivers/clk/qcom/camcc-sm8550.c
+44
-41
drivers/clk/qcom/camcc-sm8550.c
···
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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-
#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm8550-camcc.h>
···
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static struct clk_alpha_pll cam_cc_pll0 = {
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.offset = 0x0,
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+
.config = &cam_cc_pll0_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll1 = {
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.offset = 0x1000,
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.config = &cam_cc_pll1_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll2 = {
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.offset = 0x2000,
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.config = &cam_cc_pll2_config,
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.vco_table = rivian_ole_vco,
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.num_vco = ARRAY_SIZE(rivian_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
···
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static struct clk_alpha_pll cam_cc_pll3 = {
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.offset = 0x3000,
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.config = &cam_cc_pll3_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll4 = {
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.offset = 0x4000,
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.config = &cam_cc_pll4_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll5 = {
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.offset = 0x5000,
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+
.config = &cam_cc_pll5_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll6 = {
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.offset = 0x6000,
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.config = &cam_cc_pll6_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll7 = {
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.offset = 0x7000,
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.config = &cam_cc_pll7_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll8 = {
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.offset = 0x8000,
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.config = &cam_cc_pll8_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll9 = {
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.offset = 0x9000,
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.config = &cam_cc_pll9_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll10 = {
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.offset = 0xa000,
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.config = &cam_cc_pll10_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll11 = {
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.offset = 0xb000,
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.config = &cam_cc_pll11_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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static struct clk_alpha_pll cam_cc_pll12 = {
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.offset = 0xc000,
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.config = &cam_cc_pll12_config,
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.vco_table = lucid_ole_vco,
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.num_vco = ARRAY_SIZE(lucid_ole_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
···
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[CAM_CC_SFE_1_BCR] = { 0x133dc },
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};
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static struct clk_alpha_pll *cam_cc_sm8550_plls[] = {
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&cam_cc_pll0,
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&cam_cc_pll1,
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&cam_cc_pll2,
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&cam_cc_pll3,
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&cam_cc_pll4,
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&cam_cc_pll5,
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&cam_cc_pll6,
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&cam_cc_pll7,
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&cam_cc_pll8,
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&cam_cc_pll9,
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&cam_cc_pll10,
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&cam_cc_pll11,
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&cam_cc_pll12,
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};
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static u32 cam_cc_sm8550_critical_cbcrs[] = {
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0x1419c, /* CAM_CC_GDSC_CLK */
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0x142cc, /* CAM_CC_SLEEP_CLK */
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};
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static const struct regmap_config cam_cc_sm8550_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x16320,
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.fast_io = true,
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};
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static struct qcom_cc_driver_data cam_cc_sm8550_driver_data = {
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.alpha_plls = cam_cc_sm8550_plls,
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.num_alpha_plls = ARRAY_SIZE(cam_cc_sm8550_plls),
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.clk_cbcrs = cam_cc_sm8550_critical_cbcrs,
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.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8550_critical_cbcrs),
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};
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static const struct qcom_cc_desc cam_cc_sm8550_desc = {
···
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.num_resets = ARRAY_SIZE(cam_cc_sm8550_resets),
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.gdscs = cam_cc_sm8550_gdscs,
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.num_gdscs = ARRAY_SIZE(cam_cc_sm8550_gdscs),
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.use_rpm = true,
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.driver_data = &cam_cc_sm8550_driver_data,
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};
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static const struct of_device_id cam_cc_sm8550_match_table[] = {
···
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static int cam_cc_sm8550_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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ret = devm_pm_runtime_enable(&pdev->dev);
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if (ret)
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return ret;
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ret = pm_runtime_resume_and_get(&pdev->dev);
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if (ret)
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return ret;
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regmap = qcom_cc_map(pdev, &cam_cc_sm8550_desc);
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if (IS_ERR(regmap)) {
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pm_runtime_put(&pdev->dev);
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return PTR_ERR(regmap);
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}
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clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
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clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll11, regmap, &cam_cc_pll11_config);
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clk_lucid_ole_pll_configure(&cam_cc_pll12, regmap, &cam_cc_pll12_config);
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/* Keep some clocks always-on */
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qcom_branch_set_clk_en(regmap, 0x1419c); /* CAM_CC_GDSC_CLK */
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qcom_branch_set_clk_en(regmap, 0x142cc); /* CAM_CC_SLEEP_CLK */
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ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8550_desc, regmap);
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pm_runtime_put(&pdev->dev);
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return ret;
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return qcom_cc_probe(pdev, &cam_cc_sm8550_desc);
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}
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static struct platform_driver cam_cc_sm8550_driver = {