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clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe

Camera PLLs on SM8450/SM8475 require both MMCX and MXC rails to be
kept ON to configure the PLLs properly. Hence move runtime power
management, PLL configuration and enable critical clocks to
qcom_cc_really_probe() which ensures all required power domains are in
enabled state before configuring the PLLs or enabling the clocks.

This change also removes the modelling for cam_cc_gdsc_clk and keeps it
always ON from probe since using CLK_IS_CRITICAL will prevent the clock
controller associated power domains from collapsing due to clock framework
invoking clk_pm_runtime_get() during prepare.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20250530-videocc-pll-multi-pd-voting-v5-9-02303b3a582d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Jagadeesh Kona and committed by
Bjorn Andersson eb65d754 a9dc2cc7

+44 -45
+44 -45
drivers/clk/qcom/camcc-sm8450.c
··· 86 86 87 87 static struct clk_alpha_pll cam_cc_pll0 = { 88 88 .offset = 0x0, 89 + .config = &cam_cc_pll0_config, 89 90 .vco_table = lucid_evo_vco, 90 91 .num_vco = ARRAY_SIZE(lucid_evo_vco), 91 92 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 192 191 193 192 static struct clk_alpha_pll cam_cc_pll1 = { 194 193 .offset = 0x1000, 194 + .config = &cam_cc_pll1_config, 195 195 .vco_table = lucid_evo_vco, 196 196 .num_vco = ARRAY_SIZE(lucid_evo_vco), 197 197 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 259 257 260 258 static struct clk_alpha_pll cam_cc_pll2 = { 261 259 .offset = 0x2000, 260 + .config = &cam_cc_pll2_config, 262 261 .vco_table = rivian_evo_vco, 263 262 .num_vco = ARRAY_SIZE(rivian_evo_vco), 264 263 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], ··· 299 296 300 297 static struct clk_alpha_pll cam_cc_pll3 = { 301 298 .offset = 0x3000, 299 + .config = &cam_cc_pll3_config, 302 300 .vco_table = lucid_evo_vco, 303 301 .num_vco = ARRAY_SIZE(lucid_evo_vco), 304 302 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 372 368 373 369 static struct clk_alpha_pll cam_cc_pll4 = { 374 370 .offset = 0x4000, 371 + .config = &cam_cc_pll4_config, 375 372 .vco_table = lucid_evo_vco, 376 373 .num_vco = ARRAY_SIZE(lucid_evo_vco), 377 374 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 445 440 446 441 static struct clk_alpha_pll cam_cc_pll5 = { 447 442 .offset = 0x5000, 443 + .config = &cam_cc_pll5_config, 448 444 .vco_table = lucid_evo_vco, 449 445 .num_vco = ARRAY_SIZE(lucid_evo_vco), 450 446 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 518 512 519 513 static struct clk_alpha_pll cam_cc_pll6 = { 520 514 .offset = 0x6000, 515 + .config = &cam_cc_pll6_config, 521 516 .vco_table = lucid_evo_vco, 522 517 .num_vco = ARRAY_SIZE(lucid_evo_vco), 523 518 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 591 584 592 585 static struct clk_alpha_pll cam_cc_pll7 = { 593 586 .offset = 0x7000, 587 + .config = &cam_cc_pll7_config, 594 588 .vco_table = lucid_evo_vco, 595 589 .num_vco = ARRAY_SIZE(lucid_evo_vco), 596 590 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 664 656 665 657 static struct clk_alpha_pll cam_cc_pll8 = { 666 658 .offset = 0x8000, 659 + .config = &cam_cc_pll8_config, 667 660 .vco_table = lucid_evo_vco, 668 661 .num_vco = ARRAY_SIZE(lucid_evo_vco), 669 662 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], ··· 1482 1473 .num_parents = ARRAY_SIZE(cam_cc_parent_data_9_ao), 1483 1474 .flags = CLK_SET_RATE_PARENT, 1484 1475 .ops = &clk_rcg2_ops, 1485 - }, 1486 - }; 1487 - 1488 - static struct clk_branch cam_cc_gdsc_clk = { 1489 - .halt_reg = 0x1320c, 1490 - .halt_check = BRANCH_HALT, 1491 - .clkr = { 1492 - .enable_reg = 0x1320c, 1493 - .enable_mask = BIT(0), 1494 - .hw.init = &(const struct clk_init_data) { 1495 - .name = "cam_cc_gdsc_clk", 1496 - .parent_hws = (const struct clk_hw*[]) { 1497 - &cam_cc_xo_clk_src.clkr.hw, 1498 - }, 1499 - .num_parents = 1, 1500 - .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 1501 - .ops = &clk_branch2_ops, 1502 - }, 1503 1476 }, 1504 1477 }; 1505 1478 ··· 2810 2819 [CAM_CC_CSIPHY4_CLK] = &cam_cc_csiphy4_clk.clkr, 2811 2820 [CAM_CC_CSIPHY5_CLK] = &cam_cc_csiphy5_clk.clkr, 2812 2821 [CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr, 2813 - [CAM_CC_GDSC_CLK] = &cam_cc_gdsc_clk.clkr, 2814 2822 [CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr, 2815 2823 [CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr, 2816 2824 [CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr, ··· 2901 2911 [CAM_CC_SBI_BCR] = { 0x100cc }, 2902 2912 [CAM_CC_SFE_0_BCR] = { 0x1304c }, 2903 2913 [CAM_CC_SFE_1_BCR] = { 0x13094 }, 2914 + }; 2915 + 2916 + static struct clk_alpha_pll *cam_cc_sm8450_plls[] = { 2917 + &cam_cc_pll0, 2918 + &cam_cc_pll1, 2919 + &cam_cc_pll2, 2920 + &cam_cc_pll3, 2921 + &cam_cc_pll4, 2922 + &cam_cc_pll5, 2923 + &cam_cc_pll6, 2924 + &cam_cc_pll7, 2925 + &cam_cc_pll8, 2926 + }; 2927 + 2928 + static u32 cam_cc_sm8450_critical_cbcrs[] = { 2929 + 0x1320c, /* CAM_CC_GDSC_CLK */ 2904 2930 }; 2905 2931 2906 2932 static const struct regmap_config cam_cc_sm8450_regmap_config = { ··· 3027 3021 [TITAN_TOP_GDSC] = &titan_top_gdsc, 3028 3022 }; 3029 3023 3024 + static struct qcom_cc_driver_data cam_cc_sm8450_driver_data = { 3025 + .alpha_plls = cam_cc_sm8450_plls, 3026 + .num_alpha_plls = ARRAY_SIZE(cam_cc_sm8450_plls), 3027 + .clk_cbcrs = cam_cc_sm8450_critical_cbcrs, 3028 + .num_clk_cbcrs = ARRAY_SIZE(cam_cc_sm8450_critical_cbcrs), 3029 + }; 3030 + 3030 3031 static const struct qcom_cc_desc cam_cc_sm8450_desc = { 3031 3032 .config = &cam_cc_sm8450_regmap_config, 3032 3033 .clks = cam_cc_sm8450_clocks, ··· 3042 3029 .num_resets = ARRAY_SIZE(cam_cc_sm8450_resets), 3043 3030 .gdscs = cam_cc_sm8450_gdscs, 3044 3031 .num_gdscs = ARRAY_SIZE(cam_cc_sm8450_gdscs), 3032 + .use_rpm = true, 3033 + .driver_data = &cam_cc_sm8450_driver_data, 3045 3034 }; 3046 3035 3047 3036 static const struct of_device_id cam_cc_sm8450_match_table[] = { ··· 3055 3040 3056 3041 static int cam_cc_sm8450_probe(struct platform_device *pdev) 3057 3042 { 3058 - struct regmap *regmap; 3059 - 3060 - regmap = qcom_cc_map(pdev, &cam_cc_sm8450_desc); 3061 - if (IS_ERR(regmap)) 3062 - return PTR_ERR(regmap); 3063 - 3064 3043 if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { 3065 3044 /* Update CAMCC PLL0 */ 3066 3045 cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; ··· 3101 3092 cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 3102 3093 cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init; 3103 3094 3104 - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config); 3105 - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config); 3106 - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config); 3107 - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config); 3108 - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config); 3109 - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config); 3110 - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config); 3111 - clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config); 3112 - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config); 3113 - } else { 3114 - clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); 3115 - clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); 3116 - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); 3117 - clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); 3118 - clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); 3119 - clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); 3120 - clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); 3121 - clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); 3122 - clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); 3095 + cam_cc_pll0.config = &sm8475_cam_cc_pll0_config; 3096 + cam_cc_pll1.config = &sm8475_cam_cc_pll1_config; 3097 + cam_cc_pll2.config = &sm8475_cam_cc_pll2_config; 3098 + cam_cc_pll3.config = &sm8475_cam_cc_pll3_config; 3099 + cam_cc_pll4.config = &sm8475_cam_cc_pll4_config; 3100 + cam_cc_pll5.config = &sm8475_cam_cc_pll5_config; 3101 + cam_cc_pll6.config = &sm8475_cam_cc_pll6_config; 3102 + cam_cc_pll7.config = &sm8475_cam_cc_pll7_config; 3103 + cam_cc_pll8.config = &sm8475_cam_cc_pll8_config; 3123 3104 } 3124 3105 3125 - return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap); 3106 + return qcom_cc_probe(pdev, &cam_cc_sm8450_desc); 3126 3107 } 3127 3108 3128 3109 static struct platform_driver cam_cc_sm8450_driver = {