Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
phy: qcom: edp: Add Glymur platform support
The Qualcomm Glymur platform has the new v8 version of the eDP/DP PHY.
So rework the driver to support this new version and add the platform
specific configuration data.
While at it, add the rest of the AUX_CFG reset values for the v4 and v5
platforms, which makes the handling of the platforms specific array
cleaner, as they are single sized now.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://patch.msgid.link/20251224-phy-qcom-edp-add-glymur-support-v6-4-4fcba75a6fa9@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Abel Vesa
and committed by
Vinod Koul
add66a66
212cdedc
+219
-8
+219
-8
drivers/phy/qualcomm/phy-qcom-edp.c
+219
-8
drivers/phy/qualcomm/phy-qcom-edp.c
···
26
26
#include "phy-qcom-qmp-qserdes-com-v4.h"
27
27
#include "phy-qcom-qmp-qserdes-com-v6.h"
28
28
29
+
#include "phy-qcom-qmp-qserdes-dp-com-v8.h"
30
+
29
31
/* EDP_PHY registers */
30
32
#define DP_PHY_CFG 0x0010
31
33
#define DP_PHY_CFG_1 0x0014
···
78
76
int (*com_power_on)(const struct qcom_edp *edp);
79
77
int (*com_resetsm_cntrl)(const struct qcom_edp *edp);
80
78
int (*com_bias_en_clkbuflr)(const struct qcom_edp *edp);
79
+
int (*com_clk_fwd_cfg)(const struct qcom_edp *edp);
81
80
int (*com_configure_pll)(const struct qcom_edp *edp);
82
81
int (*com_configure_ssc)(const struct qcom_edp *edp);
83
82
};
···
86
83
struct qcom_edp_phy_cfg {
87
84
bool is_edp;
88
85
const u8 *aux_cfg;
86
+
const u8 *vco_div_cfg;
89
87
const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg;
90
88
const struct phy_ver_ops *ver_ops;
91
89
};
···
185
181
.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3,
186
182
};
187
183
188
-
static const u8 edp_phy_aux_cfg_v4[10] = {
189
-
0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03
184
+
static const u8 edp_phy_aux_cfg_v4[DP_AUX_CFG_SIZE] = {
185
+
0x00, 0x13, 0x24, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x00,
186
+
};
187
+
188
+
static const u8 edp_phy_vco_div_cfg_v4[4] = {
189
+
0x01, 0x01, 0x02, 0x00,
190
190
};
191
191
192
192
static const u8 edp_pre_emp_hbr_rbr_v5[4][4] = {
···
214
206
.pre_emphasis_hbr3_hbr2 = &edp_pre_emp_hbr2_hbr3_v5,
215
207
};
216
208
217
-
static const u8 edp_phy_aux_cfg_v5[10] = {
218
-
0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03
209
+
static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] = {
210
+
0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x00,
211
+
};
212
+
213
+
static const u8 edp_phy_aux_cfg_v8[DP_AUX_CFG_SIZE] = {
214
+
0x00, 0x00, 0xa0, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0x04,
215
+
};
216
+
217
+
static const u8 edp_phy_vco_div_cfg_v8[4] = {
218
+
0x00, 0x00, 0x02, 0x01,
219
219
};
220
220
221
221
static int qcom_edp_phy_init(struct phy *phy)
···
241
225
goto out_disable_supplies;
242
226
243
227
memcpy(aux_cfg, edp->cfg->aux_cfg, sizeof(aux_cfg));
228
+
229
+
ret = edp->cfg->ver_ops->com_clk_fwd_cfg(edp);
230
+
if (ret)
231
+
return ret;
244
232
245
233
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
246
234
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
···
365
345
366
346
switch (dp_opts->link_rate) {
367
347
case 1620:
368
-
vco_div = 0x1;
348
+
vco_div = edp->cfg->vco_div_cfg[0];
369
349
*pixel_freq = 1620000000UL / 2;
370
350
break;
371
351
372
352
case 2700:
373
-
vco_div = 0x1;
353
+
vco_div = edp->cfg->vco_div_cfg[1];
374
354
*pixel_freq = 2700000000UL / 2;
375
355
break;
376
356
377
357
case 5400:
378
-
vco_div = 0x2;
358
+
vco_div = edp->cfg->vco_div_cfg[2];
379
359
*pixel_freq = 5400000000UL / 4;
380
360
break;
381
361
382
362
case 8100:
383
-
vco_div = 0x0;
363
+
vco_div = edp->cfg->vco_div_cfg[3];
384
364
*pixel_freq = 8100000000UL / 6;
385
365
break;
386
366
···
416
396
417
397
return readl_poll_timeout(edp->pll + QSERDES_V4_COM_C_READY_STATUS,
418
398
val, val & BIT(0), 500, 10000);
399
+
}
400
+
401
+
static int qcom_edp_com_clk_fwd_cfg_v4(const struct qcom_edp *edp)
402
+
{
403
+
return 0;
419
404
}
420
405
421
406
static int qcom_edp_com_bias_en_clkbuflr_v4(const struct qcom_edp *edp)
···
555
530
.com_power_on = qcom_edp_phy_power_on_v4,
556
531
.com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v4,
557
532
.com_bias_en_clkbuflr = qcom_edp_com_bias_en_clkbuflr_v4,
533
+
.com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v4,
558
534
.com_configure_pll = qcom_edp_com_configure_pll_v4,
559
535
.com_configure_ssc = qcom_edp_com_configure_ssc_v4,
560
536
};
···
563
537
static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg = {
564
538
.is_edp = false,
565
539
.aux_cfg = edp_phy_aux_cfg_v5,
540
+
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
566
541
.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
567
542
.ver_ops = &qcom_edp_phy_ops_v4,
568
543
};
569
544
570
545
static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = {
571
546
.aux_cfg = edp_phy_aux_cfg_v4,
547
+
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
572
548
.ver_ops = &qcom_edp_phy_ops_v4,
573
549
};
574
550
575
551
static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg = {
576
552
.aux_cfg = edp_phy_aux_cfg_v4,
553
+
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
577
554
.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
578
555
.ver_ops = &qcom_edp_phy_ops_v4,
579
556
};
···
584
555
static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_cfg = {
585
556
.is_edp = true,
586
557
.aux_cfg = edp_phy_aux_cfg_v4,
558
+
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
587
559
.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg,
588
560
.ver_ops = &qcom_edp_phy_ops_v4,
589
561
};
···
764
734
765
735
static struct qcom_edp_phy_cfg x1e80100_phy_cfg = {
766
736
.aux_cfg = edp_phy_aux_cfg_v4,
737
+
.vco_div_cfg = edp_phy_vco_div_cfg_v4,
767
738
.swing_pre_emph_cfg = &dp_phy_swing_pre_emph_cfg,
768
739
.ver_ops = &qcom_edp_phy_ops_v6,
740
+
};
741
+
742
+
static int qcom_edp_com_configure_ssc_v8(const struct qcom_edp *edp)
743
+
{
744
+
const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
745
+
u32 step1;
746
+
u32 step2;
747
+
748
+
switch (dp_opts->link_rate) {
749
+
case 1620:
750
+
case 2700:
751
+
case 8100:
752
+
step1 = 0x5b;
753
+
step2 = 0x02;
754
+
break;
755
+
756
+
case 5400:
757
+
step1 = 0x5b;
758
+
step2 = 0x02;
759
+
break;
760
+
761
+
default:
762
+
/* Other link rates aren't supported */
763
+
return -EINVAL;
764
+
}
765
+
766
+
writel(0x01, edp->pll + DP_QSERDES_V8_COM_SSC_EN_CENTER);
767
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_SSC_ADJ_PER1);
768
+
writel(0x6b, edp->pll + DP_QSERDES_V8_COM_SSC_PER1);
769
+
writel(0x02, edp->pll + DP_QSERDES_V8_COM_SSC_PER2);
770
+
writel(step1, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0);
771
+
writel(step2, edp->pll + DP_QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0);
772
+
773
+
return 0;
774
+
}
775
+
776
+
static int qcom_edp_com_configure_pll_v8(const struct qcom_edp *edp)
777
+
{
778
+
const struct phy_configure_opts_dp *dp_opts = &edp->dp_opts;
779
+
u32 div_frac_start2_mode0;
780
+
u32 div_frac_start3_mode0;
781
+
u32 dec_start_mode0;
782
+
u32 lock_cmp1_mode0;
783
+
u32 lock_cmp2_mode0;
784
+
u32 code1_mode0;
785
+
u32 code2_mode0;
786
+
u32 hsclk_sel;
787
+
788
+
switch (dp_opts->link_rate) {
789
+
case 1620:
790
+
hsclk_sel = 0x5;
791
+
dec_start_mode0 = 0x34;
792
+
div_frac_start2_mode0 = 0xc0;
793
+
div_frac_start3_mode0 = 0x0b;
794
+
lock_cmp1_mode0 = 0x37;
795
+
lock_cmp2_mode0 = 0x04;
796
+
code1_mode0 = 0x71;
797
+
code2_mode0 = 0x0c;
798
+
break;
799
+
800
+
case 2700:
801
+
hsclk_sel = 0x3;
802
+
dec_start_mode0 = 0x34;
803
+
div_frac_start2_mode0 = 0xc0;
804
+
div_frac_start3_mode0 = 0x0b;
805
+
lock_cmp1_mode0 = 0x07;
806
+
lock_cmp2_mode0 = 0x07;
807
+
code1_mode0 = 0x71;
808
+
code2_mode0 = 0x0c;
809
+
break;
810
+
811
+
case 5400:
812
+
case 8100:
813
+
hsclk_sel = 0x2;
814
+
dec_start_mode0 = 0x4f;
815
+
div_frac_start2_mode0 = 0xa0;
816
+
div_frac_start3_mode0 = 0x01;
817
+
lock_cmp1_mode0 = 0x18;
818
+
lock_cmp2_mode0 = 0x15;
819
+
code1_mode0 = 0x14;
820
+
code2_mode0 = 0x25;
821
+
break;
822
+
823
+
default:
824
+
/* Other link rates aren't supported */
825
+
return -EINVAL;
826
+
}
827
+
828
+
writel(0x01, edp->pll + DP_QSERDES_V8_COM_SVS_MODE_CLK_SEL);
829
+
writel(0x3b, edp->pll + DP_QSERDES_V8_COM_SYSCLK_EN_SEL);
830
+
writel(0x02, edp->pll + DP_QSERDES_V8_COM_SYS_CLK_CTRL);
831
+
writel(0x0c, edp->pll + DP_QSERDES_V8_COM_CLK_ENABLE1);
832
+
writel(0x06, edp->pll + DP_QSERDES_V8_COM_SYSCLK_BUF_ENABLE);
833
+
writel(0x30, edp->pll + DP_QSERDES_V8_COM_CLK_SELECT);
834
+
writel(hsclk_sel, edp->pll + DP_QSERDES_V8_COM_HSCLK_SEL_1);
835
+
writel(0x07, edp->pll + DP_QSERDES_V8_COM_PLL_IVCO);
836
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP_EN);
837
+
writel(0x36, edp->pll + DP_QSERDES_V8_COM_PLL_CCTRL_MODE0);
838
+
writel(0x16, edp->pll + DP_QSERDES_V8_COM_PLL_RCTRL_MODE0);
839
+
writel(0x06, edp->pll + DP_QSERDES_V8_COM_CP_CTRL_MODE0);
840
+
writel(dec_start_mode0, edp->pll + DP_QSERDES_V8_COM_DEC_START_MODE0);
841
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START1_MODE0);
842
+
writel(div_frac_start2_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START2_MODE0);
843
+
writel(div_frac_start3_mode0, edp->pll + DP_QSERDES_V8_COM_DIV_FRAC_START3_MODE0);
844
+
writel(0x96, edp->pll + DP_QSERDES_V8_COM_CMN_CONFIG_1);
845
+
writel(0x3f, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN0_MODE0);
846
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_INTEGLOOP_GAIN1_MODE0);
847
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_MAP);
848
+
writel(lock_cmp1_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP1_MODE0);
849
+
writel(lock_cmp2_mode0, edp->pll + DP_QSERDES_V8_COM_LOCK_CMP2_MODE0);
850
+
851
+
writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER);
852
+
writel(0x0a, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0);
853
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL);
854
+
writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
855
+
writel(0x00, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN);
856
+
writel(0xa0, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE1_MODE0);
857
+
writel(0x01, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE2_MODE0);
858
+
859
+
writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
860
+
writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
861
+
862
+
return 0;
863
+
}
864
+
865
+
866
+
static int qcom_edp_phy_com_resetsm_cntrl_v8(const struct qcom_edp *edp)
867
+
{
868
+
u32 val;
869
+
870
+
writel(0x20, edp->pll + DP_QSERDES_V8_COM_RESETSM_CNTRL);
871
+
872
+
return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_C_READY_STATUS,
873
+
val, val & BIT(0), 500, 10000);
874
+
}
875
+
876
+
static int qcom_edp_com_clk_fwd_cfg_v8(const struct qcom_edp *edp)
877
+
{
878
+
writel(0x3f, edp->pll + DP_QSERDES_V8_COM_CLK_FWD_CONFIG_1);
879
+
880
+
return 0;
881
+
}
882
+
883
+
static int qcom_edp_com_bias_en_clkbuflr_v8(const struct qcom_edp *edp)
884
+
{
885
+
/* Turn on BIAS current for PHY/PLL */
886
+
writel(0x1f, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);
887
+
888
+
return 0;
889
+
}
890
+
891
+
static int qcom_edp_phy_power_on_v8(const struct qcom_edp *edp)
892
+
{
893
+
u32 val;
894
+
895
+
writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
896
+
DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN |
897
+
DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
898
+
edp->edp + DP_PHY_PD_CTL);
899
+
writel(0xfc, edp->edp + DP_PHY_MODE);
900
+
901
+
return readl_poll_timeout(edp->pll + DP_QSERDES_V8_COM_CMN_STATUS,
902
+
val, val & BIT(7), 5, 200);
903
+
}
904
+
905
+
static const struct phy_ver_ops qcom_edp_phy_ops_v8 = {
906
+
.com_power_on = qcom_edp_phy_power_on_v8,
907
+
.com_resetsm_cntrl = qcom_edp_phy_com_resetsm_cntrl_v8,
908
+
.com_bias_en_clkbuflr = qcom_edp_com_bias_en_clkbuflr_v8,
909
+
.com_clk_fwd_cfg = qcom_edp_com_clk_fwd_cfg_v8,
910
+
.com_configure_pll = qcom_edp_com_configure_pll_v8,
911
+
.com_configure_ssc = qcom_edp_com_configure_ssc_v8,
912
+
};
913
+
914
+
static struct qcom_edp_phy_cfg glymur_phy_cfg = {
915
+
.aux_cfg = edp_phy_aux_cfg_v8,
916
+
.vco_div_cfg = edp_phy_vco_div_cfg_v8,
917
+
.swing_pre_emph_cfg = &edp_phy_swing_pre_emph_cfg_v5,
918
+
.ver_ops = &qcom_edp_phy_ops_v8,
769
919
};
770
920
771
921
static int qcom_edp_phy_power_on(struct phy *phy)
···
1343
1133
}
1344
1134
1345
1135
static const struct of_device_id qcom_edp_phy_match_table[] = {
1136
+
{ .compatible = "qcom,glymur-dp-phy", .data = &glymur_phy_cfg, },
1346
1137
{ .compatible = "qcom,sa8775p-edp-phy", .data = &sa8775p_dp_phy_cfg, },
1347
1138
{ .compatible = "qcom,sc7280-edp-phy", .data = &sc7280_dp_phy_cfg, },
1348
1139
{ .compatible = "qcom,sc8180x-edp-phy", .data = &sc7280_dp_phy_cfg, },