Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amd/display: enable eDP DSC seamless boot support
[Why]
VBIOS supports DSC for seamless boot on newer hardware.
Reading hardware state allows proper DSC validation without breaking
existing boot display.
[What]
Remove DSC block for boot timing validation and implement hardware state
reading to populate DSC configuration from VBIOS-configured state.
Enhance dsc_read_state function in DCN401 to read additional
DSC parameters.
Reviewed-by: Yihan Zhu <yihan.zhu@amd.com>
Signed-off-by: Mohit Bawa <Mohit.Bawa@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Mohit Bawa
and committed by
Alex Deucher
add9aee8
246808e7
+80
-3
+70
-3
drivers/gpu/drm/amd/display/dc/core/dc.c
+70
-3
drivers/gpu/drm/amd/display/dc/core/dc.c
···
1922
1922
return false;
1923
1923
}
1924
1924
1925
-
/* block DSC for now, as VBIOS does not currently support DSC timings */
1926
1925
if (crtc_timing->flags.DSC) {
1927
-
DC_LOG_DEBUG("boot timing validation failed due to DSC\n");
1928
-
return false;
1926
+
struct display_stream_compressor *dsc = NULL;
1927
+
struct dcn_dsc_state dsc_state = {0};
1928
+
1929
+
/* Find DSC associated with this timing generator */
1930
+
if (tg_inst < dc->res_pool->res_cap->num_dsc) {
1931
+
dsc = dc->res_pool->dscs[tg_inst];
1932
+
}
1933
+
1934
+
if (!dsc || !dsc->funcs->dsc_read_state) {
1935
+
DC_LOG_DEBUG("boot timing validation failed due to no DSC resource or read function\n");
1936
+
return false;
1937
+
}
1938
+
1939
+
/* Read current DSC hardware state */
1940
+
dsc->funcs->dsc_read_state(dsc, &dsc_state);
1941
+
1942
+
/* Check if DSC is actually enabled in hardware */
1943
+
if (dsc_state.dsc_clock_en == 0) {
1944
+
DC_LOG_DEBUG("boot timing validation failed due to DSC not enabled in hardware\n");
1945
+
return false;
1946
+
}
1947
+
1948
+
uint32_t num_slices_h = 0;
1949
+
uint32_t num_slices_v = 0;
1950
+
1951
+
if (dsc_state.dsc_slice_width > 0) {
1952
+
num_slices_h = (crtc_timing->h_addressable + dsc_state.dsc_slice_width - 1) / dsc_state.dsc_slice_width;
1953
+
}
1954
+
1955
+
if (dsc_state.dsc_slice_height > 0) {
1956
+
num_slices_v = (crtc_timing->v_addressable + dsc_state.dsc_slice_height - 1) / dsc_state.dsc_slice_height;
1957
+
}
1958
+
1959
+
if (crtc_timing->dsc_cfg.num_slices_h != num_slices_h) {
1960
+
DC_LOG_DEBUG("boot timing validation failed due to num_slices_h mismatch\n");
1961
+
return false;
1962
+
}
1963
+
1964
+
if (crtc_timing->dsc_cfg.num_slices_v != num_slices_v) {
1965
+
DC_LOG_DEBUG("boot timing validation failed due to num_slices_v mismatch\n");
1966
+
return false;
1967
+
}
1968
+
1969
+
if (crtc_timing->dsc_cfg.bits_per_pixel != dsc_state.dsc_bits_per_pixel) {
1970
+
DC_LOG_DEBUG("boot timing validation failed due to bits_per_pixel mismatch\n");
1971
+
return false;
1972
+
}
1973
+
1974
+
if (crtc_timing->dsc_cfg.block_pred_enable != dsc_state.dsc_block_pred_enable) {
1975
+
DC_LOG_DEBUG("boot timing validation failed due to block_pred_enable mismatch\n");
1976
+
return false;
1977
+
}
1978
+
1979
+
if (crtc_timing->dsc_cfg.linebuf_depth != dsc_state.dsc_line_buf_depth) {
1980
+
DC_LOG_DEBUG("boot timing validation failed due to linebuf_depth mismatch\n");
1981
+
return false;
1982
+
}
1983
+
1984
+
if (crtc_timing->dsc_cfg.version_minor != dsc_state.dsc_version_minor) {
1985
+
DC_LOG_DEBUG("boot timing validation failed due to version_minor mismatch\n");
1986
+
return false;
1987
+
}
1988
+
1989
+
if (crtc_timing->dsc_cfg.ycbcr422_simple != dsc_state.dsc_simple_422) {
1990
+
DC_LOG_DEBUG("boot timing validation failed due to pixel encoding mismatch\n");
1991
+
return false;
1992
+
}
1993
+
1994
+
// Skip checks for is_frl, is_dp, and rc_buffer_size which are not programmed by vbios
1995
+
// or not necessary for seamless boot validation.
1929
1996
}
1930
1997
1931
1998
if (dc_is_dp_signal(link->connector_signal)) {
+5
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
+5
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
···
107
107
REG_GET(DSCC_PPS_CONFIG7, SLICE_BPG_OFFSET, &s->dsc_slice_bpg_offset);
108
108
REG_GET_2(DSCRM_DSC_FORWARD_CONFIG, DSCRM_DSC_FORWARD_EN, &s->dsc_fw_en,
109
109
DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
110
+
REG_GET(DSCC_PPS_CONFIG1, BLOCK_PRED_ENABLE, &s->dsc_block_pred_enable);
111
+
REG_GET(DSCC_PPS_CONFIG0, LINEBUF_DEPTH, &s->dsc_line_buf_depth);
112
+
REG_GET(DSCC_PPS_CONFIG0, DSC_VERSION_MINOR, &s->dsc_version_minor);
113
+
REG_GET(DSCC_CONFIG1, DSCC_RATE_CONTROL_BUFFER_MODEL_SIZE, &s->dsc_rc_buffer_size);
114
+
REG_GET(DSCC_PPS_CONFIG0, SIMPLE_422, &s->dsc_simple_422);
110
115
}
111
116
112
117
+5
drivers/gpu/drm/amd/display/dc/dsc/dsc.h
+5
drivers/gpu/drm/amd/display/dc/dsc/dsc.h
···
64
64
uint32_t dsc_chunk_size;
65
65
uint32_t dsc_fw_en;
66
66
uint32_t dsc_opp_source;
67
+
uint32_t dsc_block_pred_enable;
68
+
uint32_t dsc_line_buf_depth;
69
+
uint32_t dsc_version_minor;
70
+
uint32_t dsc_rc_buffer_size;
71
+
uint32_t dsc_simple_422;
67
72
};
68
73
69
74
struct dcn_dsc_reg_state {