Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm: import A2xx-A4xx XML display registers database
Import Adreno registers database for A2xx-A4xx from the Mesa, commit
639488f924d9 ("freedreno/registers: limit the rules schema").
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/585854/
Link: https://lore.kernel.org/r/20240401-fd-xml-shipped-v5-7-4bdb277a85a1@linaro.org
+8693
+1865
drivers/gpu/drm/msm/registers/adreno/a2xx.xml
+1865
drivers/gpu/drm/msm/registers/adreno/a2xx.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
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+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
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+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
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+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
<import file="adreno/adreno_pm4.xml"/>
8
+
9
+
10
+
<enum name="a2xx_rb_dither_type">
11
+
<value name="DITHER_PIXEL" value="0"/>
12
+
<value name="DITHER_SUBPIXEL" value="1"/>
13
+
</enum>
14
+
15
+
<enum name="a2xx_colorformatx">
16
+
<value name="COLORX_4_4_4_4" value="0"/>
17
+
<value name="COLORX_1_5_5_5" value="1"/>
18
+
<value name="COLORX_5_6_5" value="2"/>
19
+
<value name="COLORX_8" value="3"/>
20
+
<value name="COLORX_8_8" value="4"/>
21
+
<value name="COLORX_8_8_8_8" value="5"/>
22
+
<value name="COLORX_S8_8_8_8" value="6"/>
23
+
<value name="COLORX_16_FLOAT" value="7"/>
24
+
<value name="COLORX_16_16_FLOAT" value="8"/>
25
+
<value name="COLORX_16_16_16_16_FLOAT" value="9"/>
26
+
<value name="COLORX_32_FLOAT" value="10"/>
27
+
<value name="COLORX_32_32_FLOAT" value="11"/>
28
+
<value name="COLORX_32_32_32_32_FLOAT" value="12"/>
29
+
<value name="COLORX_2_3_3" value="13"/>
30
+
<value name="COLORX_8_8_8" value="14"/>
31
+
</enum>
32
+
33
+
<enum name="a2xx_sq_surfaceformat">
34
+
<value name="FMT_1_REVERSE" value="0"/>
35
+
<value name="FMT_1" value="1"/>
36
+
<value name="FMT_8" value="2"/>
37
+
<value name="FMT_1_5_5_5" value="3"/>
38
+
<value name="FMT_5_6_5" value="4"/>
39
+
<value name="FMT_6_5_5" value="5"/>
40
+
<value name="FMT_8_8_8_8" value="6"/>
41
+
<value name="FMT_2_10_10_10" value="7"/>
42
+
<value name="FMT_8_A" value="8"/>
43
+
<value name="FMT_8_B" value="9"/>
44
+
<value name="FMT_8_8" value="10"/>
45
+
<value name="FMT_Cr_Y1_Cb_Y0" value="11"/>
46
+
<value name="FMT_Y1_Cr_Y0_Cb" value="12"/>
47
+
<value name="FMT_5_5_5_1" value="13"/>
48
+
<value name="FMT_8_8_8_8_A" value="14"/>
49
+
<value name="FMT_4_4_4_4" value="15"/>
50
+
<value name="FMT_8_8_8" value="16"/>
51
+
<value name="FMT_DXT1" value="18"/>
52
+
<value name="FMT_DXT2_3" value="19"/>
53
+
<value name="FMT_DXT4_5" value="20"/>
54
+
<value name="FMT_10_10_10_2" value="21"/>
55
+
<value name="FMT_24_8" value="22"/>
56
+
<value name="FMT_16" value="24"/>
57
+
<value name="FMT_16_16" value="25"/>
58
+
<value name="FMT_16_16_16_16" value="26"/>
59
+
<value name="FMT_16_EXPAND" value="27"/>
60
+
<value name="FMT_16_16_EXPAND" value="28"/>
61
+
<value name="FMT_16_16_16_16_EXPAND" value="29"/>
62
+
<value name="FMT_16_FLOAT" value="30"/>
63
+
<value name="FMT_16_16_FLOAT" value="31"/>
64
+
<value name="FMT_16_16_16_16_FLOAT" value="32"/>
65
+
<value name="FMT_32" value="33"/>
66
+
<value name="FMT_32_32" value="34"/>
67
+
<value name="FMT_32_32_32_32" value="35"/>
68
+
<value name="FMT_32_FLOAT" value="36"/>
69
+
<value name="FMT_32_32_FLOAT" value="37"/>
70
+
<value name="FMT_32_32_32_32_FLOAT" value="38"/>
71
+
<value name="FMT_ATI_TC_RGB" value="39"/>
72
+
<value name="FMT_ATI_TC_RGBA" value="40"/>
73
+
<value name="FMT_ATI_TC_555_565_RGB" value="41"/>
74
+
<value name="FMT_ATI_TC_555_565_RGBA" value="42"/>
75
+
<value name="FMT_ATI_TC_RGBA_INTERP" value="43"/>
76
+
<value name="FMT_ATI_TC_555_565_RGBA_INTERP" value="44"/>
77
+
<value name="FMT_ETC1_RGBA_INTERP" value="46"/>
78
+
<value name="FMT_ETC1_RGB" value="47"/>
79
+
<value name="FMT_ETC1_RGBA" value="48"/>
80
+
<value name="FMT_DXN" value="49"/>
81
+
<value name="FMT_2_3_3" value="51"/>
82
+
<value name="FMT_2_10_10_10_AS_16_16_16_16" value="54"/>
83
+
<value name="FMT_10_10_10_2_AS_16_16_16_16" value="55"/>
84
+
<value name="FMT_32_32_32_FLOAT" value="57"/>
85
+
<value name="FMT_DXT3A" value="58"/>
86
+
<value name="FMT_DXT5A" value="59"/>
87
+
<value name="FMT_CTX1" value="60"/>
88
+
</enum>
89
+
90
+
<enum name="a2xx_sq_ps_vtx_mode">
91
+
<value name="POSITION_1_VECTOR" value="0"/>
92
+
<value name="POSITION_2_VECTORS_UNUSED" value="1"/>
93
+
<value name="POSITION_2_VECTORS_SPRITE" value="2"/>
94
+
<value name="POSITION_2_VECTORS_EDGE" value="3"/>
95
+
<value name="POSITION_2_VECTORS_KILL" value="4"/>
96
+
<value name="POSITION_2_VECTORS_SPRITE_KILL" value="5"/>
97
+
<value name="POSITION_2_VECTORS_EDGE_KILL" value="6"/>
98
+
<value name="MULTIPASS" value="7"/>
99
+
</enum>
100
+
101
+
<enum name="a2xx_sq_sample_cntl">
102
+
<value name="CENTROIDS_ONLY" value="0"/>
103
+
<value name="CENTERS_ONLY" value="1"/>
104
+
<value name="CENTROIDS_AND_CENTERS" value="2"/>
105
+
</enum>
106
+
107
+
<enum name="a2xx_dx_clip_space">
108
+
<value name="DXCLIP_OPENGL" value="0"/>
109
+
<value name="DXCLIP_DIRECTX" value="1"/>
110
+
</enum>
111
+
112
+
<enum name="a2xx_pa_su_sc_polymode">
113
+
<value name="POLY_DISABLED" value="0"/>
114
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<value name="POLY_DUALMODE" value="1"/>
115
+
</enum>
116
+
117
+
<enum name="a2xx_rb_edram_mode">
118
+
<value name="EDRAM_NOP" value="0"/>
119
+
<value name="COLOR_DEPTH" value="4"/>
120
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<value name="DEPTH_ONLY" value="5"/>
121
+
<value name="EDRAM_COPY" value="6"/>
122
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</enum>
123
+
124
+
<enum name="a2xx_pa_sc_pattern_bit_order">
125
+
<value name="LITTLE" value="0"/>
126
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<value name="BIG" value="1"/>
127
+
</enum>
128
+
129
+
<enum name="a2xx_pa_sc_auto_reset_cntl">
130
+
<value name="NEVER" value="0"/>
131
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<value name="EACH_PRIMITIVE" value="1"/>
132
+
<value name="EACH_PACKET" value="2"/>
133
+
</enum>
134
+
135
+
<enum name="a2xx_pa_pixcenter">
136
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<value name="PIXCENTER_D3D" value="0"/>
137
+
<value name="PIXCENTER_OGL" value="1"/>
138
+
</enum>
139
+
140
+
<enum name="a2xx_pa_roundmode">
141
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<value name="TRUNCATE" value="0"/>
142
+
<value name="ROUND" value="1"/>
143
+
<value name="ROUNDTOEVEN" value="2"/>
144
+
<value name="ROUNDTOODD" value="3"/>
145
+
</enum>
146
+
147
+
<enum name="a2xx_pa_quantmode">
148
+
<value name="ONE_SIXTEENTH" value="0"/>
149
+
<value name="ONE_EIGTH" value="1"/>
150
+
<value name="ONE_QUARTER" value="2"/>
151
+
<value name="ONE_HALF" value="3"/>
152
+
<value name="ONE" value="4"/>
153
+
</enum>
154
+
155
+
<enum name="a2xx_rb_copy_sample_select">
156
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<value name="SAMPLE_0" value="0"/>
157
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<value name="SAMPLE_1" value="1"/>
158
+
<value name="SAMPLE_2" value="2"/>
159
+
<value name="SAMPLE_3" value="3"/>
160
+
<value name="SAMPLE_01" value="4"/>
161
+
<value name="SAMPLE_23" value="5"/>
162
+
<value name="SAMPLE_0123" value="6"/>
163
+
</enum>
164
+
165
+
<enum name="a2xx_rb_blend_opcode">
166
+
<value name="BLEND2_DST_PLUS_SRC" value="0"/>
167
+
<value name="BLEND2_SRC_MINUS_DST" value="1"/>
168
+
<value name="BLEND2_MIN_DST_SRC" value="2"/>
169
+
<value name="BLEND2_MAX_DST_SRC" value="3"/>
170
+
<value name="BLEND2_DST_MINUS_SRC" value="4"/>
171
+
<value name="BLEND2_DST_PLUS_SRC_BIAS" value="5"/>
172
+
</enum>
173
+
174
+
<enum name="a2xx_su_perfcnt_select">
175
+
<value value="0" name="PERF_PAPC_PASX_REQ"/>
176
+
<value value="2" name="PERF_PAPC_PASX_FIRST_VECTOR"/>
177
+
<value value="3" name="PERF_PAPC_PASX_SECOND_VECTOR"/>
178
+
<value value="4" name="PERF_PAPC_PASX_FIRST_DEAD"/>
179
+
<value value="5" name="PERF_PAPC_PASX_SECOND_DEAD"/>
180
+
<value value="6" name="PERF_PAPC_PASX_VTX_KILL_DISCARD"/>
181
+
<value value="7" name="PERF_PAPC_PASX_VTX_NAN_DISCARD"/>
182
+
<value value="8" name="PERF_PAPC_PA_INPUT_PRIM"/>
183
+
<value value="9" name="PERF_PAPC_PA_INPUT_NULL_PRIM"/>
184
+
<value value="10" name="PERF_PAPC_PA_INPUT_EVENT_FLAG"/>
185
+
<value value="11" name="PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT"/>
186
+
<value value="12" name="PERF_PAPC_PA_INPUT_END_OF_PACKET"/>
187
+
<value value="13" name="PERF_PAPC_CLPR_CULL_PRIM"/>
188
+
<value value="15" name="PERF_PAPC_CLPR_VV_CULL_PRIM"/>
189
+
<value value="17" name="PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM"/>
190
+
<value value="18" name="PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM"/>
191
+
<value value="19" name="PERF_PAPC_CLPR_CULL_TO_NULL_PRIM"/>
192
+
<value value="21" name="PERF_PAPC_CLPR_VV_CLIP_PRIM"/>
193
+
<value value="23" name="PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE"/>
194
+
<value value="24" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_1"/>
195
+
<value value="25" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_2"/>
196
+
<value value="26" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_3"/>
197
+
<value value="27" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_4"/>
198
+
<value value="28" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_5"/>
199
+
<value value="29" name="PERF_PAPC_CLPR_CLIP_PLANE_CNT_6"/>
200
+
<value value="30" name="PERF_PAPC_CLPR_CLIP_PLANE_NEAR"/>
201
+
<value value="31" name="PERF_PAPC_CLPR_CLIP_PLANE_FAR"/>
202
+
<value value="32" name="PERF_PAPC_CLPR_CLIP_PLANE_LEFT"/>
203
+
<value value="33" name="PERF_PAPC_CLPR_CLIP_PLANE_RIGHT"/>
204
+
<value value="34" name="PERF_PAPC_CLPR_CLIP_PLANE_TOP"/>
205
+
<value value="35" name="PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM"/>
206
+
<value value="36" name="PERF_PAPC_CLSM_NULL_PRIM"/>
207
+
<value value="37" name="PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM"/>
208
+
<value value="38" name="PERF_PAPC_CLSM_CLIP_PRIM"/>
209
+
<value value="39" name="PERF_PAPC_CLSM_CULL_TO_NULL_PRIM"/>
210
+
<value value="40" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_1"/>
211
+
<value value="41" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_2"/>
212
+
<value value="42" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_3"/>
213
+
<value value="43" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_4"/>
214
+
<value value="44" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_5"/>
215
+
<value value="45" name="PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7"/>
216
+
<value value="46" name="PERF_PAPC_CLSM_NON_TRIVIAL_CULL"/>
217
+
<value value="47" name="PERF_PAPC_SU_INPUT_PRIM"/>
218
+
<value value="48" name="PERF_PAPC_SU_INPUT_CLIP_PRIM"/>
219
+
<value value="49" name="PERF_PAPC_SU_INPUT_NULL_PRIM"/>
220
+
<value value="50" name="PERF_PAPC_SU_ZERO_AREA_CULL_PRIM"/>
221
+
<value value="51" name="PERF_PAPC_SU_BACK_FACE_CULL_PRIM"/>
222
+
<value value="52" name="PERF_PAPC_SU_FRONT_FACE_CULL_PRIM"/>
223
+
<value value="53" name="PERF_PAPC_SU_POLYMODE_FACE_CULL"/>
224
+
<value value="54" name="PERF_PAPC_SU_POLYMODE_BACK_CULL"/>
225
+
<value value="55" name="PERF_PAPC_SU_POLYMODE_FRONT_CULL"/>
226
+
<value value="56" name="PERF_PAPC_SU_POLYMODE_INVALID_FILL"/>
227
+
<value value="57" name="PERF_PAPC_SU_OUTPUT_PRIM"/>
228
+
<value value="58" name="PERF_PAPC_SU_OUTPUT_CLIP_PRIM"/>
229
+
<value value="59" name="PERF_PAPC_SU_OUTPUT_NULL_PRIM"/>
230
+
<value value="60" name="PERF_PAPC_SU_OUTPUT_EVENT_FLAG"/>
231
+
<value value="61" name="PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT"/>
232
+
<value value="62" name="PERF_PAPC_SU_OUTPUT_END_OF_PACKET"/>
233
+
<value value="63" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FACE"/>
234
+
<value value="64" name="PERF_PAPC_SU_OUTPUT_POLYMODE_BACK"/>
235
+
<value value="65" name="PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT"/>
236
+
<value value="66" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE"/>
237
+
<value value="67" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK"/>
238
+
<value value="68" name="PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT"/>
239
+
<value value="69" name="PERF_PAPC_PASX_REQ_IDLE"/>
240
+
<value value="70" name="PERF_PAPC_PASX_REQ_BUSY"/>
241
+
<value value="71" name="PERF_PAPC_PASX_REQ_STALLED"/>
242
+
<value value="72" name="PERF_PAPC_PASX_REC_IDLE"/>
243
+
<value value="73" name="PERF_PAPC_PASX_REC_BUSY"/>
244
+
<value value="74" name="PERF_PAPC_PASX_REC_STARVED_SX"/>
245
+
<value value="75" name="PERF_PAPC_PASX_REC_STALLED"/>
246
+
<value value="76" name="PERF_PAPC_PASX_REC_STALLED_POS_MEM"/>
247
+
<value value="77" name="PERF_PAPC_PASX_REC_STALLED_CCGSM_IN"/>
248
+
<value value="78" name="PERF_PAPC_CCGSM_IDLE"/>
249
+
<value value="79" name="PERF_PAPC_CCGSM_BUSY"/>
250
+
<value value="80" name="PERF_PAPC_CCGSM_STALLED"/>
251
+
<value value="81" name="PERF_PAPC_CLPRIM_IDLE"/>
252
+
<value value="82" name="PERF_PAPC_CLPRIM_BUSY"/>
253
+
<value value="83" name="PERF_PAPC_CLPRIM_STALLED"/>
254
+
<value value="84" name="PERF_PAPC_CLPRIM_STARVED_CCGSM"/>
255
+
<value value="85" name="PERF_PAPC_CLIPSM_IDLE"/>
256
+
<value value="86" name="PERF_PAPC_CLIPSM_BUSY"/>
257
+
<value value="87" name="PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH"/>
258
+
<value value="88" name="PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ"/>
259
+
<value value="89" name="PERF_PAPC_CLIPSM_WAIT_CLIPGA"/>
260
+
<value value="90" name="PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP"/>
261
+
<value value="91" name="PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM"/>
262
+
<value value="92" name="PERF_PAPC_CLIPGA_IDLE"/>
263
+
<value value="93" name="PERF_PAPC_CLIPGA_BUSY"/>
264
+
<value value="94" name="PERF_PAPC_CLIPGA_STARVED_VTE_CLIP"/>
265
+
<value value="95" name="PERF_PAPC_CLIPGA_STALLED"/>
266
+
<value value="96" name="PERF_PAPC_CLIP_IDLE"/>
267
+
<value value="97" name="PERF_PAPC_CLIP_BUSY"/>
268
+
<value value="98" name="PERF_PAPC_SU_IDLE"/>
269
+
<value value="99" name="PERF_PAPC_SU_BUSY"/>
270
+
<value value="100" name="PERF_PAPC_SU_STARVED_CLIP"/>
271
+
<value value="101" name="PERF_PAPC_SU_STALLED_SC"/>
272
+
<value value="102" name="PERF_PAPC_SU_FACENESS_CULL"/>
273
+
</enum>
274
+
275
+
<enum name="a2xx_sc_perfcnt_select">
276
+
<value value="0" name="SC_SR_WINDOW_VALID"/>
277
+
<value value="1" name="SC_CW_WINDOW_VALID"/>
278
+
<value value="2" name="SC_QM_WINDOW_VALID"/>
279
+
<value value="3" name="SC_FW_WINDOW_VALID"/>
280
+
<value value="4" name="SC_EZ_WINDOW_VALID"/>
281
+
<value value="5" name="SC_IT_WINDOW_VALID"/>
282
+
<value value="6" name="SC_STARVED_BY_PA"/>
283
+
<value value="7" name="SC_STALLED_BY_RB_TILE"/>
284
+
<value value="8" name="SC_STALLED_BY_RB_SAMP"/>
285
+
<value value="9" name="SC_STARVED_BY_RB_EZ"/>
286
+
<value value="10" name="SC_STALLED_BY_SAMPLE_FF"/>
287
+
<value value="11" name="SC_STALLED_BY_SQ"/>
288
+
<value value="12" name="SC_STALLED_BY_SP"/>
289
+
<value value="13" name="SC_TOTAL_NO_PRIMS"/>
290
+
<value value="14" name="SC_NON_EMPTY_PRIMS"/>
291
+
<value value="15" name="SC_NO_TILES_PASSING_QM"/>
292
+
<value value="16" name="SC_NO_PIXELS_PRE_EZ"/>
293
+
<value value="17" name="SC_NO_PIXELS_POST_EZ"/>
294
+
</enum>
295
+
296
+
<enum name="a2xx_vgt_perfcount_select">
297
+
<value value="0" name="VGT_SQ_EVENT_WINDOW_ACTIVE"/>
298
+
<value value="1" name="VGT_SQ_SEND"/>
299
+
<value value="2" name="VGT_SQ_STALLED"/>
300
+
<value value="3" name="VGT_SQ_STARVED_BUSY"/>
301
+
<value value="4" name="VGT_SQ_STARVED_IDLE"/>
302
+
<value value="5" name="VGT_SQ_STATIC"/>
303
+
<value value="6" name="VGT_PA_EVENT_WINDOW_ACTIVE"/>
304
+
<value value="7" name="VGT_PA_CLIP_V_SEND"/>
305
+
<value value="8" name="VGT_PA_CLIP_V_STALLED"/>
306
+
<value value="9" name="VGT_PA_CLIP_V_STARVED_BUSY"/>
307
+
<value value="10" name="VGT_PA_CLIP_V_STARVED_IDLE"/>
308
+
<value value="11" name="VGT_PA_CLIP_V_STATIC"/>
309
+
<value value="12" name="VGT_PA_CLIP_P_SEND"/>
310
+
<value value="13" name="VGT_PA_CLIP_P_STALLED"/>
311
+
<value value="14" name="VGT_PA_CLIP_P_STARVED_BUSY"/>
312
+
<value value="15" name="VGT_PA_CLIP_P_STARVED_IDLE"/>
313
+
<value value="16" name="VGT_PA_CLIP_P_STATIC"/>
314
+
<value value="17" name="VGT_PA_CLIP_S_SEND"/>
315
+
<value value="18" name="VGT_PA_CLIP_S_STALLED"/>
316
+
<value value="19" name="VGT_PA_CLIP_S_STARVED_BUSY"/>
317
+
<value value="20" name="VGT_PA_CLIP_S_STARVED_IDLE"/>
318
+
<value value="21" name="VGT_PA_CLIP_S_STATIC"/>
319
+
<value value="22" name="RBIU_FIFOS_EVENT_WINDOW_ACTIVE"/>
320
+
<value value="23" name="RBIU_IMMED_DATA_FIFO_STARVED"/>
321
+
<value value="24" name="RBIU_IMMED_DATA_FIFO_STALLED"/>
322
+
<value value="25" name="RBIU_DMA_REQUEST_FIFO_STARVED"/>
323
+
<value value="26" name="RBIU_DMA_REQUEST_FIFO_STALLED"/>
324
+
<value value="27" name="RBIU_DRAW_INITIATOR_FIFO_STARVED"/>
325
+
<value value="28" name="RBIU_DRAW_INITIATOR_FIFO_STALLED"/>
326
+
<value value="29" name="BIN_PRIM_NEAR_CULL"/>
327
+
<value value="30" name="BIN_PRIM_ZERO_CULL"/>
328
+
<value value="31" name="BIN_PRIM_FAR_CULL"/>
329
+
<value value="32" name="BIN_PRIM_BIN_CULL"/>
330
+
<value value="33" name="BIN_PRIM_FACE_CULL"/>
331
+
<value value="34" name="SPARE34"/>
332
+
<value value="35" name="SPARE35"/>
333
+
<value value="36" name="SPARE36"/>
334
+
<value value="37" name="SPARE37"/>
335
+
<value value="38" name="SPARE38"/>
336
+
<value value="39" name="SPARE39"/>
337
+
<value value="40" name="TE_SU_IN_VALID"/>
338
+
<value value="41" name="TE_SU_IN_READ"/>
339
+
<value value="42" name="TE_SU_IN_PRIM"/>
340
+
<value value="43" name="TE_SU_IN_EOP"/>
341
+
<value value="44" name="TE_SU_IN_NULL_PRIM"/>
342
+
<value value="45" name="TE_WK_IN_VALID"/>
343
+
<value value="46" name="TE_WK_IN_READ"/>
344
+
<value value="47" name="TE_OUT_PRIM_VALID"/>
345
+
<value value="48" name="TE_OUT_PRIM_READ"/>
346
+
</enum>
347
+
348
+
<enum name="a2xx_tcr_perfcount_select">
349
+
<value value="0" name="DGMMPD_IPMUX0_STALL"/>
350
+
<value value="4" name="DGMMPD_IPMUX_ALL_STALL"/>
351
+
<value value="5" name="OPMUX0_L2_WRITES"/>
352
+
</enum>
353
+
354
+
<enum name="a2xx_tp_perfcount_select">
355
+
<value value="0" name="POINT_QUADS"/>
356
+
<value value="1" name="BILIN_QUADS"/>
357
+
<value value="2" name="ANISO_QUADS"/>
358
+
<value value="3" name="MIP_QUADS"/>
359
+
<value value="4" name="VOL_QUADS"/>
360
+
<value value="5" name="MIP_VOL_QUADS"/>
361
+
<value value="6" name="MIP_ANISO_QUADS"/>
362
+
<value value="7" name="VOL_ANISO_QUADS"/>
363
+
<value value="8" name="ANISO_2_1_QUADS"/>
364
+
<value value="9" name="ANISO_4_1_QUADS"/>
365
+
<value value="10" name="ANISO_6_1_QUADS"/>
366
+
<value value="11" name="ANISO_8_1_QUADS"/>
367
+
<value value="12" name="ANISO_10_1_QUADS"/>
368
+
<value value="13" name="ANISO_12_1_QUADS"/>
369
+
<value value="14" name="ANISO_14_1_QUADS"/>
370
+
<value value="15" name="ANISO_16_1_QUADS"/>
371
+
<value value="16" name="MIP_VOL_ANISO_QUADS"/>
372
+
<value value="17" name="ALIGN_2_QUADS"/>
373
+
<value value="18" name="ALIGN_4_QUADS"/>
374
+
<value value="19" name="PIX_0_QUAD"/>
375
+
<value value="20" name="PIX_1_QUAD"/>
376
+
<value value="21" name="PIX_2_QUAD"/>
377
+
<value value="22" name="PIX_3_QUAD"/>
378
+
<value value="23" name="PIX_4_QUAD"/>
379
+
<value value="24" name="TP_MIPMAP_LOD0"/>
380
+
<value value="25" name="TP_MIPMAP_LOD1"/>
381
+
<value value="26" name="TP_MIPMAP_LOD2"/>
382
+
<value value="27" name="TP_MIPMAP_LOD3"/>
383
+
<value value="28" name="TP_MIPMAP_LOD4"/>
384
+
<value value="29" name="TP_MIPMAP_LOD5"/>
385
+
<value value="30" name="TP_MIPMAP_LOD6"/>
386
+
<value value="31" name="TP_MIPMAP_LOD7"/>
387
+
<value value="32" name="TP_MIPMAP_LOD8"/>
388
+
<value value="33" name="TP_MIPMAP_LOD9"/>
389
+
<value value="34" name="TP_MIPMAP_LOD10"/>
390
+
<value value="35" name="TP_MIPMAP_LOD11"/>
391
+
<value value="36" name="TP_MIPMAP_LOD12"/>
392
+
<value value="37" name="TP_MIPMAP_LOD13"/>
393
+
<value value="38" name="TP_MIPMAP_LOD14"/>
394
+
</enum>
395
+
396
+
<enum name="a2xx_tcm_perfcount_select">
397
+
<value value="0" name="QUAD0_RD_LAT_FIFO_EMPTY"/>
398
+
<value value="3" name="QUAD0_RD_LAT_FIFO_4TH_FULL"/>
399
+
<value value="4" name="QUAD0_RD_LAT_FIFO_HALF_FULL"/>
400
+
<value value="5" name="QUAD0_RD_LAT_FIFO_FULL"/>
401
+
<value value="6" name="QUAD0_RD_LAT_FIFO_LT_4TH_FULL"/>
402
+
<value value="28" name="READ_STARVED_QUAD0"/>
403
+
<value value="32" name="READ_STARVED"/>
404
+
<value value="33" name="READ_STALLED_QUAD0"/>
405
+
<value value="37" name="READ_STALLED"/>
406
+
<value value="38" name="VALID_READ_QUAD0"/>
407
+
<value value="42" name="TC_TP_STARVED_QUAD0"/>
408
+
<value value="46" name="TC_TP_STARVED"/>
409
+
</enum>
410
+
411
+
<enum name="a2xx_tcf_perfcount_select">
412
+
<value value="0" name="VALID_CYCLES"/>
413
+
<value value="1" name="SINGLE_PHASES"/>
414
+
<value value="2" name="ANISO_PHASES"/>
415
+
<value value="3" name="MIP_PHASES"/>
416
+
<value value="4" name="VOL_PHASES"/>
417
+
<value value="5" name="MIP_VOL_PHASES"/>
418
+
<value value="6" name="MIP_ANISO_PHASES"/>
419
+
<value value="7" name="VOL_ANISO_PHASES"/>
420
+
<value value="8" name="ANISO_2_1_PHASES"/>
421
+
<value value="9" name="ANISO_4_1_PHASES"/>
422
+
<value value="10" name="ANISO_6_1_PHASES"/>
423
+
<value value="11" name="ANISO_8_1_PHASES"/>
424
+
<value value="12" name="ANISO_10_1_PHASES"/>
425
+
<value value="13" name="ANISO_12_1_PHASES"/>
426
+
<value value="14" name="ANISO_14_1_PHASES"/>
427
+
<value value="15" name="ANISO_16_1_PHASES"/>
428
+
<value value="16" name="MIP_VOL_ANISO_PHASES"/>
429
+
<value value="17" name="ALIGN_2_PHASES"/>
430
+
<value value="18" name="ALIGN_4_PHASES"/>
431
+
<value value="19" name="TPC_BUSY"/>
432
+
<value value="20" name="TPC_STALLED"/>
433
+
<value value="21" name="TPC_STARVED"/>
434
+
<value value="22" name="TPC_WORKING"/>
435
+
<value value="23" name="TPC_WALKER_BUSY"/>
436
+
<value value="24" name="TPC_WALKER_STALLED"/>
437
+
<value value="25" name="TPC_WALKER_WORKING"/>
438
+
<value value="26" name="TPC_ALIGNER_BUSY"/>
439
+
<value value="27" name="TPC_ALIGNER_STALLED"/>
440
+
<value value="28" name="TPC_ALIGNER_STALLED_BY_BLEND"/>
441
+
<value value="29" name="TPC_ALIGNER_STALLED_BY_CACHE"/>
442
+
<value value="30" name="TPC_ALIGNER_WORKING"/>
443
+
<value value="31" name="TPC_BLEND_BUSY"/>
444
+
<value value="32" name="TPC_BLEND_SYNC"/>
445
+
<value value="33" name="TPC_BLEND_STARVED"/>
446
+
<value value="34" name="TPC_BLEND_WORKING"/>
447
+
<value value="35" name="OPCODE_0x00"/>
448
+
<value value="36" name="OPCODE_0x01"/>
449
+
<value value="37" name="OPCODE_0x04"/>
450
+
<value value="38" name="OPCODE_0x10"/>
451
+
<value value="39" name="OPCODE_0x11"/>
452
+
<value value="40" name="OPCODE_0x12"/>
453
+
<value value="41" name="OPCODE_0x13"/>
454
+
<value value="42" name="OPCODE_0x18"/>
455
+
<value value="43" name="OPCODE_0x19"/>
456
+
<value value="44" name="OPCODE_0x1A"/>
457
+
<value value="45" name="OPCODE_OTHER"/>
458
+
<value value="56" name="IN_FIFO_0_EMPTY"/>
459
+
<value value="57" name="IN_FIFO_0_LT_HALF_FULL"/>
460
+
<value value="58" name="IN_FIFO_0_HALF_FULL"/>
461
+
<value value="59" name="IN_FIFO_0_FULL"/>
462
+
<value value="72" name="IN_FIFO_TPC_EMPTY"/>
463
+
<value value="73" name="IN_FIFO_TPC_LT_HALF_FULL"/>
464
+
<value value="74" name="IN_FIFO_TPC_HALF_FULL"/>
465
+
<value value="75" name="IN_FIFO_TPC_FULL"/>
466
+
<value value="76" name="TPC_TC_XFC"/>
467
+
<value value="77" name="TPC_TC_STATE"/>
468
+
<value value="78" name="TC_STALL"/>
469
+
<value value="79" name="QUAD0_TAPS"/>
470
+
<value value="83" name="QUADS"/>
471
+
<value value="84" name="TCA_SYNC_STALL"/>
472
+
<value value="85" name="TAG_STALL"/>
473
+
<value value="88" name="TCB_SYNC_STALL"/>
474
+
<value value="89" name="TCA_VALID"/>
475
+
<value value="90" name="PROBES_VALID"/>
476
+
<value value="91" name="MISS_STALL"/>
477
+
<value value="92" name="FETCH_FIFO_STALL"/>
478
+
<value value="93" name="TCO_STALL"/>
479
+
<value value="94" name="ANY_STALL"/>
480
+
<value value="95" name="TAG_MISSES"/>
481
+
<value value="96" name="TAG_HITS"/>
482
+
<value value="97" name="SUB_TAG_MISSES"/>
483
+
<value value="98" name="SET0_INVALIDATES"/>
484
+
<value value="99" name="SET1_INVALIDATES"/>
485
+
<value value="100" name="SET2_INVALIDATES"/>
486
+
<value value="101" name="SET3_INVALIDATES"/>
487
+
<value value="102" name="SET0_TAG_MISSES"/>
488
+
<value value="103" name="SET1_TAG_MISSES"/>
489
+
<value value="104" name="SET2_TAG_MISSES"/>
490
+
<value value="105" name="SET3_TAG_MISSES"/>
491
+
<value value="106" name="SET0_TAG_HITS"/>
492
+
<value value="107" name="SET1_TAG_HITS"/>
493
+
<value value="108" name="SET2_TAG_HITS"/>
494
+
<value value="109" name="SET3_TAG_HITS"/>
495
+
<value value="110" name="SET0_SUB_TAG_MISSES"/>
496
+
<value value="111" name="SET1_SUB_TAG_MISSES"/>
497
+
<value value="112" name="SET2_SUB_TAG_MISSES"/>
498
+
<value value="113" name="SET3_SUB_TAG_MISSES"/>
499
+
<value value="114" name="SET0_EVICT1"/>
500
+
<value value="115" name="SET0_EVICT2"/>
501
+
<value value="116" name="SET0_EVICT3"/>
502
+
<value value="117" name="SET0_EVICT4"/>
503
+
<value value="118" name="SET0_EVICT5"/>
504
+
<value value="119" name="SET0_EVICT6"/>
505
+
<value value="120" name="SET0_EVICT7"/>
506
+
<value value="121" name="SET0_EVICT8"/>
507
+
<value value="130" name="SET1_EVICT1"/>
508
+
<value value="131" name="SET1_EVICT2"/>
509
+
<value value="132" name="SET1_EVICT3"/>
510
+
<value value="133" name="SET1_EVICT4"/>
511
+
<value value="134" name="SET1_EVICT5"/>
512
+
<value value="135" name="SET1_EVICT6"/>
513
+
<value value="136" name="SET1_EVICT7"/>
514
+
<value value="137" name="SET1_EVICT8"/>
515
+
<value value="146" name="SET2_EVICT1"/>
516
+
<value value="147" name="SET2_EVICT2"/>
517
+
<value value="148" name="SET2_EVICT3"/>
518
+
<value value="149" name="SET2_EVICT4"/>
519
+
<value value="150" name="SET2_EVICT5"/>
520
+
<value value="151" name="SET2_EVICT6"/>
521
+
<value value="152" name="SET2_EVICT7"/>
522
+
<value value="153" name="SET2_EVICT8"/>
523
+
<value value="162" name="SET3_EVICT1"/>
524
+
<value value="163" name="SET3_EVICT2"/>
525
+
<value value="164" name="SET3_EVICT3"/>
526
+
<value value="165" name="SET3_EVICT4"/>
527
+
<value value="166" name="SET3_EVICT5"/>
528
+
<value value="167" name="SET3_EVICT6"/>
529
+
<value value="168" name="SET3_EVICT7"/>
530
+
<value value="169" name="SET3_EVICT8"/>
531
+
<value value="178" name="FF_EMPTY"/>
532
+
<value value="179" name="FF_LT_HALF_FULL"/>
533
+
<value value="180" name="FF_HALF_FULL"/>
534
+
<value value="181" name="FF_FULL"/>
535
+
<value value="182" name="FF_XFC"/>
536
+
<value value="183" name="FF_STALLED"/>
537
+
<value value="184" name="FG_MASKS"/>
538
+
<value value="185" name="FG_LEFT_MASKS"/>
539
+
<value value="186" name="FG_LEFT_MASK_STALLED"/>
540
+
<value value="187" name="FG_LEFT_NOT_DONE_STALL"/>
541
+
<value value="188" name="FG_LEFT_FG_STALL"/>
542
+
<value value="189" name="FG_LEFT_SECTORS"/>
543
+
<value value="195" name="FG0_REQUESTS"/>
544
+
<value value="196" name="FG0_STALLED"/>
545
+
<value value="199" name="MEM_REQ512"/>
546
+
<value value="200" name="MEM_REQ_SENT"/>
547
+
<value value="202" name="MEM_LOCAL_READ_REQ"/>
548
+
<value value="203" name="TC0_MH_STALLED"/>
549
+
</enum>
550
+
551
+
<enum name="a2xx_sq_perfcnt_select">
552
+
<value value="0" name="SQ_PIXEL_VECTORS_SUB"/>
553
+
<value value="1" name="SQ_VERTEX_VECTORS_SUB"/>
554
+
<value value="2" name="SQ_ALU0_ACTIVE_VTX_SIMD0"/>
555
+
<value value="3" name="SQ_ALU1_ACTIVE_VTX_SIMD0"/>
556
+
<value value="4" name="SQ_ALU0_ACTIVE_PIX_SIMD0"/>
557
+
<value value="5" name="SQ_ALU1_ACTIVE_PIX_SIMD0"/>
558
+
<value value="6" name="SQ_ALU0_ACTIVE_VTX_SIMD1"/>
559
+
<value value="7" name="SQ_ALU1_ACTIVE_VTX_SIMD1"/>
560
+
<value value="8" name="SQ_ALU0_ACTIVE_PIX_SIMD1"/>
561
+
<value value="9" name="SQ_ALU1_ACTIVE_PIX_SIMD1"/>
562
+
<value value="10" name="SQ_EXPORT_CYCLES"/>
563
+
<value value="11" name="SQ_ALU_CST_WRITTEN"/>
564
+
<value value="12" name="SQ_TEX_CST_WRITTEN"/>
565
+
<value value="13" name="SQ_ALU_CST_STALL"/>
566
+
<value value="14" name="SQ_ALU_TEX_STALL"/>
567
+
<value value="15" name="SQ_INST_WRITTEN"/>
568
+
<value value="16" name="SQ_BOOLEAN_WRITTEN"/>
569
+
<value value="17" name="SQ_LOOPS_WRITTEN"/>
570
+
<value value="18" name="SQ_PIXEL_SWAP_IN"/>
571
+
<value value="19" name="SQ_PIXEL_SWAP_OUT"/>
572
+
<value value="20" name="SQ_VERTEX_SWAP_IN"/>
573
+
<value value="21" name="SQ_VERTEX_SWAP_OUT"/>
574
+
<value value="22" name="SQ_ALU_VTX_INST_ISSUED"/>
575
+
<value value="23" name="SQ_TEX_VTX_INST_ISSUED"/>
576
+
<value value="24" name="SQ_VC_VTX_INST_ISSUED"/>
577
+
<value value="25" name="SQ_CF_VTX_INST_ISSUED"/>
578
+
<value value="26" name="SQ_ALU_PIX_INST_ISSUED"/>
579
+
<value value="27" name="SQ_TEX_PIX_INST_ISSUED"/>
580
+
<value value="28" name="SQ_VC_PIX_INST_ISSUED"/>
581
+
<value value="29" name="SQ_CF_PIX_INST_ISSUED"/>
582
+
<value value="30" name="SQ_ALU0_FIFO_EMPTY_SIMD0"/>
583
+
<value value="31" name="SQ_ALU1_FIFO_EMPTY_SIMD0"/>
584
+
<value value="32" name="SQ_ALU0_FIFO_EMPTY_SIMD1"/>
585
+
<value value="33" name="SQ_ALU1_FIFO_EMPTY_SIMD1"/>
586
+
<value value="34" name="SQ_ALU_NOPS"/>
587
+
<value value="35" name="SQ_PRED_SKIP"/>
588
+
<value value="36" name="SQ_SYNC_ALU_STALL_SIMD0_VTX"/>
589
+
<value value="37" name="SQ_SYNC_ALU_STALL_SIMD1_VTX"/>
590
+
<value value="38" name="SQ_SYNC_TEX_STALL_VTX"/>
591
+
<value value="39" name="SQ_SYNC_VC_STALL_VTX"/>
592
+
<value value="40" name="SQ_CONSTANTS_USED_SIMD0"/>
593
+
<value value="41" name="SQ_CONSTANTS_SENT_SP_SIMD0"/>
594
+
<value value="42" name="SQ_GPR_STALL_VTX"/>
595
+
<value value="43" name="SQ_GPR_STALL_PIX"/>
596
+
<value value="44" name="SQ_VTX_RS_STALL"/>
597
+
<value value="45" name="SQ_PIX_RS_STALL"/>
598
+
<value value="46" name="SQ_SX_PC_FULL"/>
599
+
<value value="47" name="SQ_SX_EXP_BUFF_FULL"/>
600
+
<value value="48" name="SQ_SX_POS_BUFF_FULL"/>
601
+
<value value="49" name="SQ_INTERP_QUADS"/>
602
+
<value value="50" name="SQ_INTERP_ACTIVE"/>
603
+
<value value="51" name="SQ_IN_PIXEL_STALL"/>
604
+
<value value="52" name="SQ_IN_VTX_STALL"/>
605
+
<value value="53" name="SQ_VTX_CNT"/>
606
+
<value value="54" name="SQ_VTX_VECTOR2"/>
607
+
<value value="55" name="SQ_VTX_VECTOR3"/>
608
+
<value value="56" name="SQ_VTX_VECTOR4"/>
609
+
<value value="57" name="SQ_PIXEL_VECTOR1"/>
610
+
<value value="58" name="SQ_PIXEL_VECTOR23"/>
611
+
<value value="59" name="SQ_PIXEL_VECTOR4"/>
612
+
<value value="60" name="SQ_CONSTANTS_USED_SIMD1"/>
613
+
<value value="61" name="SQ_CONSTANTS_SENT_SP_SIMD1"/>
614
+
<value value="62" name="SQ_SX_MEM_EXP_FULL"/>
615
+
<value value="63" name="SQ_ALU0_ACTIVE_VTX_SIMD2"/>
616
+
<value value="64" name="SQ_ALU1_ACTIVE_VTX_SIMD2"/>
617
+
<value value="65" name="SQ_ALU0_ACTIVE_PIX_SIMD2"/>
618
+
<value value="66" name="SQ_ALU1_ACTIVE_PIX_SIMD2"/>
619
+
<value value="67" name="SQ_ALU0_ACTIVE_VTX_SIMD3"/>
620
+
<value value="68" name="SQ_PERFCOUNT_VTX_QUAL_TP_DONE"/>
621
+
<value value="69" name="SQ_ALU0_ACTIVE_PIX_SIMD3"/>
622
+
<value value="70" name="SQ_PERFCOUNT_PIX_QUAL_TP_DONE"/>
623
+
<value value="71" name="SQ_ALU0_FIFO_EMPTY_SIMD2"/>
624
+
<value value="72" name="SQ_ALU1_FIFO_EMPTY_SIMD2"/>
625
+
<value value="73" name="SQ_ALU0_FIFO_EMPTY_SIMD3"/>
626
+
<value value="74" name="SQ_ALU1_FIFO_EMPTY_SIMD3"/>
627
+
<value value="75" name="SQ_SYNC_ALU_STALL_SIMD2_VTX"/>
628
+
<value value="76" name="SQ_PERFCOUNT_VTX_POP_THREAD"/>
629
+
<value value="77" name="SQ_SYNC_ALU_STALL_SIMD0_PIX"/>
630
+
<value value="78" name="SQ_SYNC_ALU_STALL_SIMD1_PIX"/>
631
+
<value value="79" name="SQ_SYNC_ALU_STALL_SIMD2_PIX"/>
632
+
<value value="80" name="SQ_PERFCOUNT_PIX_POP_THREAD"/>
633
+
<value value="81" name="SQ_SYNC_TEX_STALL_PIX"/>
634
+
<value value="82" name="SQ_SYNC_VC_STALL_PIX"/>
635
+
<value value="83" name="SQ_CONSTANTS_USED_SIMD2"/>
636
+
<value value="84" name="SQ_CONSTANTS_SENT_SP_SIMD2"/>
637
+
<value value="85" name="SQ_PERFCOUNT_VTX_DEALLOC_ACK"/>
638
+
<value value="86" name="SQ_PERFCOUNT_PIX_DEALLOC_ACK"/>
639
+
<value value="87" name="SQ_ALU0_FIFO_FULL_SIMD0"/>
640
+
<value value="88" name="SQ_ALU1_FIFO_FULL_SIMD0"/>
641
+
<value value="89" name="SQ_ALU0_FIFO_FULL_SIMD1"/>
642
+
<value value="90" name="SQ_ALU1_FIFO_FULL_SIMD1"/>
643
+
<value value="91" name="SQ_ALU0_FIFO_FULL_SIMD2"/>
644
+
<value value="92" name="SQ_ALU1_FIFO_FULL_SIMD2"/>
645
+
<value value="93" name="SQ_ALU0_FIFO_FULL_SIMD3"/>
646
+
<value value="94" name="SQ_ALU1_FIFO_FULL_SIMD3"/>
647
+
<value value="95" name="VC_PERF_STATIC"/>
648
+
<value value="96" name="VC_PERF_STALLED"/>
649
+
<value value="97" name="VC_PERF_STARVED"/>
650
+
<value value="98" name="VC_PERF_SEND"/>
651
+
<value value="99" name="VC_PERF_ACTUAL_STARVED"/>
652
+
<value value="100" name="PIXEL_THREAD_0_ACTIVE"/>
653
+
<value value="101" name="VERTEX_THREAD_0_ACTIVE"/>
654
+
<value value="102" name="PIXEL_THREAD_0_NUMBER"/>
655
+
<value value="103" name="VERTEX_THREAD_0_NUMBER"/>
656
+
<value value="104" name="VERTEX_EVENT_NUMBER"/>
657
+
<value value="105" name="PIXEL_EVENT_NUMBER"/>
658
+
<value value="106" name="PTRBUFF_EF_PUSH"/>
659
+
<value value="107" name="PTRBUFF_EF_POP_EVENT"/>
660
+
<value value="108" name="PTRBUFF_EF_POP_NEW_VTX"/>
661
+
<value value="109" name="PTRBUFF_EF_POP_DEALLOC"/>
662
+
<value value="110" name="PTRBUFF_EF_POP_PVECTOR"/>
663
+
<value value="111" name="PTRBUFF_EF_POP_PVECTOR_X"/>
664
+
<value value="112" name="PTRBUFF_EF_POP_PVECTOR_VNZ"/>
665
+
<value value="113" name="PTRBUFF_PB_DEALLOC"/>
666
+
<value value="114" name="PTRBUFF_PI_STATE_PPB_POP"/>
667
+
<value value="115" name="PTRBUFF_PI_RTR"/>
668
+
<value value="116" name="PTRBUFF_PI_READ_EN"/>
669
+
<value value="117" name="PTRBUFF_PI_BUFF_SWAP"/>
670
+
<value value="118" name="PTRBUFF_SQ_FREE_BUFF"/>
671
+
<value value="119" name="PTRBUFF_SQ_DEC"/>
672
+
<value value="120" name="PTRBUFF_SC_VALID_CNTL_EVENT"/>
673
+
<value value="121" name="PTRBUFF_SC_VALID_IJ_XFER"/>
674
+
<value value="122" name="PTRBUFF_SC_NEW_VECTOR_1_Q"/>
675
+
<value value="123" name="PTRBUFF_QUAL_NEW_VECTOR"/>
676
+
<value value="124" name="PTRBUFF_QUAL_EVENT"/>
677
+
<value value="125" name="PTRBUFF_END_BUFFER"/>
678
+
<value value="126" name="PTRBUFF_FILL_QUAD"/>
679
+
<value value="127" name="VERTS_WRITTEN_SPI"/>
680
+
<value value="128" name="TP_FETCH_INSTR_EXEC"/>
681
+
<value value="129" name="TP_FETCH_INSTR_REQ"/>
682
+
<value value="130" name="TP_DATA_RETURN"/>
683
+
<value value="131" name="SPI_WRITE_CYCLES_SP"/>
684
+
<value value="132" name="SPI_WRITES_SP"/>
685
+
<value value="133" name="SP_ALU_INSTR_EXEC"/>
686
+
<value value="134" name="SP_CONST_ADDR_TO_SQ"/>
687
+
<value value="135" name="SP_PRED_KILLS_TO_SQ"/>
688
+
<value value="136" name="SP_EXPORT_CYCLES_TO_SX"/>
689
+
<value value="137" name="SP_EXPORTS_TO_SX"/>
690
+
<value value="138" name="SQ_CYCLES_ELAPSED"/>
691
+
<value value="139" name="SQ_TCFS_OPT_ALLOC_EXEC"/>
692
+
<value value="140" name="SQ_TCFS_NO_OPT_ALLOC"/>
693
+
<value value="141" name="SQ_ALU0_NO_OPT_ALLOC"/>
694
+
<value value="142" name="SQ_ALU1_NO_OPT_ALLOC"/>
695
+
<value value="143" name="SQ_TCFS_ARB_XFC_CNT"/>
696
+
<value value="144" name="SQ_ALU0_ARB_XFC_CNT"/>
697
+
<value value="145" name="SQ_ALU1_ARB_XFC_CNT"/>
698
+
<value value="146" name="SQ_TCFS_CFS_UPDATE_CNT"/>
699
+
<value value="147" name="SQ_ALU0_CFS_UPDATE_CNT"/>
700
+
<value value="148" name="SQ_ALU1_CFS_UPDATE_CNT"/>
701
+
<value value="149" name="SQ_VTX_PUSH_THREAD_CNT"/>
702
+
<value value="150" name="SQ_VTX_POP_THREAD_CNT"/>
703
+
<value value="151" name="SQ_PIX_PUSH_THREAD_CNT"/>
704
+
<value value="152" name="SQ_PIX_POP_THREAD_CNT"/>
705
+
<value value="153" name="SQ_PIX_TOTAL"/>
706
+
<value value="154" name="SQ_PIX_KILLED"/>
707
+
</enum>
708
+
709
+
<enum name="a2xx_sx_perfcnt_select">
710
+
<value value="0" name="SX_EXPORT_VECTORS"/>
711
+
<value value="1" name="SX_DUMMY_QUADS"/>
712
+
<value value="2" name="SX_ALPHA_FAIL"/>
713
+
<value value="3" name="SX_RB_QUAD_BUSY"/>
714
+
<value value="4" name="SX_RB_COLOR_BUSY"/>
715
+
<value value="5" name="SX_RB_QUAD_STALL"/>
716
+
<value value="6" name="SX_RB_COLOR_STALL"/>
717
+
</enum>
718
+
719
+
<enum name="a2xx_rbbm_perfcount1_sel">
720
+
<value value="0" name="RBBM1_COUNT"/>
721
+
<value value="1" name="RBBM1_NRT_BUSY"/>
722
+
<value value="2" name="RBBM1_RB_BUSY"/>
723
+
<value value="3" name="RBBM1_SQ_CNTX0_BUSY"/>
724
+
<value value="4" name="RBBM1_SQ_CNTX17_BUSY"/>
725
+
<value value="5" name="RBBM1_VGT_BUSY"/>
726
+
<value value="6" name="RBBM1_VGT_NODMA_BUSY"/>
727
+
<value value="7" name="RBBM1_PA_BUSY"/>
728
+
<value value="8" name="RBBM1_SC_CNTX_BUSY"/>
729
+
<value value="9" name="RBBM1_TPC_BUSY"/>
730
+
<value value="10" name="RBBM1_TC_BUSY"/>
731
+
<value value="11" name="RBBM1_SX_BUSY"/>
732
+
<value value="12" name="RBBM1_CP_COHER_BUSY"/>
733
+
<value value="13" name="RBBM1_CP_NRT_BUSY"/>
734
+
<value value="14" name="RBBM1_GFX_IDLE_STALL"/>
735
+
<value value="15" name="RBBM1_INTERRUPT"/>
736
+
</enum>
737
+
738
+
<enum name="a2xx_cp_perfcount_sel">
739
+
<value value="0" name="ALWAYS_COUNT"/>
740
+
<value value="1" name="TRANS_FIFO_FULL"/>
741
+
<value value="2" name="TRANS_FIFO_AF"/>
742
+
<value value="3" name="RCIU_PFPTRANS_WAIT"/>
743
+
<value value="6" name="RCIU_NRTTRANS_WAIT"/>
744
+
<value value="8" name="CSF_NRT_READ_WAIT"/>
745
+
<value value="9" name="CSF_I1_FIFO_FULL"/>
746
+
<value value="10" name="CSF_I2_FIFO_FULL"/>
747
+
<value value="11" name="CSF_ST_FIFO_FULL"/>
748
+
<value value="13" name="CSF_RING_ROQ_FULL"/>
749
+
<value value="14" name="CSF_I1_ROQ_FULL"/>
750
+
<value value="15" name="CSF_I2_ROQ_FULL"/>
751
+
<value value="16" name="CSF_ST_ROQ_FULL"/>
752
+
<value value="18" name="MIU_TAG_MEM_FULL"/>
753
+
<value value="19" name="MIU_WRITECLEAN"/>
754
+
<value value="22" name="MIU_NRT_WRITE_STALLED"/>
755
+
<value value="23" name="MIU_NRT_READ_STALLED"/>
756
+
<value value="24" name="ME_WRITE_CONFIRM_FIFO_FULL"/>
757
+
<value value="25" name="ME_VS_DEALLOC_FIFO_FULL"/>
758
+
<value value="26" name="ME_PS_DEALLOC_FIFO_FULL"/>
759
+
<value value="27" name="ME_REGS_VS_EVENT_FIFO_FULL"/>
760
+
<value value="28" name="ME_REGS_PS_EVENT_FIFO_FULL"/>
761
+
<value value="29" name="ME_REGS_CF_EVENT_FIFO_FULL"/>
762
+
<value value="30" name="ME_MICRO_RB_STARVED"/>
763
+
<value value="31" name="ME_MICRO_I1_STARVED"/>
764
+
<value value="32" name="ME_MICRO_I2_STARVED"/>
765
+
<value value="33" name="ME_MICRO_ST_STARVED"/>
766
+
<value value="40" name="RCIU_RBBM_DWORD_SENT"/>
767
+
<value value="41" name="ME_BUSY_CLOCKS"/>
768
+
<value value="42" name="ME_WAIT_CONTEXT_AVAIL"/>
769
+
<value value="43" name="PFP_TYPE0_PACKET"/>
770
+
<value value="44" name="PFP_TYPE3_PACKET"/>
771
+
<value value="45" name="CSF_RB_WPTR_NEQ_RPTR"/>
772
+
<value value="46" name="CSF_I1_SIZE_NEQ_ZERO"/>
773
+
<value value="47" name="CSF_I2_SIZE_NEQ_ZERO"/>
774
+
<value value="48" name="CSF_RBI1I2_FETCHING"/>
775
+
</enum>
776
+
777
+
<enum name="a2xx_rb_perfcnt_select">
778
+
<value value="0" name="RBPERF_CNTX_BUSY"/>
779
+
<value value="1" name="RBPERF_CNTX_BUSY_MAX"/>
780
+
<value value="2" name="RBPERF_SX_QUAD_STARVED"/>
781
+
<value value="3" name="RBPERF_SX_QUAD_STARVED_MAX"/>
782
+
<value value="4" name="RBPERF_GA_GC_CH0_SYS_REQ"/>
783
+
<value value="5" name="RBPERF_GA_GC_CH0_SYS_REQ_MAX"/>
784
+
<value value="6" name="RBPERF_GA_GC_CH1_SYS_REQ"/>
785
+
<value value="7" name="RBPERF_GA_GC_CH1_SYS_REQ_MAX"/>
786
+
<value value="8" name="RBPERF_MH_STARVED"/>
787
+
<value value="9" name="RBPERF_MH_STARVED_MAX"/>
788
+
<value value="10" name="RBPERF_AZ_BC_COLOR_BUSY"/>
789
+
<value value="11" name="RBPERF_AZ_BC_COLOR_BUSY_MAX"/>
790
+
<value value="12" name="RBPERF_AZ_BC_Z_BUSY"/>
791
+
<value value="13" name="RBPERF_AZ_BC_Z_BUSY_MAX"/>
792
+
<value value="14" name="RBPERF_RB_SC_TILE_RTR_N"/>
793
+
<value value="15" name="RBPERF_RB_SC_TILE_RTR_N_MAX"/>
794
+
<value value="16" name="RBPERF_RB_SC_SAMP_RTR_N"/>
795
+
<value value="17" name="RBPERF_RB_SC_SAMP_RTR_N_MAX"/>
796
+
<value value="18" name="RBPERF_RB_SX_QUAD_RTR_N"/>
797
+
<value value="19" name="RBPERF_RB_SX_QUAD_RTR_N_MAX"/>
798
+
<value value="20" name="RBPERF_RB_SX_COLOR_RTR_N"/>
799
+
<value value="21" name="RBPERF_RB_SX_COLOR_RTR_N_MAX"/>
800
+
<value value="22" name="RBPERF_RB_SC_SAMP_LZ_BUSY"/>
801
+
<value value="23" name="RBPERF_RB_SC_SAMP_LZ_BUSY_MAX"/>
802
+
<value value="24" name="RBPERF_ZXP_STALL"/>
803
+
<value value="25" name="RBPERF_ZXP_STALL_MAX"/>
804
+
<value value="26" name="RBPERF_EVENT_PENDING"/>
805
+
<value value="27" name="RBPERF_EVENT_PENDING_MAX"/>
806
+
<value value="28" name="RBPERF_RB_MH_VALID"/>
807
+
<value value="29" name="RBPERF_RB_MH_VALID_MAX"/>
808
+
<value value="30" name="RBPERF_SX_RB_QUAD_SEND"/>
809
+
<value value="31" name="RBPERF_SX_RB_COLOR_SEND"/>
810
+
<value value="32" name="RBPERF_SC_RB_TILE_SEND"/>
811
+
<value value="33" name="RBPERF_SC_RB_SAMPLE_SEND"/>
812
+
<value value="34" name="RBPERF_SX_RB_MEM_EXPORT"/>
813
+
<value value="35" name="RBPERF_SX_RB_QUAD_EVENT"/>
814
+
<value value="36" name="RBPERF_SC_RB_TILE_EVENT_FILTERED"/>
815
+
<value value="37" name="RBPERF_SC_RB_TILE_EVENT_ALL"/>
816
+
<value value="38" name="RBPERF_RB_SC_EZ_SEND"/>
817
+
<value value="39" name="RBPERF_RB_SX_INDEX_SEND"/>
818
+
<value value="40" name="RBPERF_GMEM_INTFO_RD"/>
819
+
<value value="41" name="RBPERF_GMEM_INTF1_RD"/>
820
+
<value value="42" name="RBPERF_GMEM_INTFO_WR"/>
821
+
<value value="43" name="RBPERF_GMEM_INTF1_WR"/>
822
+
<value value="44" name="RBPERF_RB_CP_CONTEXT_DONE"/>
823
+
<value value="45" name="RBPERF_RB_CP_CACHE_FLUSH"/>
824
+
<value value="46" name="RBPERF_ZPASS_DONE"/>
825
+
<value value="47" name="RBPERF_ZCMD_VALID"/>
826
+
<value value="48" name="RBPERF_CCMD_VALID"/>
827
+
<value value="49" name="RBPERF_ACCUM_GRANT"/>
828
+
<value value="50" name="RBPERF_ACCUM_C0_GRANT"/>
829
+
<value value="51" name="RBPERF_ACCUM_C1_GRANT"/>
830
+
<value value="52" name="RBPERF_ACCUM_FULL_BE_WR"/>
831
+
<value value="53" name="RBPERF_ACCUM_REQUEST_NO_GRANT"/>
832
+
<value value="54" name="RBPERF_ACCUM_TIMEOUT_PULSE"/>
833
+
<value value="55" name="RBPERF_ACCUM_LIN_TIMEOUT_PULSE"/>
834
+
<value value="56" name="RBPERF_ACCUM_CAM_HIT_FLUSHING"/>
835
+
</enum>
836
+
837
+
<enum name="a2xx_mh_perfcnt_select">
838
+
<value value="0" name="CP_R0_REQUESTS"/>
839
+
<value value="1" name="CP_R1_REQUESTS"/>
840
+
<value value="2" name="CP_R2_REQUESTS"/>
841
+
<value value="3" name="CP_R3_REQUESTS"/>
842
+
<value value="4" name="CP_R4_REQUESTS"/>
843
+
<value value="5" name="CP_TOTAL_READ_REQUESTS"/>
844
+
<value value="6" name="CP_TOTAL_WRITE_REQUESTS"/>
845
+
<value value="7" name="CP_TOTAL_REQUESTS"/>
846
+
<value value="8" name="CP_DATA_BYTES_WRITTEN"/>
847
+
<value value="9" name="CP_WRITE_CLEAN_RESPONSES"/>
848
+
<value value="10" name="CP_R0_READ_BURSTS_RECEIVED"/>
849
+
<value value="11" name="CP_R1_READ_BURSTS_RECEIVED"/>
850
+
<value value="12" name="CP_R2_READ_BURSTS_RECEIVED"/>
851
+
<value value="13" name="CP_R3_READ_BURSTS_RECEIVED"/>
852
+
<value value="14" name="CP_R4_READ_BURSTS_RECEIVED"/>
853
+
<value value="15" name="CP_TOTAL_READ_BURSTS_RECEIVED"/>
854
+
<value value="16" name="CP_R0_DATA_BEATS_READ"/>
855
+
<value value="17" name="CP_R1_DATA_BEATS_READ"/>
856
+
<value value="18" name="CP_R2_DATA_BEATS_READ"/>
857
+
<value value="19" name="CP_R3_DATA_BEATS_READ"/>
858
+
<value value="20" name="CP_R4_DATA_BEATS_READ"/>
859
+
<value value="21" name="CP_TOTAL_DATA_BEATS_READ"/>
860
+
<value value="22" name="VGT_R0_REQUESTS"/>
861
+
<value value="23" name="VGT_R1_REQUESTS"/>
862
+
<value value="24" name="VGT_TOTAL_REQUESTS"/>
863
+
<value value="25" name="VGT_R0_READ_BURSTS_RECEIVED"/>
864
+
<value value="26" name="VGT_R1_READ_BURSTS_RECEIVED"/>
865
+
<value value="27" name="VGT_TOTAL_READ_BURSTS_RECEIVED"/>
866
+
<value value="28" name="VGT_R0_DATA_BEATS_READ"/>
867
+
<value value="29" name="VGT_R1_DATA_BEATS_READ"/>
868
+
<value value="30" name="VGT_TOTAL_DATA_BEATS_READ"/>
869
+
<value value="31" name="TC_TOTAL_REQUESTS"/>
870
+
<value value="32" name="TC_ROQ_REQUESTS"/>
871
+
<value value="33" name="TC_INFO_SENT"/>
872
+
<value value="34" name="TC_READ_BURSTS_RECEIVED"/>
873
+
<value value="35" name="TC_DATA_BEATS_READ"/>
874
+
<value value="36" name="TCD_BURSTS_READ"/>
875
+
<value value="37" name="RB_REQUESTS"/>
876
+
<value value="38" name="RB_DATA_BYTES_WRITTEN"/>
877
+
<value value="39" name="RB_WRITE_CLEAN_RESPONSES"/>
878
+
<value value="40" name="AXI_READ_REQUESTS_ID_0"/>
879
+
<value value="41" name="AXI_READ_REQUESTS_ID_1"/>
880
+
<value value="42" name="AXI_READ_REQUESTS_ID_2"/>
881
+
<value value="43" name="AXI_READ_REQUESTS_ID_3"/>
882
+
<value value="44" name="AXI_READ_REQUESTS_ID_4"/>
883
+
<value value="45" name="AXI_READ_REQUESTS_ID_5"/>
884
+
<value value="46" name="AXI_READ_REQUESTS_ID_6"/>
885
+
<value value="47" name="AXI_READ_REQUESTS_ID_7"/>
886
+
<value value="48" name="AXI_TOTAL_READ_REQUESTS"/>
887
+
<value value="49" name="AXI_WRITE_REQUESTS_ID_0"/>
888
+
<value value="50" name="AXI_WRITE_REQUESTS_ID_1"/>
889
+
<value value="51" name="AXI_WRITE_REQUESTS_ID_2"/>
890
+
<value value="52" name="AXI_WRITE_REQUESTS_ID_3"/>
891
+
<value value="53" name="AXI_WRITE_REQUESTS_ID_4"/>
892
+
<value value="54" name="AXI_WRITE_REQUESTS_ID_5"/>
893
+
<value value="55" name="AXI_WRITE_REQUESTS_ID_6"/>
894
+
<value value="56" name="AXI_WRITE_REQUESTS_ID_7"/>
895
+
<value value="57" name="AXI_TOTAL_WRITE_REQUESTS"/>
896
+
<value value="58" name="AXI_TOTAL_REQUESTS_ID_0"/>
897
+
<value value="59" name="AXI_TOTAL_REQUESTS_ID_1"/>
898
+
<value value="60" name="AXI_TOTAL_REQUESTS_ID_2"/>
899
+
<value value="61" name="AXI_TOTAL_REQUESTS_ID_3"/>
900
+
<value value="62" name="AXI_TOTAL_REQUESTS_ID_4"/>
901
+
<value value="63" name="AXI_TOTAL_REQUESTS_ID_5"/>
902
+
<value value="64" name="AXI_TOTAL_REQUESTS_ID_6"/>
903
+
<value value="65" name="AXI_TOTAL_REQUESTS_ID_7"/>
904
+
<value value="66" name="AXI_TOTAL_REQUESTS"/>
905
+
<value value="67" name="AXI_READ_CHANNEL_BURSTS_ID_0"/>
906
+
<value value="68" name="AXI_READ_CHANNEL_BURSTS_ID_1"/>
907
+
<value value="69" name="AXI_READ_CHANNEL_BURSTS_ID_2"/>
908
+
<value value="70" name="AXI_READ_CHANNEL_BURSTS_ID_3"/>
909
+
<value value="71" name="AXI_READ_CHANNEL_BURSTS_ID_4"/>
910
+
<value value="72" name="AXI_READ_CHANNEL_BURSTS_ID_5"/>
911
+
<value value="73" name="AXI_READ_CHANNEL_BURSTS_ID_6"/>
912
+
<value value="74" name="AXI_READ_CHANNEL_BURSTS_ID_7"/>
913
+
<value value="75" name="AXI_READ_CHANNEL_TOTAL_BURSTS"/>
914
+
<value value="76" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0"/>
915
+
<value value="77" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1"/>
916
+
<value value="78" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2"/>
917
+
<value value="79" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3"/>
918
+
<value value="80" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4"/>
919
+
<value value="81" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5"/>
920
+
<value value="82" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6"/>
921
+
<value value="83" name="AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7"/>
922
+
<value value="84" name="AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ"/>
923
+
<value value="85" name="AXI_WRITE_CHANNEL_BURSTS_ID_0"/>
924
+
<value value="86" name="AXI_WRITE_CHANNEL_BURSTS_ID_1"/>
925
+
<value value="87" name="AXI_WRITE_CHANNEL_BURSTS_ID_2"/>
926
+
<value value="88" name="AXI_WRITE_CHANNEL_BURSTS_ID_3"/>
927
+
<value value="89" name="AXI_WRITE_CHANNEL_BURSTS_ID_4"/>
928
+
<value value="90" name="AXI_WRITE_CHANNEL_BURSTS_ID_5"/>
929
+
<value value="91" name="AXI_WRITE_CHANNEL_BURSTS_ID_6"/>
930
+
<value value="92" name="AXI_WRITE_CHANNEL_BURSTS_ID_7"/>
931
+
<value value="93" name="AXI_WRITE_CHANNEL_TOTAL_BURSTS"/>
932
+
<value value="94" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0"/>
933
+
<value value="95" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1"/>
934
+
<value value="96" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2"/>
935
+
<value value="97" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3"/>
936
+
<value value="98" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4"/>
937
+
<value value="99" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5"/>
938
+
<value value="100" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6"/>
939
+
<value value="101" name="AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7"/>
940
+
<value value="102" name="AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN"/>
941
+
<value value="103" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0"/>
942
+
<value value="104" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1"/>
943
+
<value value="105" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2"/>
944
+
<value value="106" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3"/>
945
+
<value value="107" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4"/>
946
+
<value value="108" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5"/>
947
+
<value value="109" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6"/>
948
+
<value value="110" name="AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7"/>
949
+
<value value="111" name="AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES"/>
950
+
<value value="112" name="TOTAL_MMU_MISSES"/>
951
+
<value value="113" name="MMU_READ_MISSES"/>
952
+
<value value="114" name="MMU_WRITE_MISSES"/>
953
+
<value value="115" name="TOTAL_MMU_HITS"/>
954
+
<value value="116" name="MMU_READ_HITS"/>
955
+
<value value="117" name="MMU_WRITE_HITS"/>
956
+
<value value="118" name="SPLIT_MODE_TC_HITS"/>
957
+
<value value="119" name="SPLIT_MODE_TC_MISSES"/>
958
+
<value value="120" name="SPLIT_MODE_NON_TC_HITS"/>
959
+
<value value="121" name="SPLIT_MODE_NON_TC_MISSES"/>
960
+
<value value="122" name="STALL_AWAITING_TLB_MISS_FETCH"/>
961
+
<value value="123" name="MMU_TLB_MISS_READ_BURSTS_RECEIVED"/>
962
+
<value value="124" name="MMU_TLB_MISS_DATA_BEATS_READ"/>
963
+
<value value="125" name="CP_CYCLES_HELD_OFF"/>
964
+
<value value="126" name="VGT_CYCLES_HELD_OFF"/>
965
+
<value value="127" name="TC_CYCLES_HELD_OFF"/>
966
+
<value value="128" name="TC_ROQ_CYCLES_HELD_OFF"/>
967
+
<value value="129" name="TC_CYCLES_HELD_OFF_TCD_FULL"/>
968
+
<value value="130" name="RB_CYCLES_HELD_OFF"/>
969
+
<value value="131" name="TOTAL_CYCLES_ANY_CLNT_HELD_OFF"/>
970
+
<value value="132" name="TLB_MISS_CYCLES_HELD_OFF"/>
971
+
<value value="133" name="AXI_READ_REQUEST_HELD_OFF"/>
972
+
<value value="134" name="AXI_WRITE_REQUEST_HELD_OFF"/>
973
+
<value value="135" name="AXI_REQUEST_HELD_OFF"/>
974
+
<value value="136" name="AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT"/>
975
+
<value value="137" name="AXI_WRITE_DATA_HELD_OFF"/>
976
+
<value value="138" name="CP_SAME_PAGE_BANK_REQUESTS"/>
977
+
<value value="139" name="VGT_SAME_PAGE_BANK_REQUESTS"/>
978
+
<value value="140" name="TC_SAME_PAGE_BANK_REQUESTS"/>
979
+
<value value="141" name="TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS"/>
980
+
<value value="142" name="RB_SAME_PAGE_BANK_REQUESTS"/>
981
+
<value value="143" name="TOTAL_SAME_PAGE_BANK_REQUESTS"/>
982
+
<value value="144" name="CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
983
+
<value value="145" name="VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
984
+
<value value="146" name="TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
985
+
<value value="147" name="RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT"/>
986
+
<value value="148" name="TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT"/>
987
+
<value value="149" name="TOTAL_MH_READ_REQUESTS"/>
988
+
<value value="150" name="TOTAL_MH_WRITE_REQUESTS"/>
989
+
<value value="151" name="TOTAL_MH_REQUESTS"/>
990
+
<value value="152" name="MH_BUSY"/>
991
+
<value value="153" name="CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
992
+
<value value="154" name="VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
993
+
<value value="155" name="TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
994
+
<value value="156" name="RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE"/>
995
+
<value value="157" name="TC_ROQ_N_VALID_ENTRIES"/>
996
+
<value value="158" name="ARQ_N_ENTRIES"/>
997
+
<value value="159" name="WDB_N_ENTRIES"/>
998
+
<value value="160" name="MH_READ_LATENCY_OUTST_REQ_SUM"/>
999
+
<value value="161" name="MC_READ_LATENCY_OUTST_REQ_SUM"/>
1000
+
<value value="162" name="MC_TOTAL_READ_REQUESTS"/>
1001
+
<value value="163" name="ELAPSED_CYCLES_MH_GATED_CLK"/>
1002
+
<value value="164" name="ELAPSED_CLK_CYCLES"/>
1003
+
<value value="165" name="CP_W_16B_REQUESTS"/>
1004
+
<value value="166" name="CP_W_32B_REQUESTS"/>
1005
+
<value value="167" name="TC_16B_REQUESTS"/>
1006
+
<value value="168" name="TC_32B_REQUESTS"/>
1007
+
<value value="169" name="PA_REQUESTS"/>
1008
+
<value value="170" name="PA_DATA_BYTES_WRITTEN"/>
1009
+
<value value="171" name="PA_WRITE_CLEAN_RESPONSES"/>
1010
+
<value value="172" name="PA_CYCLES_HELD_OFF"/>
1011
+
<value value="173" name="AXI_READ_REQUEST_DATA_BEATS_ID_0"/>
1012
+
<value value="174" name="AXI_READ_REQUEST_DATA_BEATS_ID_1"/>
1013
+
<value value="175" name="AXI_READ_REQUEST_DATA_BEATS_ID_2"/>
1014
+
<value value="176" name="AXI_READ_REQUEST_DATA_BEATS_ID_3"/>
1015
+
<value value="177" name="AXI_READ_REQUEST_DATA_BEATS_ID_4"/>
1016
+
<value value="178" name="AXI_READ_REQUEST_DATA_BEATS_ID_5"/>
1017
+
<value value="179" name="AXI_READ_REQUEST_DATA_BEATS_ID_6"/>
1018
+
<value value="180" name="AXI_READ_REQUEST_DATA_BEATS_ID_7"/>
1019
+
<value value="181" name="AXI_TOTAL_READ_REQUEST_DATA_BEATS"/>
1020
+
</enum>
1021
+
1022
+
<enum name="perf_mode_cnt">
1023
+
<value name="PERF_STATE_RESET" value="0"/>
1024
+
<value name="PERF_STATE_ENABLE" value="1"/>
1025
+
<value name="PERF_STATE_FREEZE" value="2"/>
1026
+
</enum>
1027
+
1028
+
<domain name="A2XX" width="32">
1029
+
1030
+
<bitset name="a2xx_vgt_current_bin_id_min_max" inline="yes">
1031
+
<bitfield name="COLUMN" low="0" high="2" type="uint"/>
1032
+
<bitfield name="ROW" low="3" high="5" type="uint"/>
1033
+
<bitfield name="GUARD_BAND_MASK" low="6" high="8" type="uint"/>
1034
+
</bitset>
1035
+
1036
+
<reg32 offset="0x0001" name="RBBM_PATCH_RELEASE"/>
1037
+
<reg32 offset="0x003b" name="RBBM_CNTL"/>
1038
+
<reg32 offset="0x003c" name="RBBM_SOFT_RESET"/>
1039
+
<reg32 offset="0x00c0" name="CP_PFP_UCODE_ADDR"/>
1040
+
<reg32 offset="0x00c1" name="CP_PFP_UCODE_DATA"/>
1041
+
1042
+
<enum name="adreno_mmu_clnt_beh">
1043
+
<value name="BEH_NEVR" value="0"/>
1044
+
<value name="BEH_TRAN_RNG" value="1"/>
1045
+
<value name="BEH_TRAN_FLT" value="2"/>
1046
+
</enum>
1047
+
1048
+
<!--
1049
+
Note: these seem applicable only for a2xx devices with gpummu? At
1050
+
any rate, MH_MMU_CONFIG shows up in places in a3xx firmware where
1051
+
it doesn't make sense, so I think offset 0x40 must be a different
1052
+
register on a3xx.. so moving this back into A2XX domain:
1053
+
-->
1054
+
<reg32 offset="0x0040" name="MH_MMU_CONFIG">
1055
+
<bitfield name="MMU_ENABLE" pos="0" type="boolean"/>
1056
+
<bitfield name="SPLIT_MODE_ENABLE" pos="1" type="boolean"/>
1057
+
<bitfield name="RB_W_CLNT_BEHAVIOR" low="4" high="5" type="adreno_mmu_clnt_beh"/>
1058
+
<bitfield name="CP_W_CLNT_BEHAVIOR" low="6" high="7" type="adreno_mmu_clnt_beh"/>
1059
+
<bitfield name="CP_R0_CLNT_BEHAVIOR" low="8" high="9" type="adreno_mmu_clnt_beh"/>
1060
+
<bitfield name="CP_R1_CLNT_BEHAVIOR" low="10" high="11" type="adreno_mmu_clnt_beh"/>
1061
+
<bitfield name="CP_R2_CLNT_BEHAVIOR" low="12" high="13" type="adreno_mmu_clnt_beh"/>
1062
+
<bitfield name="CP_R3_CLNT_BEHAVIOR" low="14" high="15" type="adreno_mmu_clnt_beh"/>
1063
+
<bitfield name="CP_R4_CLNT_BEHAVIOR" low="16" high="17" type="adreno_mmu_clnt_beh"/>
1064
+
<bitfield name="VGT_R0_CLNT_BEHAVIOR" low="18" high="19" type="adreno_mmu_clnt_beh"/>
1065
+
<bitfield name="VGT_R1_CLNT_BEHAVIOR" low="20" high="21" type="adreno_mmu_clnt_beh"/>
1066
+
<bitfield name="TC_R_CLNT_BEHAVIOR" low="22" high="23" type="adreno_mmu_clnt_beh"/>
1067
+
<bitfield name="PA_W_CLNT_BEHAVIOR" low="24" high="25" type="adreno_mmu_clnt_beh"/>
1068
+
</reg32>
1069
+
<reg32 offset="0x0041" name="MH_MMU_VA_RANGE">
1070
+
<bitfield name="NUM_64KB_REGIONS" low="0" high="11" type="uint"/>
1071
+
<bitfield name="VA_BASE" low="12" high="31" type="uint"/>
1072
+
</reg32>
1073
+
<reg32 offset="0x0042" name="MH_MMU_PT_BASE"/>
1074
+
<reg32 offset="0x0043" name="MH_MMU_PAGE_FAULT"/>
1075
+
<reg32 offset="0x0044" name="MH_MMU_TRAN_ERROR"/>
1076
+
<reg32 offset="0x0045" name="MH_MMU_INVALIDATE">
1077
+
<bitfield name="INVALIDATE_ALL" pos="0" type="boolean"/>
1078
+
<bitfield name="INVALIDATE_TC" pos="1" type="boolean"/>
1079
+
</reg32>
1080
+
<reg32 offset="0x0046" name="MH_MMU_MPU_BASE"/>
1081
+
<reg32 offset="0x0047" name="MH_MMU_MPU_END"/>
1082
+
1083
+
<reg32 offset="0x0394" name="NQWAIT_UNTIL"/>
1084
+
<reg32 offset="0x0395" name="RBBM_PERFCOUNTER0_SELECT"/>
1085
+
<reg32 offset="0x0396" name="RBBM_PERFCOUNTER1_SELECT"/>
1086
+
<reg32 offset="0x0397" name="RBBM_PERFCOUNTER0_LO"/>
1087
+
<reg32 offset="0x0398" name="RBBM_PERFCOUNTER0_HI"/>
1088
+
<reg32 offset="0x0399" name="RBBM_PERFCOUNTER1_LO"/>
1089
+
<reg32 offset="0x039a" name="RBBM_PERFCOUNTER1_HI"/>
1090
+
<reg32 offset="0x039b" name="RBBM_DEBUG"/>
1091
+
<reg32 offset="0x039c" name="RBBM_PM_OVERRIDE1">
1092
+
<bitfield name="RBBM_AHBCLK_PM_OVERRIDE" pos="0" type="boolean"/>
1093
+
<bitfield name="SC_REG_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
1094
+
<bitfield name="SC_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
1095
+
<bitfield name="SP_TOP_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
1096
+
<bitfield name="SP_V0_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
1097
+
<bitfield name="SQ_REG_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
1098
+
<bitfield name="SQ_REG_FIFOS_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
1099
+
<bitfield name="SQ_CONST_MEM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
1100
+
<bitfield name="SQ_SQ_SCLK_PM_OVERRIDE" pos="8" type="boolean"/>
1101
+
<bitfield name="SX_SCLK_PM_OVERRIDE" pos="9" type="boolean"/>
1102
+
<bitfield name="SX_REG_SCLK_PM_OVERRIDE" pos="10" type="boolean"/>
1103
+
<bitfield name="TCM_TCO_SCLK_PM_OVERRIDE" pos="11" type="boolean"/>
1104
+
<bitfield name="TCM_TCM_SCLK_PM_OVERRIDE" pos="12" type="boolean"/>
1105
+
<bitfield name="TCM_TCD_SCLK_PM_OVERRIDE" pos="13" type="boolean"/>
1106
+
<bitfield name="TCM_REG_SCLK_PM_OVERRIDE" pos="14" type="boolean"/>
1107
+
<bitfield name="TPC_TPC_SCLK_PM_OVERRIDE" pos="15" type="boolean"/>
1108
+
<bitfield name="TPC_REG_SCLK_PM_OVERRIDE" pos="16" type="boolean"/>
1109
+
<bitfield name="TCF_TCA_SCLK_PM_OVERRIDE" pos="17" type="boolean"/>
1110
+
<bitfield name="TCF_TCB_SCLK_PM_OVERRIDE" pos="18" type="boolean"/>
1111
+
<bitfield name="TCF_TCB_READ_SCLK_PM_OVERRIDE" pos="19" type="boolean"/>
1112
+
<bitfield name="TP_TP_SCLK_PM_OVERRIDE" pos="20" type="boolean"/>
1113
+
<bitfield name="TP_REG_SCLK_PM_OVERRIDE" pos="21" type="boolean"/>
1114
+
<bitfield name="CP_G_SCLK_PM_OVERRIDE" pos="22" type="boolean"/>
1115
+
<bitfield name="CP_REG_SCLK_PM_OVERRIDE" pos="23" type="boolean"/>
1116
+
<bitfield name="CP_G_REG_SCLK_PM_OVERRIDE" pos="24" type="boolean"/>
1117
+
<bitfield name="SPI_SCLK_PM_OVERRIDE" pos="25" type="boolean"/>
1118
+
<bitfield name="RB_REG_SCLK_PM_OVERRIDE" pos="26" type="boolean"/>
1119
+
<bitfield name="RB_SCLK_PM_OVERRIDE" pos="27" type="boolean"/>
1120
+
<bitfield name="MH_MH_SCLK_PM_OVERRIDE" pos="28" type="boolean"/>
1121
+
<bitfield name="MH_REG_SCLK_PM_OVERRIDE" pos="29" type="boolean"/>
1122
+
<bitfield name="MH_MMU_SCLK_PM_OVERRIDE" pos="30" type="boolean"/>
1123
+
<bitfield name="MH_TCROQ_SCLK_PM_OVERRIDE" pos="31" type="boolean"/>
1124
+
</reg32>
1125
+
<reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2">
1126
+
<bitfield name="PA_REG_SCLK_PM_OVERRIDE" pos="0" type="boolean"/>
1127
+
<bitfield name="PA_PA_SCLK_PM_OVERRIDE" pos="1" type="boolean"/>
1128
+
<bitfield name="PA_AG_SCLK_PM_OVERRIDE" pos="2" type="boolean"/>
1129
+
<bitfield name="VGT_REG_SCLK_PM_OVERRIDE" pos="3" type="boolean"/>
1130
+
<bitfield name="VGT_FIFOS_SCLK_PM_OVERRIDE" pos="4" type="boolean"/>
1131
+
<bitfield name="VGT_VGT_SCLK_PM_OVERRIDE" pos="5" type="boolean"/>
1132
+
<bitfield name="DEBUG_PERF_SCLK_PM_OVERRIDE" pos="6" type="boolean"/>
1133
+
<bitfield name="PERM_SCLK_PM_OVERRIDE" pos="7" type="boolean"/>
1134
+
<bitfield name="GC_GA_GMEM0_PM_OVERRIDE" pos="8" type="boolean"/>
1135
+
<bitfield name="GC_GA_GMEM1_PM_OVERRIDE" pos="9" type="boolean"/>
1136
+
<bitfield name="GC_GA_GMEM2_PM_OVERRIDE" pos="10" type="boolean"/>
1137
+
<bitfield name="GC_GA_GMEM3_PM_OVERRIDE" pos="11" type="boolean"/>
1138
+
</reg32>
1139
+
<reg32 offset="0x03a0" name="RBBM_DEBUG_OUT"/>
1140
+
<reg32 offset="0x03a1" name="RBBM_DEBUG_CNTL"/>
1141
+
<reg32 offset="0x03b3" name="RBBM_READ_ERROR"/>
1142
+
<reg32 offset="0x03b4" name="RBBM_INT_CNTL">
1143
+
<bitfield name="RDERR_INT_MASK" pos="0" type="boolean"/>
1144
+
<bitfield name="DISPLAY_UPDATE_INT_MASK" pos="1" type="boolean"/>
1145
+
<bitfield name="GUI_IDLE_INT_MASK" pos="19" type="boolean"/>
1146
+
</reg32>
1147
+
<reg32 offset="0x03b5" name="RBBM_INT_STATUS"/>
1148
+
<reg32 offset="0x03b6" name="RBBM_INT_ACK"/>
1149
+
<reg32 offset="0x03b7" name="MASTER_INT_SIGNAL">
1150
+
<bitfield name="MH_INT_STAT" pos="5" type="boolean"/>
1151
+
<bitfield name="SQ_INT_STAT" pos="26" type="boolean"/>
1152
+
<bitfield name="CP_INT_STAT" pos="30" type="boolean"/>
1153
+
<bitfield name="RBBM_INT_STAT" pos="31" type="boolean"/>
1154
+
</reg32>
1155
+
<reg32 offset="0x03f9" name="RBBM_PERIPHID1"/>
1156
+
<reg32 offset="0x03fa" name="RBBM_PERIPHID2"/>
1157
+
<reg32 offset="0x0444" name="CP_PERFMON_CNTL">
1158
+
<!-- The width is uncertain -->
1159
+
<bitfield name="PERF_MODE_CNT" low="0" high="2" type="perf_mode_cnt"/>
1160
+
</reg32>
1161
+
<reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT"/>
1162
+
<reg32 offset="0x0446" name="CP_PERFCOUNTER_LO"/>
1163
+
<reg32 offset="0x0447" name="CP_PERFCOUNTER_HI"/>
1164
+
<reg32 offset="0x05d0" name="RBBM_STATUS">
1165
+
<bitfield name="CMDFIFO_AVAIL" low="0" high="4" type="uint"/>
1166
+
<bitfield name="TC_BUSY" pos="5" type="boolean"/>
1167
+
<bitfield name="HIRQ_PENDING" pos="8" type="boolean"/>
1168
+
<bitfield name="CPRQ_PENDING" pos="9" type="boolean"/>
1169
+
<bitfield name="CFRQ_PENDING" pos="10" type="boolean"/>
1170
+
<bitfield name="PFRQ_PENDING" pos="11" type="boolean"/>
1171
+
<bitfield name="VGT_BUSY_NO_DMA" pos="12" type="boolean"/>
1172
+
<bitfield name="RBBM_WU_BUSY" pos="14" type="boolean"/>
1173
+
<bitfield name="CP_NRT_BUSY" pos="16" type="boolean"/>
1174
+
<bitfield name="MH_BUSY" pos="18" type="boolean"/>
1175
+
<bitfield name="MH_COHERENCY_BUSY" pos="19" type="boolean"/>
1176
+
<bitfield name="SX_BUSY" pos="21" type="boolean"/>
1177
+
<bitfield name="TPC_BUSY" pos="22" type="boolean"/>
1178
+
<bitfield name="SC_CNTX_BUSY" pos="24" type="boolean"/>
1179
+
<bitfield name="PA_BUSY" pos="25" type="boolean"/>
1180
+
<bitfield name="VGT_BUSY" pos="26" type="boolean"/>
1181
+
<bitfield name="SQ_CNTX17_BUSY" pos="27" type="boolean"/>
1182
+
<bitfield name="SQ_CNTX0_BUSY" pos="28" type="boolean"/>
1183
+
<bitfield name="RB_CNTX_BUSY" pos="30" type="boolean"/>
1184
+
<bitfield name="GUI_ACTIVE" pos="31" type="boolean"/>
1185
+
</reg32>
1186
+
<reg32 offset="0x0a40" name="MH_ARBITER_CONFIG">
1187
+
<bitfield name="SAME_PAGE_LIMIT" low="0" high="5" type="uint"/>
1188
+
<bitfield name="SAME_PAGE_GRANULARITY" pos="6" type="boolean"/>
1189
+
<bitfield name="L1_ARB_ENABLE" pos="7" type="boolean"/>
1190
+
<bitfield name="L1_ARB_HOLD_ENABLE" pos="8" type="boolean"/>
1191
+
<bitfield name="L2_ARB_CONTROL" pos="9" type="boolean"/>
1192
+
<bitfield name="PAGE_SIZE" low="10" high="12" type="uint"/>
1193
+
<bitfield name="TC_REORDER_ENABLE" pos="13" type="boolean"/>
1194
+
<bitfield name="TC_ARB_HOLD_ENABLE" pos="14" type="boolean"/>
1195
+
<bitfield name="IN_FLIGHT_LIMIT_ENABLE" pos="15" type="boolean"/>
1196
+
<bitfield name="IN_FLIGHT_LIMIT" low="16" high="21" type="uint"/>
1197
+
<bitfield name="CP_CLNT_ENABLE" pos="22" type="boolean"/>
1198
+
<bitfield name="VGT_CLNT_ENABLE" pos="23" type="boolean"/>
1199
+
<bitfield name="TC_CLNT_ENABLE" pos="24" type="boolean"/>
1200
+
<bitfield name="RB_CLNT_ENABLE" pos="25" type="boolean"/>
1201
+
<bitfield name="PA_CLNT_ENABLE" pos="26" type="boolean"/>
1202
+
</reg32>
1203
+
<reg32 offset="0x0a42" name="MH_INTERRUPT_MASK">
1204
+
<bitfield name="AXI_READ_ERROR" pos="0" type="boolean"/>
1205
+
<bitfield name="AXI_WRITE_ERROR" pos="1" type="boolean"/>
1206
+
<bitfield name="MMU_PAGE_FAULT" pos="2" type="boolean"/>
1207
+
</reg32>
1208
+
<reg32 offset="0x0a43" name="MH_INTERRUPT_STATUS"/>
1209
+
<reg32 offset="0x0a44" name="MH_INTERRUPT_CLEAR"/>
1210
+
<reg32 offset="0x0a54" name="MH_CLNT_INTF_CTRL_CONFIG1"/>
1211
+
<reg32 offset="0x0a55" name="MH_CLNT_INTF_CTRL_CONFIG2"/>
1212
+
<reg32 offset="0x0c01" name="A220_VSC_BIN_SIZE">
1213
+
<bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1214
+
<bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
1215
+
</reg32>
1216
+
<array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
1217
+
<reg32 offset="0x0" name="CONFIG"/>
1218
+
<reg32 offset="0x1" name="DATA_ADDRESS"/>
1219
+
<reg32 offset="0x2" name="DATA_LENGTH"/>
1220
+
</array>
1221
+
<reg32 offset="0x0c38" name="PC_DEBUG_CNTL"/>
1222
+
<reg32 offset="0x0c39" name="PC_DEBUG_DATA"/>
1223
+
<reg32 offset="0x0c44" name="PA_SC_VIZ_QUERY_STATUS"/>
1224
+
<reg32 offset="0x0c80" name="GRAS_DEBUG_CNTL"/>
1225
+
<reg32 offset="0x0c80" name="PA_SU_DEBUG_CNTL"/>
1226
+
<reg32 offset="0x0c81" name="GRAS_DEBUG_DATA"/>
1227
+
<reg32 offset="0x0c81" name="PA_SU_DEBUG_DATA"/>
1228
+
<reg32 offset="0x0c86" name="PA_SU_FACE_DATA">
1229
+
<bitfield name="BASE_ADDR" low="5" high="31" type="uint"/>
1230
+
</reg32>
1231
+
<reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT">
1232
+
<bitfield name="REG_DYNAMIC" pos="0" type="boolean"/>
1233
+
<bitfield name="REG_SIZE_PIX" low="4" high="11" type="uint"/>
1234
+
<bitfield name="REG_SIZE_VTX" low="12" high="19" type="uint"/>
1235
+
</reg32>
1236
+
<reg32 offset="0x0d01" name="SQ_FLOW_CONTROL"/>
1237
+
<reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT">
1238
+
<bitfield name="INST_BASE_PIX" low="0" high="11" type="uint"/>
1239
+
<bitfield name="INST_BASE_VTX" low="16" high="27" type="uint"/>
1240
+
</reg32>
1241
+
<reg32 offset="0x0d05" name="SQ_DEBUG_MISC"/>
1242
+
<reg32 offset="0x0d34" name="SQ_INT_CNTL"/>
1243
+
<reg32 offset="0x0d35" name="SQ_INT_STATUS"/>
1244
+
<reg32 offset="0x0d36" name="SQ_INT_ACK"/>
1245
+
<reg32 offset="0x0dae" name="SQ_DEBUG_INPUT_FSM"/>
1246
+
<reg32 offset="0x0daf" name="SQ_DEBUG_CONST_MGR_FSM"/>
1247
+
<reg32 offset="0x0db0" name="SQ_DEBUG_TP_FSM"/>
1248
+
<reg32 offset="0x0db1" name="SQ_DEBUG_FSM_ALU_0"/>
1249
+
<reg32 offset="0x0db2" name="SQ_DEBUG_FSM_ALU_1"/>
1250
+
<reg32 offset="0x0db3" name="SQ_DEBUG_EXP_ALLOC"/>
1251
+
<reg32 offset="0x0db4" name="SQ_DEBUG_PTR_BUFF"/>
1252
+
<reg32 offset="0x0db5" name="SQ_DEBUG_GPR_VTX"/>
1253
+
<reg32 offset="0x0db6" name="SQ_DEBUG_GPR_PIX"/>
1254
+
<reg32 offset="0x0db7" name="SQ_DEBUG_TB_STATUS_SEL"/>
1255
+
<reg32 offset="0x0db8" name="SQ_DEBUG_VTX_TB_0"/>
1256
+
<reg32 offset="0x0db9" name="SQ_DEBUG_VTX_TB_1"/>
1257
+
<reg32 offset="0x0dba" name="SQ_DEBUG_VTX_TB_STATUS_REG"/>
1258
+
<reg32 offset="0x0dbb" name="SQ_DEBUG_VTX_TB_STATE_MEM"/>
1259
+
<reg32 offset="0x0dbc" name="SQ_DEBUG_PIX_TB_0"/>
1260
+
<reg32 offset="0x0dbd" name="SQ_DEBUG_PIX_TB_STATUS_REG_0"/>
1261
+
<reg32 offset="0x0dbe" name="SQ_DEBUG_PIX_TB_STATUS_REG_1"/>
1262
+
<reg32 offset="0x0dbf" name="SQ_DEBUG_PIX_TB_STATUS_REG_2"/>
1263
+
<reg32 offset="0x0dc0" name="SQ_DEBUG_PIX_TB_STATUS_REG_3"/>
1264
+
<reg32 offset="0x0dc1" name="SQ_DEBUG_PIX_TB_STATE_MEM"/>
1265
+
<reg32 offset="0x0e00" name="TC_CNTL_STATUS">
1266
+
<bitfield name="L2_INVALIDATE" pos="0" type="boolean"/>
1267
+
</reg32>
1268
+
<reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
1269
+
<reg32 offset="0x0f01" name="RB_BC_CONTROL">
1270
+
<bitfield name="ACCUM_LINEAR_MODE_ENABLE" pos="0" type="boolean"/>
1271
+
<bitfield name="ACCUM_TIMEOUT_SELECT" low="1" high="2" type="uint"/>
1272
+
<bitfield name="DISABLE_EDRAM_CAM" pos="3" type="boolean"/>
1273
+
<bitfield name="DISABLE_EZ_FAST_CONTEXT_SWITCH" pos="4" type="boolean"/>
1274
+
<bitfield name="DISABLE_EZ_NULL_ZCMD_DROP" pos="5" type="boolean"/>
1275
+
<bitfield name="DISABLE_LZ_NULL_ZCMD_DROP" pos="6" type="boolean"/>
1276
+
<bitfield name="ENABLE_AZ_THROTTLE" pos="7" type="boolean"/>
1277
+
<bitfield name="AZ_THROTTLE_COUNT" low="8" high="12" type="uint"/>
1278
+
<bitfield name="ENABLE_CRC_UPDATE" pos="14" type="boolean"/>
1279
+
<bitfield name="CRC_MODE" pos="15" type="boolean"/>
1280
+
<bitfield name="DISABLE_SAMPLE_COUNTERS" pos="16" type="boolean"/>
1281
+
<bitfield name="DISABLE_ACCUM" pos="17" type="boolean"/>
1282
+
<bitfield name="ACCUM_ALLOC_MASK" low="18" high="21" type="uint"/>
1283
+
<bitfield name="LINEAR_PERFORMANCE_ENABLE" pos="22" type="boolean"/>
1284
+
<bitfield name="ACCUM_DATA_FIFO_LIMIT" low="23" high="26" type="uint"/>
1285
+
<bitfield name="MEM_EXPORT_TIMEOUT_SELECT" low="27" high="28" type="uint"/>
1286
+
<bitfield name="MEM_EXPORT_LINEAR_MODE_ENABLE" pos="29" type="boolean"/>
1287
+
<bitfield name="CRC_SYSTEM" pos="30" type="boolean"/>
1288
+
<bitfield name="RESERVED6" pos="31" type="boolean"/>
1289
+
</reg32>
1290
+
<reg32 offset="0x0f02" name="RB_EDRAM_INFO"/>
1291
+
<reg32 offset="0x0f26" name="RB_DEBUG_CNTL"/>
1292
+
<reg32 offset="0x0f27" name="RB_DEBUG_DATA"/>
1293
+
<reg32 offset="0x2000" name="RB_SURFACE_INFO">
1294
+
<bitfield name="SURFACE_PITCH" low="0" high="13" type="uint"/>
1295
+
<bitfield name="MSAA_SAMPLES" low="14" high="15" type="uint"/>
1296
+
</reg32>
1297
+
<reg32 offset="0x2001" name="RB_COLOR_INFO">
1298
+
<bitfield name="FORMAT" low="0" high="3" type="a2xx_colorformatx"/>
1299
+
<bitfield name="ROUND_MODE" low="4" high="5" type="uint"/>
1300
+
<bitfield name="LINEAR" pos="6" type="boolean"/>
1301
+
<bitfield name="ENDIAN" low="7" high="8" type="uint"/>
1302
+
<bitfield name="SWAP" low="9" high="10" type="uint"/>
1303
+
<bitfield name="BASE" low="12" high="31" shr="12"/>
1304
+
</reg32>
1305
+
<reg32 offset="0x2002" name="RB_DEPTH_INFO">
1306
+
<bitfield name="DEPTH_FORMAT" pos="0" type="adreno_rb_depth_format"/>
1307
+
<bitfield name="DEPTH_BASE" low="12" high="31" type="uint" shr="12"/>
1308
+
</reg32>
1309
+
<reg32 offset="0x2005" name="A225_RB_COLOR_INFO3"/>
1310
+
<reg32 offset="0x2006" name="COHER_DEST_BASE_0"/>
1311
+
<reg32 offset="0x200e" name="PA_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
1312
+
<reg32 offset="0x200f" name="PA_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
1313
+
<reg32 offset="0x2080" name="PA_SC_WINDOW_OFFSET">
1314
+
<bitfield name="X" low="0" high="14" type="int"/>
1315
+
<bitfield name="Y" low="16" high="30" type="int"/>
1316
+
<bitfield name="DISABLE" pos="31" type="boolean"/>
1317
+
</reg32>
1318
+
<reg32 offset="0x2081" name="PA_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1319
+
<reg32 offset="0x2082" name="PA_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1320
+
<reg32 offset="0x2010" name="UNKNOWN_2010"/>
1321
+
<reg32 offset="0x2100" name="VGT_MAX_VTX_INDX"/>
1322
+
<reg32 offset="0x2101" name="VGT_MIN_VTX_INDX"/>
1323
+
<reg32 offset="0x2102" name="VGT_INDX_OFFSET"/>
1324
+
<reg32 offset="0x2103" name="A225_PC_MULTI_PRIM_IB_RESET_INDX"/>
1325
+
<reg32 offset="0x2104" name="RB_COLOR_MASK">
1326
+
<bitfield name="WRITE_RED" pos="0" type="boolean"/>
1327
+
<bitfield name="WRITE_GREEN" pos="1" type="boolean"/>
1328
+
<bitfield name="WRITE_BLUE" pos="2" type="boolean"/>
1329
+
<bitfield name="WRITE_ALPHA" pos="3" type="boolean"/>
1330
+
</reg32>
1331
+
<reg32 offset="0x2105" name="RB_BLEND_RED"/>
1332
+
<reg32 offset="0x2106" name="RB_BLEND_GREEN"/>
1333
+
<reg32 offset="0x2107" name="RB_BLEND_BLUE"/>
1334
+
<reg32 offset="0x2108" name="RB_BLEND_ALPHA"/>
1335
+
<reg32 offset="0x2109" name="RB_FOG_COLOR">
1336
+
<bitfield name="FOG_RED" low="0" high="7" type="uint"/>
1337
+
<bitfield name="FOG_GREEN" low="8" high="15" type="uint"/>
1338
+
<bitfield name="FOG_BLUE" low="16" high="23" type="uint"/>
1339
+
</reg32>
1340
+
<reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1341
+
<reg32 offset="0x210d" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1342
+
<reg32 offset="0x210e" name="RB_ALPHA_REF"/>
1343
+
<reg32 offset="0x210f" name="PA_CL_VPORT_XSCALE" type="float"/>
1344
+
<reg32 offset="0x2110" name="PA_CL_VPORT_XOFFSET" type="float"/>
1345
+
<reg32 offset="0x2111" name="PA_CL_VPORT_YSCALE" type="float"/>
1346
+
<reg32 offset="0x2112" name="PA_CL_VPORT_YOFFSET" type="float"/>
1347
+
<reg32 offset="0x2113" name="PA_CL_VPORT_ZSCALE" type="float"/>
1348
+
<reg32 offset="0x2114" name="PA_CL_VPORT_ZOFFSET" type="float"/>
1349
+
<reg32 offset="0x2180" name="SQ_PROGRAM_CNTL">
1350
+
<doc>
1351
+
note: only 0x3f worth of valid register values for VS_REGS and
1352
+
PS_REGS, but high bit is set to indicate '0 registers used':
1353
+
</doc>
1354
+
<bitfield name="VS_REGS" low="0" high="7" type="uint"/>
1355
+
<bitfield name="PS_REGS" low="8" high="15" type="uint"/>
1356
+
<bitfield name="VS_RESOURCE" pos="16" type="boolean"/>
1357
+
<bitfield name="PS_RESOURCE" pos="17" type="boolean"/>
1358
+
<bitfield name="PARAM_GEN" pos="18" type="boolean"/>
1359
+
<bitfield name="GEN_INDEX_PIX" pos="19" type="boolean"/>
1360
+
<bitfield name="VS_EXPORT_COUNT" low="20" high="23" type="uint"/>
1361
+
<bitfield name="VS_EXPORT_MODE" low="24" high="26" type="a2xx_sq_ps_vtx_mode"/>
1362
+
<bitfield name="PS_EXPORT_MODE" low="27" high="30" type="uint"/>
1363
+
<bitfield name="GEN_INDEX_VTX" pos="31" type="boolean"/>
1364
+
</reg32>
1365
+
<reg32 offset="0x2181" name="SQ_CONTEXT_MISC">
1366
+
<bitfield name="INST_PRED_OPTIMIZE" pos="0" type="boolean"/>
1367
+
<bitfield name="SC_OUTPUT_SCREEN_XY" pos="1" type="boolean"/>
1368
+
<bitfield name="SC_SAMPLE_CNTL" low="2" high="3" type="a2xx_sq_sample_cntl"/>
1369
+
<bitfield name="PARAM_GEN_POS" low="8" high="15" type="uint"/>
1370
+
<bitfield name="PERFCOUNTER_REF" pos="16" type="boolean"/>
1371
+
<bitfield name="YEILD_OPTIMIZE" pos="17" type="boolean"/>
1372
+
<bitfield name="TX_CACHE_SEL" pos="18" type="boolean"/>
1373
+
</reg32>
1374
+
<reg32 offset="0x2182" name="SQ_INTERPOLATOR_CNTL">
1375
+
<bitfield name="PARAM_SHADE" low="0" high="15" type="uint"/>
1376
+
<bitfield name="SAMPLING_PATTERN" low="16" high="31" type="uint"/>
1377
+
</reg32>
1378
+
<reg32 offset="0x2183" name="SQ_WRAPPING_0">
1379
+
<bitfield name="PARAM_WRAP_0" low="0" high="3" type="uint"/>
1380
+
<bitfield name="PARAM_WRAP_1" low="4" high="7" type="uint"/>
1381
+
<bitfield name="PARAM_WRAP_2" low="8" high="11" type="uint"/>
1382
+
<bitfield name="PARAM_WRAP_3" low="12" high="15" type="uint"/>
1383
+
<bitfield name="PARAM_WRAP_4" low="16" high="19" type="uint"/>
1384
+
<bitfield name="PARAM_WRAP_5" low="20" high="23" type="uint"/>
1385
+
<bitfield name="PARAM_WRAP_6" low="24" high="27" type="uint"/>
1386
+
<bitfield name="PARAM_WRAP_7" low="28" high="31" type="uint"/>
1387
+
</reg32>
1388
+
<reg32 offset="0x2184" name="SQ_WRAPPING_1">
1389
+
<bitfield name="PARAM_WRAP_8" low="0" high="3" type="uint"/>
1390
+
<bitfield name="PARAM_WRAP_9" low="4" high="7" type="uint"/>
1391
+
<bitfield name="PARAM_WRAP_10" low="8" high="11" type="uint"/>
1392
+
<bitfield name="PARAM_WRAP_11" low="12" high="15" type="uint"/>
1393
+
<bitfield name="PARAM_WRAP_12" low="16" high="19" type="uint"/>
1394
+
<bitfield name="PARAM_WRAP_13" low="20" high="23" type="uint"/>
1395
+
<bitfield name="PARAM_WRAP_14" low="24" high="27" type="uint"/>
1396
+
<bitfield name="PARAM_WRAP_15" low="28" high="31" type="uint"/>
1397
+
</reg32>
1398
+
<reg32 offset="0x21f6" name="SQ_PS_PROGRAM">
1399
+
<bitfield name="BASE" low="0" high="11" type="uint"/>
1400
+
<bitfield name="SIZE" low="12" high="23" type="uint"/>
1401
+
</reg32>
1402
+
<reg32 offset="0x21f7" name="SQ_VS_PROGRAM">
1403
+
<bitfield name="BASE" low="0" high="11" type="uint"/>
1404
+
<bitfield name="SIZE" low="12" high="23" type="uint"/>
1405
+
</reg32>
1406
+
<reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
1407
+
<reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
1408
+
<reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
1409
+
<reg32 offset="0x2200" name="RB_DEPTHCONTROL">
1410
+
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1411
+
<bitfield name="Z_ENABLE" pos="1" type="boolean"/>
1412
+
<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
1413
+
<bitfield name="EARLY_Z_ENABLE" pos="3" type="boolean"/>
1414
+
<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
1415
+
<bitfield name="BACKFACE_ENABLE" pos="7" type="boolean"/>
1416
+
<bitfield name="STENCILFUNC" low="8" high="10" type="adreno_compare_func"/>
1417
+
<bitfield name="STENCILFAIL" low="11" high="13" type="adreno_stencil_op"/>
1418
+
<bitfield name="STENCILZPASS" low="14" high="16" type="adreno_stencil_op"/>
1419
+
<bitfield name="STENCILZFAIL" low="17" high="19" type="adreno_stencil_op"/>
1420
+
<bitfield name="STENCILFUNC_BF" low="20" high="22" type="adreno_compare_func"/>
1421
+
<bitfield name="STENCILFAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
1422
+
<bitfield name="STENCILZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
1423
+
<bitfield name="STENCILZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
1424
+
</reg32>
1425
+
<reg32 offset="0x2201" name="RB_BLEND_CONTROL">
1426
+
<bitfield name="COLOR_SRCBLEND" low="0" high="4" type="adreno_rb_blend_factor"/>
1427
+
<bitfield name="COLOR_COMB_FCN" low="5" high="7" type="a2xx_rb_blend_opcode"/>
1428
+
<bitfield name="COLOR_DESTBLEND" low="8" high="12" type="adreno_rb_blend_factor"/>
1429
+
<bitfield name="ALPHA_SRCBLEND" low="16" high="20" type="adreno_rb_blend_factor"/>
1430
+
<bitfield name="ALPHA_COMB_FCN" low="21" high="23" type="a2xx_rb_blend_opcode"/>
1431
+
<bitfield name="ALPHA_DESTBLEND" low="24" high="28" type="adreno_rb_blend_factor"/>
1432
+
<bitfield name="BLEND_FORCE_ENABLE" pos="29" type="boolean"/>
1433
+
<bitfield name="BLEND_FORCE" pos="30" type="boolean"/>
1434
+
</reg32>
1435
+
<reg32 offset="0x2202" name="RB_COLORCONTROL">
1436
+
<bitfield name="ALPHA_FUNC" low="0" high="2" type="adreno_compare_func"/>
1437
+
<bitfield name="ALPHA_TEST_ENABLE" pos="3" type="boolean"/>
1438
+
<bitfield name="ALPHA_TO_MASK_ENABLE" pos="4" type="boolean"/>
1439
+
<bitfield name="BLEND_DISABLE" pos="5" type="boolean"/>
1440
+
<bitfield name="VOB_ENABLE" pos="6" type="boolean"/>
1441
+
<bitfield name="VS_EXPORTS_FOG" pos="7" type="boolean"/>
1442
+
<bitfield name="ROP_CODE" low="8" high="11" type="uint"/>
1443
+
<bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
1444
+
<bitfield name="DITHER_TYPE" low="14" high="15" type="a2xx_rb_dither_type"/>
1445
+
<bitfield name="PIXEL_FOG" pos="16" type="boolean"/>
1446
+
<bitfield name="ALPHA_TO_MASK_OFFSET0" low="24" high="25" type="uint"/>
1447
+
<bitfield name="ALPHA_TO_MASK_OFFSET1" low="26" high="27" type="uint"/>
1448
+
<bitfield name="ALPHA_TO_MASK_OFFSET2" low="28" high="29" type="uint"/>
1449
+
<bitfield name="ALPHA_TO_MASK_OFFSET3" low="30" high="31" type="uint"/>
1450
+
</reg32>
1451
+
<reg32 offset="0x2203" name="VGT_CURRENT_BIN_ID_MAX" type="a2xx_vgt_current_bin_id_min_max"/>
1452
+
<reg32 offset="0x2204" name="PA_CL_CLIP_CNTL">
1453
+
<bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
1454
+
<bitfield name="BOUNDARY_EDGE_FLAG_ENA" pos="18" type="boolean"/>
1455
+
<bitfield name="DX_CLIP_SPACE_DEF" pos="19" type="a2xx_dx_clip_space"/>
1456
+
<bitfield name="DIS_CLIP_ERR_DETECT" pos="20" type="boolean"/>
1457
+
<bitfield name="VTX_KILL_OR" pos="21" type="boolean"/>
1458
+
<bitfield name="XY_NAN_RETAIN" pos="22" type="boolean"/>
1459
+
<bitfield name="Z_NAN_RETAIN" pos="23" type="boolean"/>
1460
+
<bitfield name="W_NAN_RETAIN" pos="24" type="boolean"/>
1461
+
</reg32>
1462
+
<reg32 offset="0x2205" name="PA_SU_SC_MODE_CNTL">
1463
+
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1464
+
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
1465
+
<bitfield name="FACE" pos="2" type="boolean"/>
1466
+
<bitfield name="POLYMODE" low="3" high="4" type="a2xx_pa_su_sc_polymode"/>
1467
+
<bitfield name="FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
1468
+
<bitfield name="BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
1469
+
<bitfield name="POLY_OFFSET_FRONT_ENABLE" pos="11" type="boolean"/>
1470
+
<bitfield name="POLY_OFFSET_BACK_ENABLE" pos="12" type="boolean"/>
1471
+
<bitfield name="POLY_OFFSET_PARA_ENABLE" pos="13" type="boolean"/>
1472
+
<bitfield name="MSAA_ENABLE" pos="15" type="boolean"/>
1473
+
<bitfield name="VTX_WINDOW_OFFSET_ENABLE" pos="16" type="boolean"/>
1474
+
<bitfield name="LINE_STIPPLE_ENABLE" pos="18" type="boolean"/>
1475
+
<bitfield name="PROVOKING_VTX_LAST" pos="19" type="boolean"/>
1476
+
<bitfield name="PERSP_CORR_DIS" pos="20" type="boolean"/>
1477
+
<bitfield name="MULTI_PRIM_IB_ENA" pos="21" type="boolean"/>
1478
+
<bitfield name="QUAD_ORDER_ENABLE" pos="23" type="boolean"/>
1479
+
<bitfield name="WAIT_RB_IDLE_ALL_TRI" pos="25" type="boolean"/>
1480
+
<bitfield name="WAIT_RB_IDLE_FIRST_TRI_NEW_STATE" pos="26" type="boolean"/>
1481
+
<bitfield name="CLAMPED_FACENESS" pos="28" type="boolean"/>
1482
+
<bitfield name="ZERO_AREA_FACENESS" pos="29" type="boolean"/>
1483
+
<bitfield name="FACE_KILL_ENABLE" pos="30" type="boolean"/>
1484
+
<bitfield name="FACE_WRITE_ENABLE" pos="31" type="boolean"/>
1485
+
</reg32>
1486
+
<reg32 offset="0x2206" name="PA_CL_VTE_CNTL">
1487
+
<bitfield name="VPORT_X_SCALE_ENA" pos="0" type="boolean"/>
1488
+
<bitfield name="VPORT_X_OFFSET_ENA" pos="1" type="boolean"/>
1489
+
<bitfield name="VPORT_Y_SCALE_ENA" pos="2" type="boolean"/>
1490
+
<bitfield name="VPORT_Y_OFFSET_ENA" pos="3" type="boolean"/>
1491
+
<bitfield name="VPORT_Z_SCALE_ENA" pos="4" type="boolean"/>
1492
+
<bitfield name="VPORT_Z_OFFSET_ENA" pos="5" type="boolean"/>
1493
+
<bitfield name="VTX_XY_FMT" pos="8" type="boolean"/>
1494
+
<bitfield name="VTX_Z_FMT" pos="9" type="boolean"/>
1495
+
<bitfield name="VTX_W0_FMT" pos="10" type="boolean"/>
1496
+
<bitfield name="PERFCOUNTER_REF" pos="11" type="boolean"/>
1497
+
</reg32>
1498
+
<reg32 offset="0x2207" name="VGT_CURRENT_BIN_ID_MIN" type="a2xx_vgt_current_bin_id_min_max"/>
1499
+
<reg32 offset="0x2208" name="RB_MODECONTROL">
1500
+
<bitfield name="EDRAM_MODE" low="0" high="2" type="a2xx_rb_edram_mode"/>
1501
+
</reg32>
1502
+
<reg32 offset="0x2209" name="A220_RB_LRZ_VSC_CONTROL"/>
1503
+
<reg32 offset="0x220a" name="RB_SAMPLE_POS"/>
1504
+
<reg32 offset="0x220b" name="CLEAR_COLOR">
1505
+
<bitfield name="RED" low="0" high="7"/>
1506
+
<bitfield name="GREEN" low="8" high="15"/>
1507
+
<bitfield name="BLUE" low="16" high="23"/>
1508
+
<bitfield name="ALPHA" low="24" high="31"/>
1509
+
</reg32>
1510
+
<reg32 offset="0x2210" name="A220_GRAS_CONTROL"/>
1511
+
<reg32 offset="0x2280" name="PA_SU_POINT_SIZE">
1512
+
<bitfield name="HEIGHT" low="0" high="15" type="ufixed" radix="4"/>
1513
+
<bitfield name="WIDTH" low="16" high="31" type="ufixed" radix="4"/>
1514
+
</reg32>
1515
+
<reg32 offset="0x2281" name="PA_SU_POINT_MINMAX">
1516
+
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1517
+
<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1518
+
</reg32>
1519
+
<reg32 offset="0x2282" name="PA_SU_LINE_CNTL">
1520
+
<bitfield name="WIDTH" low="0" high="15" type="ufixed" radix="4"/>
1521
+
</reg32>
1522
+
<reg32 offset="0x2283" name="PA_SC_LINE_STIPPLE">
1523
+
<bitfield name="LINE_PATTERN" low="0" high="15" type="hex"/>
1524
+
<bitfield name="REPEAT_COUNT" low="16" high="23" type="uint"/>
1525
+
<bitfield name="PATTERN_BIT_ORDER" pos="28" type="a2xx_pa_sc_pattern_bit_order"/>
1526
+
<bitfield name="AUTO_RESET_CNTL" low="29" high="30" type="a2xx_pa_sc_auto_reset_cntl"/>
1527
+
</reg32>
1528
+
<reg32 offset="0x2293" name="PA_SC_VIZ_QUERY">
1529
+
<bitfield name="VIZ_QUERY_ENA" pos="0" type="boolean"/>
1530
+
<bitfield name="VIZ_QUERY_ID" low="1" high="6" type="uint"/>
1531
+
<bitfield name="KILL_PIX_POST_EARLY_Z" pos="8" type="boolean"/>
1532
+
</reg32>
1533
+
<reg32 offset="0x2294" name="VGT_ENHANCE"/>
1534
+
<reg32 offset="0x2300" name="PA_SC_LINE_CNTL">
1535
+
<bitfield name="BRES_CNTL" low="0" high="15" type="uint"/>
1536
+
<bitfield name="USE_BRES_CNTL" pos="8" type="boolean"/>
1537
+
<bitfield name="EXPAND_LINE_WIDTH" pos="9" type="boolean"/>
1538
+
<bitfield name="LAST_PIXEL" pos="10" type="boolean"/>
1539
+
</reg32>
1540
+
<reg32 offset="0x2301" name="PA_SC_AA_CONFIG">
1541
+
<bitfield name="MSAA_NUM_SAMPLES" low="0" high="2" type="uint"/>
1542
+
<bitfield name="MAX_SAMPLE_DIST" low="13" high="16" type="uint"/>
1543
+
</reg32>
1544
+
<reg32 offset="0x2302" name="PA_SU_VTX_CNTL">
1545
+
<bitfield name="PIX_CENTER" pos="0" type="a2xx_pa_pixcenter"/>
1546
+
<bitfield name="ROUND_MODE" low="1" high="2" type="a2xx_pa_roundmode"/>
1547
+
<bitfield name="QUANT_MODE" low="7" high="9" type="a2xx_pa_quantmode"/>
1548
+
</reg32>
1549
+
<reg32 offset="0x2303" name="PA_CL_GB_VERT_CLIP_ADJ" type="float"/>
1550
+
<reg32 offset="0x2304" name="PA_CL_GB_VERT_DISC_ADJ" type="float"/>
1551
+
<reg32 offset="0x2305" name="PA_CL_GB_HORZ_CLIP_ADJ" type="float"/>
1552
+
<reg32 offset="0x2306" name="PA_CL_GB_HORZ_DISC_ADJ" type="float"/>
1553
+
<reg32 offset="0x2307" name="SQ_VS_CONST">
1554
+
<bitfield name="BASE" low="0" high="8" type="uint"/>
1555
+
<bitfield name="SIZE" low="12" high="20" type="uint"/>
1556
+
</reg32>
1557
+
<reg32 offset="0x2308" name="SQ_PS_CONST">
1558
+
<bitfield name="BASE" low="0" high="8" type="uint"/>
1559
+
<bitfield name="SIZE" low="12" high="20" type="uint"/>
1560
+
</reg32>
1561
+
<reg32 offset="0x2309" name="SQ_DEBUG_MISC_0"/>
1562
+
<reg32 offset="0x230a" name="SQ_DEBUG_MISC_1"/>
1563
+
<reg32 offset="0x2312" name="PA_SC_AA_MASK"/>
1564
+
<reg32 offset="0x2316" name="VGT_VERTEX_REUSE_BLOCK_CNTL">
1565
+
<bitfield name="VTX_REUSE_DEPTH" low="0" high="2" type="uint"/>
1566
+
</reg32>
1567
+
<reg32 offset="0x2317" name="VGT_OUT_DEALLOC_CNTL">
1568
+
<bitfield name="DEALLOC_DIST" low="0" high="1" type="uint"/>
1569
+
</reg32>
1570
+
<reg32 offset="0x2318" name="RB_COPY_CONTROL">
1571
+
<bitfield name="COPY_SAMPLE_SELECT" low="0" high="2" type="a2xx_rb_copy_sample_select"/>
1572
+
<bitfield name="DEPTH_CLEAR_ENABLE" pos="3" type="boolean"/>
1573
+
<bitfield name="CLEAR_MASK" low="4" high="7" type="hex"/>
1574
+
</reg32>
1575
+
<reg32 offset="0x2319" name="RB_COPY_DEST_BASE"/>
1576
+
<reg32 offset="0x231a" name="RB_COPY_DEST_PITCH" shr="5" type="uint"/>
1577
+
<reg32 offset="0x231b" name="RB_COPY_DEST_INFO">
1578
+
<bitfield name="DEST_ENDIAN" low="0" high="2" type="adreno_rb_surface_endian"/>
1579
+
<bitfield name="LINEAR" pos="3" type="boolean"/>
1580
+
<bitfield name="FORMAT" low="4" high="7" type="a2xx_colorformatx"/>
1581
+
<bitfield name="SWAP" low="8" high="9" type="uint"/>
1582
+
<bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
1583
+
<bitfield name="DITHER_TYPE" low="12" high="13" type="a2xx_rb_dither_type"/>
1584
+
<bitfield name="WRITE_RED" pos="14" type="boolean"/>
1585
+
<bitfield name="WRITE_GREEN" pos="15" type="boolean"/>
1586
+
<bitfield name="WRITE_BLUE" pos="16" type="boolean"/>
1587
+
<bitfield name="WRITE_ALPHA" pos="17" type="boolean"/>
1588
+
</reg32>
1589
+
<reg32 offset="0x231c" name="RB_COPY_DEST_OFFSET">
1590
+
<bitfield name="X" low="0" high="12" type="uint"/>
1591
+
<bitfield name="Y" low="13" high="25" type="uint"/>
1592
+
</reg32>
1593
+
<reg32 offset="0x231d" name="RB_DEPTH_CLEAR"/>
1594
+
<reg32 offset="0x2324" name="RB_SAMPLE_COUNT_CTL"/>
1595
+
<reg32 offset="0x2326" name="RB_COLOR_DEST_MASK"/>
1596
+
<reg32 offset="0x2340" name="A225_GRAS_UCP0X"/>
1597
+
<reg32 offset="0x2357" name="A225_GRAS_UCP5W"/>
1598
+
<reg32 offset="0x2360" name="A225_GRAS_UCP_ENABLED"/>
1599
+
<reg32 offset="0x2380" name="PA_SU_POLY_OFFSET_FRONT_SCALE"/>
1600
+
<reg32 offset="0x2381" name="PA_SU_POLY_OFFSET_FRONT_OFFSET"/>
1601
+
<reg32 offset="0x2382" name="PA_SU_POLY_OFFSET_BACK_SCALE"/>
1602
+
<reg32 offset="0x2383" name="PA_SU_POLY_OFFSET_BACK_OFFSET"/>
1603
+
<reg32 offset="0x4000" name="SQ_CONSTANT_0"/>
1604
+
<reg32 offset="0x4800" name="SQ_FETCH_0"/>
1605
+
<reg32 offset="0x4900" name="SQ_CF_BOOLEANS"/>
1606
+
<reg32 offset="0x4908" name="SQ_CF_LOOP"/>
1607
+
<reg32 offset="0xa29" name="COHER_SIZE_PM4"/>
1608
+
<reg32 offset="0xa2a" name="COHER_BASE_PM4"/>
1609
+
<reg32 offset="0xa2b" name="COHER_STATUS_PM4"/>
1610
+
1611
+
<reg32 offset="0x0c88" name="PA_SU_PERFCOUNTER0_SELECT"/>
1612
+
<reg32 offset="0x0c89" name="PA_SU_PERFCOUNTER1_SELECT"/>
1613
+
<reg32 offset="0x0c8a" name="PA_SU_PERFCOUNTER2_SELECT"/>
1614
+
<reg32 offset="0x0c8b" name="PA_SU_PERFCOUNTER3_SELECT"/>
1615
+
<reg32 offset="0x0c8c" name="PA_SU_PERFCOUNTER0_LOW"/>
1616
+
<reg32 offset="0x0c8d" name="PA_SU_PERFCOUNTER0_HI"/>
1617
+
<reg32 offset="0x0c8e" name="PA_SU_PERFCOUNTER1_LOW"/>
1618
+
<reg32 offset="0x0c8f" name="PA_SU_PERFCOUNTER1_HI"/>
1619
+
<reg32 offset="0x0c90" name="PA_SU_PERFCOUNTER2_LOW"/>
1620
+
<reg32 offset="0x0c91" name="PA_SU_PERFCOUNTER2_HI"/>
1621
+
<reg32 offset="0x0c92" name="PA_SU_PERFCOUNTER3_LOW"/>
1622
+
<reg32 offset="0x0c93" name="PA_SU_PERFCOUNTER3_HI"/>
1623
+
<reg32 offset="0x0c98" name="PA_SC_PERFCOUNTER0_SELECT"/>
1624
+
<reg32 offset="0x0c99" name="PA_SC_PERFCOUNTER0_LOW"/>
1625
+
<reg32 offset="0x0c9a" name="PA_SC_PERFCOUNTER0_HI"/>
1626
+
<reg32 offset="0x0c48" name="VGT_PERFCOUNTER0_SELECT"/>
1627
+
<reg32 offset="0x0c49" name="VGT_PERFCOUNTER1_SELECT"/>
1628
+
<reg32 offset="0x0c4a" name="VGT_PERFCOUNTER2_SELECT"/>
1629
+
<reg32 offset="0x0c4b" name="VGT_PERFCOUNTER3_SELECT"/>
1630
+
<reg32 offset="0x0c4c" name="VGT_PERFCOUNTER0_LOW"/>
1631
+
<reg32 offset="0x0c4e" name="VGT_PERFCOUNTER1_LOW"/>
1632
+
<reg32 offset="0x0c50" name="VGT_PERFCOUNTER2_LOW"/>
1633
+
<reg32 offset="0x0c52" name="VGT_PERFCOUNTER3_LOW"/>
1634
+
<reg32 offset="0x0c4d" name="VGT_PERFCOUNTER0_HI"/>
1635
+
<reg32 offset="0x0c4f" name="VGT_PERFCOUNTER1_HI"/>
1636
+
<reg32 offset="0x0c51" name="VGT_PERFCOUNTER2_HI"/>
1637
+
<reg32 offset="0x0c53" name="VGT_PERFCOUNTER3_HI"/>
1638
+
<reg32 offset="0x0e05" name="TCR_PERFCOUNTER0_SELECT"/>
1639
+
<reg32 offset="0x0e08" name="TCR_PERFCOUNTER1_SELECT"/>
1640
+
<reg32 offset="0x0e06" name="TCR_PERFCOUNTER0_HI"/>
1641
+
<reg32 offset="0x0e09" name="TCR_PERFCOUNTER1_HI"/>
1642
+
<reg32 offset="0x0e07" name="TCR_PERFCOUNTER0_LOW"/>
1643
+
<reg32 offset="0x0e0a" name="TCR_PERFCOUNTER1_LOW"/>
1644
+
<reg32 offset="0x0e1f" name="TP0_PERFCOUNTER0_SELECT"/>
1645
+
<reg32 offset="0x0e20" name="TP0_PERFCOUNTER0_HI"/>
1646
+
<reg32 offset="0x0e21" name="TP0_PERFCOUNTER0_LOW"/>
1647
+
<reg32 offset="0x0e22" name="TP0_PERFCOUNTER1_SELECT"/>
1648
+
<reg32 offset="0x0e23" name="TP0_PERFCOUNTER1_HI"/>
1649
+
<reg32 offset="0x0e24" name="TP0_PERFCOUNTER1_LOW"/>
1650
+
<reg32 offset="0x0e54" name="TCM_PERFCOUNTER0_SELECT"/>
1651
+
<reg32 offset="0x0e57" name="TCM_PERFCOUNTER1_SELECT"/>
1652
+
<reg32 offset="0x0e55" name="TCM_PERFCOUNTER0_HI"/>
1653
+
<reg32 offset="0x0e58" name="TCM_PERFCOUNTER1_HI"/>
1654
+
<reg32 offset="0x0e56" name="TCM_PERFCOUNTER0_LOW"/>
1655
+
<reg32 offset="0x0e59" name="TCM_PERFCOUNTER1_LOW"/>
1656
+
<reg32 offset="0x0e5a" name="TCF_PERFCOUNTER0_SELECT"/>
1657
+
<reg32 offset="0x0e5d" name="TCF_PERFCOUNTER1_SELECT"/>
1658
+
<reg32 offset="0x0e60" name="TCF_PERFCOUNTER2_SELECT"/>
1659
+
<reg32 offset="0x0e63" name="TCF_PERFCOUNTER3_SELECT"/>
1660
+
<reg32 offset="0x0e66" name="TCF_PERFCOUNTER4_SELECT"/>
1661
+
<reg32 offset="0x0e69" name="TCF_PERFCOUNTER5_SELECT"/>
1662
+
<reg32 offset="0x0e6c" name="TCF_PERFCOUNTER6_SELECT"/>
1663
+
<reg32 offset="0x0e6f" name="TCF_PERFCOUNTER7_SELECT"/>
1664
+
<reg32 offset="0x0e72" name="TCF_PERFCOUNTER8_SELECT"/>
1665
+
<reg32 offset="0x0e75" name="TCF_PERFCOUNTER9_SELECT"/>
1666
+
<reg32 offset="0x0e78" name="TCF_PERFCOUNTER10_SELECT"/>
1667
+
<reg32 offset="0x0e7b" name="TCF_PERFCOUNTER11_SELECT"/>
1668
+
<reg32 offset="0x0e5b" name="TCF_PERFCOUNTER0_HI"/>
1669
+
<reg32 offset="0x0e5e" name="TCF_PERFCOUNTER1_HI"/>
1670
+
<reg32 offset="0x0e61" name="TCF_PERFCOUNTER2_HI"/>
1671
+
<reg32 offset="0x0e64" name="TCF_PERFCOUNTER3_HI"/>
1672
+
<reg32 offset="0x0e67" name="TCF_PERFCOUNTER4_HI"/>
1673
+
<reg32 offset="0x0e6a" name="TCF_PERFCOUNTER5_HI"/>
1674
+
<reg32 offset="0x0e6d" name="TCF_PERFCOUNTER6_HI"/>
1675
+
<reg32 offset="0x0e70" name="TCF_PERFCOUNTER7_HI"/>
1676
+
<reg32 offset="0x0e73" name="TCF_PERFCOUNTER8_HI"/>
1677
+
<reg32 offset="0x0e76" name="TCF_PERFCOUNTER9_HI"/>
1678
+
<reg32 offset="0x0e79" name="TCF_PERFCOUNTER10_HI"/>
1679
+
<reg32 offset="0x0e7c" name="TCF_PERFCOUNTER11_HI"/>
1680
+
<reg32 offset="0x0e5c" name="TCF_PERFCOUNTER0_LOW"/>
1681
+
<reg32 offset="0x0e5f" name="TCF_PERFCOUNTER1_LOW"/>
1682
+
<reg32 offset="0x0e62" name="TCF_PERFCOUNTER2_LOW"/>
1683
+
<reg32 offset="0x0e65" name="TCF_PERFCOUNTER3_LOW"/>
1684
+
<reg32 offset="0x0e68" name="TCF_PERFCOUNTER4_LOW"/>
1685
+
<reg32 offset="0x0e6b" name="TCF_PERFCOUNTER5_LOW"/>
1686
+
<reg32 offset="0x0e6e" name="TCF_PERFCOUNTER6_LOW"/>
1687
+
<reg32 offset="0x0e71" name="TCF_PERFCOUNTER7_LOW"/>
1688
+
<reg32 offset="0x0e74" name="TCF_PERFCOUNTER8_LOW"/>
1689
+
<reg32 offset="0x0e77" name="TCF_PERFCOUNTER9_LOW"/>
1690
+
<reg32 offset="0x0e7a" name="TCF_PERFCOUNTER10_LOW"/>
1691
+
<reg32 offset="0x0e7d" name="TCF_PERFCOUNTER11_LOW"/>
1692
+
<reg32 offset="0x0dc8" name="SQ_PERFCOUNTER0_SELECT"/>
1693
+
<reg32 offset="0x0dc9" name="SQ_PERFCOUNTER1_SELECT"/>
1694
+
<reg32 offset="0x0dca" name="SQ_PERFCOUNTER2_SELECT"/>
1695
+
<reg32 offset="0x0dcb" name="SQ_PERFCOUNTER3_SELECT"/>
1696
+
<reg32 offset="0x0dcc" name="SQ_PERFCOUNTER0_LOW"/>
1697
+
<reg32 offset="0x0dcd" name="SQ_PERFCOUNTER0_HI"/>
1698
+
<reg32 offset="0x0dce" name="SQ_PERFCOUNTER1_LOW"/>
1699
+
<reg32 offset="0x0dcf" name="SQ_PERFCOUNTER1_HI"/>
1700
+
<reg32 offset="0x0dd0" name="SQ_PERFCOUNTER2_LOW"/>
1701
+
<reg32 offset="0x0dd1" name="SQ_PERFCOUNTER2_HI"/>
1702
+
<reg32 offset="0x0dd2" name="SQ_PERFCOUNTER3_LOW"/>
1703
+
<reg32 offset="0x0dd3" name="SQ_PERFCOUNTER3_HI"/>
1704
+
<reg32 offset="0x0dd4" name="SX_PERFCOUNTER0_SELECT"/>
1705
+
<reg32 offset="0x0dd8" name="SX_PERFCOUNTER0_LOW"/>
1706
+
<reg32 offset="0x0dd9" name="SX_PERFCOUNTER0_HI"/>
1707
+
<reg32 offset="0x0a46" name="MH_PERFCOUNTER0_SELECT"/>
1708
+
<reg32 offset="0x0a4a" name="MH_PERFCOUNTER1_SELECT"/>
1709
+
<reg32 offset="0x0a47" name="MH_PERFCOUNTER0_CONFIG"/>
1710
+
<reg32 offset="0x0a4b" name="MH_PERFCOUNTER1_CONFIG"/>
1711
+
<reg32 offset="0x0a48" name="MH_PERFCOUNTER0_LOW"/>
1712
+
<reg32 offset="0x0a4c" name="MH_PERFCOUNTER1_LOW"/>
1713
+
<reg32 offset="0x0a49" name="MH_PERFCOUNTER0_HI"/>
1714
+
<reg32 offset="0x0a4d" name="MH_PERFCOUNTER1_HI"/>
1715
+
<reg32 offset="0x0f04" name="RB_PERFCOUNTER0_SELECT"/>
1716
+
<reg32 offset="0x0f05" name="RB_PERFCOUNTER1_SELECT"/>
1717
+
<reg32 offset="0x0f06" name="RB_PERFCOUNTER2_SELECT"/>
1718
+
<reg32 offset="0x0f07" name="RB_PERFCOUNTER3_SELECT"/>
1719
+
<reg32 offset="0x0f08" name="RB_PERFCOUNTER0_LOW"/>
1720
+
<reg32 offset="0x0f09" name="RB_PERFCOUNTER0_HI"/>
1721
+
<reg32 offset="0x0f0a" name="RB_PERFCOUNTER1_LOW"/>
1722
+
<reg32 offset="0x0f0b" name="RB_PERFCOUNTER1_HI"/>
1723
+
<reg32 offset="0x0f0c" name="RB_PERFCOUNTER2_LOW"/>
1724
+
<reg32 offset="0x0f0d" name="RB_PERFCOUNTER2_HI"/>
1725
+
<reg32 offset="0x0f0e" name="RB_PERFCOUNTER3_LOW"/>
1726
+
<reg32 offset="0x0f0f" name="RB_PERFCOUNTER3_HI"/>
1727
+
</domain>
1728
+
1729
+
<domain name="A2XX_SQ_TEX" width="32">
1730
+
<doc>Texture state dwords</doc>
1731
+
<enum name="sq_tex_clamp">
1732
+
<value name="SQ_TEX_WRAP" value="0"/>
1733
+
<value name="SQ_TEX_MIRROR" value="1"/>
1734
+
<value name="SQ_TEX_CLAMP_LAST_TEXEL" value="2"/>
1735
+
<value name="SQ_TEX_MIRROR_ONCE_LAST_TEXEL" value="3"/>
1736
+
<value name="SQ_TEX_CLAMP_HALF_BORDER" value="4"/>
1737
+
<value name="SQ_TEX_MIRROR_ONCE_HALF_BORDER" value="5"/>
1738
+
<value name="SQ_TEX_CLAMP_BORDER" value="6"/>
1739
+
<value name="SQ_TEX_MIRROR_ONCE_BORDER" value="7"/>
1740
+
</enum>
1741
+
<enum name="sq_tex_swiz">
1742
+
<value name="SQ_TEX_X" value="0"/>
1743
+
<value name="SQ_TEX_Y" value="1"/>
1744
+
<value name="SQ_TEX_Z" value="2"/>
1745
+
<value name="SQ_TEX_W" value="3"/>
1746
+
<value name="SQ_TEX_ZERO" value="4"/>
1747
+
<value name="SQ_TEX_ONE" value="5"/>
1748
+
</enum>
1749
+
<enum name="sq_tex_filter">
1750
+
<value name="SQ_TEX_FILTER_POINT" value="0"/>
1751
+
<value name="SQ_TEX_FILTER_BILINEAR" value="1"/>
1752
+
<value name="SQ_TEX_FILTER_BASEMAP" value="2"/>
1753
+
<value name="SQ_TEX_FILTER_USE_FETCH_CONST" value="3"/>
1754
+
</enum>
1755
+
<enum name="sq_tex_aniso_filter">
1756
+
<value name="SQ_TEX_ANISO_FILTER_DISABLED" value="0"/>
1757
+
<value name="SQ_TEX_ANISO_FILTER_MAX_1_1" value="1"/>
1758
+
<value name="SQ_TEX_ANISO_FILTER_MAX_2_1" value="2"/>
1759
+
<value name="SQ_TEX_ANISO_FILTER_MAX_4_1" value="3"/>
1760
+
<value name="SQ_TEX_ANISO_FILTER_MAX_8_1" value="4"/>
1761
+
<value name="SQ_TEX_ANISO_FILTER_MAX_16_1" value="5"/>
1762
+
<value name="SQ_TEX_ANISO_FILTER_USE_FETCH_CONST" value="7"/>
1763
+
</enum>
1764
+
<enum name="sq_tex_dimension">
1765
+
<value name="SQ_TEX_DIMENSION_1D" value="0"/>
1766
+
<value name="SQ_TEX_DIMENSION_2D" value="1"/>
1767
+
<value name="SQ_TEX_DIMENSION_3D" value="2"/>
1768
+
<value name="SQ_TEX_DIMENSION_CUBE" value="3"/>
1769
+
</enum>
1770
+
<enum name="sq_tex_border_color">
1771
+
<value name="SQ_TEX_BORDER_COLOR_BLACK" value="0"/>
1772
+
<value name="SQ_TEX_BORDER_COLOR_WHITE" value="1"/>
1773
+
<value name="SQ_TEX_BORDER_COLOR_ACBYCR_BLACK" value="2"/>
1774
+
<value name="SQ_TEX_BORDER_COLOR_ACBCRY_BLACK" value="3"/>
1775
+
</enum>
1776
+
<enum name="sq_tex_sign">
1777
+
<value name="SQ_TEX_SIGN_UNSIGNED" value="0"/>
1778
+
<value name="SQ_TEX_SIGN_SIGNED" value="1"/>
1779
+
<!-- biased: 2*color-1 (range -1,1 when sampling) -->
1780
+
<value name="SQ_TEX_SIGN_UNSIGNED_BIASED" value="2"/>
1781
+
<!-- gamma: sRGB to linear - doesn't seem to work on adreno? -->
1782
+
<value name="SQ_TEX_SIGN_GAMMA" value="3"/>
1783
+
</enum>
1784
+
<enum name="sq_tex_endian">
1785
+
<value name="SQ_TEX_ENDIAN_NONE" value="0"/>
1786
+
<value name="SQ_TEX_ENDIAN_8IN16" value="1"/>
1787
+
<value name="SQ_TEX_ENDIAN_8IN32" value="2"/>
1788
+
<value name="SQ_TEX_ENDIAN_16IN32" value="3"/>
1789
+
</enum>
1790
+
<enum name="sq_tex_clamp_policy">
1791
+
<value name="SQ_TEX_CLAMP_POLICY_D3D" value="0"/>
1792
+
<value name="SQ_TEX_CLAMP_POLICY_OGL" value="1"/>
1793
+
</enum>
1794
+
<enum name="sq_tex_num_format">
1795
+
<value name="SQ_TEX_NUM_FORMAT_FRAC" value="0"/>
1796
+
<value name="SQ_TEX_NUM_FORMAT_INT" value="1"/>
1797
+
</enum>
1798
+
<enum name="sq_tex_type">
1799
+
<value name="SQ_TEX_TYPE_0" value="0"/>
1800
+
<value name="SQ_TEX_TYPE_1" value="1"/>
1801
+
<value name="SQ_TEX_TYPE_2" value="2"/>
1802
+
<value name="SQ_TEX_TYPE_3" value="3"/>
1803
+
</enum>
1804
+
<reg32 offset="0" name="0">
1805
+
<bitfield name="TYPE" low="0" high="1" type="sq_tex_type"/>
1806
+
<bitfield name="SIGN_X" low="2" high="3" type="sq_tex_sign"/>
1807
+
<bitfield name="SIGN_Y" low="4" high="5" type="sq_tex_sign"/>
1808
+
<bitfield name="SIGN_Z" low="6" high="7" type="sq_tex_sign"/>
1809
+
<bitfield name="SIGN_W" low="8" high="9" type="sq_tex_sign"/>
1810
+
<bitfield name="CLAMP_X" low="10" high="12" type="sq_tex_clamp"/>
1811
+
<bitfield name="CLAMP_Y" low="13" high="15" type="sq_tex_clamp"/>
1812
+
<bitfield name="CLAMP_Z" low="16" high="18" type="sq_tex_clamp"/>
1813
+
<bitfield name="PITCH" low="22" high="30" shr="5" type="uint"/>
1814
+
<bitfield name="TILED" pos="31" type="boolean"/>
1815
+
</reg32>
1816
+
<reg32 offset="1" name="1">
1817
+
<bitfield name="FORMAT" low="0" high="5" type="a2xx_sq_surfaceformat"/>
1818
+
<bitfield name="ENDIANNESS" low="6" high="7" type="sq_tex_endian"/>
1819
+
<bitfield name="REQUEST_SIZE" low="8" high="9" type="uint"/>
1820
+
<bitfield name="STACKED" pos="10" type="boolean"/>
1821
+
<bitfield name="CLAMP_POLICY" pos="11" type="sq_tex_clamp_policy"/>
1822
+
<bitfield name="BASE_ADDRESS" low="12" high="31" type="uint" shr="12"/>
1823
+
</reg32>
1824
+
<reg32 offset="2" name="2">
1825
+
<bitfield name="WIDTH" low="0" high="12" type="uint"/>
1826
+
<bitfield name="HEIGHT" low="13" high="25" type="uint"/>
1827
+
<bitfield name="DEPTH" low="26" high="31" type="uint"/>
1828
+
<!-- 1d/3d have different bit configurations -->
1829
+
</reg32>
1830
+
<reg32 offset="3" name="3">
1831
+
<bitfield name="NUM_FORMAT" pos="0" type="sq_tex_num_format"/>
1832
+
<bitfield name="SWIZ_X" low="1" high="3" type="sq_tex_swiz"/>
1833
+
<bitfield name="SWIZ_Y" low="4" high="6" type="sq_tex_swiz"/>
1834
+
<bitfield name="SWIZ_Z" low="7" high="9" type="sq_tex_swiz"/>
1835
+
<bitfield name="SWIZ_W" low="10" high="12" type="sq_tex_swiz"/>
1836
+
<bitfield name="EXP_ADJUST" low="13" high="18" type="int"/>
1837
+
<bitfield name="XY_MAG_FILTER" low="19" high="20" type="sq_tex_filter"/>
1838
+
<bitfield name="XY_MIN_FILTER" low="21" high="22" type="sq_tex_filter"/>
1839
+
<bitfield name="MIP_FILTER" low="23" high="24" type="sq_tex_filter"/>
1840
+
<bitfield name="ANISO_FILTER" low="25" high="27" type="sq_tex_aniso_filter"/>
1841
+
<bitfield name="BORDER_SIZE" pos="31" type="uint"/>
1842
+
</reg32>
1843
+
<reg32 offset="4" name="4">
1844
+
<bitfield name="VOL_MAG_FILTER" pos="0" type="sq_tex_filter"/>
1845
+
<bitfield name="VOL_MIN_FILTER" pos="1" type="sq_tex_filter"/>
1846
+
<bitfield name="MIP_MIN_LEVEL" low="2" high="5" type="uint"/>
1847
+
<bitfield name="MIP_MAX_LEVEL" low="6" high="9" type="uint"/>
1848
+
<bitfield name="MAX_ANISO_WALK" pos="10" type="boolean"/>
1849
+
<bitfield name="MIN_ANISO_WALK" pos="11" type="boolean"/>
1850
+
<bitfield name="LOD_BIAS" low="12" high="21" type="fixed" radix="5"/>
1851
+
<bitfield name="GRAD_EXP_ADJUST_H" low="22" high="26" type="uint"/>
1852
+
<bitfield name="GRAD_EXP_ADJUST_V" low="27" high="31" type="uint"/>
1853
+
</reg32>
1854
+
<reg32 offset="5" name="5">
1855
+
<bitfield name="BORDER_COLOR" low="0" high="1" type="sq_tex_border_color"/>
1856
+
<bitfield name="FORCE_BCW_MAX" pos="2" type="boolean"/>
1857
+
<bitfield name="TRI_CLAMP" low="3" high="4" type="uint"/>
1858
+
<bitfield name="ANISO_BIAS" low="5" high="8" type="fixed" radix="0"/> <!-- radix unknown -->
1859
+
<bitfield name="DIMENSION" low="9" high="10" type="sq_tex_dimension"/>
1860
+
<bitfield name="PACKED_MIPS" pos="11" type="boolean"/>
1861
+
<bitfield name="MIP_ADDRESS" low="12" high="31" type="uint" shr="12"/>
1862
+
</reg32>
1863
+
</domain>
1864
+
1865
+
</database>
+1751
drivers/gpu/drm/msm/registers/adreno/a3xx.xml
+1751
drivers/gpu/drm/msm/registers/adreno/a3xx.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
<import file="adreno/adreno_pm4.xml"/>
8
+
9
+
<enum name="a3xx_tile_mode">
10
+
<value name="LINEAR" value="0"/>
11
+
<value name="TILE_4X4" value="1"/> <!-- "normal" case for textures -->
12
+
<value name="TILE_32X32" value="2"/> <!-- only used in GMEM -->
13
+
<value name="TILE_4X2" value="3"/> <!-- only used for CrCb -->
14
+
</enum>
15
+
16
+
<enum name="a3xx_state_block_id">
17
+
<value name="HLSQ_BLOCK_ID_TP_TEX" value="2"/>
18
+
<value name="HLSQ_BLOCK_ID_TP_MIPMAP" value="3"/>
19
+
<value name="HLSQ_BLOCK_ID_SP_VS" value="4"/>
20
+
<value name="HLSQ_BLOCK_ID_SP_FS" value="6"/>
21
+
</enum>
22
+
23
+
<enum name="a3xx_cache_opcode">
24
+
<value name="INVALIDATE" value="1"/>
25
+
</enum>
26
+
27
+
<enum name="a3xx_vtx_fmt">
28
+
<value name="VFMT_32_FLOAT" value="0x0"/>
29
+
<value name="VFMT_32_32_FLOAT" value="0x1"/>
30
+
<value name="VFMT_32_32_32_FLOAT" value="0x2"/>
31
+
<value name="VFMT_32_32_32_32_FLOAT" value="0x3"/>
32
+
33
+
<value name="VFMT_16_FLOAT" value="0x4"/>
34
+
<value name="VFMT_16_16_FLOAT" value="0x5"/>
35
+
<value name="VFMT_16_16_16_FLOAT" value="0x6"/>
36
+
<value name="VFMT_16_16_16_16_FLOAT" value="0x7"/>
37
+
38
+
<value name="VFMT_32_FIXED" value="0x8"/>
39
+
<value name="VFMT_32_32_FIXED" value="0x9"/>
40
+
<value name="VFMT_32_32_32_FIXED" value="0xa"/>
41
+
<value name="VFMT_32_32_32_32_FIXED" value="0xb"/>
42
+
43
+
<value name="VFMT_16_SINT" value="0x10"/>
44
+
<value name="VFMT_16_16_SINT" value="0x11"/>
45
+
<value name="VFMT_16_16_16_SINT" value="0x12"/>
46
+
<value name="VFMT_16_16_16_16_SINT" value="0x13"/>
47
+
<value name="VFMT_16_UINT" value="0x14"/>
48
+
<value name="VFMT_16_16_UINT" value="0x15"/>
49
+
<value name="VFMT_16_16_16_UINT" value="0x16"/>
50
+
<value name="VFMT_16_16_16_16_UINT" value="0x17"/>
51
+
<value name="VFMT_16_SNORM" value="0x18"/>
52
+
<value name="VFMT_16_16_SNORM" value="0x19"/>
53
+
<value name="VFMT_16_16_16_SNORM" value="0x1a"/>
54
+
<value name="VFMT_16_16_16_16_SNORM" value="0x1b"/>
55
+
<value name="VFMT_16_UNORM" value="0x1c"/>
56
+
<value name="VFMT_16_16_UNORM" value="0x1d"/>
57
+
<value name="VFMT_16_16_16_UNORM" value="0x1e"/>
58
+
<value name="VFMT_16_16_16_16_UNORM" value="0x1f"/>
59
+
60
+
<!-- seems to be no NORM variants for 32bit.. -->
61
+
<value name="VFMT_32_UINT" value="0x20"/>
62
+
<value name="VFMT_32_32_UINT" value="0x21"/>
63
+
<value name="VFMT_32_32_32_UINT" value="0x22"/>
64
+
<value name="VFMT_32_32_32_32_UINT" value="0x23"/>
65
+
<value name="VFMT_32_SINT" value="0x24"/>
66
+
<value name="VFMT_32_32_SINT" value="0x25"/>
67
+
<value name="VFMT_32_32_32_SINT" value="0x26"/>
68
+
<value name="VFMT_32_32_32_32_SINT" value="0x27"/>
69
+
70
+
<value name="VFMT_8_UINT" value="0x28"/>
71
+
<value name="VFMT_8_8_UINT" value="0x29"/>
72
+
<value name="VFMT_8_8_8_UINT" value="0x2a"/>
73
+
<value name="VFMT_8_8_8_8_UINT" value="0x2b"/>
74
+
<value name="VFMT_8_UNORM" value="0x2c"/>
75
+
<value name="VFMT_8_8_UNORM" value="0x2d"/>
76
+
<value name="VFMT_8_8_8_UNORM" value="0x2e"/>
77
+
<value name="VFMT_8_8_8_8_UNORM" value="0x2f"/>
78
+
<value name="VFMT_8_SINT" value="0x30"/>
79
+
<value name="VFMT_8_8_SINT" value="0x31"/>
80
+
<value name="VFMT_8_8_8_SINT" value="0x32"/>
81
+
<value name="VFMT_8_8_8_8_SINT" value="0x33"/>
82
+
<value name="VFMT_8_SNORM" value="0x34"/>
83
+
<value name="VFMT_8_8_SNORM" value="0x35"/>
84
+
<value name="VFMT_8_8_8_SNORM" value="0x36"/>
85
+
<value name="VFMT_8_8_8_8_SNORM" value="0x37"/>
86
+
<value name="VFMT_10_10_10_2_UINT" value="0x38"/>
87
+
<value name="VFMT_10_10_10_2_UNORM" value="0x39"/>
88
+
<value name="VFMT_10_10_10_2_SINT" value="0x3a"/>
89
+
<value name="VFMT_10_10_10_2_SNORM" value="0x3b"/>
90
+
<value name="VFMT_2_10_10_10_UINT" value="0x3c"/>
91
+
<value name="VFMT_2_10_10_10_UNORM" value="0x3d"/>
92
+
<value name="VFMT_2_10_10_10_SINT" value="0x3e"/>
93
+
<value name="VFMT_2_10_10_10_SNORM" value="0x3f"/>
94
+
95
+
<value name="VFMT_NONE" value="0xff"/>
96
+
</enum>
97
+
98
+
<enum name="a3xx_tex_fmt">
99
+
<value name="TFMT_5_6_5_UNORM" value="0x4"/>
100
+
<value name="TFMT_5_5_5_1_UNORM" value="0x5"/>
101
+
<value name="TFMT_4_4_4_4_UNORM" value="0x7"/>
102
+
<value name="TFMT_Z16_UNORM" value="0x9"/>
103
+
<value name="TFMT_X8Z24_UNORM" value="0xa"/>
104
+
<value name="TFMT_Z32_FLOAT" value="0xb"/>
105
+
106
+
<!--
107
+
The NV12 tiled/linear formats seem to require gang'd sampler
108
+
slots (ie. sampler state N plus N+1) for Y and UV planes.
109
+
They fetch yuv in single sam instruction, but still require
110
+
colorspace conversion in the shader.
111
+
-->
112
+
<value name="TFMT_UV_64X32" value="0x10"/>
113
+
<value name="TFMT_VU_64X32" value="0x11"/>
114
+
<value name="TFMT_Y_64X32" value="0x12"/>
115
+
<value name="TFMT_NV12_64X32" value="0x13"/>
116
+
<value name="TFMT_UV_LINEAR" value="0x14"/>
117
+
<value name="TFMT_VU_LINEAR" value="0x15"/>
118
+
<value name="TFMT_Y_LINEAR" value="0x16"/>
119
+
<value name="TFMT_NV12_LINEAR" value="0x17"/>
120
+
<value name="TFMT_I420_Y" value="0x18"/>
121
+
<value name="TFMT_I420_U" value="0x1a"/>
122
+
<value name="TFMT_I420_V" value="0x1b"/>
123
+
124
+
<value name="TFMT_ATC_RGB" value="0x20"/>
125
+
<value name="TFMT_ATC_RGBA_EXPLICIT" value="0x21"/>
126
+
<value name="TFMT_ETC1" value="0x22"/>
127
+
<value name="TFMT_ATC_RGBA_INTERPOLATED" value="0x23"/>
128
+
129
+
<value name="TFMT_DXT1" value="0x24"/>
130
+
<value name="TFMT_DXT3" value="0x25"/>
131
+
<value name="TFMT_DXT5" value="0x26"/>
132
+
133
+
<value name="TFMT_2_10_10_10_UNORM" value="0x28"/>
134
+
<value name="TFMT_10_10_10_2_UNORM" value="0x29"/>
135
+
<value name="TFMT_9_9_9_E5_FLOAT" value="0x2a"/>
136
+
<value name="TFMT_11_11_10_FLOAT" value="0x2b"/>
137
+
<value name="TFMT_A8_UNORM" value="0x2c"/> <!-- GL_ALPHA -->
138
+
<value name="TFMT_L8_UNORM" value="0x2d"/>
139
+
<value name="TFMT_L8_A8_UNORM" value="0x2f"/> <!-- GL_LUMINANCE_ALPHA -->
140
+
141
+
<!--
142
+
NOTE: GL_ALPHA and GL_LUMINANCE_ALPHA aren't handled in a similar way
143
+
to float16, float32.. but they seem to use non-standard swizzle too..
144
+
perhaps we can ditch that if the pattern follows of 0xn0, 0xn1, 0xn2,
145
+
0xn3 for 1, 2, 3, 4 components respectively..
146
+
147
+
Only formats filled in below are the ones that have been observed by
148
+
the blob or tested.. you can guess what the missing ones are..
149
+
-->
150
+
151
+
<value name="TFMT_8_UNORM" value="0x30"/> <!-- GL_LUMINANCE -->
152
+
<value name="TFMT_8_8_UNORM" value="0x31"/>
153
+
<value name="TFMT_8_8_8_UNORM" value="0x32"/>
154
+
<value name="TFMT_8_8_8_8_UNORM" value="0x33"/>
155
+
156
+
<value name="TFMT_8_SNORM" value="0x34"/>
157
+
<value name="TFMT_8_8_SNORM" value="0x35"/>
158
+
<value name="TFMT_8_8_8_SNORM" value="0x36"/>
159
+
<value name="TFMT_8_8_8_8_SNORM" value="0x37"/>
160
+
161
+
<value name="TFMT_8_UINT" value="0x38"/>
162
+
<value name="TFMT_8_8_UINT" value="0x39"/>
163
+
<value name="TFMT_8_8_8_UINT" value="0x3a"/>
164
+
<value name="TFMT_8_8_8_8_UINT" value="0x3b"/>
165
+
166
+
<value name="TFMT_8_SINT" value="0x3c"/>
167
+
<value name="TFMT_8_8_SINT" value="0x3d"/>
168
+
<value name="TFMT_8_8_8_SINT" value="0x3e"/>
169
+
<value name="TFMT_8_8_8_8_SINT" value="0x3f"/>
170
+
171
+
<value name="TFMT_16_FLOAT" value="0x40"/>
172
+
<value name="TFMT_16_16_FLOAT" value="0x41"/>
173
+
<!-- TFMT_FLOAT_16_16_16 -->
174
+
<value name="TFMT_16_16_16_16_FLOAT" value="0x43"/>
175
+
176
+
<value name="TFMT_16_UINT" value="0x44"/>
177
+
<value name="TFMT_16_16_UINT" value="0x45"/>
178
+
<value name="TFMT_16_16_16_16_UINT" value="0x47"/>
179
+
180
+
<value name="TFMT_16_SINT" value="0x48"/>
181
+
<value name="TFMT_16_16_SINT" value="0x49"/>
182
+
<value name="TFMT_16_16_16_16_SINT" value="0x4b"/>
183
+
184
+
<value name="TFMT_16_UNORM" value="0x4c"/>
185
+
<value name="TFMT_16_16_UNORM" value="0x4d"/>
186
+
<value name="TFMT_16_16_16_16_UNORM" value="0x4f"/>
187
+
188
+
<value name="TFMT_16_SNORM" value="0x50"/>
189
+
<value name="TFMT_16_16_SNORM" value="0x51"/>
190
+
<value name="TFMT_16_16_16_16_SNORM" value="0x53"/>
191
+
192
+
<value name="TFMT_32_FLOAT" value="0x54"/>
193
+
<value name="TFMT_32_32_FLOAT" value="0x55"/>
194
+
<!-- TFMT_32_32_32_FLOAT -->
195
+
<value name="TFMT_32_32_32_32_FLOAT" value="0x57"/>
196
+
197
+
<value name="TFMT_32_UINT" value="0x58"/>
198
+
<value name="TFMT_32_32_UINT" value="0x59"/>
199
+
<value name="TFMT_32_32_32_32_UINT" value="0x5b"/>
200
+
201
+
<value name="TFMT_32_SINT" value="0x5c"/>
202
+
<value name="TFMT_32_32_SINT" value="0x5d"/>
203
+
<value name="TFMT_32_32_32_32_SINT" value="0x5f"/>
204
+
205
+
<value name="TFMT_2_10_10_10_UINT" value="0x60"/>
206
+
<value name="TFMT_10_10_10_2_UINT" value="0x61"/>
207
+
208
+
<value name="TFMT_ETC2_RG11_SNORM" value="0x70"/>
209
+
<value name="TFMT_ETC2_RG11_UNORM" value="0x71"/>
210
+
<value name="TFMT_ETC2_R11_SNORM" value="0x72"/>
211
+
<value name="TFMT_ETC2_R11_UNORM" value="0x73"/>
212
+
<value name="TFMT_ETC2_RGBA8" value="0x74"/>
213
+
<value name="TFMT_ETC2_RGB8A1" value="0x75"/>
214
+
<value name="TFMT_ETC2_RGB8" value="0x76"/>
215
+
216
+
<value name="TFMT_NONE" value="0xff"/>
217
+
</enum>
218
+
219
+
<enum name="a3xx_color_fmt">
220
+
<value name="RB_R5G6B5_UNORM" value="0x00"/>
221
+
<value name="RB_R5G5B5A1_UNORM" value="0x01"/>
222
+
<value name="RB_R4G4B4A4_UNORM" value="0x03"/>
223
+
<value name="RB_R8G8B8_UNORM" value="0x04"/>
224
+
<value name="RB_R8G8B8A8_UNORM" value="0x08"/>
225
+
<value name="RB_R8G8B8A8_SNORM" value="0x09"/>
226
+
<value name="RB_R8G8B8A8_UINT" value="0x0a"/>
227
+
<value name="RB_R8G8B8A8_SINT" value="0x0b"/>
228
+
<value name="RB_R8G8_UNORM" value="0x0c"/>
229
+
<value name="RB_R8G8_SNORM" value="0x0d"/>
230
+
<value name="RB_R8G8_UINT" value="0x0e"/>
231
+
<value name="RB_R8G8_SINT" value="0x0f"/>
232
+
<value name="RB_R10G10B10A2_UNORM" value="0x10"/>
233
+
<value name="RB_A2R10G10B10_UNORM" value="0x11"/>
234
+
<value name="RB_R10G10B10A2_UINT" value="0x12"/>
235
+
<value name="RB_A2R10G10B10_UINT" value="0x13"/>
236
+
237
+
<value name="RB_A8_UNORM" value="0x14"/>
238
+
<value name="RB_R8_UNORM" value="0x15"/>
239
+
240
+
<value name="RB_R16_FLOAT" value="0x18"/>
241
+
<value name="RB_R16G16_FLOAT" value="0x19"/>
242
+
<value name="RB_R16G16B16A16_FLOAT" value="0x1b"/> <!-- GL_HALF_FLOAT_OES -->
243
+
<value name="RB_R11G11B10_FLOAT" value="0x1c"/>
244
+
245
+
<value name="RB_R16_SNORM" value="0x20"/>
246
+
<value name="RB_R16G16_SNORM" value="0x21"/>
247
+
<value name="RB_R16G16B16A16_SNORM" value="0x23"/>
248
+
249
+
<value name="RB_R16_UNORM" value="0x24"/>
250
+
<value name="RB_R16G16_UNORM" value="0x25"/>
251
+
<value name="RB_R16G16B16A16_UNORM" value="0x27"/>
252
+
253
+
<value name="RB_R16_SINT" value="0x28"/>
254
+
<value name="RB_R16G16_SINT" value="0x29"/>
255
+
<value name="RB_R16G16B16A16_SINT" value="0x2b"/>
256
+
257
+
<value name="RB_R16_UINT" value="0x2c"/>
258
+
<value name="RB_R16G16_UINT" value="0x2d"/>
259
+
<value name="RB_R16G16B16A16_UINT" value="0x2f"/>
260
+
261
+
<value name="RB_R32_FLOAT" value="0x30"/>
262
+
<value name="RB_R32G32_FLOAT" value="0x31"/>
263
+
<value name="RB_R32G32B32A32_FLOAT" value="0x33"/> <!-- GL_FLOAT -->
264
+
265
+
<value name="RB_R32_SINT" value="0x34"/>
266
+
<value name="RB_R32G32_SINT" value="0x35"/>
267
+
<value name="RB_R32G32B32A32_SINT" value="0x37"/>
268
+
269
+
<value name="RB_R32_UINT" value="0x38"/>
270
+
<value name="RB_R32G32_UINT" value="0x39"/>
271
+
<value name="RB_R32G32B32A32_UINT" value="0x3b"/>
272
+
273
+
<value name="RB_NONE" value="0xff"/>
274
+
</enum>
275
+
276
+
<enum name="a3xx_cp_perfcounter_select">
277
+
<value value="0x00" name="CP_ALWAYS_COUNT"/>
278
+
<value value="0x03" name="CP_AHB_PFPTRANS_WAIT"/>
279
+
<value value="0x06" name="CP_AHB_NRTTRANS_WAIT"/>
280
+
<value value="0x08" name="CP_CSF_NRT_READ_WAIT"/>
281
+
<value value="0x09" name="CP_CSF_I1_FIFO_FULL"/>
282
+
<value value="0x0a" name="CP_CSF_I2_FIFO_FULL"/>
283
+
<value value="0x0b" name="CP_CSF_ST_FIFO_FULL"/>
284
+
<value value="0x0c" name="CP_RESERVED_12"/>
285
+
<value value="0x0d" name="CP_CSF_RING_ROQ_FULL"/>
286
+
<value value="0x0e" name="CP_CSF_I1_ROQ_FULL"/>
287
+
<value value="0x0f" name="CP_CSF_I2_ROQ_FULL"/>
288
+
<value value="0x10" name="CP_CSF_ST_ROQ_FULL"/>
289
+
<value value="0x11" name="CP_RESERVED_17"/>
290
+
<value value="0x12" name="CP_MIU_TAG_MEM_FULL"/>
291
+
<value value="0x16" name="CP_MIU_NRT_WRITE_STALLED"/>
292
+
<value value="0x17" name="CP_MIU_NRT_READ_STALLED"/>
293
+
<value value="0x1a" name="CP_ME_REGS_RB_DONE_FIFO_FULL"/>
294
+
<value value="0x1b" name="CP_ME_REGS_VS_EVENT_FIFO_FULL"/>
295
+
<value value="0x1c" name="CP_ME_REGS_PS_EVENT_FIFO_FULL"/>
296
+
<value value="0x1d" name="CP_ME_REGS_CF_EVENT_FIFO_FULL"/>
297
+
<value value="0x1e" name="CP_ME_MICRO_RB_STARVED"/>
298
+
<value value="0x28" name="CP_AHB_RBBM_DWORD_SENT"/>
299
+
<value value="0x29" name="CP_ME_BUSY_CLOCKS"/>
300
+
<value value="0x2a" name="CP_ME_WAIT_CONTEXT_AVAIL"/>
301
+
<value value="0x2b" name="CP_PFP_TYPE0_PACKET"/>
302
+
<value value="0x2c" name="CP_PFP_TYPE3_PACKET"/>
303
+
<value value="0x2d" name="CP_CSF_RB_WPTR_NEQ_RPTR"/>
304
+
<value value="0x2e" name="CP_CSF_I1_SIZE_NEQ_ZERO"/>
305
+
<value value="0x2f" name="CP_CSF_I2_SIZE_NEQ_ZERO"/>
306
+
<value value="0x30" name="CP_CSF_RBI1I2_FETCHING"/>
307
+
</enum>
308
+
309
+
<enum name="a3xx_gras_tse_perfcounter_select">
310
+
<value value="0x00" name="GRAS_TSEPERF_INPUT_PRIM"/>
311
+
<value value="0x01" name="GRAS_TSEPERF_INPUT_NULL_PRIM"/>
312
+
<value value="0x02" name="GRAS_TSEPERF_TRIVAL_REJ_PRIM"/>
313
+
<value value="0x03" name="GRAS_TSEPERF_CLIPPED_PRIM"/>
314
+
<value value="0x04" name="GRAS_TSEPERF_NEW_PRIM"/>
315
+
<value value="0x05" name="GRAS_TSEPERF_ZERO_AREA_PRIM"/>
316
+
<value value="0x06" name="GRAS_TSEPERF_FACENESS_CULLED_PRIM"/>
317
+
<value value="0x07" name="GRAS_TSEPERF_ZERO_PIXEL_PRIM"/>
318
+
<value value="0x08" name="GRAS_TSEPERF_OUTPUT_NULL_PRIM"/>
319
+
<value value="0x09" name="GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM"/>
320
+
<value value="0x0a" name="GRAS_TSEPERF_PRE_CLIP_PRIM"/>
321
+
<value value="0x0b" name="GRAS_TSEPERF_POST_CLIP_PRIM"/>
322
+
<value value="0x0c" name="GRAS_TSEPERF_WORKING_CYCLES"/>
323
+
<value value="0x0d" name="GRAS_TSEPERF_PC_STARVE"/>
324
+
<value value="0x0e" name="GRAS_TSERASPERF_STALL"/>
325
+
</enum>
326
+
327
+
<enum name="a3xx_gras_ras_perfcounter_select">
328
+
<value value="0x00" name="GRAS_RASPERF_16X16_TILES"/>
329
+
<value value="0x01" name="GRAS_RASPERF_8X8_TILES"/>
330
+
<value value="0x02" name="GRAS_RASPERF_4X4_TILES"/>
331
+
<value value="0x03" name="GRAS_RASPERF_WORKING_CYCLES"/>
332
+
<value value="0x04" name="GRAS_RASPERF_STALL_CYCLES_BY_RB"/>
333
+
<value value="0x05" name="GRAS_RASPERF_STALL_CYCLES_BY_VSC"/>
334
+
<value value="0x06" name="GRAS_RASPERF_STARVE_CYCLES_BY_TSE"/>
335
+
</enum>
336
+
337
+
<enum name="a3xx_hlsq_perfcounter_select">
338
+
<value value="0x00" name="HLSQ_PERF_SP_VS_CONSTANT"/>
339
+
<value value="0x01" name="HLSQ_PERF_SP_VS_INSTRUCTIONS"/>
340
+
<value value="0x02" name="HLSQ_PERF_SP_FS_CONSTANT"/>
341
+
<value value="0x03" name="HLSQ_PERF_SP_FS_INSTRUCTIONS"/>
342
+
<value value="0x04" name="HLSQ_PERF_TP_STATE"/>
343
+
<value value="0x05" name="HLSQ_PERF_QUADS"/>
344
+
<value value="0x06" name="HLSQ_PERF_PIXELS"/>
345
+
<value value="0x07" name="HLSQ_PERF_VERTICES"/>
346
+
<value value="0x08" name="HLSQ_PERF_FS8_THREADS"/>
347
+
<value value="0x09" name="HLSQ_PERF_FS16_THREADS"/>
348
+
<value value="0x0a" name="HLSQ_PERF_FS32_THREADS"/>
349
+
<value value="0x0b" name="HLSQ_PERF_VS8_THREADS"/>
350
+
<value value="0x0c" name="HLSQ_PERF_VS16_THREADS"/>
351
+
<value value="0x0d" name="HLSQ_PERF_SP_VS_DATA_BYTES"/>
352
+
<value value="0x0e" name="HLSQ_PERF_SP_FS_DATA_BYTES"/>
353
+
<value value="0x0f" name="HLSQ_PERF_ACTIVE_CYCLES"/>
354
+
<value value="0x10" name="HLSQ_PERF_STALL_CYCLES_SP_STATE"/>
355
+
<value value="0x11" name="HLSQ_PERF_STALL_CYCLES_SP_VS"/>
356
+
<value value="0x12" name="HLSQ_PERF_STALL_CYCLES_SP_FS"/>
357
+
<value value="0x13" name="HLSQ_PERF_STALL_CYCLES_UCHE"/>
358
+
<value value="0x14" name="HLSQ_PERF_RBBM_LOAD_CYCLES"/>
359
+
<value value="0x15" name="HLSQ_PERF_DI_TO_VS_START_SP0"/>
360
+
<value value="0x16" name="HLSQ_PERF_DI_TO_FS_START_SP0"/>
361
+
<value value="0x17" name="HLSQ_PERF_VS_START_TO_DONE_SP0"/>
362
+
<value value="0x18" name="HLSQ_PERF_FS_START_TO_DONE_SP0"/>
363
+
<value value="0x19" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_VS"/>
364
+
<value value="0x1a" name="HLSQ_PERF_SP_STATE_COPY_CYCLES_FS"/>
365
+
<value value="0x1b" name="HLSQ_PERF_UCHE_LATENCY_CYCLES"/>
366
+
<value value="0x1c" name="HLSQ_PERF_UCHE_LATENCY_COUNT"/>
367
+
</enum>
368
+
369
+
<enum name="a3xx_pc_perfcounter_select">
370
+
<value value="0x00" name="PC_PCPERF_VISIBILITY_STREAMS"/>
371
+
<value value="0x01" name="PC_PCPERF_TOTAL_INSTANCES"/>
372
+
<value value="0x02" name="PC_PCPERF_PRIMITIVES_PC_VPC"/>
373
+
<value value="0x03" name="PC_PCPERF_PRIMITIVES_KILLED_BY_VS"/>
374
+
<value value="0x04" name="PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS"/>
375
+
<value value="0x05" name="PC_PCPERF_DRAWCALLS_KILLED_BY_VS"/>
376
+
<value value="0x06" name="PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS"/>
377
+
<value value="0x07" name="PC_PCPERF_VERTICES_TO_VFD"/>
378
+
<value value="0x08" name="PC_PCPERF_REUSED_VERTICES"/>
379
+
<value value="0x09" name="PC_PCPERF_CYCLES_STALLED_BY_VFD"/>
380
+
<value value="0x0a" name="PC_PCPERF_CYCLES_STALLED_BY_TSE"/>
381
+
<value value="0x0b" name="PC_PCPERF_CYCLES_STALLED_BY_VBIF"/>
382
+
<value value="0x0c" name="PC_PCPERF_CYCLES_IS_WORKING"/>
383
+
</enum>
384
+
385
+
<enum name="a3xx_rb_perfcounter_select">
386
+
<value value="0x00" name="RB_RBPERF_ACTIVE_CYCLES_ANY"/>
387
+
<value value="0x01" name="RB_RBPERF_ACTIVE_CYCLES_ALL"/>
388
+
<value value="0x02" name="RB_RBPERF_STARVE_CYCLES_BY_SP"/>
389
+
<value value="0x03" name="RB_RBPERF_STARVE_CYCLES_BY_RAS"/>
390
+
<value value="0x04" name="RB_RBPERF_STARVE_CYCLES_BY_MARB"/>
391
+
<value value="0x05" name="RB_RBPERF_STALL_CYCLES_BY_MARB"/>
392
+
<value value="0x06" name="RB_RBPERF_STALL_CYCLES_BY_HLSQ"/>
393
+
<value value="0x07" name="RB_RBPERF_RB_MARB_DATA"/>
394
+
<value value="0x08" name="RB_RBPERF_SP_RB_QUAD"/>
395
+
<value value="0x09" name="RB_RBPERF_RAS_EARLY_Z_QUADS"/>
396
+
<value value="0x0a" name="RB_RBPERF_GMEM_CH0_READ"/>
397
+
<value value="0x0b" name="RB_RBPERF_GMEM_CH1_READ"/>
398
+
<value value="0x0c" name="RB_RBPERF_GMEM_CH0_WRITE"/>
399
+
<value value="0x0d" name="RB_RBPERF_GMEM_CH1_WRITE"/>
400
+
<value value="0x0e" name="RB_RBPERF_CP_CONTEXT_DONE"/>
401
+
<value value="0x0f" name="RB_RBPERF_CP_CACHE_FLUSH"/>
402
+
<value value="0x10" name="RB_RBPERF_CP_ZPASS_DONE"/>
403
+
</enum>
404
+
405
+
<enum name="a3xx_rbbm_perfcounter_select">
406
+
<value value="0" name="RBBM_ALAWYS_ON"/>
407
+
<value value="1" name="RBBM_VBIF_BUSY"/>
408
+
<value value="2" name="RBBM_TSE_BUSY"/>
409
+
<value value="3" name="RBBM_RAS_BUSY"/>
410
+
<value value="4" name="RBBM_PC_DCALL_BUSY"/>
411
+
<value value="5" name="RBBM_PC_VSD_BUSY"/>
412
+
<value value="6" name="RBBM_VFD_BUSY"/>
413
+
<value value="7" name="RBBM_VPC_BUSY"/>
414
+
<value value="8" name="RBBM_UCHE_BUSY"/>
415
+
<value value="9" name="RBBM_VSC_BUSY"/>
416
+
<value value="10" name="RBBM_HLSQ_BUSY"/>
417
+
<value value="11" name="RBBM_ANY_RB_BUSY"/>
418
+
<value value="12" name="RBBM_ANY_TEX_BUSY"/>
419
+
<value value="13" name="RBBM_ANY_USP_BUSY"/>
420
+
<value value="14" name="RBBM_ANY_MARB_BUSY"/>
421
+
<value value="15" name="RBBM_ANY_ARB_BUSY"/>
422
+
<value value="16" name="RBBM_AHB_STATUS_BUSY"/>
423
+
<value value="17" name="RBBM_AHB_STATUS_STALLED"/>
424
+
<value value="18" name="RBBM_AHB_STATUS_TXFR"/>
425
+
<value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
426
+
<value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
427
+
<value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
428
+
<value value="22" name="RBBM_RBBM_STATUS_MASKED"/>
429
+
</enum>
430
+
431
+
<enum name="a3xx_sp_perfcounter_select">
432
+
<value value="0x00" name="SP_LM_LOAD_INSTRUCTIONS"/>
433
+
<value value="0x01" name="SP_LM_STORE_INSTRUCTIONS"/>
434
+
<value value="0x02" name="SP_LM_ATOMICS"/>
435
+
<value value="0x03" name="SP_UCHE_LOAD_INSTRUCTIONS"/>
436
+
<value value="0x04" name="SP_UCHE_STORE_INSTRUCTIONS"/>
437
+
<value value="0x05" name="SP_UCHE_ATOMICS"/>
438
+
<value value="0x06" name="SP_VS_TEX_INSTRUCTIONS"/>
439
+
<value value="0x07" name="SP_VS_CFLOW_INSTRUCTIONS"/>
440
+
<value value="0x08" name="SP_VS_EFU_INSTRUCTIONS"/>
441
+
<value value="0x09" name="SP_VS_FULL_ALU_INSTRUCTIONS"/>
442
+
<value value="0x0a" name="SP_VS_HALF_ALU_INSTRUCTIONS"/>
443
+
<value value="0x0b" name="SP_FS_TEX_INSTRUCTIONS"/>
444
+
<value value="0x0c" name="SP_FS_CFLOW_INSTRUCTIONS"/>
445
+
<value value="0x0d" name="SP_FS_EFU_INSTRUCTIONS"/>
446
+
<value value="0x0e" name="SP_FS_FULL_ALU_INSTRUCTIONS"/>
447
+
<value value="0x0f" name="SP_FS_HALF_ALU_INSTRUCTIONS"/>
448
+
<value value="0x10" name="SP_FS_BARY_INSTRUCTIONS"/>
449
+
<value value="0x11" name="SP_VS_INSTRUCTIONS"/>
450
+
<value value="0x12" name="SP_FS_INSTRUCTIONS"/>
451
+
<value value="0x13" name="SP_ADDR_LOCK_COUNT"/>
452
+
<value value="0x14" name="SP_UCHE_READ_TRANS"/>
453
+
<value value="0x15" name="SP_UCHE_WRITE_TRANS"/>
454
+
<value value="0x16" name="SP_EXPORT_VPC_TRANS"/>
455
+
<value value="0x17" name="SP_EXPORT_RB_TRANS"/>
456
+
<value value="0x18" name="SP_PIXELS_KILLED"/>
457
+
<value value="0x19" name="SP_ICL1_REQUESTS"/>
458
+
<value value="0x1a" name="SP_ICL1_MISSES"/>
459
+
<value value="0x1b" name="SP_ICL0_REQUESTS"/>
460
+
<value value="0x1c" name="SP_ICL0_MISSES"/>
461
+
<value value="0x1d" name="SP_ALU_ACTIVE_CYCLES"/>
462
+
<value value="0x1e" name="SP_EFU_ACTIVE_CYCLES"/>
463
+
<value value="0x1f" name="SP_STALL_CYCLES_BY_VPC"/>
464
+
<value value="0x20" name="SP_STALL_CYCLES_BY_TP"/>
465
+
<value value="0x21" name="SP_STALL_CYCLES_BY_UCHE"/>
466
+
<value value="0x22" name="SP_STALL_CYCLES_BY_RB"/>
467
+
<value value="0x23" name="SP_ACTIVE_CYCLES_ANY"/>
468
+
<value value="0x24" name="SP_ACTIVE_CYCLES_ALL"/>
469
+
</enum>
470
+
471
+
<enum name="a3xx_tp_perfcounter_select">
472
+
<value value="0x00" name="TPL1_TPPERF_L1_REQUESTS"/>
473
+
<value value="0x01" name="TPL1_TPPERF_TP0_L1_REQUESTS"/>
474
+
<value value="0x02" name="TPL1_TPPERF_TP0_L1_MISSES"/>
475
+
<value value="0x03" name="TPL1_TPPERF_TP1_L1_REQUESTS"/>
476
+
<value value="0x04" name="TPL1_TPPERF_TP1_L1_MISSES"/>
477
+
<value value="0x05" name="TPL1_TPPERF_TP2_L1_REQUESTS"/>
478
+
<value value="0x06" name="TPL1_TPPERF_TP2_L1_MISSES"/>
479
+
<value value="0x07" name="TPL1_TPPERF_TP3_L1_REQUESTS"/>
480
+
<value value="0x08" name="TPL1_TPPERF_TP3_L1_MISSES"/>
481
+
<value value="0x09" name="TPL1_TPPERF_OUTPUT_TEXELS_POINT"/>
482
+
<value value="0x0a" name="TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR"/>
483
+
<value value="0x0b" name="TPL1_TPPERF_OUTPUT_TEXELS_MIP"/>
484
+
<value value="0x0c" name="TPL1_TPPERF_OUTPUT_TEXELS_ANISO"/>
485
+
<value value="0x0d" name="TPL1_TPPERF_BILINEAR_OPS"/>
486
+
<value value="0x0e" name="TPL1_TPPERF_QUADSQUADS_OFFSET"/>
487
+
<value value="0x0f" name="TPL1_TPPERF_QUADQUADS_SHADOW"/>
488
+
<value value="0x10" name="TPL1_TPPERF_QUADS_ARRAY"/>
489
+
<value value="0x11" name="TPL1_TPPERF_QUADS_PROJECTION"/>
490
+
<value value="0x12" name="TPL1_TPPERF_QUADS_GRADIENT"/>
491
+
<value value="0x13" name="TPL1_TPPERF_QUADS_1D2D"/>
492
+
<value value="0x14" name="TPL1_TPPERF_QUADS_3DCUBE"/>
493
+
<value value="0x15" name="TPL1_TPPERF_ZERO_LOD"/>
494
+
<value value="0x16" name="TPL1_TPPERF_OUTPUT_TEXELS"/>
495
+
<value value="0x17" name="TPL1_TPPERF_ACTIVE_CYCLES_ANY"/>
496
+
<value value="0x18" name="TPL1_TPPERF_ACTIVE_CYCLES_ALL"/>
497
+
<value value="0x19" name="TPL1_TPPERF_STALL_CYCLES_BY_ARB"/>
498
+
<value value="0x1a" name="TPL1_TPPERF_LATENCY"/>
499
+
<value value="0x1b" name="TPL1_TPPERF_LATENCY_TRANS"/>
500
+
</enum>
501
+
502
+
<enum name="a3xx_vfd_perfcounter_select">
503
+
<value value="0" name="VFD_PERF_UCHE_BYTE_FETCHED"/>
504
+
<value value="1" name="VFD_PERF_UCHE_TRANS"/>
505
+
<value value="2" name="VFD_PERF_VPC_BYPASS_COMPONENTS"/>
506
+
<value value="3" name="VFD_PERF_FETCH_INSTRUCTIONS"/>
507
+
<value value="4" name="VFD_PERF_DECODE_INSTRUCTIONS"/>
508
+
<value value="5" name="VFD_PERF_ACTIVE_CYCLES"/>
509
+
<value value="6" name="VFD_PERF_STALL_CYCLES_UCHE"/>
510
+
<value value="7" name="VFD_PERF_STALL_CYCLES_HLSQ"/>
511
+
<value value="8" name="VFD_PERF_STALL_CYCLES_VPC_BYPASS"/>
512
+
<value value="9" name="VFD_PERF_STALL_CYCLES_VPC_ALLOC"/>
513
+
</enum>
514
+
515
+
<enum name="a3xx_vpc_perfcounter_select">
516
+
<value value="0" name="VPC_PERF_SP_LM_PRIMITIVES"/>
517
+
<value value="1" name="VPC_PERF_COMPONENTS_FROM_SP"/>
518
+
<value value="2" name="VPC_PERF_SP_LM_COMPONENTS"/>
519
+
<value value="3" name="VPC_PERF_ACTIVE_CYCLES"/>
520
+
<value value="4" name="VPC_PERF_STALL_CYCLES_LM"/>
521
+
<value value="5" name="VPC_PERF_STALL_CYCLES_RAS"/>
522
+
</enum>
523
+
524
+
<enum name="a3xx_uche_perfcounter_select">
525
+
<value value="0x00" name="UCHE_UCHEPERF_VBIF_READ_BEATS_TP"/>
526
+
<value value="0x01" name="UCHE_UCHEPERF_VBIF_READ_BEATS_VFD"/>
527
+
<value value="0x02" name="UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ"/>
528
+
<value value="0x03" name="UCHE_UCHEPERF_VBIF_READ_BEATS_MARB"/>
529
+
<value value="0x04" name="UCHE_UCHEPERF_VBIF_READ_BEATS_SP"/>
530
+
<value value="0x08" name="UCHE_UCHEPERF_READ_REQUESTS_TP"/>
531
+
<value value="0x09" name="UCHE_UCHEPERF_READ_REQUESTS_VFD"/>
532
+
<value value="0x0a" name="UCHE_UCHEPERF_READ_REQUESTS_HLSQ"/>
533
+
<value value="0x0b" name="UCHE_UCHEPERF_READ_REQUESTS_MARB"/>
534
+
<value value="0x0c" name="UCHE_UCHEPERF_READ_REQUESTS_SP"/>
535
+
<value value="0x0d" name="UCHE_UCHEPERF_WRITE_REQUESTS_MARB"/>
536
+
<value value="0x0e" name="UCHE_UCHEPERF_WRITE_REQUESTS_SP"/>
537
+
<value value="0x0f" name="UCHE_UCHEPERF_TAG_CHECK_FAILS"/>
538
+
<value value="0x10" name="UCHE_UCHEPERF_EVICTS"/>
539
+
<value value="0x11" name="UCHE_UCHEPERF_FLUSHES"/>
540
+
<value value="0x12" name="UCHE_UCHEPERF_VBIF_LATENCY_CYCLES"/>
541
+
<value value="0x13" name="UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES"/>
542
+
<value value="0x14" name="UCHE_UCHEPERF_ACTIVE_CYCLES"/>
543
+
</enum>
544
+
545
+
<enum name="a3xx_intp_mode">
546
+
<value name="SMOOTH" value="0"/>
547
+
<value name="FLAT" value="1"/>
548
+
<value name="ZERO" value="2"/>
549
+
<value name="ONE" value="3"/>
550
+
</enum>
551
+
552
+
<enum name="a3xx_repl_mode">
553
+
<value name="S" value="1"/>
554
+
<value name="T" value="2"/>
555
+
<value name="ONE_T" value="3"/>
556
+
</enum>
557
+
558
+
<domain name="A3XX" width="32">
559
+
<!-- RBBM registers -->
560
+
<reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
561
+
<reg32 offset="0x0001" name="RBBM_HW_RELEASE"/>
562
+
<reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
563
+
<reg32 offset="0x0010" name="RBBM_CLOCK_CTL"/>
564
+
<reg32 offset="0x0012" name="RBBM_SP_HYST_CNT"/>
565
+
<reg32 offset="0x0018" name="RBBM_SW_RESET_CMD"/>
566
+
<reg32 offset="0x0020" name="RBBM_AHB_CTL0"/>
567
+
<reg32 offset="0x0021" name="RBBM_AHB_CTL1"/>
568
+
<reg32 offset="0x0022" name="RBBM_AHB_CMD"/>
569
+
<reg32 offset="0x0027" name="RBBM_AHB_ERROR_STATUS"/>
570
+
<reg32 offset="0x002e" name="RBBM_GPR0_CTL"/>
571
+
<reg32 offset="0x0030" name="RBBM_STATUS">
572
+
<bitfield name="HI_BUSY" pos="0" type="boolean"/>
573
+
<bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
574
+
<bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
575
+
<bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
576
+
<bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
577
+
<bitfield name="TSE_BUSY" pos="16" type="boolean"/>
578
+
<bitfield name="RAS_BUSY" pos="17" type="boolean"/>
579
+
<bitfield name="RB_BUSY" pos="18" type="boolean"/>
580
+
<bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
581
+
<bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
582
+
<bitfield name="VFD_BUSY" pos="21" type="boolean"/>
583
+
<bitfield name="VPC_BUSY" pos="22" type="boolean"/>
584
+
<bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
585
+
<bitfield name="SP_BUSY" pos="24" type="boolean"/>
586
+
<bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
587
+
<bitfield name="MARB_BUSY" pos="26" type="boolean"/>
588
+
<bitfield name="VSC_BUSY" pos="27" type="boolean"/>
589
+
<bitfield name="ARB_BUSY" pos="28" type="boolean"/>
590
+
<bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
591
+
<bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
592
+
<bitfield name="GPU_BUSY" pos="31" type="boolean"/>
593
+
</reg32>
594
+
<!-- used in fw CP_WAIT_FOR_IDLE, similar to NQWAIT_UNTIL on a2xx: -->
595
+
<reg32 offset="0x0040" name="RBBM_NQWAIT_UNTIL"/>
596
+
<reg32 offset="0x0033" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
597
+
<reg32 offset="0x0050" name="RBBM_INTERFACE_HANG_INT_CTL"/>
598
+
<reg32 offset="0x0051" name="RBBM_INTERFACE_HANG_MASK_CTL0"/>
599
+
<reg32 offset="0x0054" name="RBBM_INTERFACE_HANG_MASK_CTL1"/>
600
+
<reg32 offset="0x0057" name="RBBM_INTERFACE_HANG_MASK_CTL2"/>
601
+
<reg32 offset="0x005a" name="RBBM_INTERFACE_HANG_MASK_CTL3"/>
602
+
603
+
<bitset name="A3XX_INT0">
604
+
<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
605
+
<bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
606
+
<bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>
607
+
<bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
608
+
<bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
609
+
<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>
610
+
<bitfield name="VFD_ERROR" pos="6" type="boolean"/>
611
+
<bitfield name="CP_SW_INT" pos="7" type="boolean"/>
612
+
<bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>
613
+
<bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>
614
+
<bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>
615
+
<bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>
616
+
<bitfield name="CP_DMA" pos="12" type="boolean"/>
617
+
<bitfield name="CP_IB2_INT" pos="13" type="boolean"/>
618
+
<bitfield name="CP_IB1_INT" pos="14" type="boolean"/>
619
+
<bitfield name="CP_RB_INT" pos="15" type="boolean"/>
620
+
<bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>
621
+
<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
622
+
<bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>
623
+
<bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>
624
+
<bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>
625
+
<bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>
626
+
<bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>
627
+
<bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>
628
+
</bitset>
629
+
630
+
631
+
<!--
632
+
set in pm4 fw INVALID_JUMP_TABLE_ENTRY and CP_INTERRUPT (compare
633
+
to CP_INT_STATUS in a2xx firmware), so this seems to be the a3xx
634
+
way for fw to raise and irq:
635
+
-->
636
+
<reg32 offset="0x0060" name="RBBM_INT_SET_CMD" type="A3XX_INT0"/>
637
+
<reg32 offset="0x0061" name="RBBM_INT_CLEAR_CMD" type="A3XX_INT0"/>
638
+
<reg32 offset="0x0063" name="RBBM_INT_0_MASK" type="A3XX_INT0"/>
639
+
<reg32 offset="0x0064" name="RBBM_INT_0_STATUS" type="A3XX_INT0"/>
640
+
<reg32 offset="0x0080" name="RBBM_PERFCTR_CTL">
641
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
642
+
</reg32>
643
+
<reg32 offset="0x0081" name="RBBM_PERFCTR_LOAD_CMD0"/>
644
+
<reg32 offset="0x0082" name="RBBM_PERFCTR_LOAD_CMD1"/>
645
+
<reg32 offset="0x0084" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
646
+
<reg32 offset="0x0085" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
647
+
<reg32 offset="0x0086" name="RBBM_PERFCOUNTER0_SELECT" type="a3xx_rbbm_perfcounter_select"/>
648
+
<reg32 offset="0x0087" name="RBBM_PERFCOUNTER1_SELECT" type="a3xx_rbbm_perfcounter_select"/>
649
+
<reg32 offset="0x0088" name="RBBM_GPU_BUSY_MASKED"/>
650
+
<reg32 offset="0x0090" name="RBBM_PERFCTR_CP_0_LO"/>
651
+
<reg32 offset="0x0091" name="RBBM_PERFCTR_CP_0_HI"/>
652
+
<reg32 offset="0x0092" name="RBBM_PERFCTR_RBBM_0_LO"/>
653
+
<reg32 offset="0x0093" name="RBBM_PERFCTR_RBBM_0_HI"/>
654
+
<reg32 offset="0x0094" name="RBBM_PERFCTR_RBBM_1_LO"/>
655
+
<reg32 offset="0x0095" name="RBBM_PERFCTR_RBBM_1_HI"/>
656
+
<reg32 offset="0x0096" name="RBBM_PERFCTR_PC_0_LO"/>
657
+
<reg32 offset="0x0097" name="RBBM_PERFCTR_PC_0_HI"/>
658
+
<reg32 offset="0x0098" name="RBBM_PERFCTR_PC_1_LO"/>
659
+
<reg32 offset="0x0099" name="RBBM_PERFCTR_PC_1_HI"/>
660
+
<reg32 offset="0x009a" name="RBBM_PERFCTR_PC_2_LO"/>
661
+
<reg32 offset="0x009b" name="RBBM_PERFCTR_PC_2_HI"/>
662
+
<reg32 offset="0x009c" name="RBBM_PERFCTR_PC_3_LO"/>
663
+
<reg32 offset="0x009d" name="RBBM_PERFCTR_PC_3_HI"/>
664
+
<reg32 offset="0x009e" name="RBBM_PERFCTR_VFD_0_LO"/>
665
+
<reg32 offset="0x009f" name="RBBM_PERFCTR_VFD_0_HI"/>
666
+
<reg32 offset="0x00a0" name="RBBM_PERFCTR_VFD_1_LO"/>
667
+
<reg32 offset="0x00a1" name="RBBM_PERFCTR_VFD_1_HI"/>
668
+
<reg32 offset="0x00a2" name="RBBM_PERFCTR_HLSQ_0_LO"/>
669
+
<reg32 offset="0x00a3" name="RBBM_PERFCTR_HLSQ_0_HI"/>
670
+
<reg32 offset="0x00a4" name="RBBM_PERFCTR_HLSQ_1_LO"/>
671
+
<reg32 offset="0x00a5" name="RBBM_PERFCTR_HLSQ_1_HI"/>
672
+
<reg32 offset="0x00a6" name="RBBM_PERFCTR_HLSQ_2_LO"/>
673
+
<reg32 offset="0x00a7" name="RBBM_PERFCTR_HLSQ_2_HI"/>
674
+
<reg32 offset="0x00a8" name="RBBM_PERFCTR_HLSQ_3_LO"/>
675
+
<reg32 offset="0x00a9" name="RBBM_PERFCTR_HLSQ_3_HI"/>
676
+
<reg32 offset="0x00aa" name="RBBM_PERFCTR_HLSQ_4_LO"/>
677
+
<reg32 offset="0x00ab" name="RBBM_PERFCTR_HLSQ_4_HI"/>
678
+
<reg32 offset="0x00ac" name="RBBM_PERFCTR_HLSQ_5_LO"/>
679
+
<reg32 offset="0x00ad" name="RBBM_PERFCTR_HLSQ_5_HI"/>
680
+
<reg32 offset="0x00ae" name="RBBM_PERFCTR_VPC_0_LO"/>
681
+
<reg32 offset="0x00af" name="RBBM_PERFCTR_VPC_0_HI"/>
682
+
<reg32 offset="0x00b0" name="RBBM_PERFCTR_VPC_1_LO"/>
683
+
<reg32 offset="0x00b1" name="RBBM_PERFCTR_VPC_1_HI"/>
684
+
<reg32 offset="0x00b2" name="RBBM_PERFCTR_TSE_0_LO"/>
685
+
<reg32 offset="0x00b3" name="RBBM_PERFCTR_TSE_0_HI"/>
686
+
<reg32 offset="0x00b4" name="RBBM_PERFCTR_TSE_1_LO"/>
687
+
<reg32 offset="0x00b5" name="RBBM_PERFCTR_TSE_1_HI"/>
688
+
<reg32 offset="0x00b6" name="RBBM_PERFCTR_RAS_0_LO"/>
689
+
<reg32 offset="0x00b7" name="RBBM_PERFCTR_RAS_0_HI"/>
690
+
<reg32 offset="0x00b8" name="RBBM_PERFCTR_RAS_1_LO"/>
691
+
<reg32 offset="0x00b9" name="RBBM_PERFCTR_RAS_1_HI"/>
692
+
<reg32 offset="0x00ba" name="RBBM_PERFCTR_UCHE_0_LO"/>
693
+
<reg32 offset="0x00bb" name="RBBM_PERFCTR_UCHE_0_HI"/>
694
+
<reg32 offset="0x00bc" name="RBBM_PERFCTR_UCHE_1_LO"/>
695
+
<reg32 offset="0x00bd" name="RBBM_PERFCTR_UCHE_1_HI"/>
696
+
<reg32 offset="0x00be" name="RBBM_PERFCTR_UCHE_2_LO"/>
697
+
<reg32 offset="0x00bf" name="RBBM_PERFCTR_UCHE_2_HI"/>
698
+
<reg32 offset="0x00c0" name="RBBM_PERFCTR_UCHE_3_LO"/>
699
+
<reg32 offset="0x00c1" name="RBBM_PERFCTR_UCHE_3_HI"/>
700
+
<reg32 offset="0x00c2" name="RBBM_PERFCTR_UCHE_4_LO"/>
701
+
<reg32 offset="0x00c3" name="RBBM_PERFCTR_UCHE_4_HI"/>
702
+
<reg32 offset="0x00c4" name="RBBM_PERFCTR_UCHE_5_LO"/>
703
+
<reg32 offset="0x00c5" name="RBBM_PERFCTR_UCHE_5_HI"/>
704
+
<reg32 offset="0x00c6" name="RBBM_PERFCTR_TP_0_LO"/>
705
+
<reg32 offset="0x00c7" name="RBBM_PERFCTR_TP_0_HI"/>
706
+
<reg32 offset="0x00c8" name="RBBM_PERFCTR_TP_1_LO"/>
707
+
<reg32 offset="0x00c9" name="RBBM_PERFCTR_TP_1_HI"/>
708
+
<reg32 offset="0x00ca" name="RBBM_PERFCTR_TP_2_LO"/>
709
+
<reg32 offset="0x00cb" name="RBBM_PERFCTR_TP_2_HI"/>
710
+
<reg32 offset="0x00cc" name="RBBM_PERFCTR_TP_3_LO"/>
711
+
<reg32 offset="0x00cd" name="RBBM_PERFCTR_TP_3_HI"/>
712
+
<reg32 offset="0x00ce" name="RBBM_PERFCTR_TP_4_LO"/>
713
+
<reg32 offset="0x00cf" name="RBBM_PERFCTR_TP_4_HI"/>
714
+
<reg32 offset="0x00d0" name="RBBM_PERFCTR_TP_5_LO"/>
715
+
<reg32 offset="0x00d1" name="RBBM_PERFCTR_TP_5_HI"/>
716
+
<reg32 offset="0x00d2" name="RBBM_PERFCTR_SP_0_LO"/>
717
+
<reg32 offset="0x00d3" name="RBBM_PERFCTR_SP_0_HI"/>
718
+
<reg32 offset="0x00d4" name="RBBM_PERFCTR_SP_1_LO"/>
719
+
<reg32 offset="0x00d5" name="RBBM_PERFCTR_SP_1_HI"/>
720
+
<reg32 offset="0x00d6" name="RBBM_PERFCTR_SP_2_LO"/>
721
+
<reg32 offset="0x00d7" name="RBBM_PERFCTR_SP_2_HI"/>
722
+
<reg32 offset="0x00d8" name="RBBM_PERFCTR_SP_3_LO"/>
723
+
<reg32 offset="0x00d9" name="RBBM_PERFCTR_SP_3_HI"/>
724
+
<reg32 offset="0x00da" name="RBBM_PERFCTR_SP_4_LO"/>
725
+
<reg32 offset="0x00db" name="RBBM_PERFCTR_SP_4_HI"/>
726
+
<reg32 offset="0x00dc" name="RBBM_PERFCTR_SP_5_LO"/>
727
+
<reg32 offset="0x00dd" name="RBBM_PERFCTR_SP_5_HI"/>
728
+
<reg32 offset="0x00de" name="RBBM_PERFCTR_SP_6_LO"/>
729
+
<reg32 offset="0x00df" name="RBBM_PERFCTR_SP_6_HI"/>
730
+
<reg32 offset="0x00e0" name="RBBM_PERFCTR_SP_7_LO"/>
731
+
<reg32 offset="0x00e1" name="RBBM_PERFCTR_SP_7_HI"/>
732
+
<reg32 offset="0x00e2" name="RBBM_PERFCTR_RB_0_LO"/>
733
+
<reg32 offset="0x00e3" name="RBBM_PERFCTR_RB_0_HI"/>
734
+
<reg32 offset="0x00e4" name="RBBM_PERFCTR_RB_1_LO"/>
735
+
<reg32 offset="0x00e5" name="RBBM_PERFCTR_RB_1_HI"/>
736
+
<reg32 offset="0x00ea" name="RBBM_PERFCTR_PWR_0_LO"/>
737
+
<reg32 offset="0x00eb" name="RBBM_PERFCTR_PWR_0_HI"/>
738
+
<reg32 offset="0x00ec" name="RBBM_PERFCTR_PWR_1_LO"/>
739
+
<reg32 offset="0x00ed" name="RBBM_PERFCTR_PWR_1_HI"/>
740
+
<reg32 offset="0x0100" name="RBBM_RBBM_CTL"/>
741
+
<reg32 offset="0x0111" name="RBBM_DEBUG_BUS_CTL"/>
742
+
<reg32 offset="0x0112" name="RBBM_DEBUG_BUS_DATA_STATUS"/>
743
+
744
+
<!-- CP registers -->
745
+
<reg32 offset="0x01c9" name="CP_PFP_UCODE_ADDR"/>
746
+
<reg32 offset="0x01ca" name="CP_PFP_UCODE_DATA"/>
747
+
<reg32 offset="0x01cc" name="CP_ROQ_ADDR"/>
748
+
<reg32 offset="0x01cd" name="CP_ROQ_DATA"/>
749
+
<reg32 offset="0x01d1" name="CP_MERCIU_ADDR"/>
750
+
<reg32 offset="0x01d2" name="CP_MERCIU_DATA"/>
751
+
<reg32 offset="0x01d3" name="CP_MERCIU_DATA2"/>
752
+
<!-- see a3xx_snapshot_cp_meq().. looks like the way to dump queue between pfp and pm4 -->
753
+
<reg32 offset="0x01da" name="CP_MEQ_ADDR"/>
754
+
<reg32 offset="0x01db" name="CP_MEQ_DATA"/>
755
+
<reg32 offset="0x01f5" name="CP_WFI_PEND_CTR"/>
756
+
<reg32 offset="0x039d" name="RBBM_PM_OVERRIDE2"/>
757
+
758
+
<reg32 offset="0x0445" name="CP_PERFCOUNTER_SELECT" type="a3xx_cp_perfcounter_select"/>
759
+
<reg32 offset="0x045c" name="CP_HW_FAULT"/>
760
+
<reg32 offset="0x045e" name="CP_PROTECT_CTRL"/>
761
+
<reg32 offset="0x045f" name="CP_PROTECT_STATUS"/>
762
+
<array offset="0x0460" name="CP_PROTECT" stride="1" length="16">
763
+
<reg32 offset="0x0" name="REG"/>
764
+
</array>
765
+
<reg32 offset="0x054d" name="CP_AHB_FAULT"/>
766
+
767
+
<reg32 offset="0x0d00" name="SQ_GPR_MANAGEMENT"/>
768
+
<reg32 offset="0x0d02" name="SQ_INST_STORE_MANAGMENT"/>
769
+
<reg32 offset="0x0e1e" name="TP0_CHICKEN"/>
770
+
771
+
<!-- these I guess or either SP or HLSQ since related to shader core setup: -->
772
+
<reg32 offset="0x0e22" name="SP_GLOBAL_MEM_SIZE" type="uint">
773
+
<doc>
774
+
The pair of MEM_SIZE/ADDR registers get programmed
775
+
in sequence with the size/addr of each buffer.
776
+
</doc>
777
+
</reg32>
778
+
<reg32 offset="0x0e23" name="SP_GLOBAL_MEM_ADDR"/>
779
+
780
+
<!-- GRAS registers -->
781
+
<reg32 offset="0x2040" name="GRAS_CL_CLIP_CNTL">
782
+
<bitfield name="IJ_PERSP_CENTER" pos="12" type="boolean"/>
783
+
<bitfield name="IJ_NON_PERSP_CENTER" pos="13" type="boolean"/>
784
+
<bitfield name="IJ_PERSP_CENTROID" pos="14" type="boolean"/>
785
+
<bitfield name="IJ_NON_PERSP_CENTROID" pos="15" type="boolean"/>
786
+
<bitfield name="CLIP_DISABLE" pos="16" type="boolean"/>
787
+
<bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
788
+
<bitfield name="VP_CLIP_CODE_IGNORE" pos="19" type="boolean"/>
789
+
<bitfield name="VP_XFORM_DISABLE" pos="20" type="boolean"/>
790
+
<bitfield name="PERSP_DIVISION_DISABLE" pos="21" type="boolean"/>
791
+
<bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean">
792
+
<doc>aka clip_halfz</doc>
793
+
</bitfield>
794
+
<!-- set when gl_FragCoord.z is enabled in frag shader: -->
795
+
<bitfield name="ZCOORD" pos="23" type="boolean"/>
796
+
<bitfield name="WCOORD" pos="24" type="boolean"/>
797
+
<!-- set when frag shader writes z (so early z test disabled: -->
798
+
<bitfield name="ZCLIP_DISABLE" pos="25" type="boolean"/>
799
+
<bitfield name="NUM_USER_CLIP_PLANES" low="26" high="28" type="uint"/>
800
+
</reg32>
801
+
<reg32 offset="0x2044" name="GRAS_CL_GB_CLIP_ADJ">
802
+
<bitfield name="HORZ" low="0" high="9" type="uint"/>
803
+
<bitfield name="VERT" low="10" high="19" type="uint"/>
804
+
</reg32>
805
+
<reg32 offset="0x2048" name="GRAS_CL_VPORT_XOFFSET" type="float"/>
806
+
<reg32 offset="0x2049" name="GRAS_CL_VPORT_XSCALE" type="float"/>
807
+
<reg32 offset="0x204a" name="GRAS_CL_VPORT_YOFFSET" type="float"/>
808
+
<reg32 offset="0x204b" name="GRAS_CL_VPORT_YSCALE" type="float"/>
809
+
<reg32 offset="0x204c" name="GRAS_CL_VPORT_ZOFFSET" type="float"/>
810
+
<reg32 offset="0x204d" name="GRAS_CL_VPORT_ZSCALE" type="float"/>
811
+
<reg32 offset="0x2068" name="GRAS_SU_POINT_MINMAX">
812
+
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
813
+
<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
814
+
</reg32>
815
+
<reg32 offset="0x2069" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
816
+
<reg32 offset="0x206c" name="GRAS_SU_POLY_OFFSET_SCALE">
817
+
<bitfield name="VAL" low="0" high="23" type="fixed" radix="20"/>
818
+
<doc>range of -8.0 to 8.0</doc>
819
+
</reg32>
820
+
<reg32 offset="0x206d" name="GRAS_SU_POLY_OFFSET_OFFSET" radix="6" type="fixed">
821
+
<doc>range of -512.0 to 512.0</doc>
822
+
</reg32>
823
+
<reg32 offset="0x2070" name="GRAS_SU_MODE_CONTROL">
824
+
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
825
+
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
826
+
<bitfield name="FRONT_CW" pos="2" type="boolean"/>
827
+
<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
828
+
<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
829
+
</reg32>
830
+
<reg32 offset="0x2072" name="GRAS_SC_CONTROL">
831
+
<!-- complete wild-ass-guess for sizes of these bitfields.. -->
832
+
<bitfield name="RENDER_MODE" low="4" high="7" type="a3xx_render_mode"/>
833
+
<bitfield name="MSAA_SAMPLES" low="8" high="11" type="a3xx_msaa_samples"/>
834
+
<bitfield name="RASTER_MODE" low="12" high="15"/>
835
+
</reg32>
836
+
837
+
<reg32 offset="0x2074" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
838
+
<reg32 offset="0x2075" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
839
+
<reg32 offset="0x2079" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
840
+
<reg32 offset="0x207a" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
841
+
842
+
<!-- RB registers -->
843
+
<reg32 offset="0x20c0" name="RB_MODE_CONTROL">
844
+
<!-- guess on the # of bits here.. -->
845
+
<bitfield name="GMEM_BYPASS" pos="7" type="boolean"/>
846
+
<doc>
847
+
RENDER_MODE is RB_RESOLVE_PASS for gmem->mem, otherwise RB_RENDER_PASS
848
+
</doc>
849
+
<bitfield name="RENDER_MODE" low="8" high="10" type="a3xx_render_mode"/>
850
+
<bitfield name="MRT" low="12" high="13" type="uint">
851
+
<doc>render targets - 1</doc>
852
+
</bitfield>
853
+
<bitfield name="MARB_CACHE_SPLIT_MODE" pos="15" type="boolean"/>
854
+
<bitfield name="PACKER_TIMER_ENABLE" pos="16" type="boolean"/>
855
+
</reg32>
856
+
<reg32 offset="0x20c1" name="RB_RENDER_CONTROL">
857
+
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
858
+
<bitfield name="YUV_IN_ENABLE" pos="1" type="boolean"/>
859
+
<bitfield name="COV_VALUE_INPUT_ENABLE" pos="2" type="boolean"/>
860
+
<!-- set when gl_FrontFacing is accessed in frag shader: -->
861
+
<bitfield name="FACENESS" pos="3" type="boolean"/>
862
+
<bitfield name="BIN_WIDTH" low="4" high="11" shr="5" type="uint"/>
863
+
<bitfield name="DISABLE_COLOR_PIPE" pos="12" type="boolean"/>
864
+
<!--
865
+
ENABLE_GMEM not set on mem2gmem.. so possibly it is actually
866
+
controlling blend or readback from GMEM??
867
+
-->
868
+
<bitfield name="ENABLE_GMEM" pos="13" type="boolean"/>
869
+
<bitfield name="COORD_MASK" low="14" high="17" type="hex"/>
870
+
<bitfield name="I_CLAMP_ENABLE" pos="19" type="boolean"/>
871
+
<bitfield name="COV_VALUE_OUTPUT_ENABLE" pos="20" type="boolean"/>
872
+
<bitfield name="ALPHA_TEST" pos="22" type="boolean"/>
873
+
<bitfield name="ALPHA_TEST_FUNC" low="24" high="26" type="adreno_compare_func"/>
874
+
<bitfield name="ALPHA_TO_COVERAGE" pos="30" type="boolean"/>
875
+
<bitfield name="ALPHA_TO_ONE" pos="31" type="boolean"/>
876
+
</reg32>
877
+
<reg32 offset="0x20c2" name="RB_MSAA_CONTROL">
878
+
<bitfield name="DISABLE" pos="10" type="boolean"/>
879
+
<bitfield name="SAMPLES" low="12" high="15" type="a3xx_msaa_samples"/>
880
+
<bitfield name="SAMPLE_MASK" low="16" high="31" type="hex"/>
881
+
</reg32>
882
+
<reg32 offset="0x20c3" name="RB_ALPHA_REF">
883
+
<bitfield name="UINT" low="8" high="15" type="hex"/>
884
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
885
+
</reg32>
886
+
<array offset="0x20c4" name="RB_MRT" stride="4" length="4">
887
+
<reg32 offset="0x0" name="CONTROL">
888
+
<bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
889
+
<!-- both these bits seem to get set when enabling GL_BLEND.. -->
890
+
<bitfield name="BLEND" pos="4" type="boolean"/>
891
+
<bitfield name="BLEND2" pos="5" type="boolean"/>
892
+
<bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
893
+
<bitfield name="DITHER_MODE" low="12" high="13" type="adreno_rb_dither_mode"/>
894
+
<bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
895
+
</reg32>
896
+
<reg32 offset="0x1" name="BUF_INFO">
897
+
<bitfield name="COLOR_FORMAT" low="0" high="5" type="a3xx_color_fmt"/>
898
+
<bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a3xx_tile_mode"/>
899
+
<bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
900
+
<bitfield name="COLOR_SRGB" pos="14" type="boolean"/>
901
+
<doc>
902
+
Pitch (actually, appears to be pitch in bytes, so really is a stride)
903
+
in GMEM, so pitch of the current tile.
904
+
</doc>
905
+
<bitfield name="COLOR_BUF_PITCH" low="17" high="31" shr="5" type="uint"/>
906
+
</reg32>
907
+
<reg32 offset="0x2" name="BUF_BASE">
908
+
<doc>offset into GMEM (or system memory address in bypass mode)</doc>
909
+
<bitfield name="COLOR_BUF_BASE" low="4" high="31" shr="5" type="hex"/>
910
+
</reg32>
911
+
<reg32 offset="0x3" name="BLEND_CONTROL">
912
+
<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
913
+
<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
914
+
<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
915
+
<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
916
+
<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
917
+
<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
918
+
<bitfield name="CLAMP_ENABLE" pos="29" type="boolean"/>
919
+
</reg32>
920
+
</array>
921
+
922
+
<reg32 offset="0x20e4" name="RB_BLEND_RED">
923
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
924
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
925
+
</reg32>
926
+
<reg32 offset="0x20e5" name="RB_BLEND_GREEN">
927
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
928
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
929
+
</reg32>
930
+
<reg32 offset="0x20e6" name="RB_BLEND_BLUE">
931
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
932
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
933
+
</reg32>
934
+
<reg32 offset="0x20e7" name="RB_BLEND_ALPHA">
935
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
936
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
937
+
</reg32>
938
+
939
+
<reg32 offset="0x20e8" name="RB_CLEAR_COLOR_DW0"/>
940
+
<reg32 offset="0x20e9" name="RB_CLEAR_COLOR_DW1"/>
941
+
<reg32 offset="0x20ea" name="RB_CLEAR_COLOR_DW2"/>
942
+
<reg32 offset="0x20eb" name="RB_CLEAR_COLOR_DW3"/>
943
+
<reg32 offset="0x20ec" name="RB_COPY_CONTROL">
944
+
<!-- not sure # of bits -->
945
+
<bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
946
+
<bitfield name="DEPTHCLEAR" pos="3" type="boolean"/>
947
+
<bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
948
+
<bitfield name="MSAA_SRGB_DOWNSAMPLE" pos="7" type="boolean"/>
949
+
<bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
950
+
<bitfield name="DEPTH32_RESOLVE" pos="12" type="boolean"/> <!-- enabled on a Z32F copy -->
951
+
<bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
952
+
</reg32>
953
+
<reg32 offset="0x20ed" name="RB_COPY_DEST_BASE">
954
+
<bitfield name="BASE" low="4" high="31" shr="5" type="hex"/>
955
+
</reg32>
956
+
<reg32 offset="0x20ee" name="RB_COPY_DEST_PITCH">
957
+
<doc>actually, appears to be pitch in bytes, so really is a stride</doc>
958
+
<!-- not actually sure about max pitch... -->
959
+
<bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
960
+
</reg32>
961
+
<reg32 offset="0x20ef" name="RB_COPY_DEST_INFO">
962
+
<bitfield name="TILE" low="0" high="1" type="a3xx_tile_mode"/>
963
+
<bitfield name="FORMAT" low="2" high="7" type="a3xx_color_fmt"/>
964
+
<bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
965
+
<bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
966
+
<bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
967
+
<bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
968
+
</reg32>
969
+
<reg32 offset="0x2100" name="RB_DEPTH_CONTROL">
970
+
<!--
971
+
guessing that this matches a2xx with the stencil fields
972
+
moved out into RB_STENCIL_CONTROL?
973
+
-->
974
+
<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
975
+
<bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
976
+
<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
977
+
<bitfield name="EARLY_Z_DISABLE" pos="3" type="boolean"/>
978
+
<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
979
+
<bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
980
+
<doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
981
+
<bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
982
+
</reg32>
983
+
<reg32 offset="0x2101" name="RB_DEPTH_CLEAR">
984
+
<doc>seems to be always set to 0x00000000</doc>
985
+
</reg32>
986
+
<reg32 offset="0x2102" name="RB_DEPTH_INFO">
987
+
<bitfield name="DEPTH_FORMAT" low="0" high="1" type="adreno_rb_depth_format"/>
988
+
<doc>
989
+
DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
990
+
bin_w * bin_h / 1024 (possible rounded up to multiple of
991
+
something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
992
+
80.. so maybe it needs to be multiple of 8??
993
+
</doc>
994
+
<bitfield name="DEPTH_BASE" low="11" high="31" shr="12" type="hex"/>
995
+
</reg32>
996
+
<reg32 offset="0x2103" name="RB_DEPTH_PITCH" shr="3" type="uint">
997
+
<doc>
998
+
Pitch of depth buffer or combined depth+stencil buffer
999
+
in z24s8 cases.
1000
+
</doc>
1001
+
</reg32>
1002
+
<reg32 offset="0x2104" name="RB_STENCIL_CONTROL">
1003
+
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1004
+
<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
1005
+
<!--
1006
+
set for stencil operations that require read from stencil
1007
+
buffer, but not for example for stencil clear (which does
1008
+
not require read).. so guessing this is analogous to
1009
+
READ_DEST_ENABLE for color buffer..
1010
+
-->
1011
+
<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
1012
+
<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
1013
+
<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
1014
+
<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
1015
+
<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
1016
+
<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
1017
+
<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
1018
+
<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
1019
+
<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
1020
+
</reg32>
1021
+
<reg32 offset="0x2105" name="RB_STENCIL_CLEAR">
1022
+
<doc>seems to be always set to 0x00000000</doc>
1023
+
</reg32>
1024
+
<reg32 offset="0x2106" name="RB_STENCIL_INFO">
1025
+
<doc>Base address for stencil when not using interleaved depth/stencil</doc>
1026
+
<bitfield name="STENCIL_BASE" low="11" high="31" shr="12" type="hex"/>
1027
+
</reg32>
1028
+
<reg32 offset="0x2107" name="RB_STENCIL_PITCH" shr="3" type="uint">
1029
+
<doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
1030
+
</reg32>
1031
+
<reg32 offset="0x2108" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1032
+
<reg32 offset="0x2109" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1033
+
<!-- VSC == visibility stream c?? -->
1034
+
<reg32 offset="0x210c" name="RB_LRZ_VSC_CONTROL">
1035
+
<doc>seems to be set to 0x00000002 during binning pass</doc>
1036
+
<bitfield name="BINNING_ENABLE" pos="1" type="boolean"/>
1037
+
</reg32>
1038
+
<reg32 offset="0x210e" name="RB_WINDOW_OFFSET">
1039
+
<doc>X/Y offset of current bin</doc>
1040
+
<bitfield name="X" low="0" high="15" type="uint"/>
1041
+
<bitfield name="Y" low="16" high="31" type="uint"/>
1042
+
</reg32>
1043
+
<reg32 offset="0x2110" name="RB_SAMPLE_COUNT_CONTROL">
1044
+
<bitfield name="RESET" pos="0" type="boolean"/>
1045
+
<bitfield name="COPY" pos="1" type="boolean"/>
1046
+
</reg32>
1047
+
<reg32 offset="0x2111" name="RB_SAMPLE_COUNT_ADDR"/>
1048
+
<reg32 offset="0x2114" name="RB_Z_CLAMP_MIN"/>
1049
+
<reg32 offset="0x2115" name="RB_Z_CLAMP_MAX"/>
1050
+
1051
+
<!-- PC registers -->
1052
+
<reg32 offset="0x21e1" name="VGT_BIN_BASE">
1053
+
<doc>
1054
+
seems to be where firmware writes BIN_DATA_ADDR from
1055
+
CP_SET_BIN_DATA packet.. probably should be called
1056
+
PC_BIN_BASE (just using name from yamato for now)
1057
+
</doc>
1058
+
</reg32>
1059
+
<reg32 offset="0x21e2" name="VGT_BIN_SIZE">
1060
+
<doc>probably should be PC_BIN_SIZE</doc>
1061
+
</reg32>
1062
+
<reg32 offset="0x21e4" name="PC_VSTREAM_CONTROL">
1063
+
<doc>SIZE is current pipe width * height (in tiles)</doc>
1064
+
<bitfield name="SIZE" low="16" high="21" type="uint"/>
1065
+
<doc>
1066
+
N is some sort of slot # between 0..(SIZE-1). In case
1067
+
multiple tiles use same pipe, each tile gets unique slot #
1068
+
</doc>
1069
+
<bitfield name="N" low="22" high="26" type="uint"/>
1070
+
</reg32>
1071
+
<reg32 offset="0x21ea" name="PC_VERTEX_REUSE_BLOCK_CNTL"/>
1072
+
<reg32 offset="0x21ec" name="PC_PRIM_VTX_CNTL">
1073
+
<doc>
1074
+
STRIDE_IN_VPC: ALIGN(next_outloc - 8, 4) / 4
1075
+
(but, in cases where you'd expect 1, the blob driver uses
1076
+
2, so possibly 0 (no varying) or minimum of 2)
1077
+
</doc>
1078
+
<bitfield name="STRIDE_IN_VPC" low="0" high="4" type="uint"/>
1079
+
<bitfield name="POLYMODE_FRONT_PTYPE" low="5" high="7" type="adreno_pa_su_sc_draw"/>
1080
+
<bitfield name="POLYMODE_BACK_PTYPE" low="8" high="10" type="adreno_pa_su_sc_draw"/>
1081
+
<bitfield name="POLYMODE_ENABLE" pos="12" type="boolean"/>
1082
+
<bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
1083
+
<bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
1084
+
<!-- PSIZE bit set if gl_PointSize written: -->
1085
+
<bitfield name="PSIZE" pos="26" type="boolean"/>
1086
+
</reg32>
1087
+
<reg32 offset="0x21ed" name="PC_RESTART_INDEX"/>
1088
+
1089
+
<!-- HLSQ registers -->
1090
+
<bitset name="a3xx_hlsq_vs_fs_control_reg" inline="yes">
1091
+
<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
1092
+
<bitfield name="CONSTSTARTOFFSET" low="12" high="20" type="uint"/>
1093
+
<bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
1094
+
</bitset>
1095
+
<bitset name="a3xx_hlsq_const_vs_fs_presv_range_reg" inline="yes">
1096
+
<!-- are these a3xx_regid?? -->
1097
+
<bitfield name="STARTENTRY" low="0" high="8"/>
1098
+
<bitfield name="ENDENTRY" low="16" high="24"/>
1099
+
</bitset>
1100
+
1101
+
<reg32 offset="0x2200" name="HLSQ_CONTROL_0_REG">
1102
+
<bitfield name="FSTHREADSIZE" low="4" high="5" type="a3xx_threadsize"/>
1103
+
<bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
1104
+
<bitfield name="COMPUTEMODE" pos="8" type="boolean"/>
1105
+
<bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
1106
+
<bitfield name="RESERVED2" pos="10" type="boolean"/>
1107
+
<bitfield name="CYCLETIMEOUTLIMITVPC" low="12" high="23" type="uint"/>
1108
+
<bitfield name="FSONLYTEX" pos="25" type="boolean"/>
1109
+
<bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
1110
+
<bitfield name="CONSTMODE" pos="27" type="uint"/>
1111
+
<bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
1112
+
<bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
1113
+
<bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
1114
+
<bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
1115
+
</reg32>
1116
+
<reg32 offset="0x2201" name="HLSQ_CONTROL_1_REG">
1117
+
<bitfield name="VSTHREADSIZE" low="6" high="7" type="a3xx_threadsize"/>
1118
+
<bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
1119
+
<bitfield name="FRAGCOORDXYREGID" low="16" high="23" type="a3xx_regid"/>
1120
+
<bitfield name="FRAGCOORDZWREGID" low="24" high="31" type="a3xx_regid"/>
1121
+
</reg32>
1122
+
<reg32 offset="0x2202" name="HLSQ_CONTROL_2_REG">
1123
+
<bitfield name="FACENESSREGID" low="2" high="9" type="a3xx_regid"/>
1124
+
<bitfield name="COVVALUEREGID" low="18" high="25" type="a3xx_regid"/>
1125
+
<bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
1126
+
</reg32>
1127
+
<reg32 offset="0x2203" name="HLSQ_CONTROL_3_REG">
1128
+
<bitfield name="IJPERSPCENTERREGID" low="0" high="7" type="a3xx_regid"/>
1129
+
<bitfield name="IJNONPERSPCENTERREGID" low="8" high="15" type="a3xx_regid"/>
1130
+
<bitfield name="IJPERSPCENTROIDREGID" low="16" high="23" type="a3xx_regid"/>
1131
+
<bitfield name="IJNONPERSPCENTROIDREGID" low="24" high="31" type="a3xx_regid"/>
1132
+
</reg32>
1133
+
<reg32 offset="0x2204" name="HLSQ_VS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
1134
+
<reg32 offset="0x2205" name="HLSQ_FS_CONTROL_REG" type="a3xx_hlsq_vs_fs_control_reg"/>
1135
+
<reg32 offset="0x2206" name="HLSQ_CONST_VSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
1136
+
<reg32 offset="0x2207" name="HLSQ_CONST_FSPRESV_RANGE_REG" type="a3xx_hlsq_const_vs_fs_presv_range_reg"/>
1137
+
<reg32 offset="0x220a" name="HLSQ_CL_NDRANGE_0_REG">
1138
+
<bitfield name="WORKDIM" low="0" high="1" type="uint"/>
1139
+
<bitfield name="LOCALSIZE0" low="2" high="11" type="uint"/>
1140
+
<bitfield name="LOCALSIZE1" low="12" high="21" type="uint"/>
1141
+
<bitfield name="LOCALSIZE2" low="22" high="31" type="uint"/>
1142
+
</reg32>
1143
+
<array offset="0x220b" name="HLSQ_CL_GLOBAL_WORK" stride="2" length="3">
1144
+
<doc>indexed by dimension</doc>
1145
+
<reg32 offset="0" name="SIZE" type="uint"/>
1146
+
<reg32 offset="1" name="OFFSET" type="uint"/>
1147
+
</array>
1148
+
<reg32 offset="0x2211" name="HLSQ_CL_CONTROL_0_REG"/>
1149
+
<reg32 offset="0x2212" name="HLSQ_CL_CONTROL_1_REG"/>
1150
+
<reg32 offset="0x2214" name="HLSQ_CL_KERNEL_CONST_REG"/>
1151
+
<array offset="0x2215" name="HLSQ_CL_KERNEL_GROUP" stride="1" length="3">
1152
+
<doc>indexed by dimension, global_size / local_size</doc>
1153
+
<reg32 offset="0" name="RATIO" type="uint"/>
1154
+
</array>
1155
+
<reg32 offset="0x2216" name="HLSQ_CL_KERNEL_GROUP_Y_REG" type="uint"/>
1156
+
<reg32 offset="0x2217" name="HLSQ_CL_KERNEL_GROUP_Z_REG" type="uint"/>
1157
+
<reg32 offset="0x221a" name="HLSQ_CL_WG_OFFSET_REG"/>
1158
+
1159
+
<!-- VFD registers -->
1160
+
<reg32 offset="0x2240" name="VFD_CONTROL_0">
1161
+
<doc>
1162
+
TOTALATTRTOVS is # of attributes to vertex shader, in register
1163
+
slots (ie. vec4+vec3 -> 7)
1164
+
</doc>
1165
+
<bitfield name="TOTALATTRTOVS" low="0" high="17" type="uint"/>
1166
+
<bitfield name="PACKETSIZE" low="18" high="21" type="uint"/>
1167
+
<doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
1168
+
<bitfield name="STRMDECINSTRCNT" low="22" high="26" type="uint"/>
1169
+
<doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
1170
+
<bitfield name="STRMFETCHINSTRCNT" low="27" high="31" type="uint"/>
1171
+
</reg32>
1172
+
<reg32 offset="0x2241" name="VFD_CONTROL_1">
1173
+
<doc>MAXSTORAGE could be # of attributes/vbo's</doc>
1174
+
<bitfield name="MAXSTORAGE" low="0" high="3" type="uint"/>
1175
+
<bitfield name="MAXTHRESHOLD" low="4" high="7" type="uint"/>
1176
+
<bitfield name="MINTHRESHOLD" low="8" high="11" type="uint"/>
1177
+
<bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
1178
+
<bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
1179
+
</reg32>
1180
+
<reg32 offset="0x2242" name="VFD_INDEX_MIN" type="uint"/>
1181
+
<reg32 offset="0x2243" name="VFD_INDEX_MAX" type="uint"/>
1182
+
<reg32 offset="0x2244" name="VFD_INSTANCEID_OFFSET" type="uint"/>
1183
+
<reg32 offset="0x2245" name="VFD_INDEX_OFFSET" type="uint"/>
1184
+
<array offset="0x2246" name="VFD_FETCH" stride="2" length="16">
1185
+
<reg32 offset="0x0" name="INSTR_0">
1186
+
<bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
1187
+
<bitfield name="BUFSTRIDE" low="7" high="15" type="uint"/>
1188
+
<bitfield name="INSTANCED" pos="16" type="boolean"/>
1189
+
<bitfield name="SWITCHNEXT" pos="17" type="boolean"/>
1190
+
<bitfield name="INDEXCODE" low="18" high="23" type="uint"/>
1191
+
<bitfield name="STEPRATE" low="24" high="31" type="uint"/>
1192
+
</reg32>
1193
+
<reg32 offset="0x1" name="INSTR_1"/>
1194
+
</array>
1195
+
<array offset="0x2266" name="VFD_DECODE" stride="1" length="16">
1196
+
<reg32 offset="0x0" name="INSTR">
1197
+
<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
1198
+
<!-- not sure if this is a bit flag and another flag above it, or?? -->
1199
+
<bitfield name="CONSTFILL" pos="4" type="boolean"/>
1200
+
<bitfield name="FORMAT" low="6" high="11" type="a3xx_vtx_fmt"/>
1201
+
<bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
1202
+
<bitfield name="INT" pos="20" type="boolean"/>
1203
+
<doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
1204
+
<bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
1205
+
<bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
1206
+
<bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
1207
+
<bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
1208
+
</reg32>
1209
+
</array>
1210
+
<reg32 offset="0x227e" name="VFD_VS_THREADING_THRESHOLD">
1211
+
<bitfield name="REGID_THRESHOLD" low="0" high="3" type="uint"/>
1212
+
<!-- <bitfield name="RESERVED6" low="4" high="7" type="uint"/> -->
1213
+
<bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
1214
+
</reg32>
1215
+
1216
+
<!-- VPC registers -->
1217
+
<reg32 offset="0x2280" name="VPC_ATTR">
1218
+
<bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
1219
+
<!-- PSIZE bit set if gl_PointSize written: -->
1220
+
<bitfield name="PSIZE" pos="9" type="boolean"/>
1221
+
<bitfield name="THRDASSIGN" low="12" high="27" type="uint"/>
1222
+
<bitfield name="LMSIZE" low="28" high="31" type="uint"/>
1223
+
</reg32>
1224
+
<reg32 offset="0x2281" name="VPC_PACK">
1225
+
<!-- these are always seem to be set to same as TOTALATTR -->
1226
+
<bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
1227
+
<bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
1228
+
</reg32>
1229
+
<!--
1230
+
varying interpolate mode. One field per scalar/component
1231
+
(since varying slots are scalar, so things don't have to
1232
+
be aligned to vec4).
1233
+
4 regs * 16 scalar components each => 16 vec4
1234
+
-->
1235
+
<array offset="0x2282" name="VPC_VARYING_INTERP" stride="1" length="4">
1236
+
<reg32 offset="0x0" name="MODE">
1237
+
<bitfield name="C0" low="0" high="1" type="a3xx_intp_mode"/>
1238
+
<bitfield name="C1" low="2" high="3" type="a3xx_intp_mode"/>
1239
+
<bitfield name="C2" low="4" high="5" type="a3xx_intp_mode"/>
1240
+
<bitfield name="C3" low="6" high="7" type="a3xx_intp_mode"/>
1241
+
<bitfield name="C4" low="8" high="9" type="a3xx_intp_mode"/>
1242
+
<bitfield name="C5" low="10" high="11" type="a3xx_intp_mode"/>
1243
+
<bitfield name="C6" low="12" high="13" type="a3xx_intp_mode"/>
1244
+
<bitfield name="C7" low="14" high="15" type="a3xx_intp_mode"/>
1245
+
<bitfield name="C8" low="16" high="17" type="a3xx_intp_mode"/>
1246
+
<bitfield name="C9" low="18" high="19" type="a3xx_intp_mode"/>
1247
+
<bitfield name="CA" low="20" high="21" type="a3xx_intp_mode"/>
1248
+
<bitfield name="CB" low="22" high="23" type="a3xx_intp_mode"/>
1249
+
<bitfield name="CC" low="24" high="25" type="a3xx_intp_mode"/>
1250
+
<bitfield name="CD" low="26" high="27" type="a3xx_intp_mode"/>
1251
+
<bitfield name="CE" low="28" high="29" type="a3xx_intp_mode"/>
1252
+
<bitfield name="CF" low="30" high="31" type="a3xx_intp_mode"/>
1253
+
</reg32>
1254
+
</array>
1255
+
<array offset="0x2286" name="VPC_VARYING_PS_REPL" stride="1" length="4">
1256
+
<reg32 offset="0x0" name="MODE">
1257
+
<bitfield name="C0" low="0" high="1" type="a3xx_repl_mode"/>
1258
+
<bitfield name="C1" low="2" high="3" type="a3xx_repl_mode"/>
1259
+
<bitfield name="C2" low="4" high="5" type="a3xx_repl_mode"/>
1260
+
<bitfield name="C3" low="6" high="7" type="a3xx_repl_mode"/>
1261
+
<bitfield name="C4" low="8" high="9" type="a3xx_repl_mode"/>
1262
+
<bitfield name="C5" low="10" high="11" type="a3xx_repl_mode"/>
1263
+
<bitfield name="C6" low="12" high="13" type="a3xx_repl_mode"/>
1264
+
<bitfield name="C7" low="14" high="15" type="a3xx_repl_mode"/>
1265
+
<bitfield name="C8" low="16" high="17" type="a3xx_repl_mode"/>
1266
+
<bitfield name="C9" low="18" high="19" type="a3xx_repl_mode"/>
1267
+
<bitfield name="CA" low="20" high="21" type="a3xx_repl_mode"/>
1268
+
<bitfield name="CB" low="22" high="23" type="a3xx_repl_mode"/>
1269
+
<bitfield name="CC" low="24" high="25" type="a3xx_repl_mode"/>
1270
+
<bitfield name="CD" low="26" high="27" type="a3xx_repl_mode"/>
1271
+
<bitfield name="CE" low="28" high="29" type="a3xx_repl_mode"/>
1272
+
<bitfield name="CF" low="30" high="31" type="a3xx_repl_mode"/>
1273
+
</reg32>
1274
+
</array>
1275
+
<reg32 offset="0x228a" name="VPC_VARY_CYLWRAP_ENABLE_0"/>
1276
+
<reg32 offset="0x228b" name="VPC_VARY_CYLWRAP_ENABLE_1"/>
1277
+
1278
+
<!-- SP registers -->
1279
+
<bitset name="a3xx_vs_fs_length_reg" inline="yes">
1280
+
<bitfield name="SHADERLENGTH" low="0" high="31" type="uint"/>
1281
+
</bitset>
1282
+
1283
+
<bitset name="sp_vs_fs_obj_offset_reg" inline="yes">
1284
+
<bitfield name="FIRSTEXECINSTROFFSET" low="0" high="15" type="uint"/>
1285
+
<doc>
1286
+
From register spec:
1287
+
SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
1288
+
start offset in on chip RAM,
1289
+
128bit aligned
1290
+
</doc>
1291
+
<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1292
+
<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1293
+
</bitset>
1294
+
1295
+
<reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
1296
+
<!-- this bit is set during resolve pass: -->
1297
+
<bitfield name="RESOLVE" pos="16" type="boolean"/>
1298
+
<bitfield name="CONSTMODE" pos="18" type="uint"/>
1299
+
<bitfield name="BINNING" pos="19" type="boolean"/>
1300
+
<bitfield name="SLEEPMODE" low="20" high="21" type="uint"/>
1301
+
<!-- L0MODE==1 when oxiliForceSpL0ModeBuffer=1 -->
1302
+
<bitfield name="L0MODE" low="22" high="23" type="uint"/>
1303
+
</reg32>
1304
+
<reg32 offset="0x22c4" name="SP_VS_CTRL_REG0">
1305
+
<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1306
+
<bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
1307
+
<!-- maybe CACHEINVALID is two bits?? -->
1308
+
<bitfield name="CACHEINVALID" pos="2" type="boolean"/>
1309
+
<bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
1310
+
<doc>
1311
+
The full/half register footprint is in units of four components,
1312
+
so if r0.x is used, that counts as all of r0.[xyzw] as used.
1313
+
There are separate full/half register footprint values as the
1314
+
full and half registers are independent (not overlapping).
1315
+
Presumably the thread scheduler hardware allocates the full/half
1316
+
register names from the actual physical register file and
1317
+
handles the register renaming.
1318
+
</doc>
1319
+
<bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
1320
+
<bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
1321
+
<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
1322
+
<bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
1323
+
<doc>
1324
+
From regspec:
1325
+
SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
1326
+
If bit31 is 1, it means overflow
1327
+
or any long shader.
1328
+
</doc>
1329
+
<bitfield name="LENGTH" low="24" high="31" type="uint"/>
1330
+
</reg32>
1331
+
<reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
1332
+
<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
1333
+
<!--
1334
+
not sure about full vs half const.. I can't get blob generate
1335
+
something with a mediump/lowp uniform.
1336
+
-->
1337
+
<bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
1338
+
<bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
1339
+
</reg32>
1340
+
<reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
1341
+
<bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1342
+
<bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
1343
+
<bitfield name="POS2DMODE" pos="16" type="boolean"/>
1344
+
<bitfield name="TOTALVSOUTVAR" low="20" high="24" type="uint"/>
1345
+
</reg32>
1346
+
<array offset="0x22c7" name="SP_VS_OUT" stride="1" length="8">
1347
+
<reg32 offset="0x0" name="REG">
1348
+
<bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
1349
+
<bitfield name="A_HALF" pos="8" type="boolean"/>
1350
+
<bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1351
+
<bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
1352
+
<bitfield name="B_HALF" pos="24" type="boolean"/>
1353
+
<bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1354
+
</reg32>
1355
+
</array>
1356
+
<array offset="0x22d0" name="SP_VS_VPC_DST" stride="1" length="4">
1357
+
<reg32 offset="0x0" name="REG">
1358
+
<doc>
1359
+
These seem to be offsets for storage of the varyings.
1360
+
Always seems to start from 8, possibly loc 0 and 4
1361
+
are for gl_Position and gl_PointSize?
1362
+
</doc>
1363
+
<bitfield name="OUTLOC0" low="0" high="6" type="uint"/>
1364
+
<bitfield name="OUTLOC1" low="8" high="14" type="uint"/>
1365
+
<bitfield name="OUTLOC2" low="16" high="22" type="uint"/>
1366
+
<bitfield name="OUTLOC3" low="24" high="30" type="uint"/>
1367
+
</reg32>
1368
+
</array>
1369
+
<reg32 offset="0x22d4" name="SP_VS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
1370
+
<doc>
1371
+
SP_VS_OBJ_START_REG contains pointer to the vertex shader program,
1372
+
immediately followed by the binning shader program (although I
1373
+
guess that is probably just re-using the same gpu buffer)
1374
+
</doc>
1375
+
<reg32 offset="0x22d5" name="SP_VS_OBJ_START_REG"/>
1376
+
<reg32 offset="0x22d6" name="SP_VS_PVT_MEM_PARAM_REG">
1377
+
<bitfield name="MEMSIZEPERITEM" low="0" high="7" shr="7">
1378
+
<doc>The size of memory that ldp/stp can address, in 128 byte increments.</doc>
1379
+
</bitfield>
1380
+
<bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
1381
+
<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
1382
+
</reg32>
1383
+
<reg32 offset="0x22d7" name="SP_VS_PVT_MEM_ADDR_REG">
1384
+
<bitfield name="BURSTLEN" low="0" high="4"/>
1385
+
<bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
1386
+
</reg32>
1387
+
<reg32 offset="0x22d8" name="SP_VS_PVT_MEM_SIZE_REG"/>
1388
+
<reg32 offset="0x22df" name="SP_VS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
1389
+
<reg32 offset="0x22e0" name="SP_FS_CTRL_REG0">
1390
+
<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1391
+
<bitfield name="INSTRBUFFERMODE" pos="1" type="a3xx_instrbuffermode"/>
1392
+
<!-- maybe CACHEINVALID is two bits?? -->
1393
+
<bitfield name="CACHEINVALID" pos="2" type="boolean"/>
1394
+
<bitfield name="ALUSCHMODE" pos="3" type="boolean"/>
1395
+
<doc>
1396
+
The full/half register footprint is in units of four components,
1397
+
so if r0.x is used, that counts as all of r0.[xyzw] as used.
1398
+
There are separate full/half register footprint values as the
1399
+
full and half registers are independent (not overlapping).
1400
+
Presumably the thread scheduler hardware allocates the full/half
1401
+
register names from the actual physical register file and
1402
+
handles the register renaming.
1403
+
</doc>
1404
+
<bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
1405
+
<bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
1406
+
<bitfield name="FSBYPASSENABLE" pos="17" type="boolean"/>
1407
+
<bitfield name="INOUTREGOVERLAP" pos="18" type="boolean"/>
1408
+
<bitfield name="OUTORDERED" pos="19" type="boolean"/>
1409
+
<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
1410
+
<bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
1411
+
<bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
1412
+
<bitfield name="COMPUTEMODE" pos="23" type="boolean"/>
1413
+
<doc>
1414
+
From regspec:
1415
+
SP_FS_CTRL_REG0.FS_LENGTH [31:24]: FS length, unit = 256bits.
1416
+
If bit31 is 1, it means overflow
1417
+
or any long shader.
1418
+
</doc>
1419
+
<bitfield name="LENGTH" low="24" high="31" type="uint"/>
1420
+
</reg32>
1421
+
<reg32 offset="0x22e1" name="SP_FS_CTRL_REG1">
1422
+
<bitfield name="CONSTLENGTH" low="0" high="9" type="uint"/>
1423
+
<bitfield name="CONSTFOOTPRINT" low="10" high="19" type="uint"/>
1424
+
<bitfield name="INITIALOUTSTANDING" low="20" high="23" type="uint"/>
1425
+
<bitfield name="HALFPRECVAROFFSET" low="24" high="30" type="uint"/>
1426
+
</reg32>
1427
+
<reg32 offset="0x22e2" name="SP_FS_OBJ_OFFSET_REG" type="sp_vs_fs_obj_offset_reg"/>
1428
+
<doc>SP_FS_OBJ_START_REG contains pointer to fragment shader program</doc>
1429
+
<reg32 offset="0x22e3" name="SP_FS_OBJ_START_REG"/>
1430
+
<reg32 offset="0x22e4" name="SP_FS_PVT_MEM_PARAM_REG">
1431
+
<bitfield name="MEMSIZEPERITEM" low="0" high="7" type="uint"/>
1432
+
<bitfield name="HWSTACKOFFSET" low="8" high="23" type="uint"/>
1433
+
<bitfield name="HWSTACKSIZEPERTHREAD" low="24" high="31" type="uint"/>
1434
+
</reg32>
1435
+
<reg32 offset="0x22e5" name="SP_FS_PVT_MEM_ADDR_REG">
1436
+
<bitfield name="BURSTLEN" low="0" high="4"/>
1437
+
<bitfield name="SHADERSTARTADDRESS" shr="5" low="5" high="31"/>
1438
+
</reg32>
1439
+
<reg32 offset="0x22e6" name="SP_FS_PVT_MEM_SIZE_REG"/>
1440
+
<reg32 offset="0x22e8" name="SP_FS_FLAT_SHAD_MODE_REG_0">
1441
+
<doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
1442
+
</reg32>
1443
+
<reg32 offset="0x22e9" name="SP_FS_FLAT_SHAD_MODE_REG_1">
1444
+
<doc>seems to be one bit per scalar, '1' for flat, '0' for smooth</doc>
1445
+
</reg32>
1446
+
<reg32 offset="0x22ec" name="SP_FS_OUTPUT_REG">
1447
+
<bitfield name="MRT" low="0" high="1" type="uint">
1448
+
<doc>render targets - 1</doc>
1449
+
</bitfield>
1450
+
<bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
1451
+
<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
1452
+
</reg32>
1453
+
<array offset="0x22f0" name="SP_FS_MRT" stride="1" length="4">
1454
+
<reg32 offset="0x0" name="REG">
1455
+
<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
1456
+
<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
1457
+
<bitfield name="SINT" pos="10" type="boolean"/>
1458
+
<bitfield name="UINT" pos="11" type="boolean"/>
1459
+
</reg32>
1460
+
</array>
1461
+
<array offset="0x22f4" name="SP_FS_IMAGE_OUTPUT" stride="1" length="4">
1462
+
<reg32 offset="0x0" name="REG">
1463
+
<bitfield name="MRTFORMAT" low="0" high="5" type="a3xx_color_fmt"/>
1464
+
</reg32>
1465
+
</array>
1466
+
<reg32 offset="0x22ff" name="SP_FS_LENGTH_REG" type="a3xx_vs_fs_length_reg"/>
1467
+
1468
+
<reg32 offset="0x2301" name="PA_SC_AA_CONFIG"/>
1469
+
<!-- TPL1 registers -->
1470
+
<!-- assume VS/FS_TEX_OFFSET is same -->
1471
+
<bitset name="a3xx_tpl1_tp_vs_fs_tex_offset" inline="yes">
1472
+
<bitfield name="SAMPLEROFFSET" low="0" high="7" type="uint"/>
1473
+
<bitfield name="MEMOBJOFFSET" low="8" high="15" type="uint"/>
1474
+
<!-- not sure the size of this: -->
1475
+
<bitfield name="BASETABLEPTR" low="16" high="31" type="uint"/>
1476
+
</bitset>
1477
+
<reg32 offset="0x2340" name="TPL1_TP_VS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
1478
+
<reg32 offset="0x2341" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
1479
+
<reg32 offset="0x2342" name="TPL1_TP_FS_TEX_OFFSET" type="a3xx_tpl1_tp_vs_fs_tex_offset"/>
1480
+
<reg32 offset="0x2343" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
1481
+
1482
+
<!-- VBIF registers -->
1483
+
<reg32 offset="0x3001" name="VBIF_CLKON"/>
1484
+
<reg32 offset="0x300c" name="VBIF_FIXED_SORT_EN"/>
1485
+
<reg32 offset="0x300d" name="VBIF_FIXED_SORT_SEL0"/>
1486
+
<reg32 offset="0x300e" name="VBIF_FIXED_SORT_SEL1"/>
1487
+
<reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
1488
+
<reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
1489
+
<reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
1490
+
<reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
1491
+
<reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
1492
+
<reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
1493
+
<reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
1494
+
<reg32 offset="0x3034" name="VBIF_OUT_RD_LIM_CONF0"/>
1495
+
<reg32 offset="0x3035" name="VBIF_OUT_WR_LIM_CONF0"/>
1496
+
<reg32 offset="0x3036" name="VBIF_DDR_OUT_MAX_BURST"/>
1497
+
<reg32 offset="0x303c" name="VBIF_ARB_CTL"/>
1498
+
<reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
1499
+
<reg32 offset="0x3058" name="VBIF_OUT_AXI_AMEMTYPE_CONF0"/>
1500
+
<reg32 offset="0x305e" name="VBIF_OUT_AXI_AOOO_EN"/>
1501
+
<reg32 offset="0x305f" name="VBIF_OUT_AXI_AOOO"/>
1502
+
1503
+
<bitset name="a3xx_vbif_perf_cnt" inline="yes">
1504
+
<bitfield name="CNT0" pos="0" type="boolean"/>
1505
+
<bitfield name="CNT1" pos="1" type="boolean"/>
1506
+
<bitfield name="PWRCNT0" pos="2" type="boolean"/>
1507
+
<bitfield name="PWRCNT1" pos="3" type="boolean"/>
1508
+
<bitfield name="PWRCNT2" pos="4" type="boolean"/>
1509
+
</bitset>
1510
+
1511
+
<reg32 offset="0x3070" name="VBIF_PERF_CNT_EN" type="a3xx_vbif_perf_cnt"/>
1512
+
<reg32 offset="0x3071" name="VBIF_PERF_CNT_CLR" type="a3xx_vbif_perf_cnt"/>
1513
+
<reg32 offset="0x3072" name="VBIF_PERF_CNT_SEL"/>
1514
+
<reg32 offset="0x3073" name="VBIF_PERF_CNT0_LO"/>
1515
+
<reg32 offset="0x3074" name="VBIF_PERF_CNT0_HI"/>
1516
+
<reg32 offset="0x3075" name="VBIF_PERF_CNT1_LO"/>
1517
+
<reg32 offset="0x3076" name="VBIF_PERF_CNT1_HI"/>
1518
+
<reg32 offset="0x3077" name="VBIF_PERF_PWR_CNT0_LO"/>
1519
+
<reg32 offset="0x3078" name="VBIF_PERF_PWR_CNT0_HI"/>
1520
+
<reg32 offset="0x3079" name="VBIF_PERF_PWR_CNT1_LO"/>
1521
+
<reg32 offset="0x307a" name="VBIF_PERF_PWR_CNT1_HI"/>
1522
+
<reg32 offset="0x307b" name="VBIF_PERF_PWR_CNT2_LO"/>
1523
+
<reg32 offset="0x307c" name="VBIF_PERF_PWR_CNT2_HI"/>
1524
+
1525
+
1526
+
<reg32 offset="0x0c01" name="VSC_BIN_SIZE">
1527
+
<bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1528
+
<bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
1529
+
</reg32>
1530
+
1531
+
<reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS"/>
1532
+
<array offset="0x0c06" name="VSC_PIPE" stride="3" length="8">
1533
+
<reg32 offset="0x0" name="CONFIG">
1534
+
<doc>
1535
+
Configures the mapping between VSC_PIPE buffer and
1536
+
bin, X/Y specify the bin index in the horiz/vert
1537
+
direction (0,0 is upper left, 0,1 is leftmost bin
1538
+
on second row, and so on). W/H specify the number
1539
+
of bins assigned to this VSC_PIPE in the horiz/vert
1540
+
dimension.
1541
+
</doc>
1542
+
<bitfield name="X" low="0" high="9" type="uint"/>
1543
+
<bitfield name="Y" low="10" high="19" type="uint"/>
1544
+
<bitfield name="W" low="20" high="23" type="uint"/>
1545
+
<bitfield name="H" low="24" high="27" type="uint"/>
1546
+
</reg32>
1547
+
<reg32 offset="0x1" name="DATA_ADDRESS"/>
1548
+
<reg32 offset="0x2" name="DATA_LENGTH"/>
1549
+
</array>
1550
+
<reg32 offset="0x0c3c" name="VSC_BIN_CONTROL">
1551
+
<doc>seems to be set to 0x00000001 during binning pass</doc>
1552
+
<bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
1553
+
</reg32>
1554
+
<reg32 offset="0x0c3d" name="UNKNOWN_0C3D">
1555
+
<doc>seems to be always set to 0x00000001</doc>
1556
+
</reg32>
1557
+
<reg32 offset="0x0c48" name="PC_PERFCOUNTER0_SELECT" type="a3xx_pc_perfcounter_select"/>
1558
+
<reg32 offset="0x0c49" name="PC_PERFCOUNTER1_SELECT" type="a3xx_pc_perfcounter_select"/>
1559
+
<reg32 offset="0x0c4a" name="PC_PERFCOUNTER2_SELECT" type="a3xx_pc_perfcounter_select"/>
1560
+
<reg32 offset="0x0c4b" name="PC_PERFCOUNTER3_SELECT" type="a3xx_pc_perfcounter_select"/>
1561
+
<reg32 offset="0x0c81" name="GRAS_TSE_DEBUG_ECO">
1562
+
<doc>seems to be always set to 0x00000001</doc>
1563
+
</reg32>
1564
+
1565
+
<reg32 offset="0x0c88" name="GRAS_PERFCOUNTER0_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
1566
+
<reg32 offset="0x0c89" name="GRAS_PERFCOUNTER1_SELECT" type="a3xx_gras_tse_perfcounter_select"/>
1567
+
<reg32 offset="0x0c8a" name="GRAS_PERFCOUNTER2_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
1568
+
<reg32 offset="0x0c8b" name="GRAS_PERFCOUNTER3_SELECT" type="a3xx_gras_ras_perfcounter_select"/>
1569
+
<array offset="0x0ca0" name="GRAS_CL_USER_PLANE" stride="4" length="6">
1570
+
<reg32 offset="0x0" name="X"/>
1571
+
<reg32 offset="0x1" name="Y"/>
1572
+
<reg32 offset="0x2" name="Z"/>
1573
+
<reg32 offset="0x3" name="W"/>
1574
+
</array>
1575
+
<reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
1576
+
<reg32 offset="0x0cc1" name="RB_DEBUG_ECO_CONTROLS_ADDR"/>
1577
+
<reg32 offset="0x0cc6" name="RB_PERFCOUNTER0_SELECT" type="a3xx_rb_perfcounter_select"/>
1578
+
<reg32 offset="0x0cc7" name="RB_PERFCOUNTER1_SELECT" type="a3xx_rb_perfcounter_select"/>
1579
+
<reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
1580
+
<bitfield name="WIDTH" low="0" high="13" type="uint"/>
1581
+
<bitfield name="HEIGHT" low="14" high="27" type="uint"/>
1582
+
</reg32>
1583
+
<reg32 offset="0x0e00" name="HLSQ_PERFCOUNTER0_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1584
+
<reg32 offset="0x0e01" name="HLSQ_PERFCOUNTER1_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1585
+
<reg32 offset="0x0e02" name="HLSQ_PERFCOUNTER2_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1586
+
<reg32 offset="0x0e03" name="HLSQ_PERFCOUNTER3_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1587
+
<reg32 offset="0x0e04" name="HLSQ_PERFCOUNTER4_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1588
+
<reg32 offset="0x0e05" name="HLSQ_PERFCOUNTER5_SELECT" type="a3xx_hlsq_perfcounter_select"/>
1589
+
<reg32 offset="0x0e43" name="UNKNOWN_0E43">
1590
+
<doc>seems to be always set to 0x00000001</doc>
1591
+
</reg32>
1592
+
<reg32 offset="0x0e44" name="VFD_PERFCOUNTER0_SELECT" type="a3xx_vfd_perfcounter_select"/>
1593
+
<reg32 offset="0x0e45" name="VFD_PERFCOUNTER1_SELECT" type="a3xx_vfd_perfcounter_select"/>
1594
+
<reg32 offset="0x0e61" name="VPC_VPC_DEBUG_RAM_SEL"/>
1595
+
<reg32 offset="0x0e62" name="VPC_VPC_DEBUG_RAM_READ"/>
1596
+
<reg32 offset="0x0e64" name="VPC_PERFCOUNTER0_SELECT" type="a3xx_vpc_perfcounter_select"/>
1597
+
<reg32 offset="0x0e65" name="VPC_PERFCOUNTER1_SELECT" type="a3xx_vpc_perfcounter_select"/>
1598
+
<reg32 offset="0x0e82" name="UCHE_CACHE_MODE_CONTROL_REG"/>
1599
+
<reg32 offset="0x0e84" name="UCHE_PERFCOUNTER0_SELECT" type="a3xx_uche_perfcounter_select"/>
1600
+
<reg32 offset="0x0e85" name="UCHE_PERFCOUNTER1_SELECT" type="a3xx_uche_perfcounter_select"/>
1601
+
<reg32 offset="0x0e86" name="UCHE_PERFCOUNTER2_SELECT" type="a3xx_uche_perfcounter_select"/>
1602
+
<reg32 offset="0x0e87" name="UCHE_PERFCOUNTER3_SELECT" type="a3xx_uche_perfcounter_select"/>
1603
+
<reg32 offset="0x0e88" name="UCHE_PERFCOUNTER4_SELECT" type="a3xx_uche_perfcounter_select"/>
1604
+
<reg32 offset="0x0e89" name="UCHE_PERFCOUNTER5_SELECT" type="a3xx_uche_perfcounter_select"/>
1605
+
<reg32 offset="0x0ea0" name="UCHE_CACHE_INVALIDATE0_REG">
1606
+
<!-- might be shifted right by 5, assuming 32byte cache line size.. -->
1607
+
<bitfield name="ADDR" low="0" high="27" type="hex"/>
1608
+
</reg32>
1609
+
<reg32 offset="0x0ea1" name="UCHE_CACHE_INVALIDATE1_REG">
1610
+
<!-- might be shifted right by 5, assuming 32byte cache line size.. -->
1611
+
<bitfield name="ADDR" low="0" high="27" type="hex"/>
1612
+
<!-- I'd assume 2 bits, for FLUSH/INVALIDATE/CLEAN? -->
1613
+
<bitfield name="OPCODE" low="28" high="29" type="a3xx_cache_opcode"/>
1614
+
<bitfield name="ENTIRE_CACHE" pos="31" type="boolean"/>
1615
+
</reg32>
1616
+
<reg32 offset="0x0ea6" name="UNKNOWN_0EA6"/>
1617
+
<reg32 offset="0x0ec4" name="SP_PERFCOUNTER0_SELECT" type="a3xx_sp_perfcounter_select"/>
1618
+
<reg32 offset="0x0ec5" name="SP_PERFCOUNTER1_SELECT" type="a3xx_sp_perfcounter_select"/>
1619
+
<reg32 offset="0x0ec6" name="SP_PERFCOUNTER2_SELECT" type="a3xx_sp_perfcounter_select"/>
1620
+
<reg32 offset="0x0ec7" name="SP_PERFCOUNTER3_SELECT" type="a3xx_sp_perfcounter_select"/>
1621
+
<reg32 offset="0x0ec8" name="SP_PERFCOUNTER4_SELECT" type="a3xx_sp_perfcounter_select"/>
1622
+
<reg32 offset="0x0ec9" name="SP_PERFCOUNTER5_SELECT" type="a3xx_sp_perfcounter_select"/>
1623
+
<reg32 offset="0x0eca" name="SP_PERFCOUNTER6_SELECT" type="a3xx_sp_perfcounter_select"/>
1624
+
<reg32 offset="0x0ecb" name="SP_PERFCOUNTER7_SELECT" type="a3xx_sp_perfcounter_select"/>
1625
+
<reg32 offset="0x0ee0" name="UNKNOWN_0EE0">
1626
+
<doc>seems to be always set to 0x00000003</doc>
1627
+
</reg32>
1628
+
<reg32 offset="0x0f03" name="UNKNOWN_0F03">
1629
+
<doc>seems to be always set to 0x00000001</doc>
1630
+
</reg32>
1631
+
<reg32 offset="0x0f04" name="TP_PERFCOUNTER0_SELECT" type="a3xx_tp_perfcounter_select"/>
1632
+
<reg32 offset="0x0f05" name="TP_PERFCOUNTER1_SELECT" type="a3xx_tp_perfcounter_select"/>
1633
+
<reg32 offset="0x0f06" name="TP_PERFCOUNTER2_SELECT" type="a3xx_tp_perfcounter_select"/>
1634
+
<reg32 offset="0x0f07" name="TP_PERFCOUNTER3_SELECT" type="a3xx_tp_perfcounter_select"/>
1635
+
<reg32 offset="0x0f08" name="TP_PERFCOUNTER4_SELECT" type="a3xx_tp_perfcounter_select"/>
1636
+
<reg32 offset="0x0f09" name="TP_PERFCOUNTER5_SELECT" type="a3xx_tp_perfcounter_select"/>
1637
+
1638
+
<!-- this seems to be the register that CP_RUN_OPENCL writes: -->
1639
+
<reg32 offset="0x21f0" name="VGT_CL_INITIATOR"/>
1640
+
1641
+
<!-- seems to be same as a2xx according to fwdump.. -->
1642
+
<reg32 offset="0x21f9" name="VGT_EVENT_INITIATOR"/>
1643
+
<reg32 offset="0x21fc" name="VGT_DRAW_INITIATOR" type="vgt_draw_initiator"/>
1644
+
<reg32 offset="0x21fd" name="VGT_IMMED_DATA"/>
1645
+
</domain>
1646
+
1647
+
<domain name="A3XX_TEX_SAMP" width="32">
1648
+
<doc>Texture sampler dwords</doc>
1649
+
<enum name="a3xx_tex_filter">
1650
+
<value name="A3XX_TEX_NEAREST" value="0"/>
1651
+
<value name="A3XX_TEX_LINEAR" value="1"/>
1652
+
<value name="A3XX_TEX_ANISO" value="2"/>
1653
+
</enum>
1654
+
<enum name="a3xx_tex_clamp">
1655
+
<value name="A3XX_TEX_REPEAT" value="0"/>
1656
+
<value name="A3XX_TEX_CLAMP_TO_EDGE" value="1"/>
1657
+
<value name="A3XX_TEX_MIRROR_REPEAT" value="2"/>
1658
+
<value name="A3XX_TEX_CLAMP_TO_BORDER" value="3"/>
1659
+
<value name="A3XX_TEX_MIRROR_CLAMP" value="4"/>
1660
+
</enum>
1661
+
<enum name="a3xx_tex_aniso">
1662
+
<value name="A3XX_TEX_ANISO_1" value="0"/>
1663
+
<value name="A3XX_TEX_ANISO_2" value="1"/>
1664
+
<value name="A3XX_TEX_ANISO_4" value="2"/>
1665
+
<value name="A3XX_TEX_ANISO_8" value="3"/>
1666
+
<value name="A3XX_TEX_ANISO_16" value="4"/>
1667
+
</enum>
1668
+
<reg32 offset="0" name="0">
1669
+
<bitfield name="CLAMPENABLE" pos="0" type="boolean"/>
1670
+
<bitfield name="MIPFILTER_LINEAR" pos="1" type="boolean"/>
1671
+
<bitfield name="XY_MAG" low="2" high="3" type="a3xx_tex_filter"/>
1672
+
<bitfield name="XY_MIN" low="4" high="5" type="a3xx_tex_filter"/>
1673
+
<bitfield name="WRAP_S" low="6" high="8" type="a3xx_tex_clamp"/>
1674
+
<bitfield name="WRAP_T" low="9" high="11" type="a3xx_tex_clamp"/>
1675
+
<bitfield name="WRAP_R" low="12" high="14" type="a3xx_tex_clamp"/>
1676
+
<bitfield name="ANISO" low="15" high="17" type="a3xx_tex_aniso"/>
1677
+
<bitfield name="COMPARE_FUNC" low="20" high="22" type="adreno_compare_func"/>
1678
+
<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="24" type="boolean"/>
1679
+
<!-- UNNORM_COORDS == CLK_NORMALIZED_COORDS_FALSE -->
1680
+
<bitfield name="UNNORM_COORDS" pos="31" type="boolean"/>
1681
+
</reg32>
1682
+
<reg32 offset="1" name="1">
1683
+
<bitfield name="LOD_BIAS" low="0" high="10" type="fixed" radix="6"/>
1684
+
<bitfield name="MAX_LOD" low="12" high="21" type="ufixed" radix="6"/>
1685
+
<bitfield name="MIN_LOD" low="22" high="31" type="ufixed" radix="6"/>
1686
+
</reg32>
1687
+
</domain>
1688
+
1689
+
<domain name="A3XX_TEX_CONST" width="32">
1690
+
<doc>Texture constant dwords</doc>
1691
+
<enum name="a3xx_tex_swiz">
1692
+
<!-- same as a2xx? -->
1693
+
<value name="A3XX_TEX_X" value="0"/>
1694
+
<value name="A3XX_TEX_Y" value="1"/>
1695
+
<value name="A3XX_TEX_Z" value="2"/>
1696
+
<value name="A3XX_TEX_W" value="3"/>
1697
+
<value name="A3XX_TEX_ZERO" value="4"/>
1698
+
<value name="A3XX_TEX_ONE" value="5"/>
1699
+
</enum>
1700
+
<enum name="a3xx_tex_type">
1701
+
<value name="A3XX_TEX_1D" value="0"/>
1702
+
<value name="A3XX_TEX_2D" value="1"/>
1703
+
<value name="A3XX_TEX_CUBE" value="2"/>
1704
+
<value name="A3XX_TEX_3D" value="3"/>
1705
+
</enum>
1706
+
<enum name="a3xx_tex_msaa">
1707
+
<value name="A3XX_TPL1_MSAA1X" value="0"/>
1708
+
<value name="A3XX_TPL1_MSAA2X" value="1"/>
1709
+
<value name="A3XX_TPL1_MSAA4X" value="2"/>
1710
+
<value name="A3XX_TPL1_MSAA8X" value="3"/>
1711
+
</enum>
1712
+
<reg32 offset="0" name="0">
1713
+
<bitfield name="TILE_MODE" low="0" high="1" type="a3xx_tile_mode"/>
1714
+
<bitfield name="SRGB" pos="2" type="boolean"/>
1715
+
<bitfield name="SWIZ_X" low="4" high="6" type="a3xx_tex_swiz"/>
1716
+
<bitfield name="SWIZ_Y" low="7" high="9" type="a3xx_tex_swiz"/>
1717
+
<bitfield name="SWIZ_Z" low="10" high="12" type="a3xx_tex_swiz"/>
1718
+
<bitfield name="SWIZ_W" low="13" high="15" type="a3xx_tex_swiz"/>
1719
+
<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
1720
+
<bitfield name="MSAATEX" low="20" high="21" type="a3xx_tex_msaa"/>
1721
+
<bitfield name="FMT" low="22" high="28" type="a3xx_tex_fmt"/>
1722
+
<bitfield name="NOCONVERT" pos="29" type="boolean"/>
1723
+
<bitfield name="TYPE" low="30" high="31" type="a3xx_tex_type"/>
1724
+
</reg32>
1725
+
<reg32 offset="1" name="1">
1726
+
<bitfield name="HEIGHT" low="0" high="13" type="uint"/>
1727
+
<bitfield name="WIDTH" low="14" high="27" type="uint"/>
1728
+
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 16) -->
1729
+
<bitfield name="PITCHALIGN" low="28" high="31" type="uint"/>
1730
+
</reg32>
1731
+
<reg32 offset="2" name="2">
1732
+
<doc>INDX is index of texture address(es) in MIPMAP state block</doc>
1733
+
<bitfield name="INDX" low="0" high="8" type="uint"/>
1734
+
<doc>Pitch in bytes (so actually stride)</doc>
1735
+
<bitfield name="PITCH" low="12" high="29" type="uint"/>
1736
+
<doc>SWAP bit is set for BGRA instead of RGBA</doc>
1737
+
<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
1738
+
</reg32>
1739
+
<reg32 offset="3" name="3">
1740
+
<!--
1741
+
Update: the two LAYERSZn seem not to be the same thing.
1742
+
According to Ilia's experimentation the first one goes up
1743
+
to at *least* bit 14..
1744
+
-->
1745
+
<bitfield name="LAYERSZ1" low="0" high="16" shr="12" type="uint"/>
1746
+
<bitfield name="DEPTH" low="17" high="27" type="uint"/>
1747
+
<bitfield name="LAYERSZ2" low="28" high="31" shr="12" type="uint"/>
1748
+
</reg32>
1749
+
</domain>
1750
+
1751
+
</database>
+2409
drivers/gpu/drm/msm/registers/adreno/a4xx.xml
+2409
drivers/gpu/drm/msm/registers/adreno/a4xx.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
<import file="adreno/adreno_pm4.xml"/>
8
+
9
+
<enum name="a4xx_color_fmt">
10
+
<value name="RB4_A8_UNORM" value="0x01"/>
11
+
<value name="RB4_R8_UNORM" value="0x02"/>
12
+
<value name="RB4_R8_SNORM" value="0x03"/>
13
+
<value name="RB4_R8_UINT" value="0x04"/>
14
+
<value name="RB4_R8_SINT" value="0x05"/>
15
+
16
+
<value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17
+
<value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18
+
<value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19
+
<value name="RB4_R8G8_UNORM" value="0x0f"/>
20
+
<value name="RB4_R8G8_SNORM" value="0x10"/>
21
+
<value name="RB4_R8G8_UINT" value="0x11"/>
22
+
<value name="RB4_R8G8_SINT" value="0x12"/>
23
+
<value name="RB4_R16_UNORM" value="0x13"/>
24
+
<value name="RB4_R16_SNORM" value="0x14"/>
25
+
<value name="RB4_R16_FLOAT" value="0x15"/>
26
+
<value name="RB4_R16_UINT" value="0x16"/>
27
+
<value name="RB4_R16_SINT" value="0x17"/>
28
+
29
+
<value name="RB4_R8G8B8_UNORM" value="0x19"/>
30
+
31
+
<value name="RB4_R8G8B8A8_UNORM" value="0x1a"/>
32
+
<value name="RB4_R8G8B8A8_SNORM" value="0x1c"/>
33
+
<value name="RB4_R8G8B8A8_UINT" value="0x1d"/>
34
+
<value name="RB4_R8G8B8A8_SINT" value="0x1e"/>
35
+
<value name="RB4_R10G10B10A2_UNORM" value="0x1f"/>
36
+
<value name="RB4_R10G10B10A2_UINT" value="0x22"/>
37
+
<value name="RB4_R11G11B10_FLOAT" value="0x27"/>
38
+
<value name="RB4_R16G16_UNORM" value="0x28"/>
39
+
<value name="RB4_R16G16_SNORM" value="0x29"/>
40
+
<value name="RB4_R16G16_FLOAT" value="0x2a"/>
41
+
<value name="RB4_R16G16_UINT" value="0x2b"/>
42
+
<value name="RB4_R16G16_SINT" value="0x2c"/>
43
+
<value name="RB4_R32_FLOAT" value="0x2d"/>
44
+
<value name="RB4_R32_UINT" value="0x2e"/>
45
+
<value name="RB4_R32_SINT" value="0x2f"/>
46
+
47
+
<value name="RB4_R16G16B16A16_UNORM" value="0x34"/>
48
+
<value name="RB4_R16G16B16A16_SNORM" value="0x35"/>
49
+
<value name="RB4_R16G16B16A16_FLOAT" value="0x36"/>
50
+
<value name="RB4_R16G16B16A16_UINT" value="0x37"/>
51
+
<value name="RB4_R16G16B16A16_SINT" value="0x38"/>
52
+
<value name="RB4_R32G32_FLOAT" value="0x39"/>
53
+
<value name="RB4_R32G32_UINT" value="0x3a"/>
54
+
<value name="RB4_R32G32_SINT" value="0x3b"/>
55
+
56
+
<value name="RB4_R32G32B32A32_FLOAT" value="0x3c"/>
57
+
<value name="RB4_R32G32B32A32_UINT" value="0x3d"/>
58
+
<value name="RB4_R32G32B32A32_SINT" value="0x3e"/>
59
+
60
+
<value name="RB4_NONE" value="0xff"/>
61
+
</enum>
62
+
63
+
<enum name="a4xx_tile_mode">
64
+
<value name="TILE4_LINEAR" value="0"/>
65
+
<value name="TILE4_2" value="2"/>
66
+
<value name="TILE4_3" value="3"/>
67
+
</enum>
68
+
69
+
<enum name="a4xx_vtx_fmt" prefix="chipset">
70
+
<!-- hmm, shifted one compared to a3xx?!? -->
71
+
<value name="VFMT4_32_FLOAT" value="0x1"/>
72
+
<value name="VFMT4_32_32_FLOAT" value="0x2"/>
73
+
<value name="VFMT4_32_32_32_FLOAT" value="0x3"/>
74
+
<value name="VFMT4_32_32_32_32_FLOAT" value="0x4"/>
75
+
76
+
<value name="VFMT4_16_FLOAT" value="0x5"/>
77
+
<value name="VFMT4_16_16_FLOAT" value="0x6"/>
78
+
<value name="VFMT4_16_16_16_FLOAT" value="0x7"/>
79
+
<value name="VFMT4_16_16_16_16_FLOAT" value="0x8"/>
80
+
81
+
<value name="VFMT4_32_FIXED" value="0x9"/>
82
+
<value name="VFMT4_32_32_FIXED" value="0xa"/>
83
+
<value name="VFMT4_32_32_32_FIXED" value="0xb"/>
84
+
<value name="VFMT4_32_32_32_32_FIXED" value="0xc"/>
85
+
86
+
<value name="VFMT4_11_11_10_FLOAT" value="0xd"/>
87
+
88
+
<!-- beyond here it does not appear to be shifted -->
89
+
<value name="VFMT4_16_SINT" value="0x10"/>
90
+
<value name="VFMT4_16_16_SINT" value="0x11"/>
91
+
<value name="VFMT4_16_16_16_SINT" value="0x12"/>
92
+
<value name="VFMT4_16_16_16_16_SINT" value="0x13"/>
93
+
<value name="VFMT4_16_UINT" value="0x14"/>
94
+
<value name="VFMT4_16_16_UINT" value="0x15"/>
95
+
<value name="VFMT4_16_16_16_UINT" value="0x16"/>
96
+
<value name="VFMT4_16_16_16_16_UINT" value="0x17"/>
97
+
<value name="VFMT4_16_SNORM" value="0x18"/>
98
+
<value name="VFMT4_16_16_SNORM" value="0x19"/>
99
+
<value name="VFMT4_16_16_16_SNORM" value="0x1a"/>
100
+
<value name="VFMT4_16_16_16_16_SNORM" value="0x1b"/>
101
+
<value name="VFMT4_16_UNORM" value="0x1c"/>
102
+
<value name="VFMT4_16_16_UNORM" value="0x1d"/>
103
+
<value name="VFMT4_16_16_16_UNORM" value="0x1e"/>
104
+
<value name="VFMT4_16_16_16_16_UNORM" value="0x1f"/>
105
+
106
+
<value name="VFMT4_32_UINT" value="0x20"/>
107
+
<value name="VFMT4_32_32_UINT" value="0x21"/>
108
+
<value name="VFMT4_32_32_32_UINT" value="0x22"/>
109
+
<value name="VFMT4_32_32_32_32_UINT" value="0x23"/>
110
+
<value name="VFMT4_32_SINT" value="0x24"/>
111
+
<value name="VFMT4_32_32_SINT" value="0x25"/>
112
+
<value name="VFMT4_32_32_32_SINT" value="0x26"/>
113
+
<value name="VFMT4_32_32_32_32_SINT" value="0x27"/>
114
+
115
+
<value name="VFMT4_8_UINT" value="0x28"/>
116
+
<value name="VFMT4_8_8_UINT" value="0x29"/>
117
+
<value name="VFMT4_8_8_8_UINT" value="0x2a"/>
118
+
<value name="VFMT4_8_8_8_8_UINT" value="0x2b"/>
119
+
<value name="VFMT4_8_UNORM" value="0x2c"/>
120
+
<value name="VFMT4_8_8_UNORM" value="0x2d"/>
121
+
<value name="VFMT4_8_8_8_UNORM" value="0x2e"/>
122
+
<value name="VFMT4_8_8_8_8_UNORM" value="0x2f"/>
123
+
<value name="VFMT4_8_SINT" value="0x30"/>
124
+
<value name="VFMT4_8_8_SINT" value="0x31"/>
125
+
<value name="VFMT4_8_8_8_SINT" value="0x32"/>
126
+
<value name="VFMT4_8_8_8_8_SINT" value="0x33"/>
127
+
<value name="VFMT4_8_SNORM" value="0x34"/>
128
+
<value name="VFMT4_8_8_SNORM" value="0x35"/>
129
+
<value name="VFMT4_8_8_8_SNORM" value="0x36"/>
130
+
<value name="VFMT4_8_8_8_8_SNORM" value="0x37"/>
131
+
132
+
<value name="VFMT4_10_10_10_2_UINT" value="0x38"/>
133
+
<value name="VFMT4_10_10_10_2_UNORM" value="0x39"/>
134
+
<value name="VFMT4_10_10_10_2_SINT" value="0x3a"/>
135
+
<value name="VFMT4_10_10_10_2_SNORM" value="0x3b"/>
136
+
<value name="VFMT4_2_10_10_10_UINT" value="0x3c"/>
137
+
<value name="VFMT4_2_10_10_10_UNORM" value="0x3d"/>
138
+
<value name="VFMT4_2_10_10_10_SINT" value="0x3e"/>
139
+
<value name="VFMT4_2_10_10_10_SNORM" value="0x3f"/>
140
+
141
+
<value name="VFMT4_NONE" value="0xff"/>
142
+
</enum>
143
+
144
+
<enum name="a4xx_tex_fmt">
145
+
<!-- 0x00 .. 0x02 -->
146
+
147
+
<!-- 8-bit formats -->
148
+
<value name="TFMT4_A8_UNORM" value="0x03"/>
149
+
<value name="TFMT4_8_UNORM" value="0x04"/>
150
+
<value name="TFMT4_8_SNORM" value="0x05"/>
151
+
<value name="TFMT4_8_UINT" value="0x06"/>
152
+
<value name="TFMT4_8_SINT" value="0x07"/>
153
+
154
+
<!-- 16-bit formats -->
155
+
<value name="TFMT4_4_4_4_4_UNORM" value="0x08"/>
156
+
<value name="TFMT4_5_5_5_1_UNORM" value="0x09"/>
157
+
<!-- 0x0a -->
158
+
<value name="TFMT4_5_6_5_UNORM" value="0x0b"/>
159
+
160
+
<!-- 0x0c -->
161
+
162
+
<value name="TFMT4_L8_A8_UNORM" value="0x0d"/>
163
+
<value name="TFMT4_8_8_UNORM" value="0x0e"/>
164
+
<value name="TFMT4_8_8_SNORM" value="0x0f"/>
165
+
<value name="TFMT4_8_8_UINT" value="0x10"/>
166
+
<value name="TFMT4_8_8_SINT" value="0x11"/>
167
+
168
+
<value name="TFMT4_16_UNORM" value="0x12"/>
169
+
<value name="TFMT4_16_SNORM" value="0x13"/>
170
+
<value name="TFMT4_16_FLOAT" value="0x14"/>
171
+
<value name="TFMT4_16_UINT" value="0x15"/>
172
+
<value name="TFMT4_16_SINT" value="0x16"/>
173
+
174
+
<!-- 0x17 .. 0x1b -->
175
+
176
+
<!-- 32-bit formats -->
177
+
<value name="TFMT4_8_8_8_8_UNORM" value="0x1c"/>
178
+
<value name="TFMT4_8_8_8_8_SNORM" value="0x1d"/>
179
+
<value name="TFMT4_8_8_8_8_UINT" value="0x1e"/>
180
+
<value name="TFMT4_8_8_8_8_SINT" value="0x1f"/>
181
+
182
+
<value name="TFMT4_9_9_9_E5_FLOAT" value="0x20"/>
183
+
<value name="TFMT4_10_10_10_2_UNORM" value="0x21"/>
184
+
<value name="TFMT4_10_10_10_2_UINT" value="0x22"/>
185
+
<!-- 0x23 .. 0x24 -->
186
+
<value name="TFMT4_11_11_10_FLOAT" value="0x25"/>
187
+
188
+
<value name="TFMT4_16_16_UNORM" value="0x26"/>
189
+
<value name="TFMT4_16_16_SNORM" value="0x27"/>
190
+
<value name="TFMT4_16_16_FLOAT" value="0x28"/>
191
+
<value name="TFMT4_16_16_UINT" value="0x29"/>
192
+
<value name="TFMT4_16_16_SINT" value="0x2a"/>
193
+
194
+
<value name="TFMT4_32_FLOAT" value="0x2b"/>
195
+
<value name="TFMT4_32_UINT" value="0x2c"/>
196
+
<value name="TFMT4_32_SINT" value="0x2d"/>
197
+
198
+
<!-- 0x2e .. 0x32 -->
199
+
200
+
<!-- 64-bit formats -->
201
+
<value name="TFMT4_16_16_16_16_UNORM" value="0x33"/>
202
+
<value name="TFMT4_16_16_16_16_SNORM" value="0x34"/>
203
+
<value name="TFMT4_16_16_16_16_FLOAT" value="0x35"/>
204
+
<value name="TFMT4_16_16_16_16_UINT" value="0x36"/>
205
+
<value name="TFMT4_16_16_16_16_SINT" value="0x37"/>
206
+
207
+
<value name="TFMT4_32_32_FLOAT" value="0x38"/>
208
+
<value name="TFMT4_32_32_UINT" value="0x39"/>
209
+
<value name="TFMT4_32_32_SINT" value="0x3a"/>
210
+
211
+
<!-- 96-bit formats -->
212
+
<value name="TFMT4_32_32_32_FLOAT" value="0x3b"/>
213
+
<value name="TFMT4_32_32_32_UINT" value="0x3c"/>
214
+
<value name="TFMT4_32_32_32_SINT" value="0x3d"/>
215
+
216
+
<!-- 0x3e -->
217
+
218
+
<!-- 128-bit formats -->
219
+
<value name="TFMT4_32_32_32_32_FLOAT" value="0x3f"/>
220
+
<value name="TFMT4_32_32_32_32_UINT" value="0x40"/>
221
+
<value name="TFMT4_32_32_32_32_SINT" value="0x41"/>
222
+
223
+
<!-- 0x42 .. 0x46 -->
224
+
<value name="TFMT4_X8Z24_UNORM" value="0x47"/>
225
+
<!-- 0x48 .. 0x55 -->
226
+
227
+
<!-- compressed formats -->
228
+
<value name="TFMT4_DXT1" value="0x56"/>
229
+
<value name="TFMT4_DXT3" value="0x57"/>
230
+
<value name="TFMT4_DXT5" value="0x58"/>
231
+
<!-- 0x59 -->
232
+
<value name="TFMT4_RGTC1_UNORM" value="0x5a"/>
233
+
<value name="TFMT4_RGTC1_SNORM" value="0x5b"/>
234
+
<!-- 0x5c .. 0x5d -->
235
+
<value name="TFMT4_RGTC2_UNORM" value="0x5e"/>
236
+
<value name="TFMT4_RGTC2_SNORM" value="0x5f"/>
237
+
<!-- 0x60 -->
238
+
<value name="TFMT4_BPTC_UFLOAT" value="0x61"/>
239
+
<value name="TFMT4_BPTC_FLOAT" value="0x62"/>
240
+
<value name="TFMT4_BPTC" value="0x63"/>
241
+
<value name="TFMT4_ATC_RGB" value="0x64"/>
242
+
<value name="TFMT4_ATC_RGBA_EXPLICIT" value="0x65"/>
243
+
<value name="TFMT4_ATC_RGBA_INTERPOLATED" value="0x66"/>
244
+
<value name="TFMT4_ETC2_RG11_UNORM" value="0x67"/>
245
+
<value name="TFMT4_ETC2_RG11_SNORM" value="0x68"/>
246
+
<value name="TFMT4_ETC2_R11_UNORM" value="0x69"/>
247
+
<value name="TFMT4_ETC2_R11_SNORM" value="0x6a"/>
248
+
<value name="TFMT4_ETC1" value="0x6b"/>
249
+
<value name="TFMT4_ETC2_RGB8" value="0x6c"/>
250
+
<value name="TFMT4_ETC2_RGBA8" value="0x6d"/>
251
+
<value name="TFMT4_ETC2_RGB8A1" value="0x6e"/>
252
+
<value name="TFMT4_ASTC_4x4" value="0x6f"/>
253
+
<value name="TFMT4_ASTC_5x4" value="0x70"/>
254
+
<value name="TFMT4_ASTC_5x5" value="0x71"/>
255
+
<value name="TFMT4_ASTC_6x5" value="0x72"/>
256
+
<value name="TFMT4_ASTC_6x6" value="0x73"/>
257
+
<value name="TFMT4_ASTC_8x5" value="0x74"/>
258
+
<value name="TFMT4_ASTC_8x6" value="0x75"/>
259
+
<value name="TFMT4_ASTC_8x8" value="0x76"/>
260
+
<value name="TFMT4_ASTC_10x5" value="0x77"/>
261
+
<value name="TFMT4_ASTC_10x6" value="0x78"/>
262
+
<value name="TFMT4_ASTC_10x8" value="0x79"/>
263
+
<value name="TFMT4_ASTC_10x10" value="0x7a"/>
264
+
<value name="TFMT4_ASTC_12x10" value="0x7b"/>
265
+
<value name="TFMT4_ASTC_12x12" value="0x7c"/>
266
+
<!-- 0x7d .. 0x7f -->
267
+
268
+
<value name="TFMT4_NONE" value="0xff"/>
269
+
</enum>
270
+
271
+
<enum name="a4xx_depth_format">
272
+
<value name="DEPTH4_NONE" value="0"/>
273
+
<value name="DEPTH4_16" value="1"/>
274
+
<value name="DEPTH4_24_8" value="2"/>
275
+
<value name="DEPTH4_32" value="3"/>
276
+
</enum>
277
+
278
+
<!--
279
+
NOTE counters extracted from test-perf log with the following awful
280
+
script:
281
+
##################
282
+
#!/bin/bash
283
+
284
+
log=$1
285
+
286
+
grep -F "counter
287
+
countable
288
+
group" $log | grep -v gl > shortlist.txt
289
+
290
+
countable=""
291
+
IFS=$'\n'; for line in $(cat shortlist.txt); do
292
+
# parse ######### group[$n]: $name
293
+
l=${line########### group}
294
+
if [ $l != $line ]; then
295
+
group=`echo $line | awk '{print $3}'`
296
+
echo "Group: $group"
297
+
continue
298
+
fi
299
+
# parse ######### counter[$n]: $name
300
+
l=${line########### counter}
301
+
if [ $l != $line ]; then
302
+
countable=`echo $line | awk '{print $3}'`
303
+
#echo " Countable: $countable"
304
+
continue
305
+
fi
306
+
# parse countable:
307
+
l=${line## countable:}
308
+
if [ $l != $line ]; then
309
+
val=`echo $line | awk '{print $2}'`
310
+
echo "<value value=\"$val\" name=\"$countable\"/>"
311
+
fi
312
+
313
+
done
314
+
##################
315
+
-->
316
+
<enum name="a4xx_ccu_perfcounter_select">
317
+
<value value="0" name="CCU_BUSY_CYCLES"/>
318
+
<value value="2" name="CCU_RB_DEPTH_RETURN_STALL"/>
319
+
<value value="3" name="CCU_RB_COLOR_RETURN_STALL"/>
320
+
<value value="6" name="CCU_DEPTH_BLOCKS"/>
321
+
<value value="7" name="CCU_COLOR_BLOCKS"/>
322
+
<value value="8" name="CCU_DEPTH_BLOCK_HIT"/>
323
+
<value value="9" name="CCU_COLOR_BLOCK_HIT"/>
324
+
<value value="10" name="CCU_DEPTH_FLAG1_COUNT"/>
325
+
<value value="11" name="CCU_DEPTH_FLAG2_COUNT"/>
326
+
<value value="12" name="CCU_DEPTH_FLAG3_COUNT"/>
327
+
<value value="13" name="CCU_DEPTH_FLAG4_COUNT"/>
328
+
<value value="14" name="CCU_COLOR_FLAG1_COUNT"/>
329
+
<value value="15" name="CCU_COLOR_FLAG2_COUNT"/>
330
+
<value value="16" name="CCU_COLOR_FLAG3_COUNT"/>
331
+
<value value="17" name="CCU_COLOR_FLAG4_COUNT"/>
332
+
<value value="18" name="CCU_PARTIAL_BLOCK_READ"/>
333
+
</enum>
334
+
335
+
<!--
336
+
NOTE other than CP_ALWAYS_COUNT (which is the only one we use so far),
337
+
on a3xx the countable #'s from AMD_performance_monitor disagreed with
338
+
TRM. All these #'s for a4xx come from AMD_performance_monitor, so
339
+
perhaps they should be taken with a grain of salt
340
+
-->
341
+
<enum name="a4xx_cp_perfcounter_select">
342
+
<!-- first ctr at least seems same as a3xx, so we can measure freq -->
343
+
<value value="0" name="CP_ALWAYS_COUNT"/>
344
+
<value value="1" name="CP_BUSY"/>
345
+
<value value="2" name="CP_PFP_IDLE"/>
346
+
<value value="3" name="CP_PFP_BUSY_WORKING"/>
347
+
<value value="4" name="CP_PFP_STALL_CYCLES_ANY"/>
348
+
<value value="5" name="CP_PFP_STARVE_CYCLES_ANY"/>
349
+
<value value="6" name="CP_PFP_STARVED_PER_LOAD_ADDR"/>
350
+
<value value="7" name="CP_PFP_STALLED_PER_STORE_ADDR"/>
351
+
<value value="8" name="CP_PFP_PC_PROFILE"/>
352
+
<value value="9" name="CP_PFP_MATCH_PM4_PKT_PROFILE"/>
353
+
<value value="10" name="CP_PFP_COND_INDIRECT_DISCARDED"/>
354
+
<value value="11" name="CP_LONG_RESUMPTIONS"/>
355
+
<value value="12" name="CP_RESUME_CYCLES"/>
356
+
<value value="13" name="CP_RESUME_TO_BOUNDARY_CYCLES"/>
357
+
<value value="14" name="CP_LONG_PREEMPTIONS"/>
358
+
<value value="15" name="CP_PREEMPT_CYCLES"/>
359
+
<value value="16" name="CP_PREEMPT_TO_BOUNDARY_CYCLES"/>
360
+
<value value="17" name="CP_ME_FIFO_EMPTY_PFP_IDLE"/>
361
+
<value value="18" name="CP_ME_FIFO_EMPTY_PFP_BUSY"/>
362
+
<value value="19" name="CP_ME_FIFO_NOT_EMPTY_NOT_FULL"/>
363
+
<value value="20" name="CP_ME_FIFO_FULL_ME_BUSY"/>
364
+
<value value="21" name="CP_ME_FIFO_FULL_ME_NON_WORKING"/>
365
+
<value value="22" name="CP_ME_WAITING_FOR_PACKETS"/>
366
+
<value value="23" name="CP_ME_BUSY_WORKING"/>
367
+
<value value="24" name="CP_ME_STARVE_CYCLES_ANY"/>
368
+
<value value="25" name="CP_ME_STARVE_CYCLES_PER_PROFILE"/>
369
+
<value value="26" name="CP_ME_STALL_CYCLES_PER_PROFILE"/>
370
+
<value value="27" name="CP_ME_PC_PROFILE"/>
371
+
<value value="28" name="CP_RCIU_FIFO_EMPTY"/>
372
+
<value value="29" name="CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL"/>
373
+
<value value="30" name="CP_RCIU_FIFO_FULL"/>
374
+
<value value="31" name="CP_RCIU_FIFO_FULL_NO_CONTEXT"/>
375
+
<value value="32" name="CP_RCIU_FIFO_FULL_AHB_MASTER"/>
376
+
<value value="33" name="CP_RCIU_FIFO_FULL_OTHER"/>
377
+
<value value="34" name="CP_AHB_IDLE"/>
378
+
<value value="35" name="CP_AHB_STALL_ON_GRANT_NO_SPLIT"/>
379
+
<value value="36" name="CP_AHB_STALL_ON_GRANT_SPLIT"/>
380
+
<value value="37" name="CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE"/>
381
+
<value value="38" name="CP_AHB_BUSY_WORKING"/>
382
+
<value value="39" name="CP_AHB_BUSY_STALL_ON_HRDY"/>
383
+
<value value="40" name="CP_AHB_BUSY_STALL_ON_HRDY_PROFILE"/>
384
+
</enum>
385
+
386
+
<enum name="a4xx_gras_ras_perfcounter_select">
387
+
<value value="0" name="RAS_SUPER_TILES"/>
388
+
<value value="1" name="RAS_8X8_TILES"/>
389
+
<value value="2" name="RAS_4X4_TILES"/>
390
+
<value value="3" name="RAS_BUSY_CYCLES"/>
391
+
<value value="4" name="RAS_STALL_CYCLES_BY_RB"/>
392
+
<value value="5" name="RAS_STALL_CYCLES_BY_VSC"/>
393
+
<value value="6" name="RAS_STARVE_CYCLES_BY_TSE"/>
394
+
<value value="7" name="RAS_SUPERTILE_CYCLES"/>
395
+
<value value="8" name="RAS_TILE_CYCLES"/>
396
+
<value value="9" name="RAS_FULLY_COVERED_SUPER_TILES"/>
397
+
<value value="10" name="RAS_FULLY_COVERED_8X8_TILES"/>
398
+
<value value="11" name="RAS_4X4_PRIM"/>
399
+
<value value="12" name="RAS_8X4_4X8_PRIM"/>
400
+
<value value="13" name="RAS_8X8_PRIM"/>
401
+
</enum>
402
+
403
+
<enum name="a4xx_gras_tse_perfcounter_select">
404
+
<value value="0" name="TSE_INPUT_PRIM"/>
405
+
<value value="1" name="TSE_INPUT_NULL_PRIM"/>
406
+
<value value="2" name="TSE_TRIVAL_REJ_PRIM"/>
407
+
<value value="3" name="TSE_CLIPPED_PRIM"/>
408
+
<value value="4" name="TSE_NEW_PRIM"/>
409
+
<value value="5" name="TSE_ZERO_AREA_PRIM"/>
410
+
<value value="6" name="TSE_FACENESS_CULLED_PRIM"/>
411
+
<value value="7" name="TSE_ZERO_PIXEL_PRIM"/>
412
+
<value value="8" name="TSE_OUTPUT_NULL_PRIM"/>
413
+
<value value="9" name="TSE_OUTPUT_VISIBLE_PRIM"/>
414
+
<value value="10" name="TSE_PRE_CLIP_PRIM"/>
415
+
<value value="11" name="TSE_POST_CLIP_PRIM"/>
416
+
<value value="12" name="TSE_BUSY_CYCLES"/>
417
+
<value value="13" name="TSE_PC_STARVE"/>
418
+
<value value="14" name="TSE_RAS_STALL"/>
419
+
<value value="15" name="TSE_STALL_BARYPLANE_FIFO_FULL"/>
420
+
<value value="16" name="TSE_STALL_ZPLANE_FIFO_FULL"/>
421
+
</enum>
422
+
423
+
<enum name="a4xx_hlsq_perfcounter_select">
424
+
<value value="0" name="HLSQ_SP_VS_STAGE_CONSTANT"/>
425
+
<value value="1" name="HLSQ_SP_VS_STAGE_INSTRUCTIONS"/>
426
+
<value value="2" name="HLSQ_SP_FS_STAGE_CONSTANT"/>
427
+
<value value="3" name="HLSQ_SP_FS_STAGE_INSTRUCTIONS"/>
428
+
<value value="4" name="HLSQ_TP_STATE"/>
429
+
<value value="5" name="HLSQ_QUADS"/>
430
+
<value value="6" name="HLSQ_PIXELS"/>
431
+
<value value="7" name="HLSQ_VERTICES"/>
432
+
<value value="13" name="HLSQ_SP_VS_STAGE_DATA_BYTES"/>
433
+
<value value="14" name="HLSQ_SP_FS_STAGE_DATA_BYTES"/>
434
+
<value value="15" name="HLSQ_BUSY_CYCLES"/>
435
+
<value value="16" name="HLSQ_STALL_CYCLES_SP_STATE"/>
436
+
<value value="17" name="HLSQ_STALL_CYCLES_SP_VS_STAGE"/>
437
+
<value value="18" name="HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
438
+
<value value="19" name="HLSQ_STALL_CYCLES_UCHE"/>
439
+
<value value="20" name="HLSQ_RBBM_LOAD_CYCLES"/>
440
+
<value value="21" name="HLSQ_DI_TO_VS_START_SP"/>
441
+
<value value="22" name="HLSQ_DI_TO_FS_START_SP"/>
442
+
<value value="23" name="HLSQ_VS_STAGE_START_TO_DONE_SP"/>
443
+
<value value="24" name="HLSQ_FS_STAGE_START_TO_DONE_SP"/>
444
+
<value value="25" name="HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE"/>
445
+
<value value="26" name="HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE"/>
446
+
<value value="27" name="HLSQ_UCHE_LATENCY_CYCLES"/>
447
+
<value value="28" name="HLSQ_UCHE_LATENCY_COUNT"/>
448
+
<value value="29" name="HLSQ_STARVE_CYCLES_VFD"/>
449
+
</enum>
450
+
451
+
<enum name="a4xx_pc_perfcounter_select">
452
+
<value value="0" name="PC_VIS_STREAMS_LOADED"/>
453
+
<value value="2" name="PC_VPC_PRIMITIVES"/>
454
+
<value value="3" name="PC_DEAD_PRIM"/>
455
+
<value value="4" name="PC_LIVE_PRIM"/>
456
+
<value value="5" name="PC_DEAD_DRAWCALLS"/>
457
+
<value value="6" name="PC_LIVE_DRAWCALLS"/>
458
+
<value value="7" name="PC_VERTEX_MISSES"/>
459
+
<value value="9" name="PC_STALL_CYCLES_VFD"/>
460
+
<value value="10" name="PC_STALL_CYCLES_TSE"/>
461
+
<value value="11" name="PC_STALL_CYCLES_UCHE"/>
462
+
<value value="12" name="PC_WORKING_CYCLES"/>
463
+
<value value="13" name="PC_IA_VERTICES"/>
464
+
<value value="14" name="PC_GS_PRIMITIVES"/>
465
+
<value value="15" name="PC_HS_INVOCATIONS"/>
466
+
<value value="16" name="PC_DS_INVOCATIONS"/>
467
+
<value value="17" name="PC_DS_PRIMITIVES"/>
468
+
<value value="20" name="PC_STARVE_CYCLES_FOR_INDEX"/>
469
+
<value value="21" name="PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
470
+
<value value="22" name="PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
471
+
<value value="23" name="PC_STALL_CYCLES_TESS"/>
472
+
<value value="24" name="PC_STARVE_CYCLES_FOR_POSITION"/>
473
+
<value value="25" name="PC_MODE0_DRAWCALL"/>
474
+
<value value="26" name="PC_MODE1_DRAWCALL"/>
475
+
<value value="27" name="PC_MODE2_DRAWCALL"/>
476
+
<value value="28" name="PC_MODE3_DRAWCALL"/>
477
+
<value value="29" name="PC_MODE4_DRAWCALL"/>
478
+
<value value="30" name="PC_PREDICATED_DEAD_DRAWCALL"/>
479
+
<value value="31" name="PC_STALL_CYCLES_BY_TSE_ONLY"/>
480
+
<value value="32" name="PC_STALL_CYCLES_BY_VPC_ONLY"/>
481
+
<value value="33" name="PC_VPC_POS_DATA_TRANSACTION"/>
482
+
<value value="34" name="PC_BUSY_CYCLES"/>
483
+
<value value="35" name="PC_STARVE_CYCLES_DI"/>
484
+
<value value="36" name="PC_STALL_CYCLES_VPC"/>
485
+
<value value="37" name="TESS_WORKING_CYCLES"/>
486
+
<value value="38" name="TESS_NUM_CYCLES_SETUP_WORKING"/>
487
+
<value value="39" name="TESS_NUM_CYCLES_PTGEN_WORKING"/>
488
+
<value value="40" name="TESS_NUM_CYCLES_CONNGEN_WORKING"/>
489
+
<value value="41" name="TESS_BUSY_CYCLES"/>
490
+
<value value="42" name="TESS_STARVE_CYCLES_PC"/>
491
+
<value value="43" name="TESS_STALL_CYCLES_PC"/>
492
+
</enum>
493
+
494
+
<enum name="a4xx_pwr_perfcounter_select">
495
+
<!-- NOTE not actually used.. see RBBM_RBBM_CTL.RESET_PWR_CTR0/1 -->
496
+
<value value="0" name="PWR_CORE_CLOCK_CYCLES"/>
497
+
<value value="1" name="PWR_BUSY_CLOCK_CYCLES"/>
498
+
</enum>
499
+
500
+
<enum name="a4xx_rb_perfcounter_select">
501
+
<value value="0" name="RB_BUSY_CYCLES"/>
502
+
<value value="1" name="RB_BUSY_CYCLES_BINNING"/>
503
+
<value value="2" name="RB_BUSY_CYCLES_RENDERING"/>
504
+
<value value="3" name="RB_BUSY_CYCLES_RESOLVE"/>
505
+
<value value="4" name="RB_STARVE_CYCLES_BY_SP"/>
506
+
<value value="5" name="RB_STARVE_CYCLES_BY_RAS"/>
507
+
<value value="6" name="RB_STARVE_CYCLES_BY_MARB"/>
508
+
<value value="7" name="RB_STALL_CYCLES_BY_MARB"/>
509
+
<value value="8" name="RB_STALL_CYCLES_BY_HLSQ"/>
510
+
<value value="9" name="RB_RB_RB_MARB_DATA"/>
511
+
<value value="10" name="RB_SP_RB_QUAD"/>
512
+
<value value="11" name="RB_RAS_RB_Z_QUADS"/>
513
+
<value value="12" name="RB_GMEM_CH0_READ"/>
514
+
<value value="13" name="RB_GMEM_CH1_READ"/>
515
+
<value value="14" name="RB_GMEM_CH0_WRITE"/>
516
+
<value value="15" name="RB_GMEM_CH1_WRITE"/>
517
+
<value value="16" name="RB_CP_CONTEXT_DONE"/>
518
+
<value value="17" name="RB_CP_CACHE_FLUSH"/>
519
+
<value value="18" name="RB_CP_ZPASS_DONE"/>
520
+
<value value="19" name="RB_STALL_FIFO0_FULL"/>
521
+
<value value="20" name="RB_STALL_FIFO1_FULL"/>
522
+
<value value="21" name="RB_STALL_FIFO2_FULL"/>
523
+
<value value="22" name="RB_STALL_FIFO3_FULL"/>
524
+
<value value="23" name="RB_RB_HLSQ_TRANSACTIONS"/>
525
+
<value value="24" name="RB_Z_READ"/>
526
+
<value value="25" name="RB_Z_WRITE"/>
527
+
<value value="26" name="RB_C_READ"/>
528
+
<value value="27" name="RB_C_WRITE"/>
529
+
<value value="28" name="RB_C_READ_LATENCY"/>
530
+
<value value="29" name="RB_Z_READ_LATENCY"/>
531
+
<value value="30" name="RB_STALL_BY_UCHE"/>
532
+
<value value="31" name="RB_MARB_UCHE_TRANSACTIONS"/>
533
+
<value value="32" name="RB_CACHE_STALL_MISS"/>
534
+
<value value="33" name="RB_CACHE_STALL_FIFO_FULL"/>
535
+
<value value="34" name="RB_8BIT_BLENDER_UNITS_ACTIVE"/>
536
+
<value value="35" name="RB_16BIT_BLENDER_UNITS_ACTIVE"/>
537
+
<value value="36" name="RB_SAMPLER_UNITS_ACTIVE"/>
538
+
<value value="38" name="RB_TOTAL_PASS"/>
539
+
<value value="39" name="RB_Z_PASS"/>
540
+
<value value="40" name="RB_Z_FAIL"/>
541
+
<value value="41" name="RB_S_FAIL"/>
542
+
<value value="42" name="RB_POWER0"/>
543
+
<value value="43" name="RB_POWER1"/>
544
+
<value value="44" name="RB_POWER2"/>
545
+
<value value="45" name="RB_POWER3"/>
546
+
<value value="46" name="RB_POWER4"/>
547
+
<value value="47" name="RB_POWER5"/>
548
+
<value value="48" name="RB_POWER6"/>
549
+
<value value="49" name="RB_POWER7"/>
550
+
</enum>
551
+
552
+
<enum name="a4xx_rbbm_perfcounter_select">
553
+
<value value="0" name="RBBM_ALWAYS_ON"/>
554
+
<value value="1" name="RBBM_VBIF_BUSY"/>
555
+
<value value="2" name="RBBM_TSE_BUSY"/>
556
+
<value value="3" name="RBBM_RAS_BUSY"/>
557
+
<value value="4" name="RBBM_PC_DCALL_BUSY"/>
558
+
<value value="5" name="RBBM_PC_VSD_BUSY"/>
559
+
<value value="6" name="RBBM_VFD_BUSY"/>
560
+
<value value="7" name="RBBM_VPC_BUSY"/>
561
+
<value value="8" name="RBBM_UCHE_BUSY"/>
562
+
<value value="9" name="RBBM_VSC_BUSY"/>
563
+
<value value="10" name="RBBM_HLSQ_BUSY"/>
564
+
<value value="11" name="RBBM_ANY_RB_BUSY"/>
565
+
<value value="12" name="RBBM_ANY_TPL1_BUSY"/>
566
+
<value value="13" name="RBBM_ANY_SP_BUSY"/>
567
+
<value value="14" name="RBBM_ANY_MARB_BUSY"/>
568
+
<value value="15" name="RBBM_ANY_ARB_BUSY"/>
569
+
<value value="16" name="RBBM_AHB_STATUS_BUSY"/>
570
+
<value value="17" name="RBBM_AHB_STATUS_STALLED"/>
571
+
<value value="18" name="RBBM_AHB_STATUS_TXFR"/>
572
+
<value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
573
+
<value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
574
+
<value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
575
+
<value value="22" name="RBBM_STATUS_MASKED"/>
576
+
<value value="23" name="RBBM_CP_BUSY_GFX_CORE_IDLE"/>
577
+
<value value="24" name="RBBM_TESS_BUSY"/>
578
+
<value value="25" name="RBBM_COM_BUSY"/>
579
+
<value value="32" name="RBBM_DCOM_BUSY"/>
580
+
<value value="33" name="RBBM_ANY_CCU_BUSY"/>
581
+
<value value="34" name="RBBM_DPM_BUSY"/>
582
+
</enum>
583
+
584
+
<enum name="a4xx_sp_perfcounter_select">
585
+
<value value="0" name="SP_LM_LOAD_INSTRUCTIONS"/>
586
+
<value value="1" name="SP_LM_STORE_INSTRUCTIONS"/>
587
+
<value value="2" name="SP_LM_ATOMICS"/>
588
+
<value value="3" name="SP_GM_LOAD_INSTRUCTIONS"/>
589
+
<value value="4" name="SP_GM_STORE_INSTRUCTIONS"/>
590
+
<value value="5" name="SP_GM_ATOMICS"/>
591
+
<value value="6" name="SP_VS_STAGE_TEX_INSTRUCTIONS"/>
592
+
<value value="7" name="SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
593
+
<value value="8" name="SP_VS_STAGE_EFU_INSTRUCTIONS"/>
594
+
<value value="9" name="SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
595
+
<value value="10" name="SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
596
+
<value value="11" name="SP_FS_STAGE_TEX_INSTRUCTIONS"/>
597
+
<value value="12" name="SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
598
+
<value value="13" name="SP_FS_STAGE_EFU_INSTRUCTIONS"/>
599
+
<value value="14" name="SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
600
+
<value value="15" name="SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
601
+
<value value="17" name="SP_VS_INSTRUCTIONS"/>
602
+
<value value="18" name="SP_FS_INSTRUCTIONS"/>
603
+
<value value="19" name="SP_ADDR_LOCK_COUNT"/>
604
+
<value value="20" name="SP_UCHE_READ_TRANS"/>
605
+
<value value="21" name="SP_UCHE_WRITE_TRANS"/>
606
+
<value value="22" name="SP_EXPORT_VPC_TRANS"/>
607
+
<value value="23" name="SP_EXPORT_RB_TRANS"/>
608
+
<value value="24" name="SP_PIXELS_KILLED"/>
609
+
<value value="25" name="SP_ICL1_REQUESTS"/>
610
+
<value value="26" name="SP_ICL1_MISSES"/>
611
+
<value value="27" name="SP_ICL0_REQUESTS"/>
612
+
<value value="28" name="SP_ICL0_MISSES"/>
613
+
<value value="29" name="SP_ALU_WORKING_CYCLES"/>
614
+
<value value="30" name="SP_EFU_WORKING_CYCLES"/>
615
+
<value value="31" name="SP_STALL_CYCLES_BY_VPC"/>
616
+
<value value="32" name="SP_STALL_CYCLES_BY_TP"/>
617
+
<value value="33" name="SP_STALL_CYCLES_BY_UCHE"/>
618
+
<value value="34" name="SP_STALL_CYCLES_BY_RB"/>
619
+
<value value="35" name="SP_BUSY_CYCLES"/>
620
+
<value value="36" name="SP_HS_INSTRUCTIONS"/>
621
+
<value value="37" name="SP_DS_INSTRUCTIONS"/>
622
+
<value value="38" name="SP_GS_INSTRUCTIONS"/>
623
+
<value value="39" name="SP_CS_INSTRUCTIONS"/>
624
+
<value value="40" name="SP_SCHEDULER_NON_WORKING"/>
625
+
<value value="41" name="SP_WAVE_CONTEXTS"/>
626
+
<value value="42" name="SP_WAVE_CONTEXT_CYCLES"/>
627
+
<value value="43" name="SP_POWER0"/>
628
+
<value value="44" name="SP_POWER1"/>
629
+
<value value="45" name="SP_POWER2"/>
630
+
<value value="46" name="SP_POWER3"/>
631
+
<value value="47" name="SP_POWER4"/>
632
+
<value value="48" name="SP_POWER5"/>
633
+
<value value="49" name="SP_POWER6"/>
634
+
<value value="50" name="SP_POWER7"/>
635
+
<value value="51" name="SP_POWER8"/>
636
+
<value value="52" name="SP_POWER9"/>
637
+
<value value="53" name="SP_POWER10"/>
638
+
<value value="54" name="SP_POWER11"/>
639
+
<value value="55" name="SP_POWER12"/>
640
+
<value value="56" name="SP_POWER13"/>
641
+
<value value="57" name="SP_POWER14"/>
642
+
<value value="58" name="SP_POWER15"/>
643
+
</enum>
644
+
645
+
<enum name="a4xx_tp_perfcounter_select">
646
+
<value value="0" name="TP_L1_REQUESTS"/>
647
+
<value value="1" name="TP_L1_MISSES"/>
648
+
<value value="8" name="TP_QUADS_OFFSET"/>
649
+
<value value="9" name="TP_QUAD_SHADOW"/>
650
+
<value value="10" name="TP_QUADS_ARRAY"/>
651
+
<value value="11" name="TP_QUADS_GRADIENT"/>
652
+
<value value="12" name="TP_QUADS_1D2D"/>
653
+
<value value="13" name="TP_QUADS_3DCUBE"/>
654
+
<value value="16" name="TP_BUSY_CYCLES"/>
655
+
<value value="17" name="TP_STALL_CYCLES_BY_ARB"/>
656
+
<value value="20" name="TP_STATE_CACHE_REQUESTS"/>
657
+
<value value="21" name="TP_STATE_CACHE_MISSES"/>
658
+
<value value="22" name="TP_POWER0"/>
659
+
<value value="23" name="TP_POWER1"/>
660
+
<value value="24" name="TP_POWER2"/>
661
+
<value value="25" name="TP_POWER3"/>
662
+
<value value="26" name="TP_POWER4"/>
663
+
<value value="27" name="TP_POWER5"/>
664
+
<value value="28" name="TP_POWER6"/>
665
+
<value value="29" name="TP_POWER7"/>
666
+
</enum>
667
+
668
+
<enum name="a4xx_uche_perfcounter_select">
669
+
<value value="0" name="UCHE_VBIF_READ_BEATS_TP"/>
670
+
<value value="1" name="UCHE_VBIF_READ_BEATS_VFD"/>
671
+
<value value="2" name="UCHE_VBIF_READ_BEATS_HLSQ"/>
672
+
<value value="3" name="UCHE_VBIF_READ_BEATS_MARB"/>
673
+
<value value="4" name="UCHE_VBIF_READ_BEATS_SP"/>
674
+
<value value="5" name="UCHE_READ_REQUESTS_TP"/>
675
+
<value value="6" name="UCHE_READ_REQUESTS_VFD"/>
676
+
<value value="7" name="UCHE_READ_REQUESTS_HLSQ"/>
677
+
<value value="8" name="UCHE_READ_REQUESTS_MARB"/>
678
+
<value value="9" name="UCHE_READ_REQUESTS_SP"/>
679
+
<value value="10" name="UCHE_WRITE_REQUESTS_MARB"/>
680
+
<value value="11" name="UCHE_WRITE_REQUESTS_SP"/>
681
+
<value value="12" name="UCHE_TAG_CHECK_FAILS"/>
682
+
<value value="13" name="UCHE_EVICTS"/>
683
+
<value value="14" name="UCHE_FLUSHES"/>
684
+
<value value="15" name="UCHE_VBIF_LATENCY_CYCLES"/>
685
+
<value value="16" name="UCHE_VBIF_LATENCY_SAMPLES"/>
686
+
<value value="17" name="UCHE_BUSY_CYCLES"/>
687
+
<value value="18" name="UCHE_VBIF_READ_BEATS_PC"/>
688
+
<value value="19" name="UCHE_READ_REQUESTS_PC"/>
689
+
<value value="20" name="UCHE_WRITE_REQUESTS_VPC"/>
690
+
<value value="21" name="UCHE_STALL_BY_VBIF"/>
691
+
<value value="22" name="UCHE_WRITE_REQUESTS_VSC"/>
692
+
<value value="23" name="UCHE_POWER0"/>
693
+
<value value="24" name="UCHE_POWER1"/>
694
+
<value value="25" name="UCHE_POWER2"/>
695
+
<value value="26" name="UCHE_POWER3"/>
696
+
<value value="27" name="UCHE_POWER4"/>
697
+
<value value="28" name="UCHE_POWER5"/>
698
+
<value value="29" name="UCHE_POWER6"/>
699
+
<value value="30" name="UCHE_POWER7"/>
700
+
</enum>
701
+
702
+
<enum name="a4xx_vbif_perfcounter_select">
703
+
<value value="0" name="AXI_READ_REQUESTS_ID_0"/>
704
+
<value value="1" name="AXI_READ_REQUESTS_ID_1"/>
705
+
<value value="2" name="AXI_READ_REQUESTS_ID_2"/>
706
+
<value value="3" name="AXI_READ_REQUESTS_ID_3"/>
707
+
<value value="4" name="AXI_READ_REQUESTS_ID_4"/>
708
+
<value value="5" name="AXI_READ_REQUESTS_ID_5"/>
709
+
<value value="6" name="AXI_READ_REQUESTS_ID_6"/>
710
+
<value value="7" name="AXI_READ_REQUESTS_ID_7"/>
711
+
<value value="8" name="AXI_READ_REQUESTS_ID_8"/>
712
+
<value value="9" name="AXI_READ_REQUESTS_ID_9"/>
713
+
<value value="10" name="AXI_READ_REQUESTS_ID_10"/>
714
+
<value value="11" name="AXI_READ_REQUESTS_ID_11"/>
715
+
<value value="12" name="AXI_READ_REQUESTS_ID_12"/>
716
+
<value value="13" name="AXI_READ_REQUESTS_ID_13"/>
717
+
<value value="14" name="AXI_READ_REQUESTS_ID_14"/>
718
+
<value value="15" name="AXI_READ_REQUESTS_ID_15"/>
719
+
<value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
720
+
<value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
721
+
<value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
722
+
<value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
723
+
<value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
724
+
<value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
725
+
<value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
726
+
<value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
727
+
<value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
728
+
<value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
729
+
<value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
730
+
<value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
731
+
<value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
732
+
<value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
733
+
<value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
734
+
<value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
735
+
<value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
736
+
<value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
737
+
<value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
738
+
<value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
739
+
<value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
740
+
<value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
741
+
<value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
742
+
<value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
743
+
<value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
744
+
<value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
745
+
<value value="42" name="AXI_TOTAL_REQUESTS"/>
746
+
<value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
747
+
<value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
748
+
<value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
749
+
<value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
750
+
<value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
751
+
<value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
752
+
<value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
753
+
<value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
754
+
<value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
755
+
<value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
756
+
<value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
757
+
<value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
758
+
<value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
759
+
<value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
760
+
<value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
761
+
<value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
762
+
<value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
763
+
<value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
764
+
<value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
765
+
<value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
766
+
<value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
767
+
<value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
768
+
<value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
769
+
<value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
770
+
<value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
771
+
<value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
772
+
<value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
773
+
<value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
774
+
<value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
775
+
<value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
776
+
<value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
777
+
<value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
778
+
<value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
779
+
<value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
780
+
<value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
781
+
<value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
782
+
<value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
783
+
<value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
784
+
<value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
785
+
<value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
786
+
<value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
787
+
<value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
788
+
<value value="85" name="AXI_DATA_BEATS_TOTAL"/>
789
+
<value value="86" name="CYCLES_HELD_OFF_ID_0"/>
790
+
<value value="87" name="CYCLES_HELD_OFF_ID_1"/>
791
+
<value value="88" name="CYCLES_HELD_OFF_ID_2"/>
792
+
<value value="89" name="CYCLES_HELD_OFF_ID_3"/>
793
+
<value value="90" name="CYCLES_HELD_OFF_ID_4"/>
794
+
<value value="91" name="CYCLES_HELD_OFF_ID_5"/>
795
+
<value value="92" name="CYCLES_HELD_OFF_ID_6"/>
796
+
<value value="93" name="CYCLES_HELD_OFF_ID_7"/>
797
+
<value value="94" name="CYCLES_HELD_OFF_ID_8"/>
798
+
<value value="95" name="CYCLES_HELD_OFF_ID_9"/>
799
+
<value value="96" name="CYCLES_HELD_OFF_ID_10"/>
800
+
<value value="97" name="CYCLES_HELD_OFF_ID_11"/>
801
+
<value value="98" name="CYCLES_HELD_OFF_ID_12"/>
802
+
<value value="99" name="CYCLES_HELD_OFF_ID_13"/>
803
+
<value value="100" name="CYCLES_HELD_OFF_ID_14"/>
804
+
<value value="101" name="CYCLES_HELD_OFF_ID_15"/>
805
+
<value value="102" name="AXI_READ_REQUEST_HELD_OFF"/>
806
+
<value value="103" name="AXI_WRITE_REQUEST_HELD_OFF"/>
807
+
<value value="104" name="AXI_REQUEST_HELD_OFF"/>
808
+
<value value="105" name="AXI_WRITE_DATA_HELD_OFF"/>
809
+
<value value="106" name="OCMEM_AXI_READ_REQUEST_HELD_OFF"/>
810
+
<value value="107" name="OCMEM_AXI_WRITE_REQUEST_HELD_OFF"/>
811
+
<value value="108" name="OCMEM_AXI_REQUEST_HELD_OFF"/>
812
+
<value value="109" name="OCMEM_AXI_WRITE_DATA_HELD_OFF"/>
813
+
<value value="110" name="ELAPSED_CYCLES_DDR"/>
814
+
<value value="111" name="ELAPSED_CYCLES_OCMEM"/>
815
+
</enum>
816
+
817
+
<enum name="a4xx_vfd_perfcounter_select">
818
+
<value value="0" name="VFD_UCHE_BYTE_FETCHED"/>
819
+
<value value="1" name="VFD_UCHE_TRANS"/>
820
+
<value value="3" name="VFD_FETCH_INSTRUCTIONS"/>
821
+
<value value="5" name="VFD_BUSY_CYCLES"/>
822
+
<value value="6" name="VFD_STALL_CYCLES_UCHE"/>
823
+
<value value="7" name="VFD_STALL_CYCLES_HLSQ"/>
824
+
<value value="8" name="VFD_STALL_CYCLES_VPC_BYPASS"/>
825
+
<value value="9" name="VFD_STALL_CYCLES_VPC_ALLOC"/>
826
+
<value value="13" name="VFD_MODE_0_FIBERS"/>
827
+
<value value="14" name="VFD_MODE_1_FIBERS"/>
828
+
<value value="15" name="VFD_MODE_2_FIBERS"/>
829
+
<value value="16" name="VFD_MODE_3_FIBERS"/>
830
+
<value value="17" name="VFD_MODE_4_FIBERS"/>
831
+
<value value="18" name="VFD_BFIFO_STALL"/>
832
+
<value value="19" name="VFD_NUM_VERTICES_TOTAL"/>
833
+
<value value="20" name="VFD_PACKER_FULL"/>
834
+
<value value="21" name="VFD_UCHE_REQUEST_FIFO_FULL"/>
835
+
<value value="22" name="VFD_STARVE_CYCLES_PC"/>
836
+
<value value="23" name="VFD_STARVE_CYCLES_UCHE"/>
837
+
</enum>
838
+
839
+
<enum name="a4xx_vpc_perfcounter_select">
840
+
<value value="2" name="VPC_SP_LM_COMPONENTS"/>
841
+
<value value="3" name="VPC_SP0_LM_BYTES"/>
842
+
<value value="4" name="VPC_SP1_LM_BYTES"/>
843
+
<value value="5" name="VPC_SP2_LM_BYTES"/>
844
+
<value value="6" name="VPC_SP3_LM_BYTES"/>
845
+
<value value="7" name="VPC_WORKING_CYCLES"/>
846
+
<value value="8" name="VPC_STALL_CYCLES_LM"/>
847
+
<value value="9" name="VPC_STARVE_CYCLES_RAS"/>
848
+
<value value="10" name="VPC_STREAMOUT_CYCLES"/>
849
+
<value value="12" name="VPC_UCHE_TRANSACTIONS"/>
850
+
<value value="13" name="VPC_STALL_CYCLES_UCHE"/>
851
+
<value value="14" name="VPC_BUSY_CYCLES"/>
852
+
<value value="15" name="VPC_STARVE_CYCLES_SP"/>
853
+
</enum>
854
+
855
+
<enum name="a4xx_vsc_perfcounter_select">
856
+
<value value="0" name="VSC_BUSY_CYCLES"/>
857
+
<value value="1" name="VSC_WORKING_CYCLES"/>
858
+
<value value="2" name="VSC_STALL_CYCLES_UCHE"/>
859
+
<value value="3" name="VSC_STARVE_CYCLES_RAS"/>
860
+
<value value="4" name="VSC_EOT_NUM"/>
861
+
</enum>
862
+
863
+
<domain name="A4XX" width="32">
864
+
<!-- RB registers -->
865
+
<reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
866
+
<reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
867
+
<reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
868
+
<reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
869
+
<reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
870
+
<reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
871
+
<reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
872
+
<reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
873
+
<reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
874
+
<reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
875
+
<reg32 offset="0x0cd0" name="RB_PERFCTR_CCU_SEL_1" type="a4xx_ccu_perfcounter_select"/>
876
+
<reg32 offset="0x0cd1" name="RB_PERFCTR_CCU_SEL_2" type="a4xx_ccu_perfcounter_select"/>
877
+
<reg32 offset="0x0cd2" name="RB_PERFCTR_CCU_SEL_3" type="a4xx_ccu_perfcounter_select"/>
878
+
<reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
879
+
<bitfield name="WIDTH" low="0" high="13" type="uint"/>
880
+
<bitfield name="HEIGHT" low="16" high="29" type="uint"/>
881
+
</reg32>
882
+
<reg32 offset="0x20cc" name="RB_CLEAR_COLOR_DW0"/>
883
+
<reg32 offset="0x20cd" name="RB_CLEAR_COLOR_DW1"/>
884
+
<reg32 offset="0x20ce" name="RB_CLEAR_COLOR_DW2"/>
885
+
<reg32 offset="0x20cf" name="RB_CLEAR_COLOR_DW3"/>
886
+
<reg32 offset="0x20a0" name="RB_MODE_CONTROL">
887
+
<!--
888
+
for non-bypass mode, these are bin width/height.. although
889
+
possibly bigger bitfields to hold entire width/height for
890
+
gmem-bypass?? Either way, it appears to need to be multiple
891
+
of 32..
892
+
-->
893
+
<bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
894
+
<bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/>
895
+
<bitfield name="ENABLE_GMEM" pos="16" type="boolean"/>
896
+
</reg32>
897
+
<reg32 offset="0x20a1" name="RB_RENDER_CONTROL">
898
+
<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
899
+
<!-- nearly everything has bit3 set.. -->
900
+
<!-- bit5 set on resolve and tiling pass -->
901
+
<bitfield name="DISABLE_COLOR_PIPE" pos="5" type="boolean"/>
902
+
</reg32>
903
+
<reg32 offset="0x20a2" name="RB_MSAA_CONTROL">
904
+
<bitfield name="DISABLE" pos="12" type="boolean"/>
905
+
<bitfield name="SAMPLES" low="13" high="15" type="uint"/>
906
+
</reg32>
907
+
<reg32 offset="0x20a3" name="RB_RENDER_CONTROL2">
908
+
<bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
909
+
<bitfield name="SAMPLEMASK" pos="4" type="boolean"/>
910
+
<bitfield name="FACENESS" pos="5" type="boolean"/>
911
+
<bitfield name="SAMPLEID" pos="6" type="boolean"/>
912
+
<bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
913
+
<bitfield name="SAMPLEID_HR" pos="11" type="boolean"/>
914
+
<bitfield name="IJ_PERSP_PIXEL" pos="12" type="boolean"/>
915
+
<!-- the 2 below are just educated guesses -->
916
+
<bitfield name="IJ_PERSP_CENTROID" pos="13" type="boolean"/>
917
+
<bitfield name="IJ_PERSP_SAMPLE" pos="14" type="boolean"/>
918
+
<!-- needs to be enabled to get nopersp values,
919
+
perhaps other cases too? -->
920
+
<bitfield name="SIZE" pos="15" type="boolean"/>
921
+
</reg32>
922
+
<array offset="0x20a4" name="RB_MRT" stride="5" length="8">
923
+
<reg32 offset="0x0" name="CONTROL">
924
+
<bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
925
+
<!-- both these bits seem to get set when enabling GL_BLEND.. -->
926
+
<bitfield name="BLEND" pos="4" type="boolean"/>
927
+
<bitfield name="BLEND2" pos="5" type="boolean"/>
928
+
<bitfield name="ROP_ENABLE" pos="6" type="boolean"/>
929
+
<bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
930
+
<bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
931
+
</reg32>
932
+
<reg32 offset="0x1" name="BUF_INFO">
933
+
<bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/>
934
+
<!--
935
+
guestimate position of COLOR_TILE_MODE.. this works out if
936
+
common value is 2, like on a3xx..
937
+
-->
938
+
<bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a4xx_tile_mode"/>
939
+
<bitfield name="DITHER_MODE" low="9" high="10" type="adreno_rb_dither_mode"/>
940
+
<bitfield name="COLOR_SWAP" low="11" high="12" type="a3xx_color_swap"/>
941
+
<bitfield name="COLOR_SRGB" pos="13" type="boolean"/>
942
+
<!-- note: possibly some # of lsb's aren't there: -->
943
+
<doc>
944
+
Pitch (actually, appears to be pitch in bytes, so really is a stride)
945
+
in GMEM, so pitch of the current tile.
946
+
</doc>
947
+
<bitfield name="COLOR_BUF_PITCH" low="14" high="31" shr="4" type="uint"/>
948
+
</reg32>
949
+
<reg32 offset="0x2" name="BASE"/>
950
+
<reg32 offset="0x3" name="CONTROL3">
951
+
<!-- probably missing some lsb's.. and guessing upper size -->
952
+
<!-- pitch * cpp * msaa: -->
953
+
<bitfield name="STRIDE" low="3" high="25" type="uint"/>
954
+
</reg32>
955
+
<reg32 offset="0x4" name="BLEND_CONTROL">
956
+
<bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
957
+
<bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
958
+
<bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
959
+
<bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
960
+
<bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
961
+
<bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
962
+
</reg32>
963
+
</array>
964
+
965
+
<reg32 offset="0x20f0" name="RB_BLEND_RED">
966
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
967
+
<bitfield name="SINT" low="8" high="15" type="hex"/>
968
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
969
+
</reg32>
970
+
<reg32 offset="0x20f1" name="RB_BLEND_RED_F32" type="float"/>
971
+
972
+
<reg32 offset="0x20f2" name="RB_BLEND_GREEN">
973
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
974
+
<bitfield name="SINT" low="8" high="15" type="hex"/>
975
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
976
+
</reg32>
977
+
<reg32 offset="0x20f3" name="RB_BLEND_GREEN_F32" type="float"/>
978
+
979
+
<reg32 offset="0x20f4" name="RB_BLEND_BLUE">
980
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
981
+
<bitfield name="SINT" low="8" high="15" type="hex"/>
982
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
983
+
</reg32>
984
+
<reg32 offset="0x20f5" name="RB_BLEND_BLUE_F32" type="float"/>
985
+
986
+
<reg32 offset="0x20f6" name="RB_BLEND_ALPHA">
987
+
<bitfield name="UINT" low="0" high="7" type="hex"/>
988
+
<bitfield name="SINT" low="8" high="15" type="hex"/>
989
+
<bitfield name="FLOAT" low="16" high="31" type="float"/>
990
+
</reg32>
991
+
<reg32 offset="0x20f7" name="RB_BLEND_ALPHA_F32" type="float"/>
992
+
993
+
<reg32 offset="0x20f8" name="RB_ALPHA_CONTROL">
994
+
<bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
995
+
<bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
996
+
<bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
997
+
</reg32>
998
+
<reg32 offset="0x20f9" name="RB_FS_OUTPUT">
999
+
<!-- per-mrt enable bit -->
1000
+
<bitfield name="ENABLE_BLEND" low="0" high="7"/>
1001
+
<bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
1002
+
<!-- a guess? -->
1003
+
<bitfield name="SAMPLE_MASK" low="16" high="31"/>
1004
+
</reg32>
1005
+
<reg32 offset="0x20fa" name="RB_SAMPLE_COUNT_CONTROL">
1006
+
<bitfield name="COPY" pos="1" type="boolean"/>
1007
+
<bitfield name="ADDR" low="2" high="31" shr="2"/>
1008
+
</reg32>
1009
+
<!-- always 00000000 for binning pass, else 0000000f: -->
1010
+
<reg32 offset="0x20fb" name="RB_RENDER_COMPONENTS">
1011
+
<bitfield name="RT0" low="0" high="3"/>
1012
+
<bitfield name="RT1" low="4" high="7"/>
1013
+
<bitfield name="RT2" low="8" high="11"/>
1014
+
<bitfield name="RT3" low="12" high="15"/>
1015
+
<bitfield name="RT4" low="16" high="19"/>
1016
+
<bitfield name="RT5" low="20" high="23"/>
1017
+
<bitfield name="RT6" low="24" high="27"/>
1018
+
<bitfield name="RT7" low="28" high="31"/>
1019
+
</reg32>
1020
+
1021
+
<reg32 offset="0x20fc" name="RB_COPY_CONTROL">
1022
+
<!-- not sure # of bits -->
1023
+
<bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
1024
+
<bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
1025
+
<bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
1026
+
<bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
1027
+
</reg32>
1028
+
<reg32 offset="0x20fd" name="RB_COPY_DEST_BASE">
1029
+
<bitfield name="BASE" low="5" high="31" shr="5" type="hex"/>
1030
+
</reg32>
1031
+
<reg32 offset="0x20fe" name="RB_COPY_DEST_PITCH">
1032
+
<doc>actually, appears to be pitch in bytes, so really is a stride</doc>
1033
+
<!-- not actually sure about max pitch... -->
1034
+
<bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
1035
+
</reg32>
1036
+
<reg32 offset="0x20ff" name="RB_COPY_DEST_INFO">
1037
+
<bitfield name="FORMAT" low="2" high="7" type="a4xx_color_fmt"/>
1038
+
<bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
1039
+
<bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
1040
+
<bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
1041
+
<bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
1042
+
<bitfield name="TILE" low="24" high="25" type="a4xx_tile_mode"/>
1043
+
</reg32>
1044
+
<reg32 offset="0x2100" name="RB_FS_OUTPUT_REG">
1045
+
<!-- bit0 set except for binning pass.. -->
1046
+
<bitfield name="MRT" low="0" high="3" type="uint"/>
1047
+
<bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
1048
+
</reg32>
1049
+
<reg32 offset="0x2101" name="RB_DEPTH_CONTROL">
1050
+
<!--
1051
+
guessing that this matches a2xx with the stencil fields
1052
+
moved out into RB_STENCIL_CONTROL?
1053
+
-->
1054
+
<bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1055
+
<bitfield name="Z_TEST_ENABLE" pos="1" type="boolean"/>
1056
+
<bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
1057
+
<bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
1058
+
<bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
1059
+
<bitfield name="EARLY_Z_DISABLE" pos="16" type="boolean"/>
1060
+
<bitfield name="FORCE_FRAGZ_TO_FS" pos="17" type="boolean"/>
1061
+
<doc>Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
1062
+
<bitfield name="Z_READ_ENABLE" pos="31" type="boolean"/>
1063
+
</reg32>
1064
+
<reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/>
1065
+
<reg32 offset="0x2103" name="RB_DEPTH_INFO">
1066
+
<bitfield name="DEPTH_FORMAT" low="0" high="1" type="a4xx_depth_format"/>
1067
+
<doc>
1068
+
DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
1069
+
bin_w * bin_h / 1024 (possible rounded up to multiple of
1070
+
something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
1071
+
80.. so maybe it needs to be multiple of 8??
1072
+
</doc>
1073
+
<bitfield name="DEPTH_BASE" low="12" high="31" shr="12" type="hex"/>
1074
+
</reg32>
1075
+
<reg32 offset="0x2104" name="RB_DEPTH_PITCH" shr="5" type="uint">
1076
+
<doc>stride of depth/stencil buffer</doc>
1077
+
</reg32>
1078
+
<reg32 offset="0x2105" name="RB_DEPTH_PITCH2" shr="5" type="uint">
1079
+
<doc>???</doc>
1080
+
</reg32>
1081
+
<reg32 offset="0x2106" name="RB_STENCIL_CONTROL">
1082
+
<bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1083
+
<bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
1084
+
<!--
1085
+
set for stencil operations that require read from stencil
1086
+
buffer, but not for example for stencil clear (which does
1087
+
not require read).. so guessing this is analogous to
1088
+
READ_DEST_ENABLE for color buffer..
1089
+
-->
1090
+
<bitfield name="STENCIL_READ" pos="2" type="boolean"/>
1091
+
<bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
1092
+
<bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
1093
+
<bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
1094
+
<bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
1095
+
<bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
1096
+
<bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
1097
+
<bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
1098
+
<bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
1099
+
</reg32>
1100
+
<reg32 offset="0x2107" name="RB_STENCIL_CONTROL2">
1101
+
<!--
1102
+
This seems to be set by blob if there is a stencil buffer
1103
+
at all in GMEM, regardless of whether it is enabled for
1104
+
a particular draw (ie. RB_STENCIL_CONTROL). Not really
1105
+
sure if that is required or just a quirk of the blob
1106
+
-->
1107
+
<bitfield name="STENCIL_BUFFER" pos="0" type="boolean"/>
1108
+
</reg32>
1109
+
<reg32 offset="0x2108" name="RB_STENCIL_INFO">
1110
+
<bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
1111
+
<doc>Base address for stencil when not using interleaved depth/stencil</doc>
1112
+
<bitfield name="STENCIL_BASE" low="12" high="31" shr="12" type="hex"/>
1113
+
</reg32>
1114
+
<reg32 offset="0x2109" name="RB_STENCIL_PITCH" shr="5" type="uint">
1115
+
<doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
1116
+
</reg32>
1117
+
1118
+
<reg32 offset="0x210b" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1119
+
<reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1120
+
<reg32 offset="0x210d" name="RB_BIN_OFFSET" type="adreno_reg_xy"/>
1121
+
<array offset="0x2120" name="RB_VPORT_Z_CLAMP" stride="2" length="16">
1122
+
<reg32 offset="0x0" name="MIN"/>
1123
+
<reg32 offset="0x1" name="MAX"/>
1124
+
</array>
1125
+
1126
+
<!-- RBBM registers -->
1127
+
<reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
1128
+
<reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
1129
+
<array offset="0x4" name="RBBM_CLOCK_CTL_TP" stride="1" length="4">
1130
+
<reg32 offset="0x0" name="REG"/>
1131
+
</array>
1132
+
<array offset="0x8" name="RBBM_CLOCK_CTL2_TP" stride="1" length="4">
1133
+
<reg32 offset="0x0" name="REG"/>
1134
+
</array>
1135
+
<array offset="0xc" name="RBBM_CLOCK_HYST_TP" stride="1" length="4">
1136
+
<reg32 offset="0x0" name="REG"/>
1137
+
</array>
1138
+
<array offset="0x10" name="RBBM_CLOCK_DELAY_TP" stride="1" length="4">
1139
+
<reg32 offset="0x0" name="REG"/>
1140
+
</array>
1141
+
<reg32 offset="0x0014" name="RBBM_CLOCK_CTL_UCHE "/>
1142
+
<reg32 offset="0x0015" name="RBBM_CLOCK_CTL2_UCHE"/>
1143
+
<reg32 offset="0x0016" name="RBBM_CLOCK_CTL3_UCHE"/>
1144
+
<reg32 offset="0x0017" name="RBBM_CLOCK_CTL4_UCHE"/>
1145
+
<reg32 offset="0x0018" name="RBBM_CLOCK_HYST_UCHE"/>
1146
+
<reg32 offset="0x0019" name="RBBM_CLOCK_DELAY_UCHE"/>
1147
+
<reg32 offset="0x001a" name="RBBM_CLOCK_MODE_GPC"/>
1148
+
<reg32 offset="0x001b" name="RBBM_CLOCK_DELAY_GPC"/>
1149
+
<reg32 offset="0x001c" name="RBBM_CLOCK_HYST_GPC"/>
1150
+
<reg32 offset="0x001d" name="RBBM_CLOCK_CTL_TSE_RAS_RBBM"/>
1151
+
<reg32 offset="0x001e" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1152
+
<reg32 offset="0x001f" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1153
+
<reg32 offset="0x0020" name="RBBM_CLOCK_CTL"/>
1154
+
<reg32 offset="0x0021" name="RBBM_SP_HYST_CNT"/>
1155
+
<reg32 offset="0x0022" name="RBBM_SW_RESET_CMD"/>
1156
+
<reg32 offset="0x0023" name="RBBM_AHB_CTL0"/>
1157
+
<reg32 offset="0x0024" name="RBBM_AHB_CTL1"/>
1158
+
<reg32 offset="0x0025" name="RBBM_AHB_CMD"/>
1159
+
<reg32 offset="0x0026" name="RBBM_RB_SUB_BLOCK_SEL_CTL"/>
1160
+
<reg32 offset="0x0028" name="RBBM_RAM_ACC_63_32"/>
1161
+
<reg32 offset="0x002b" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
1162
+
<reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CTL"/>
1163
+
<reg32 offset="0x0034" name="RBBM_INTERFACE_HANG_MASK_CTL4"/>
1164
+
<reg32 offset="0x0036" name="RBBM_INT_CLEAR_CMD"/>
1165
+
<reg32 offset="0x0037" name="RBBM_INT_0_MASK"/>
1166
+
<reg32 offset="0x003e" name="RBBM_RBBM_CTL"/>
1167
+
<reg32 offset="0x003f" name="RBBM_AHB_DEBUG_CTL"/>
1168
+
<reg32 offset="0x0041" name="RBBM_VBIF_DEBUG_CTL"/>
1169
+
<reg32 offset="0x0042" name="RBBM_CLOCK_CTL2"/>
1170
+
<reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1171
+
<reg32 offset="0x0047" name="RBBM_RESET_CYCLES"/>
1172
+
<reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CTL"/>
1173
+
<reg32 offset="0x004a" name="RBBM_CFG_DEBBUS_SEL_A"/>
1174
+
<reg32 offset="0x004b" name="RBBM_CFG_DEBBUS_SEL_B"/>
1175
+
<reg32 offset="0x004c" name="RBBM_CFG_DEBBUS_SEL_C"/>
1176
+
<reg32 offset="0x004d" name="RBBM_CFG_DEBBUS_SEL_D"/>
1177
+
<reg32 offset="0x0098" name="RBBM_POWER_CNTL_IP">
1178
+
<bitfield name="SW_COLLAPSE" pos="0" type="boolean"/>
1179
+
<bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
1180
+
</reg32>
1181
+
<reg32 offset="0x009c" name="RBBM_PERFCTR_CP_0_LO"/>
1182
+
<reg32 offset="0x009d" name="RBBM_PERFCTR_CP_0_HI"/>
1183
+
<reg32 offset="0x009e" name="RBBM_PERFCTR_CP_1_LO"/>
1184
+
<reg32 offset="0x009f" name="RBBM_PERFCTR_CP_1_HI"/>
1185
+
<reg32 offset="0x00a0" name="RBBM_PERFCTR_CP_2_LO"/>
1186
+
<reg32 offset="0x00a1" name="RBBM_PERFCTR_CP_2_HI"/>
1187
+
<reg32 offset="0x00a2" name="RBBM_PERFCTR_CP_3_LO"/>
1188
+
<reg32 offset="0x00a3" name="RBBM_PERFCTR_CP_3_HI"/>
1189
+
<reg32 offset="0x00a4" name="RBBM_PERFCTR_CP_4_LO"/>
1190
+
<reg32 offset="0x00a5" name="RBBM_PERFCTR_CP_4_HI"/>
1191
+
<reg32 offset="0x00a6" name="RBBM_PERFCTR_CP_5_LO"/>
1192
+
<reg32 offset="0x00a7" name="RBBM_PERFCTR_CP_5_HI"/>
1193
+
<reg32 offset="0x00a8" name="RBBM_PERFCTR_CP_6_LO"/>
1194
+
<reg32 offset="0x00a9" name="RBBM_PERFCTR_CP_6_HI"/>
1195
+
<reg32 offset="0x00aa" name="RBBM_PERFCTR_CP_7_LO"/>
1196
+
<reg32 offset="0x00ab" name="RBBM_PERFCTR_CP_7_HI"/>
1197
+
<reg32 offset="0x00ac" name="RBBM_PERFCTR_RBBM_0_LO"/>
1198
+
<reg32 offset="0x00ad" name="RBBM_PERFCTR_RBBM_0_HI"/>
1199
+
<reg32 offset="0x00ae" name="RBBM_PERFCTR_RBBM_1_LO"/>
1200
+
<reg32 offset="0x00af" name="RBBM_PERFCTR_RBBM_1_HI"/>
1201
+
<reg32 offset="0x00b0" name="RBBM_PERFCTR_RBBM_2_LO"/>
1202
+
<reg32 offset="0x00b1" name="RBBM_PERFCTR_RBBM_2_HI"/>
1203
+
<reg32 offset="0x00b2" name="RBBM_PERFCTR_RBBM_3_LO"/>
1204
+
<reg32 offset="0x00b3" name="RBBM_PERFCTR_RBBM_3_HI"/>
1205
+
<reg32 offset="0x00b4" name="RBBM_PERFCTR_PC_0_LO"/>
1206
+
<reg32 offset="0x00b5" name="RBBM_PERFCTR_PC_0_HI"/>
1207
+
<reg32 offset="0x00b6" name="RBBM_PERFCTR_PC_1_LO"/>
1208
+
<reg32 offset="0x00b7" name="RBBM_PERFCTR_PC_1_HI"/>
1209
+
<reg32 offset="0x00b8" name="RBBM_PERFCTR_PC_2_LO"/>
1210
+
<reg32 offset="0x00b9" name="RBBM_PERFCTR_PC_2_HI"/>
1211
+
<reg32 offset="0x00ba" name="RBBM_PERFCTR_PC_3_LO"/>
1212
+
<reg32 offset="0x00bb" name="RBBM_PERFCTR_PC_3_HI"/>
1213
+
<reg32 offset="0x00bc" name="RBBM_PERFCTR_PC_4_LO"/>
1214
+
<reg32 offset="0x00bd" name="RBBM_PERFCTR_PC_4_HI"/>
1215
+
<reg32 offset="0x00be" name="RBBM_PERFCTR_PC_5_LO"/>
1216
+
<reg32 offset="0x00bf" name="RBBM_PERFCTR_PC_5_HI"/>
1217
+
<reg32 offset="0x00c0" name="RBBM_PERFCTR_PC_6_LO"/>
1218
+
<reg32 offset="0x00c1" name="RBBM_PERFCTR_PC_6_HI"/>
1219
+
<reg32 offset="0x00c2" name="RBBM_PERFCTR_PC_7_LO"/>
1220
+
<reg32 offset="0x00c3" name="RBBM_PERFCTR_PC_7_HI"/>
1221
+
<reg32 offset="0x00c4" name="RBBM_PERFCTR_VFD_0_LO"/>
1222
+
<reg32 offset="0x00c5" name="RBBM_PERFCTR_VFD_0_HI"/>
1223
+
<reg32 offset="0x00c6" name="RBBM_PERFCTR_VFD_1_LO"/>
1224
+
<reg32 offset="0x00c7" name="RBBM_PERFCTR_VFD_1_HI"/>
1225
+
<reg32 offset="0x00c8" name="RBBM_PERFCTR_VFD_2_LO"/>
1226
+
<reg32 offset="0x00c9" name="RBBM_PERFCTR_VFD_2_HI"/>
1227
+
<reg32 offset="0x00ca" name="RBBM_PERFCTR_VFD_3_LO"/>
1228
+
<reg32 offset="0x00cb" name="RBBM_PERFCTR_VFD_3_HI"/>
1229
+
<reg32 offset="0x00cc" name="RBBM_PERFCTR_VFD_4_LO"/>
1230
+
<reg32 offset="0x00cd" name="RBBM_PERFCTR_VFD_4_HI"/>
1231
+
<reg32 offset="0x00ce" name="RBBM_PERFCTR_VFD_5_LO"/>
1232
+
<reg32 offset="0x00cf" name="RBBM_PERFCTR_VFD_5_HI"/>
1233
+
<reg32 offset="0x00d0" name="RBBM_PERFCTR_VFD_6_LO"/>
1234
+
<reg32 offset="0x00d1" name="RBBM_PERFCTR_VFD_6_HI"/>
1235
+
<reg32 offset="0x00d2" name="RBBM_PERFCTR_VFD_7_LO"/>
1236
+
<reg32 offset="0x00d3" name="RBBM_PERFCTR_VFD_7_HI"/>
1237
+
<reg32 offset="0x00d4" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1238
+
<reg32 offset="0x00d5" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1239
+
<reg32 offset="0x00d6" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1240
+
<reg32 offset="0x00d7" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1241
+
<reg32 offset="0x00d8" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1242
+
<reg32 offset="0x00d9" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1243
+
<reg32 offset="0x00da" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1244
+
<reg32 offset="0x00db" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1245
+
<reg32 offset="0x00dc" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1246
+
<reg32 offset="0x00dd" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1247
+
<reg32 offset="0x00de" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1248
+
<reg32 offset="0x00df" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1249
+
<reg32 offset="0x00e0" name="RBBM_PERFCTR_HLSQ_6_LO"/>
1250
+
<reg32 offset="0x00e1" name="RBBM_PERFCTR_HLSQ_6_HI"/>
1251
+
<reg32 offset="0x00e2" name="RBBM_PERFCTR_HLSQ_7_LO"/>
1252
+
<reg32 offset="0x00e3" name="RBBM_PERFCTR_HLSQ_7_HI"/>
1253
+
<reg32 offset="0x00e4" name="RBBM_PERFCTR_VPC_0_LO"/>
1254
+
<reg32 offset="0x00e5" name="RBBM_PERFCTR_VPC_0_HI"/>
1255
+
<reg32 offset="0x00e6" name="RBBM_PERFCTR_VPC_1_LO"/>
1256
+
<reg32 offset="0x00e7" name="RBBM_PERFCTR_VPC_1_HI"/>
1257
+
<reg32 offset="0x00e8" name="RBBM_PERFCTR_VPC_2_LO"/>
1258
+
<reg32 offset="0x00e9" name="RBBM_PERFCTR_VPC_2_HI"/>
1259
+
<reg32 offset="0x00ea" name="RBBM_PERFCTR_VPC_3_LO"/>
1260
+
<reg32 offset="0x00eb" name="RBBM_PERFCTR_VPC_3_HI"/>
1261
+
<reg32 offset="0x00ec" name="RBBM_PERFCTR_CCU_0_LO"/>
1262
+
<reg32 offset="0x00ed" name="RBBM_PERFCTR_CCU_0_HI"/>
1263
+
<reg32 offset="0x00ee" name="RBBM_PERFCTR_CCU_1_LO"/>
1264
+
<reg32 offset="0x00ef" name="RBBM_PERFCTR_CCU_1_HI"/>
1265
+
<reg32 offset="0x00f0" name="RBBM_PERFCTR_CCU_2_LO"/>
1266
+
<reg32 offset="0x00f1" name="RBBM_PERFCTR_CCU_2_HI"/>
1267
+
<reg32 offset="0x00f2" name="RBBM_PERFCTR_CCU_3_LO"/>
1268
+
<reg32 offset="0x00f3" name="RBBM_PERFCTR_CCU_3_HI"/>
1269
+
<reg32 offset="0x00f4" name="RBBM_PERFCTR_TSE_0_LO"/>
1270
+
<reg32 offset="0x00f5" name="RBBM_PERFCTR_TSE_0_HI"/>
1271
+
<reg32 offset="0x00f6" name="RBBM_PERFCTR_TSE_1_LO"/>
1272
+
<reg32 offset="0x00f7" name="RBBM_PERFCTR_TSE_1_HI"/>
1273
+
<reg32 offset="0x00f8" name="RBBM_PERFCTR_TSE_2_LO"/>
1274
+
<reg32 offset="0x00f9" name="RBBM_PERFCTR_TSE_2_HI"/>
1275
+
<reg32 offset="0x00fa" name="RBBM_PERFCTR_TSE_3_LO"/>
1276
+
<reg32 offset="0x00fb" name="RBBM_PERFCTR_TSE_3_HI"/>
1277
+
<reg32 offset="0x00fc" name="RBBM_PERFCTR_RAS_0_LO"/>
1278
+
<reg32 offset="0x00fd" name="RBBM_PERFCTR_RAS_0_HI"/>
1279
+
<reg32 offset="0x00fe" name="RBBM_PERFCTR_RAS_1_LO"/>
1280
+
<reg32 offset="0x00ff" name="RBBM_PERFCTR_RAS_1_HI"/>
1281
+
<reg32 offset="0x0100" name="RBBM_PERFCTR_RAS_2_LO"/>
1282
+
<reg32 offset="0x0101" name="RBBM_PERFCTR_RAS_2_HI"/>
1283
+
<reg32 offset="0x0102" name="RBBM_PERFCTR_RAS_3_LO"/>
1284
+
<reg32 offset="0x0103" name="RBBM_PERFCTR_RAS_3_HI"/>
1285
+
<reg32 offset="0x0104" name="RBBM_PERFCTR_UCHE_0_LO"/>
1286
+
<reg32 offset="0x0105" name="RBBM_PERFCTR_UCHE_0_HI"/>
1287
+
<reg32 offset="0x0106" name="RBBM_PERFCTR_UCHE_1_LO"/>
1288
+
<reg32 offset="0x0107" name="RBBM_PERFCTR_UCHE_1_HI"/>
1289
+
<reg32 offset="0x0108" name="RBBM_PERFCTR_UCHE_2_LO"/>
1290
+
<reg32 offset="0x0109" name="RBBM_PERFCTR_UCHE_2_HI"/>
1291
+
<reg32 offset="0x010a" name="RBBM_PERFCTR_UCHE_3_LO"/>
1292
+
<reg32 offset="0x010b" name="RBBM_PERFCTR_UCHE_3_HI"/>
1293
+
<reg32 offset="0x010c" name="RBBM_PERFCTR_UCHE_4_LO"/>
1294
+
<reg32 offset="0x010d" name="RBBM_PERFCTR_UCHE_4_HI"/>
1295
+
<reg32 offset="0x010e" name="RBBM_PERFCTR_UCHE_5_LO"/>
1296
+
<reg32 offset="0x010f" name="RBBM_PERFCTR_UCHE_5_HI"/>
1297
+
<reg32 offset="0x0110" name="RBBM_PERFCTR_UCHE_6_LO"/>
1298
+
<reg32 offset="0x0111" name="RBBM_PERFCTR_UCHE_6_HI"/>
1299
+
<reg32 offset="0x0112" name="RBBM_PERFCTR_UCHE_7_LO"/>
1300
+
<reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/>
1301
+
<reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
1302
+
<reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
1303
+
<reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/>
1304
+
<reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/>
1305
+
<reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/>
1306
+
<reg32 offset="0x0119" name="RBBM_PERFCTR_TP_2_HI"/>
1307
+
<reg32 offset="0x011a" name="RBBM_PERFCTR_TP_3_LO"/>
1308
+
<reg32 offset="0x011b" name="RBBM_PERFCTR_TP_3_HI"/>
1309
+
<reg32 offset="0x011c" name="RBBM_PERFCTR_TP_4_LO"/>
1310
+
<reg32 offset="0x011d" name="RBBM_PERFCTR_TP_4_HI"/>
1311
+
<reg32 offset="0x011e" name="RBBM_PERFCTR_TP_5_LO"/>
1312
+
<reg32 offset="0x011f" name="RBBM_PERFCTR_TP_5_HI"/>
1313
+
<reg32 offset="0x0120" name="RBBM_PERFCTR_TP_6_LO"/>
1314
+
<reg32 offset="0x0121" name="RBBM_PERFCTR_TP_6_HI"/>
1315
+
<reg32 offset="0x0122" name="RBBM_PERFCTR_TP_7_LO"/>
1316
+
<reg32 offset="0x0123" name="RBBM_PERFCTR_TP_7_HI"/>
1317
+
<reg32 offset="0x0124" name="RBBM_PERFCTR_SP_0_LO"/>
1318
+
<reg32 offset="0x0125" name="RBBM_PERFCTR_SP_0_HI"/>
1319
+
<reg32 offset="0x0126" name="RBBM_PERFCTR_SP_1_LO"/>
1320
+
<reg32 offset="0x0127" name="RBBM_PERFCTR_SP_1_HI"/>
1321
+
<reg32 offset="0x0128" name="RBBM_PERFCTR_SP_2_LO"/>
1322
+
<reg32 offset="0x0129" name="RBBM_PERFCTR_SP_2_HI"/>
1323
+
<reg32 offset="0x012a" name="RBBM_PERFCTR_SP_3_LO"/>
1324
+
<reg32 offset="0x012b" name="RBBM_PERFCTR_SP_3_HI"/>
1325
+
<reg32 offset="0x012c" name="RBBM_PERFCTR_SP_4_LO"/>
1326
+
<reg32 offset="0x012d" name="RBBM_PERFCTR_SP_4_HI"/>
1327
+
<reg32 offset="0x012e" name="RBBM_PERFCTR_SP_5_LO"/>
1328
+
<reg32 offset="0x012f" name="RBBM_PERFCTR_SP_5_HI"/>
1329
+
<reg32 offset="0x0130" name="RBBM_PERFCTR_SP_6_LO"/>
1330
+
<reg32 offset="0x0131" name="RBBM_PERFCTR_SP_6_HI"/>
1331
+
<reg32 offset="0x0132" name="RBBM_PERFCTR_SP_7_LO"/>
1332
+
<reg32 offset="0x0133" name="RBBM_PERFCTR_SP_7_HI"/>
1333
+
<reg32 offset="0x0134" name="RBBM_PERFCTR_SP_8_LO"/>
1334
+
<reg32 offset="0x0135" name="RBBM_PERFCTR_SP_8_HI"/>
1335
+
<reg32 offset="0x0136" name="RBBM_PERFCTR_SP_9_LO"/>
1336
+
<reg32 offset="0x0137" name="RBBM_PERFCTR_SP_9_HI"/>
1337
+
<reg32 offset="0x0138" name="RBBM_PERFCTR_SP_10_LO"/>
1338
+
<reg32 offset="0x0139" name="RBBM_PERFCTR_SP_10_HI"/>
1339
+
<reg32 offset="0x013a" name="RBBM_PERFCTR_SP_11_LO"/>
1340
+
<reg32 offset="0x013b" name="RBBM_PERFCTR_SP_11_HI"/>
1341
+
<reg32 offset="0x013c" name="RBBM_PERFCTR_RB_0_LO"/>
1342
+
<reg32 offset="0x013d" name="RBBM_PERFCTR_RB_0_HI"/>
1343
+
<reg32 offset="0x013e" name="RBBM_PERFCTR_RB_1_LO"/>
1344
+
<reg32 offset="0x013f" name="RBBM_PERFCTR_RB_1_HI"/>
1345
+
<reg32 offset="0x0140" name="RBBM_PERFCTR_RB_2_LO"/>
1346
+
<reg32 offset="0x0141" name="RBBM_PERFCTR_RB_2_HI"/>
1347
+
<reg32 offset="0x0142" name="RBBM_PERFCTR_RB_3_LO"/>
1348
+
<reg32 offset="0x0143" name="RBBM_PERFCTR_RB_3_HI"/>
1349
+
<reg32 offset="0x0144" name="RBBM_PERFCTR_RB_4_LO"/>
1350
+
<reg32 offset="0x0145" name="RBBM_PERFCTR_RB_4_HI"/>
1351
+
<reg32 offset="0x0146" name="RBBM_PERFCTR_RB_5_LO"/>
1352
+
<reg32 offset="0x0147" name="RBBM_PERFCTR_RB_5_HI"/>
1353
+
<reg32 offset="0x0148" name="RBBM_PERFCTR_RB_6_LO"/>
1354
+
<reg32 offset="0x0149" name="RBBM_PERFCTR_RB_6_HI"/>
1355
+
<reg32 offset="0x014a" name="RBBM_PERFCTR_RB_7_LO"/>
1356
+
<reg32 offset="0x014b" name="RBBM_PERFCTR_RB_7_HI"/>
1357
+
<reg32 offset="0x014c" name="RBBM_PERFCTR_VSC_0_LO"/>
1358
+
<reg32 offset="0x014d" name="RBBM_PERFCTR_VSC_0_HI"/>
1359
+
<reg32 offset="0x014e" name="RBBM_PERFCTR_VSC_1_LO"/>
1360
+
<reg32 offset="0x014f" name="RBBM_PERFCTR_VSC_1_HI"/>
1361
+
<reg32 offset="0x0166" name="RBBM_PERFCTR_PWR_0_LO"/>
1362
+
<reg32 offset="0x0167" name="RBBM_PERFCTR_PWR_0_HI"/>
1363
+
<reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/>
1364
+
<reg32 offset="0x0169" name="RBBM_PERFCTR_PWR_1_HI"/>
1365
+
<reg32 offset="0x016e" name="RBBM_ALWAYSON_COUNTER_LO"/>
1366
+
<reg32 offset="0x016f" name="RBBM_ALWAYSON_COUNTER_HI"/>
1367
+
<array offset="0x0068" name="RBBM_CLOCK_CTL_SP" stride="1" length="4">
1368
+
<reg32 offset="0x0" name="REG"/>
1369
+
</array>
1370
+
<array offset="0x006c" name="RBBM_CLOCK_CTL2_SP" stride="1" length="4">
1371
+
<reg32 offset="0x0" name="REG"/>
1372
+
</array>
1373
+
<array offset="0x0070" name="RBBM_CLOCK_HYST_SP" stride="1" length="4">
1374
+
<reg32 offset="0x0" name="REG"/>
1375
+
</array>
1376
+
<array offset="0x0074" name="RBBM_CLOCK_DELAY_SP" stride="1" length="4">
1377
+
<reg32 offset="0x0" name="REG"/>
1378
+
</array>
1379
+
<array offset="0x0078" name="RBBM_CLOCK_CTL_RB" stride="1" length="4">
1380
+
<reg32 offset="0x0" name="REG"/>
1381
+
</array>
1382
+
<array offset="0x007c" name="RBBM_CLOCK_CTL2_RB" stride="1" length="4">
1383
+
<reg32 offset="0x0" name="REG"/>
1384
+
</array>
1385
+
<array offset="0x0082" name="RBBM_CLOCK_CTL_MARB_CCU" stride="1" length="4">
1386
+
<reg32 offset="0x0" name="REG"/>
1387
+
</array>
1388
+
<array offset="0x0086" name="RBBM_CLOCK_HYST_RB_MARB_CCU" stride="1" length="4">
1389
+
<reg32 offset="0x0" name="REG"/>
1390
+
</array>
1391
+
<reg32 offset="0x0080" name="RBBM_CLOCK_HYST_COM_DCOM"/>
1392
+
<reg32 offset="0x0081" name="RBBM_CLOCK_CTL_COM_DCOM"/>
1393
+
<reg32 offset="0x008a" name="RBBM_CLOCK_CTL_HLSQ"/>
1394
+
<reg32 offset="0x008b" name="RBBM_CLOCK_HYST_HLSQ"/>
1395
+
<reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1396
+
<bitset name="A4XX_CGC_HLSQ">
1397
+
<bitfield name="EARLY_CYC" low="20" high="22" type="uint"/>
1398
+
</bitset>
1399
+
<reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_COM_DCOM"/>
1400
+
<array offset="0x008e" name="RBBM_CLOCK_DELAY_RB_MARB_CCU_L1" stride="1" length="4">
1401
+
<reg32 offset="0x0" name="REG"/>
1402
+
</array>
1403
+
<bitset name="A4XX_INT0">
1404
+
<bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
1405
+
<bitfield name="RBBM_AHB_ERROR" pos="1" type="boolean"/>
1406
+
<bitfield name="RBBM_REG_TIMEOUT" pos="2" type="boolean"/>
1407
+
<bitfield name="RBBM_ME_MS_TIMEOUT" pos="3" type="boolean"/>
1408
+
<bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4" type="boolean"/>
1409
+
<bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5" type="boolean"/>
1410
+
<bitfield name="VFD_ERROR" pos="6" type="boolean"/>
1411
+
<bitfield name="CP_SW_INT" pos="7" type="boolean"/>
1412
+
<bitfield name="CP_T0_PACKET_IN_IB" pos="8" type="boolean"/>
1413
+
<bitfield name="CP_OPCODE_ERROR" pos="9" type="boolean"/>
1414
+
<bitfield name="CP_RESERVED_BIT_ERROR" pos="10" type="boolean"/>
1415
+
<bitfield name="CP_HW_FAULT" pos="11" type="boolean"/>
1416
+
<bitfield name="CP_DMA" pos="12" type="boolean"/>
1417
+
<bitfield name="CP_IB2_INT" pos="13" type="boolean"/>
1418
+
<bitfield name="CP_IB1_INT" pos="14" type="boolean"/>
1419
+
<bitfield name="CP_RB_INT" pos="15" type="boolean"/>
1420
+
<bitfield name="CP_REG_PROTECT_FAULT" pos="16" type="boolean"/>
1421
+
<bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
1422
+
<bitfield name="CP_VS_DONE_TS" pos="18" type="boolean"/>
1423
+
<bitfield name="CP_PS_DONE_TS" pos="19" type="boolean"/>
1424
+
<bitfield name="CACHE_FLUSH_TS" pos="20" type="boolean"/>
1425
+
<bitfield name="CP_AHB_ERROR_HALT" pos="21" type="boolean"/>
1426
+
<bitfield name="MISC_HANG_DETECT" pos="24" type="boolean"/>
1427
+
<bitfield name="UCHE_OOB_ACCESS" pos="25" type="boolean"/>
1428
+
</bitset>
1429
+
1430
+
<reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/>
1431
+
<reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/>
1432
+
<reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/>
1433
+
<reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/>
1434
+
<reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/>
1435
+
<reg32 offset="0x0173" name="RBBM_PERFCTR_LOAD_CMD2"/>
1436
+
<reg32 offset="0x0174" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1437
+
<reg32 offset="0x0175" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1438
+
<reg32 offset="0x0176" name="RBBM_PERFCTR_RBBM_SEL_0" type="a4xx_rbbm_perfcounter_select"/>
1439
+
<reg32 offset="0x0177" name="RBBM_PERFCTR_RBBM_SEL_1" type="a4xx_rbbm_perfcounter_select"/>
1440
+
<reg32 offset="0x0178" name="RBBM_PERFCTR_RBBM_SEL_2" type="a4xx_rbbm_perfcounter_select"/>
1441
+
<reg32 offset="0x0179" name="RBBM_PERFCTR_RBBM_SEL_3" type="a4xx_rbbm_perfcounter_select"/>
1442
+
<reg32 offset="0x017a" name="RBBM_GPU_BUSY_MASKED"/>
1443
+
<reg32 offset="0x017d" name="RBBM_INT_0_STATUS"/>
1444
+
<reg32 offset="0x0182" name="RBBM_CLOCK_STATUS"/>
1445
+
<reg32 offset="0x0189" name="RBBM_AHB_STATUS"/>
1446
+
<reg32 offset="0x018c" name="RBBM_AHB_ME_SPLIT_STATUS"/>
1447
+
<reg32 offset="0x018d" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
1448
+
<reg32 offset="0x018f" name="RBBM_AHB_ERROR_STATUS"/>
1449
+
<reg32 offset="0x0191" name="RBBM_STATUS">
1450
+
<bitfield name="HI_BUSY" pos="0" type="boolean"/>
1451
+
<bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
1452
+
<bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
1453
+
<bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
1454
+
<bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
1455
+
<bitfield name="TSE_BUSY" pos="16" type="boolean"/>
1456
+
<bitfield name="RAS_BUSY" pos="17" type="boolean"/>
1457
+
<bitfield name="RB_BUSY" pos="18" type="boolean"/>
1458
+
<bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
1459
+
<bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
1460
+
<bitfield name="VFD_BUSY" pos="21" type="boolean"/>
1461
+
<bitfield name="VPC_BUSY" pos="22" type="boolean"/>
1462
+
<bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
1463
+
<bitfield name="SP_BUSY" pos="24" type="boolean"/>
1464
+
<bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
1465
+
<bitfield name="MARB_BUSY" pos="26" type="boolean"/>
1466
+
<bitfield name="VSC_BUSY" pos="27" type="boolean"/>
1467
+
<bitfield name="ARB_BUSY" pos="28" type="boolean"/>
1468
+
<bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
1469
+
<bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
1470
+
<bitfield name="GPU_BUSY" pos="31" type="boolean"/>
1471
+
</reg32>
1472
+
<reg32 offset="0x019f" name="RBBM_INTERFACE_RRDY_STATUS5"/>
1473
+
<reg32 offset="0x01b0" name="RBBM_POWER_STATUS">
1474
+
<bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
1475
+
</reg32>
1476
+
<reg32 offset="0x01b8" name="RBBM_WAIT_IDLE_CLOCKS_CTL2"/>
1477
+
1478
+
<!-- CP registers -->
1479
+
<reg32 offset="0x0228" name="CP_SCRATCH_UMASK"/>
1480
+
<reg32 offset="0x0229" name="CP_SCRATCH_ADDR"/>
1481
+
<reg32 offset="0x0200" name="CP_RB_BASE"/>
1482
+
<reg32 offset="0x0201" name="CP_RB_CNTL"/>
1483
+
<reg32 offset="0x0205" name="CP_RB_WPTR"/>
1484
+
<reg32 offset="0x0203" name="CP_RB_RPTR_ADDR"/>
1485
+
<reg32 offset="0x0204" name="CP_RB_RPTR"/>
1486
+
<reg32 offset="0x0206" name="CP_IB1_BASE"/>
1487
+
<reg32 offset="0x0207" name="CP_IB1_BUFSZ"/>
1488
+
<reg32 offset="0x0208" name="CP_IB2_BASE"/>
1489
+
<reg32 offset="0x0209" name="CP_IB2_BUFSZ"/>
1490
+
<reg32 offset="0x020c" name="CP_ME_NRT_ADDR"/>
1491
+
<reg32 offset="0x020d" name="CP_ME_NRT_DATA"/>
1492
+
<reg32 offset="0x0217" name="CP_ME_RB_DONE_DATA"/>
1493
+
<reg32 offset="0x0219" name="CP_QUEUE_THRESH2"/>
1494
+
<reg32 offset="0x021b" name="CP_MERCIU_SIZE"/>
1495
+
<reg32 offset="0x021c" name="CP_ROQ_ADDR"/>
1496
+
<reg32 offset="0x021d" name="CP_ROQ_DATA"/>
1497
+
<reg32 offset="0x021e" name="CP_MEQ_ADDR"/>
1498
+
<reg32 offset="0x021f" name="CP_MEQ_DATA"/>
1499
+
<reg32 offset="0x0220" name="CP_MERCIU_ADDR"/>
1500
+
<reg32 offset="0x0221" name="CP_MERCIU_DATA"/>
1501
+
<reg32 offset="0x0222" name="CP_MERCIU_DATA2"/>
1502
+
<reg32 offset="0x0223" name="CP_PFP_UCODE_ADDR"/>
1503
+
<reg32 offset="0x0224" name="CP_PFP_UCODE_DATA"/>
1504
+
<reg32 offset="0x0225" name="CP_ME_RAM_WADDR"/>
1505
+
<reg32 offset="0x0226" name="CP_ME_RAM_RADDR"/>
1506
+
<reg32 offset="0x0227" name="CP_ME_RAM_DATA"/>
1507
+
<reg32 offset="0x022a" name="CP_PREEMPT"/>
1508
+
<reg32 offset="0x022c" name="CP_CNTL"/>
1509
+
<reg32 offset="0x022d" name="CP_ME_CNTL"/>
1510
+
<reg32 offset="0x022e" name="CP_DEBUG"/>
1511
+
<reg32 offset="0x0231" name="CP_DEBUG_ECO_CONTROL"/>
1512
+
<reg32 offset="0x0232" name="CP_DRAW_STATE_ADDR"/>
1513
+
<array offset="0x0240" name="CP_PROTECT" stride="1" length="16">
1514
+
<reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
1515
+
</array>
1516
+
<reg32 offset="0x0250" name="CP_PROTECT_CTRL"/>
1517
+
<reg32 offset="0x04c0" name="CP_ST_BASE"/>
1518
+
<reg32 offset="0x04ce" name="CP_STQ_AVAIL"/>
1519
+
<reg32 offset="0x04d0" name="CP_MERCIU_STAT"/>
1520
+
<reg32 offset="0x04d2" name="CP_WFI_PEND_CTR"/>
1521
+
<reg32 offset="0x04d8" name="CP_HW_FAULT"/>
1522
+
<reg32 offset="0x04da" name="CP_PROTECT_STATUS"/>
1523
+
<reg32 offset="0x04dd" name="CP_EVENTS_IN_FLIGHT"/>
1524
+
<reg32 offset="0x0500" name="CP_PERFCTR_CP_SEL_0" type="a4xx_cp_perfcounter_select"/>
1525
+
<reg32 offset="0x0501" name="CP_PERFCTR_CP_SEL_1" type="a4xx_cp_perfcounter_select"/>
1526
+
<reg32 offset="0x0502" name="CP_PERFCTR_CP_SEL_2" type="a4xx_cp_perfcounter_select"/>
1527
+
<reg32 offset="0x0503" name="CP_PERFCTR_CP_SEL_3" type="a4xx_cp_perfcounter_select"/>
1528
+
<reg32 offset="0x0504" name="CP_PERFCTR_CP_SEL_4" type="a4xx_cp_perfcounter_select"/>
1529
+
<reg32 offset="0x0505" name="CP_PERFCTR_CP_SEL_5" type="a4xx_cp_perfcounter_select"/>
1530
+
<reg32 offset="0x0506" name="CP_PERFCTR_CP_SEL_6" type="a4xx_cp_perfcounter_select"/>
1531
+
<reg32 offset="0x0507" name="CP_PERFCTR_CP_SEL_7" type="a4xx_cp_perfcounter_select"/>
1532
+
<reg32 offset="0x050b" name="CP_PERFCOMBINER_SELECT"/>
1533
+
<array offset="0x0578" name="CP_SCRATCH" stride="1" length="23">
1534
+
<reg32 offset="0x0" name="REG"/>
1535
+
</array>
1536
+
1537
+
1538
+
<!-- SP registers -->
1539
+
<reg32 offset="0x0ec0" name="SP_VS_STATUS"/>
1540
+
<reg32 offset="0x0ec3" name="SP_MODE_CONTROL"/>
1541
+
1542
+
<reg32 offset="0x0ec4" name="SP_PERFCTR_SP_SEL_0" type="a4xx_sp_perfcounter_select"/>
1543
+
<reg32 offset="0x0ec5" name="SP_PERFCTR_SP_SEL_1" type="a4xx_sp_perfcounter_select"/>
1544
+
<reg32 offset="0x0ec6" name="SP_PERFCTR_SP_SEL_2" type="a4xx_sp_perfcounter_select"/>
1545
+
<reg32 offset="0x0ec7" name="SP_PERFCTR_SP_SEL_3" type="a4xx_sp_perfcounter_select"/>
1546
+
<reg32 offset="0x0ec8" name="SP_PERFCTR_SP_SEL_4" type="a4xx_sp_perfcounter_select"/>
1547
+
<reg32 offset="0x0ec9" name="SP_PERFCTR_SP_SEL_5" type="a4xx_sp_perfcounter_select"/>
1548
+
<reg32 offset="0x0eca" name="SP_PERFCTR_SP_SEL_6" type="a4xx_sp_perfcounter_select"/>
1549
+
<reg32 offset="0x0ecb" name="SP_PERFCTR_SP_SEL_7" type="a4xx_sp_perfcounter_select"/>
1550
+
<reg32 offset="0x0ecc" name="SP_PERFCTR_SP_SEL_8" type="a4xx_sp_perfcounter_select"/>
1551
+
<reg32 offset="0x0ecd" name="SP_PERFCTR_SP_SEL_9" type="a4xx_sp_perfcounter_select"/>
1552
+
<reg32 offset="0x0ece" name="SP_PERFCTR_SP_SEL_10" type="a4xx_sp_perfcounter_select"/>
1553
+
<reg32 offset="0x0ecf" name="SP_PERFCTR_SP_SEL_11" type="a4xx_sp_perfcounter_select"/>
1554
+
1555
+
<reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
1556
+
<bitfield name="BINNING_PASS" pos="19" type="boolean"/>
1557
+
</reg32>
1558
+
<reg32 offset="0x22c1" name="SP_INSTR_CACHE_CTRL">
1559
+
<!-- set when VS in buffer mode: -->
1560
+
<bitfield name="VS_BUFFER" pos="7" type="boolean"/>
1561
+
<!-- set when FS in buffer mode: -->
1562
+
<bitfield name="FS_BUFFER" pos="8" type="boolean"/>
1563
+
<!-- set when both VS or FS in buffer mode: -->
1564
+
<bitfield name="INSTR_BUFFER" pos="10" type="boolean"/>
1565
+
<!-- TODO other bits probably matter when other stages active? -->
1566
+
</reg32>
1567
+
1568
+
<bitset name="a4xx_sp_vs_fs_ctrl_reg0" inline="yes">
1569
+
<!--
1570
+
NOTE that SP_{VS,FS}_CTRL_REG1 are different, but so far REG0
1571
+
appears to be the same..
1572
+
-->
1573
+
<bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1574
+
<!-- VARYING bit only for FS.. think it controls emitting (ei) flag? -->
1575
+
<bitfield name="VARYING" pos="1" type="boolean"/>
1576
+
<!-- maybe CACHEINVALID is two bits?? -->
1577
+
<bitfield name="CACHEINVALID" pos="2" type="boolean"/>
1578
+
<doc>
1579
+
The full/half register footprint is in units of four components,
1580
+
so if r0.x is used, that counts as all of r0.[xyzw] as used.
1581
+
There are separate full/half register footprint values as the
1582
+
full and half registers are independent (not overlapping).
1583
+
Presumably the thread scheduler hardware allocates the full/half
1584
+
register names from the actual physical register file and
1585
+
handles the register renaming.
1586
+
</doc>
1587
+
<bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
1588
+
<bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
1589
+
<!-- maybe INOUTREGOVERLAP is a bitflag? -->
1590
+
<bitfield name="INOUTREGOVERLAP" low="18" high="19" type="uint"/>
1591
+
<bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
1592
+
<bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
1593
+
<bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
1594
+
</bitset>
1595
+
1596
+
<reg32 offset="0x22c4" name="SP_VS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1597
+
<reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
1598
+
<bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
1599
+
<bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
1600
+
</reg32>
1601
+
<reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
1602
+
<bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1603
+
<bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
1604
+
<bitfield name="TOTALVSOUTVAR" low="20" high="31" type="uint"/>
1605
+
</reg32>
1606
+
<array offset="0x22c7" name="SP_VS_OUT" stride="1" length="16">
1607
+
<reg32 offset="0x0" name="REG">
1608
+
<bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1609
+
<bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1610
+
<bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
1611
+
<bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1612
+
</reg32>
1613
+
</array>
1614
+
<array offset="0x22d8" name="SP_VS_VPC_DST" stride="1" length="8">
1615
+
<reg32 offset="0x0" name="REG">
1616
+
<doc>
1617
+
These seem to be offsets for storage of the varyings.
1618
+
Always seems to start from 8, possibly loc 0 and 4
1619
+
are for gl_Position and gl_PointSize?
1620
+
</doc>
1621
+
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1622
+
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
1623
+
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
1624
+
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
1625
+
</reg32>
1626
+
</array>
1627
+
1628
+
<reg32 offset="0x22e0" name="SP_VS_OBJ_OFFSET_REG">
1629
+
<!-- always 00000000: -->
1630
+
<doc>
1631
+
From register spec:
1632
+
SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
1633
+
start offset in on chip RAM,
1634
+
128bit aligned
1635
+
</doc>
1636
+
<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1637
+
<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1638
+
</reg32>
1639
+
<reg32 offset="0x22e1" name="SP_VS_OBJ_START"/>
1640
+
<reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>
1641
+
<reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/>
1642
+
<reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/>
1643
+
<reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1644
+
<reg32 offset="0x22e9" name="SP_FS_CTRL_REG1">
1645
+
<bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
1646
+
<bitfield name="FACENESS" pos="19" type="boolean"/>
1647
+
<bitfield name="VARYING" pos="20" type="boolean"/>
1648
+
<bitfield name="FRAGCOORD" pos="21" type="boolean"/>
1649
+
</reg32>
1650
+
<reg32 offset="0x22ea" name="SP_FS_OBJ_OFFSET_REG">
1651
+
<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1652
+
<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1653
+
</reg32>
1654
+
<reg32 offset="0x22eb" name="SP_FS_OBJ_START"/>
1655
+
<reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>
1656
+
<reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/>
1657
+
<reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/>
1658
+
<reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG">
1659
+
<bitfield name="MRT" low="0" high="3" type="uint"/>
1660
+
<bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
1661
+
<!-- TODO double check.. for now assume same as a3xx -->
1662
+
<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
1663
+
<bitfield name="SAMPLEMASK_REGID" low="24" high="31" type="a3xx_regid"/>
1664
+
</reg32>
1665
+
<array offset="0x22f1" name="SP_FS_MRT" stride="1" length="8">
1666
+
<reg32 offset="0x0" name="REG">
1667
+
<bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
1668
+
<bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
1669
+
<bitfield name="COLOR_SINT" pos="10" type="boolean"/>
1670
+
<bitfield name="COLOR_UINT" pos="11" type="boolean"/>
1671
+
<bitfield name="MRTFORMAT" low="12" high="17" type="a4xx_color_fmt"/>
1672
+
<bitfield name="COLOR_SRGB" pos="18" type="boolean"/>
1673
+
</reg32>
1674
+
</array>
1675
+
<reg32 offset="0x2300" name="SP_CS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1676
+
<reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/>
1677
+
<reg32 offset="0x2302" name="SP_CS_OBJ_START"/>
1678
+
<reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/>
1679
+
<reg32 offset="0x2304" name="SP_CS_PVT_MEM_ADDR"/>
1680
+
<reg32 offset="0x2305" name="SP_CS_PVT_MEM_SIZE"/>
1681
+
<reg32 offset="0x2306" name="SP_CS_LENGTH_REG" type="uint"/>
1682
+
<reg32 offset="0x230d" name="SP_HS_OBJ_OFFSET_REG">
1683
+
<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1684
+
<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1685
+
</reg32>
1686
+
<reg32 offset="0x230e" name="SP_HS_OBJ_START"/>
1687
+
<reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>
1688
+
<reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/>
1689
+
<reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/>
1690
+
1691
+
<reg32 offset="0x231a" name="SP_DS_PARAM_REG">
1692
+
<bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1693
+
<bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
1694
+
</reg32>
1695
+
<array offset="0x231b" name="SP_DS_OUT" stride="1" length="16">
1696
+
<reg32 offset="0x0" name="REG">
1697
+
<bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1698
+
<bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1699
+
<bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
1700
+
<bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1701
+
</reg32>
1702
+
</array>
1703
+
<array offset="0x232c" name="SP_DS_VPC_DST" stride="1" length="8">
1704
+
<reg32 offset="0x0" name="REG">
1705
+
<doc>
1706
+
These seem to be offsets for storage of the varyings.
1707
+
Always seems to start from 8, possibly loc 0 and 4
1708
+
are for gl_Position and gl_PointSize?
1709
+
</doc>
1710
+
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1711
+
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
1712
+
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
1713
+
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
1714
+
</reg32>
1715
+
</array>
1716
+
<reg32 offset="0x2334" name="SP_DS_OBJ_OFFSET_REG">
1717
+
<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1718
+
<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1719
+
</reg32>
1720
+
<reg32 offset="0x2335" name="SP_DS_OBJ_START"/>
1721
+
<reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>
1722
+
<reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/>
1723
+
<reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/>
1724
+
1725
+
<reg32 offset="0x2341" name="SP_GS_PARAM_REG">
1726
+
<bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1727
+
<bitfield name="PRIMREGID" low="8" high="15" type="a3xx_regid"/>
1728
+
<bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
1729
+
</reg32>
1730
+
<array offset="0x2342" name="SP_GS_OUT" stride="1" length="16">
1731
+
<reg32 offset="0x0" name="REG">
1732
+
<bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1733
+
<bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1734
+
<bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
1735
+
<bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1736
+
</reg32>
1737
+
</array>
1738
+
<array offset="0x2353" name="SP_GS_VPC_DST" stride="1" length="8">
1739
+
<reg32 offset="0x0" name="REG">
1740
+
<doc>
1741
+
These seem to be offsets for storage of the varyings.
1742
+
Always seems to start from 8, possibly loc 0 and 4
1743
+
are for gl_Position and gl_PointSize?
1744
+
</doc>
1745
+
<bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1746
+
<bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
1747
+
<bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
1748
+
<bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
1749
+
</reg32>
1750
+
</array>
1751
+
<reg32 offset="0x235b" name="SP_GS_OBJ_OFFSET_REG">
1752
+
<bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1753
+
<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1754
+
</reg32>
1755
+
<reg32 offset="0x235c" name="SP_GS_OBJ_START"/>
1756
+
<reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>
1757
+
<reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/>
1758
+
<reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/>
1759
+
1760
+
<!-- VPC registers -->
1761
+
<reg32 offset="0x0e60" name="VPC_DEBUG_RAM_SEL"/>
1762
+
<reg32 offset="0x0e61" name="VPC_DEBUG_RAM_READ"/>
1763
+
<reg32 offset="0x0e64" name="VPC_DEBUG_ECO_CONTROL"/>
1764
+
<reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_0" type="a4xx_vpc_perfcounter_select"/>
1765
+
<reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_1" type="a4xx_vpc_perfcounter_select"/>
1766
+
<reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_2" type="a4xx_vpc_perfcounter_select"/>
1767
+
<reg32 offset="0x0e68" name="VPC_PERFCTR_VPC_SEL_3" type="a4xx_vpc_perfcounter_select"/>
1768
+
<reg32 offset="0x2140" name="VPC_ATTR">
1769
+
<bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
1770
+
<!-- PSIZE bit set if gl_PointSize written: -->
1771
+
<bitfield name="PSIZE" pos="9" type="boolean"/>
1772
+
<bitfield name="THRDASSIGN" low="12" high="13" type="uint"/>
1773
+
<bitfield name="ENABLE" pos="25" type="boolean"/>
1774
+
</reg32>
1775
+
<reg32 offset="0x2141" name="VPC_PACK">
1776
+
<bitfield name="NUMBYPASSVAR" low="0" high="7" type="uint"/>
1777
+
<bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
1778
+
<bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
1779
+
</reg32>
1780
+
<array offset="0x2142" name="VPC_VARYING_INTERP" stride="1" length="8">
1781
+
<reg32 offset="0x0" name="MODE"/>
1782
+
</array>
1783
+
<array offset="0x214a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
1784
+
<reg32 offset="0x0" name="MODE"/>
1785
+
</array>
1786
+
1787
+
<reg32 offset="0x216e" name="VPC_SO_FLUSH_WADDR_3"/>
1788
+
1789
+
<!-- VSC registers -->
1790
+
<reg32 offset="0x0c00" name="VSC_BIN_SIZE">
1791
+
<bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1792
+
<bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
1793
+
</reg32>
1794
+
<reg32 offset="0x0c01" name="VSC_SIZE_ADDRESS"/>
1795
+
<reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS2"/>
1796
+
<reg32 offset="0x0c03" name="VSC_DEBUG_ECO_CONTROL"/>
1797
+
<array offset="0x0c08" name="VSC_PIPE_CONFIG" stride="1" length="8">
1798
+
<reg32 offset="0x0" name="REG">
1799
+
<doc>
1800
+
Configures the mapping between VSC_PIPE buffer and
1801
+
bin, X/Y specify the bin index in the horiz/vert
1802
+
direction (0,0 is upper left, 0,1 is leftmost bin
1803
+
on second row, and so on). W/H specify the number
1804
+
of bins assigned to this VSC_PIPE in the horiz/vert
1805
+
dimension.
1806
+
</doc>
1807
+
<bitfield name="X" low="0" high="9" type="uint"/>
1808
+
<bitfield name="Y" low="10" high="19" type="uint"/>
1809
+
<bitfield name="W" low="20" high="23" type="uint"/>
1810
+
<bitfield name="H" low="24" high="27" type="uint"/>
1811
+
</reg32>
1812
+
</array>
1813
+
<array offset="0x0c10" name="VSC_PIPE_DATA_ADDRESS" stride="1" length="8">
1814
+
<reg32 offset="0x0" name="REG"/>
1815
+
</array>
1816
+
<array offset="0x0c18" name="VSC_PIPE_DATA_LENGTH" stride="1" length="8">
1817
+
<reg32 offset="0x0" name="REG"/>
1818
+
</array>
1819
+
<reg32 offset="0x0c41" name="VSC_PIPE_PARTIAL_POSN_1"/>
1820
+
<reg32 offset="0x0c50" name="VSC_PERFCTR_VSC_SEL_0" type="a4xx_vsc_perfcounter_select"/>
1821
+
<reg32 offset="0x0c51" name="VSC_PERFCTR_VSC_SEL_1" type="a4xx_vsc_perfcounter_select"/>
1822
+
1823
+
<!-- VFD registers -->
1824
+
<reg32 offset="0x0e40" name="VFD_DEBUG_CONTROL"/>
1825
+
<reg32 offset="0x0e43" name="VFD_PERFCTR_VFD_SEL_0" type="a4xx_vfd_perfcounter_select"/>
1826
+
<reg32 offset="0x0e44" name="VFD_PERFCTR_VFD_SEL_1" type="a4xx_vfd_perfcounter_select"/>
1827
+
<reg32 offset="0x0e45" name="VFD_PERFCTR_VFD_SEL_2" type="a4xx_vfd_perfcounter_select"/>
1828
+
<reg32 offset="0x0e46" name="VFD_PERFCTR_VFD_SEL_3" type="a4xx_vfd_perfcounter_select"/>
1829
+
<reg32 offset="0x0e47" name="VFD_PERFCTR_VFD_SEL_4" type="a4xx_vfd_perfcounter_select"/>
1830
+
<reg32 offset="0x0e48" name="VFD_PERFCTR_VFD_SEL_5" type="a4xx_vfd_perfcounter_select"/>
1831
+
<reg32 offset="0x0e49" name="VFD_PERFCTR_VFD_SEL_6" type="a4xx_vfd_perfcounter_select"/>
1832
+
<reg32 offset="0x0e4a" name="VFD_PERFCTR_VFD_SEL_7" type="a4xx_vfd_perfcounter_select"/>
1833
+
<reg32 offset="0x21d0" name="VGT_CL_INITIATOR"/>
1834
+
<reg32 offset="0x21d9" name="VGT_EVENT_INITIATOR"/>
1835
+
<reg32 offset="0x2200" name="VFD_CONTROL_0">
1836
+
<doc>
1837
+
TOTALATTRTOVS is # of attributes to vertex shader, in register
1838
+
slots (ie. vec4+vec3 -> 7)
1839
+
</doc>
1840
+
<bitfield name="TOTALATTRTOVS" low="0" high="7" type="uint"/>
1841
+
<doc>
1842
+
BYPASSATTROVS seems to count varyings that are just directly
1843
+
assigned from attributes (ie, "vFoo = aFoo;")
1844
+
</doc>
1845
+
<bitfield name="BYPASSATTROVS" low="9" high="16" type="uint"/>
1846
+
<doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
1847
+
<bitfield name="STRMDECINSTRCNT" low="20" high="25" type="uint"/>
1848
+
<doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
1849
+
<bitfield name="STRMFETCHINSTRCNT" low="26" high="31" type="uint"/>
1850
+
</reg32>
1851
+
<reg32 offset="0x2201" name="VFD_CONTROL_1">
1852
+
<doc>MAXSTORAGE could be # of attributes/vbo's</doc>
1853
+
<bitfield name="MAXSTORAGE" low="0" high="15" type="uint"/>
1854
+
<bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
1855
+
<bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
1856
+
</reg32>
1857
+
<reg32 offset="0x2202" name="VFD_CONTROL_2"/>
1858
+
<reg32 offset="0x2203" name="VFD_CONTROL_3">
1859
+
<bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
1860
+
<bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
1861
+
<bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
1862
+
</reg32>
1863
+
<reg32 offset="0x2204" name="VFD_CONTROL_4"/>
1864
+
<reg32 offset="0x2208" name="VFD_INDEX_OFFSET"/>
1865
+
<array offset="0x220a" name="VFD_FETCH" stride="4" length="32">
1866
+
<reg32 offset="0x0" name="INSTR_0">
1867
+
<bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
1868
+
<bitfield name="BUFSTRIDE" low="7" high="16" type="uint"/>
1869
+
<bitfield name="SWITCHNEXT" pos="19" type="boolean"/>
1870
+
<bitfield name="INSTANCED" pos="20" type="boolean"/>
1871
+
</reg32>
1872
+
<reg32 offset="0x1" name="INSTR_1"/>
1873
+
<reg32 offset="0x2" name="INSTR_2">
1874
+
<bitfield name="SIZE" low="0" high="31"/>
1875
+
</reg32>
1876
+
<reg32 offset="0x3" name="INSTR_3">
1877
+
<!-- might well be bigger.. -->
1878
+
<bitfield name="STEPRATE" low="0" high="8" type="uint"/>
1879
+
</reg32>
1880
+
</array>
1881
+
<array offset="0x228a" name="VFD_DECODE" stride="1" length="32">
1882
+
<reg32 offset="0x0" name="INSTR">
1883
+
<bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
1884
+
<!-- not sure if this is a bit flag and another flag above it, or?? -->
1885
+
<bitfield name="CONSTFILL" pos="4" type="boolean"/>
1886
+
<bitfield name="FORMAT" low="6" high="11" type="a4xx_vtx_fmt"/>
1887
+
<bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
1888
+
<bitfield name="INT" pos="20" type="boolean"/>
1889
+
<doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
1890
+
<bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
1891
+
<bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
1892
+
<bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
1893
+
<bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
1894
+
</reg32>
1895
+
</array>
1896
+
1897
+
<!-- TPL1 registers -->
1898
+
<reg32 offset="0x0f00" name="TPL1_DEBUG_ECO_CONTROL"/>
1899
+
<!-- always 0000003a: -->
1900
+
<reg32 offset="0x0f03" name="TPL1_TP_MODE_CONTROL"/>
1901
+
<reg32 offset="0x0f04" name="TPL1_PERFCTR_TP_SEL_0" type="a4xx_tp_perfcounter_select"/>
1902
+
<reg32 offset="0x0f05" name="TPL1_PERFCTR_TP_SEL_1" type="a4xx_tp_perfcounter_select"/>
1903
+
<reg32 offset="0x0f06" name="TPL1_PERFCTR_TP_SEL_2" type="a4xx_tp_perfcounter_select"/>
1904
+
<reg32 offset="0x0f07" name="TPL1_PERFCTR_TP_SEL_3" type="a4xx_tp_perfcounter_select"/>
1905
+
<reg32 offset="0x0f08" name="TPL1_PERFCTR_TP_SEL_4" type="a4xx_tp_perfcounter_select"/>
1906
+
<reg32 offset="0x0f09" name="TPL1_PERFCTR_TP_SEL_5" type="a4xx_tp_perfcounter_select"/>
1907
+
<reg32 offset="0x0f0a" name="TPL1_PERFCTR_TP_SEL_6" type="a4xx_tp_perfcounter_select"/>
1908
+
<reg32 offset="0x0f0b" name="TPL1_PERFCTR_TP_SEL_7" type="a4xx_tp_perfcounter_select"/>
1909
+
<reg32 offset="0x2380" name="TPL1_TP_TEX_OFFSET"/>
1910
+
<reg32 offset="0x2381" name="TPL1_TP_TEX_COUNT">
1911
+
<bitfield name="VS" low="0" high="7" type="uint"/>
1912
+
<bitfield name="HS" low="8" high="15" type="uint"/>
1913
+
<bitfield name="DS" low="16" high="23" type="uint"/>
1914
+
<bitfield name="GS" low="24" high="31" type="uint"/>
1915
+
</reg32>
1916
+
<reg32 offset="0x2384" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
1917
+
<reg32 offset="0x2387" name="TPL1_TP_HS_BORDER_COLOR_BASE_ADDR"/>
1918
+
<reg32 offset="0x238a" name="TPL1_TP_DS_BORDER_COLOR_BASE_ADDR"/>
1919
+
<reg32 offset="0x238d" name="TPL1_TP_GS_BORDER_COLOR_BASE_ADDR"/>
1920
+
<reg32 offset="0x23a0" name="TPL1_TP_FS_TEX_COUNT">
1921
+
<bitfield name="FS" low="0" high="7" type="uint"/>
1922
+
<bitfield name="CS" low="8" high="15" type="uint"/>
1923
+
</reg32>
1924
+
<reg32 offset="0x23a1" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
1925
+
<reg32 offset="0x23a4" name="TPL1_TP_CS_BORDER_COLOR_BASE_ADDR"/>
1926
+
<reg32 offset="0x23a5" name="TPL1_TP_CS_SAMPLER_BASE_ADDR"/>
1927
+
<reg32 offset="0x23a6" name="TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR"/>
1928
+
1929
+
<!-- GRAS registers -->
1930
+
<reg32 offset="0x0c80" name="GRAS_TSE_STATUS"/>
1931
+
<reg32 offset="0x0c81" name="GRAS_DEBUG_ECO_CONTROL"/>
1932
+
<reg32 offset="0x0c88" name="GRAS_PERFCTR_TSE_SEL_0" type="a4xx_gras_tse_perfcounter_select"/>
1933
+
<reg32 offset="0x0c89" name="GRAS_PERFCTR_TSE_SEL_1" type="a4xx_gras_tse_perfcounter_select"/>
1934
+
<reg32 offset="0x0c8a" name="GRAS_PERFCTR_TSE_SEL_2" type="a4xx_gras_tse_perfcounter_select"/>
1935
+
<reg32 offset="0x0c8b" name="GRAS_PERFCTR_TSE_SEL_3" type="a4xx_gras_tse_perfcounter_select"/>
1936
+
<reg32 offset="0x0c8c" name="GRAS_PERFCTR_RAS_SEL_0" type="a4xx_gras_ras_perfcounter_select"/>
1937
+
<reg32 offset="0x0c8d" name="GRAS_PERFCTR_RAS_SEL_1" type="a4xx_gras_ras_perfcounter_select"/>
1938
+
<reg32 offset="0x0c8e" name="GRAS_PERFCTR_RAS_SEL_2" type="a4xx_gras_ras_perfcounter_select"/>
1939
+
<reg32 offset="0x0c8f" name="GRAS_PERFCTR_RAS_SEL_3" type="a4xx_gras_ras_perfcounter_select"/>
1940
+
<reg32 offset="0x2000" name="GRAS_CL_CLIP_CNTL">
1941
+
<bitfield name="CLIP_DISABLE" pos="15" type="boolean"/>
1942
+
<bitfield name="ZNEAR_CLIP_DISABLE" pos="16" type="boolean"/>
1943
+
<bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
1944
+
<bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean"/>
1945
+
</reg32>
1946
+
<reg32 offset="0x2003" name="GRAS_CNTL">
1947
+
<bitfield name="IJ_PERSP" pos="0" type="boolean"/>
1948
+
<bitfield name="IJ_LINEAR" pos="1" type="boolean"/>
1949
+
</reg32>
1950
+
<reg32 offset="0x2004" name="GRAS_CL_GB_CLIP_ADJ">
1951
+
<bitfield name="HORZ" low="0" high="9" type="uint"/>
1952
+
<bitfield name="VERT" low="10" high="19" type="uint"/>
1953
+
</reg32>
1954
+
<reg32 offset="0x2008" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1955
+
<reg32 offset="0x2009" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1956
+
<reg32 offset="0x200a" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1957
+
<reg32 offset="0x200b" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1958
+
<reg32 offset="0x200c" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1959
+
<reg32 offset="0x200d" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1960
+
<reg32 offset="0x2070" name="GRAS_SU_POINT_MINMAX">
1961
+
<bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1962
+
<bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1963
+
</reg32>
1964
+
<reg32 offset="0x2071" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1965
+
<reg32 offset="0x2073" name="GRAS_ALPHA_CONTROL">
1966
+
<bitfield name="ALPHA_TEST_ENABLE" pos="2" type="boolean"/>
1967
+
<bitfield name="FORCE_FRAGZ_TO_FS" pos="3" type="boolean"/>
1968
+
</reg32>
1969
+
<reg32 offset="0x2074" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1970
+
<reg32 offset="0x2075" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1971
+
<reg32 offset="0x2076" name="GRAS_SU_POLY_OFFSET_CLAMP" type="float"/>
1972
+
<reg32 offset="0x2077" name="GRAS_DEPTH_CONTROL">
1973
+
<!-- guestimating that this is GRAS based on addr -->
1974
+
<bitfield name="FORMAT" low="0" high="1" type="a4xx_depth_format"/>
1975
+
</reg32>
1976
+
<reg32 offset="0x2078" name="GRAS_SU_MODE_CONTROL">
1977
+
<bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1978
+
<bitfield name="CULL_BACK" pos="1" type="boolean"/>
1979
+
<bitfield name="FRONT_CW" pos="2" type="boolean"/>
1980
+
<bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1981
+
<bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1982
+
<bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1983
+
<!-- bit20 set whenever RENDER_MODE = RB_RENDERING_PASS -->
1984
+
<bitfield name="RENDERING_PASS" pos="20" type="boolean"/>
1985
+
</reg32>
1986
+
<reg32 offset="0x207b" name="GRAS_SC_CONTROL">
1987
+
<!-- complete wild-ass-guess for sizes of these bitfields.. -->
1988
+
<bitfield name="RENDER_MODE" low="2" high="3" type="a3xx_render_mode"/>
1989
+
<bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
1990
+
<bitfield name="MSAA_DISABLE" pos="11" type="boolean"/>
1991
+
<bitfield name="RASTER_MODE" low="12" high="15"/>
1992
+
</reg32>
1993
+
<reg32 offset="0x207c" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
1994
+
<reg32 offset="0x207d" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
1995
+
<reg32 offset="0x209c" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1996
+
<reg32 offset="0x209d" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1997
+
<reg32 offset="0x209e" name="GRAS_SC_EXTENT_WINDOW_BR" type="adreno_reg_xy"/>
1998
+
<reg32 offset="0x209f" name="GRAS_SC_EXTENT_WINDOW_TL" type="adreno_reg_xy"/>
1999
+
2000
+
<!-- UCHE registers -->
2001
+
<reg32 offset="0x0e80" name="UCHE_CACHE_MODE_CONTROL"/>
2002
+
<reg32 offset="0x0e83" name="UCHE_TRAP_BASE_LO"/>
2003
+
<reg32 offset="0x0e84" name="UCHE_TRAP_BASE_HI"/>
2004
+
<reg32 offset="0x0e88" name="UCHE_CACHE_STATUS"/>
2005
+
<reg32 offset="0x0e8a" name="UCHE_INVALIDATE0"/>
2006
+
<reg32 offset="0x0e8b" name="UCHE_INVALIDATE1"/>
2007
+
<reg32 offset="0x0e8c" name="UCHE_CACHE_WAYS_VFD"/>
2008
+
<reg32 offset="0x0e8e" name="UCHE_PERFCTR_UCHE_SEL_0" type="a4xx_uche_perfcounter_select"/>
2009
+
<reg32 offset="0x0e8f" name="UCHE_PERFCTR_UCHE_SEL_1" type="a4xx_uche_perfcounter_select"/>
2010
+
<reg32 offset="0x0e90" name="UCHE_PERFCTR_UCHE_SEL_2" type="a4xx_uche_perfcounter_select"/>
2011
+
<reg32 offset="0x0e91" name="UCHE_PERFCTR_UCHE_SEL_3" type="a4xx_uche_perfcounter_select"/>
2012
+
<reg32 offset="0x0e92" name="UCHE_PERFCTR_UCHE_SEL_4" type="a4xx_uche_perfcounter_select"/>
2013
+
<reg32 offset="0x0e93" name="UCHE_PERFCTR_UCHE_SEL_5" type="a4xx_uche_perfcounter_select"/>
2014
+
<reg32 offset="0x0e94" name="UCHE_PERFCTR_UCHE_SEL_6" type="a4xx_uche_perfcounter_select"/>
2015
+
<reg32 offset="0x0e95" name="UCHE_PERFCTR_UCHE_SEL_7" type="a4xx_uche_perfcounter_select"/>
2016
+
2017
+
<!-- HLSQ registers -->
2018
+
<reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD"/>
2019
+
<reg32 offset="0x0e04" name="HLSQ_DEBUG_ECO_CONTROL"/>
2020
+
<!-- always 00000000: -->
2021
+
<reg32 offset="0x0e05" name="HLSQ_MODE_CONTROL"/>
2022
+
<reg32 offset="0x0e0e" name="HLSQ_PERF_PIPE_MASK"/>
2023
+
<reg32 offset="0x0e06" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a4xx_hlsq_perfcounter_select"/>
2024
+
<reg32 offset="0x0e07" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a4xx_hlsq_perfcounter_select"/>
2025
+
<reg32 offset="0x0e08" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a4xx_hlsq_perfcounter_select"/>
2026
+
<reg32 offset="0x0e09" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a4xx_hlsq_perfcounter_select"/>
2027
+
<reg32 offset="0x0e0a" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a4xx_hlsq_perfcounter_select"/>
2028
+
<reg32 offset="0x0e0b" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a4xx_hlsq_perfcounter_select"/>
2029
+
<reg32 offset="0x0e0c" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a4xx_hlsq_perfcounter_select"/>
2030
+
<reg32 offset="0x0e0d" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a4xx_hlsq_perfcounter_select"/>
2031
+
<reg32 offset="0x23c0" name="HLSQ_CONTROL_0_REG">
2032
+
<!-- I guess same as a3xx, but so far only seen 08000050 -->
2033
+
<bitfield name="FSTHREADSIZE" pos="4" type="a3xx_threadsize"/>
2034
+
<bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
2035
+
<bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
2036
+
<bitfield name="RESERVED2" pos="10" type="boolean"/>
2037
+
<bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
2038
+
<bitfield name="CONSTMODE" pos="27" type="uint"/>
2039
+
<bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
2040
+
<bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
2041
+
<bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
2042
+
<bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
2043
+
</reg32>
2044
+
<reg32 offset="0x23c1" name="HLSQ_CONTROL_1_REG">
2045
+
<bitfield name="VSTHREADSIZE" pos="6" type="a3xx_threadsize"/>
2046
+
<bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
2047
+
<bitfield name="RESERVED1" pos="9" type="boolean"/>
2048
+
<bitfield name="COORDREGID" low="16" high="23" type="a3xx_regid"/>
2049
+
<!-- set if gl_FragCoord.[zw] used in frag shader: -->
2050
+
<bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
2051
+
</reg32>
2052
+
<reg32 offset="0x23c2" name="HLSQ_CONTROL_2_REG">
2053
+
<bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
2054
+
<bitfield name="FACEREGID" low="2" high="9" type="a3xx_regid"/>
2055
+
<bitfield name="SAMPLEID_REGID" low="10" high="17" type="a3xx_regid"/>
2056
+
<bitfield name="SAMPLEMASK_REGID" low="18" high="25" type="a3xx_regid"/>
2057
+
</reg32>
2058
+
<reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG">
2059
+
<!-- register loaded with position (bary.f) -->
2060
+
<bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
2061
+
<bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
2062
+
<bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
2063
+
<bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
2064
+
</reg32>
2065
+
<!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading -->
2066
+
<reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG">
2067
+
<bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
2068
+
<bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
2069
+
</reg32>
2070
+
2071
+
<bitset name="a4xx_xs_control_reg" inline="yes">
2072
+
<bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
2073
+
<bitfield name="CONSTOBJECTOFFSET" low="8" high="14" type="uint"/>
2074
+
<bitfield name="SSBO_ENABLE" pos="15" type="boolean"/>
2075
+
<bitfield name="ENABLED" pos="16" type="boolean"/>
2076
+
<bitfield name="SHADEROBJOFFSET" low="17" high="23" type="uint"/>
2077
+
<bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
2078
+
</bitset>
2079
+
<reg32 offset="0x23c5" name="HLSQ_VS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2080
+
<reg32 offset="0x23c6" name="HLSQ_FS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2081
+
<reg32 offset="0x23c7" name="HLSQ_HS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2082
+
<reg32 offset="0x23c8" name="HLSQ_DS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2083
+
<reg32 offset="0x23c9" name="HLSQ_GS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2084
+
<reg32 offset="0x23ca" name="HLSQ_CS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2085
+
<reg32 offset="0x23cd" name="HLSQ_CL_NDRANGE_0">
2086
+
<bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2087
+
<!-- localsize is value minus one: -->
2088
+
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
2089
+
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
2090
+
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
2091
+
</reg32>
2092
+
<reg32 offset="0x23ce" name="HLSQ_CL_NDRANGE_1">
2093
+
<bitfield name="SIZE_X" low="0" high="31" type="uint"/>
2094
+
</reg32>
2095
+
<reg32 offset="0x23cf" name="HLSQ_CL_NDRANGE_2"/>
2096
+
<reg32 offset="0x23d0" name="HLSQ_CL_NDRANGE_3">
2097
+
<bitfield name="SIZE_Y" low="0" high="31" type="uint"/>
2098
+
</reg32>
2099
+
<reg32 offset="0x23d1" name="HLSQ_CL_NDRANGE_4"/>
2100
+
<reg32 offset="0x23d2" name="HLSQ_CL_NDRANGE_5">
2101
+
<bitfield name="SIZE_Z" low="0" high="31" type="uint"/>
2102
+
</reg32>
2103
+
<reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/>
2104
+
<reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0">
2105
+
<bitfield name="WGIDCONSTID" low="0" high="11" type="a3xx_regid"/>
2106
+
<bitfield name="KERNELDIMCONSTID" low="12" high="23" type="a3xx_regid"/>
2107
+
<bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
2108
+
</reg32>
2109
+
<reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1">
2110
+
<!-- GLOBALSIZECONSTID? "kernel size" -->
2111
+
<bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
2112
+
<bitfield name="WORKGROUPSIZECONSTID" low="12" high="23" type="a3xx_regid"/>
2113
+
</reg32>
2114
+
<reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST">
2115
+
<!-- GLOBALOFFSETCONSTID -->
2116
+
<bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
2117
+
<bitfield name="NUMWGCONSTID" low="12" high="23" type="a3xx_regid"/>
2118
+
</reg32>
2119
+
<reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/>
2120
+
<reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/>
2121
+
<reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/>
2122
+
<reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET">
2123
+
<!-- WGOFFSETCONSTID -->
2124
+
<bitfield name="UNK0CONSTID" low="0" high="11" type="a3xx_regid"/>
2125
+
</reg32>
2126
+
<reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/>
2127
+
2128
+
<!-- PC registers -->
2129
+
<reg32 offset="0x0d00" name="PC_BINNING_COMMAND">
2130
+
<bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
2131
+
</reg32>
2132
+
<reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR"/>
2133
+
<reg32 offset="0x0d0c" name="PC_DRAWCALL_SETUP_OVERRIDE"/>
2134
+
<reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a4xx_pc_perfcounter_select"/>
2135
+
<reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a4xx_pc_perfcounter_select"/>
2136
+
<reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a4xx_pc_perfcounter_select"/>
2137
+
<reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a4xx_pc_perfcounter_select"/>
2138
+
<reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a4xx_pc_perfcounter_select"/>
2139
+
<reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a4xx_pc_perfcounter_select"/>
2140
+
<reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a4xx_pc_perfcounter_select"/>
2141
+
<reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a4xx_pc_perfcounter_select"/>
2142
+
<reg32 offset="0x21c0" name="PC_BIN_BASE"/>
2143
+
<reg32 offset="0x21c2" name="PC_VSTREAM_CONTROL">
2144
+
<doc>SIZE is current pipe width * height (in tiles)</doc>
2145
+
<bitfield name="SIZE" low="16" high="21" type="uint"/>
2146
+
<doc>
2147
+
N is some sort of slot # between 0..(SIZE-1). In case
2148
+
multiple tiles use same pipe, each tile gets unique slot #
2149
+
</doc>
2150
+
<bitfield name="N" low="22" high="26" type="uint"/>
2151
+
</reg32>
2152
+
<reg32 offset="0x21c4" name="PC_PRIM_VTX_CNTL">
2153
+
<!-- bit0 set if there is >= 1 varying (actually used by FS) -->
2154
+
<bitfield name="VAROUT" low="0" high="3" type="uint">
2155
+
<doc>in groups of 4x vec4, blob only uses values
2156
+
0, 1, 2, 4, 6, 8</doc>
2157
+
</bitfield>
2158
+
<bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
2159
+
<bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
2160
+
<!-- PSIZE bit set if gl_PointSize written: -->
2161
+
<bitfield name="PSIZE" pos="26" type="boolean"/>
2162
+
</reg32>
2163
+
<reg32 offset="0x21c5" name="PC_PRIM_VTX_CNTL2">
2164
+
<bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
2165
+
<bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
2166
+
<bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
2167
+
</reg32>
2168
+
<reg32 offset="0x21c6" name="PC_RESTART_INDEX"/>
2169
+
<reg32 offset="0x21e5" name="PC_GS_PARAM">
2170
+
<bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- +1, i.e. max is 1024 -->
2171
+
<bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- +1, i.e. max is 32 -->
2172
+
<bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
2173
+
<bitfield name="LAYER" pos="31" type="boolean"/>
2174
+
</reg32>
2175
+
<reg32 offset="0x21e7" name="PC_HS_PARAM">
2176
+
<bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
2177
+
<bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
2178
+
<bitfield name="CW" pos="23" type="boolean"/>
2179
+
<bitfield name="CONNECTED" pos="24" type="boolean"/>
2180
+
</reg32>
2181
+
2182
+
<!-- VBIF registers -->
2183
+
<reg32 offset="0x3000" name="VBIF_VERSION"/>
2184
+
<reg32 offset="0x3001" name="VBIF_CLKON">
2185
+
<bitfield name="FORCE_ON_TESTBUS" pos="0" type="boolean"/>
2186
+
</reg32>
2187
+
<reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
2188
+
<reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
2189
+
<reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
2190
+
<reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
2191
+
<reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
2192
+
<reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
2193
+
<reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
2194
+
<reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
2195
+
<reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
2196
+
<reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
2197
+
<reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
2198
+
<reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
2199
+
<reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a4xx_vbif_perfcounter_select"/>
2200
+
<reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a4xx_vbif_perfcounter_select"/>
2201
+
<reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a4xx_vbif_perfcounter_select"/>
2202
+
<reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a4xx_vbif_perfcounter_select"/>
2203
+
<reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
2204
+
<reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
2205
+
<reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
2206
+
<reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
2207
+
<reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
2208
+
<reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
2209
+
<reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
2210
+
<reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
2211
+
<reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
2212
+
<reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
2213
+
<reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
2214
+
2215
+
<!--
2216
+
Unknown registers:
2217
+
(mostly related to DX11 features not used yet, I guess?)
2218
+
-->
2219
+
2220
+
<!-- always 00000006: -->
2221
+
<reg32 offset="0x0cc5" name="UNKNOWN_0CC5"/>
2222
+
2223
+
<!-- always 00000000: -->
2224
+
<reg32 offset="0x0cc6" name="UNKNOWN_0CC6"/>
2225
+
2226
+
<!-- always 00000001: -->
2227
+
<reg32 offset="0x0d01" name="UNKNOWN_0D01"/>
2228
+
2229
+
<!-- always 00000000: -->
2230
+
<reg32 offset="0x0e42" name="UNKNOWN_0E42"/>
2231
+
2232
+
<!-- always 00040000: -->
2233
+
<reg32 offset="0x0ec2" name="UNKNOWN_0EC2"/>
2234
+
2235
+
<!-- always 00000000: -->
2236
+
<reg32 offset="0x2001" name="UNKNOWN_2001"/>
2237
+
2238
+
<!-- always 00000000: -->
2239
+
<reg32 offset="0x209b" name="UNKNOWN_209B"/>
2240
+
2241
+
<!-- always 00000000: -->
2242
+
<reg32 offset="0x20ef" name="UNKNOWN_20EF"/>
2243
+
2244
+
<!-- always 00000000: -->
2245
+
<reg32 offset="0x2152" name="UNKNOWN_2152"/>
2246
+
2247
+
<!-- always 00000000: -->
2248
+
<reg32 offset="0x2153" name="UNKNOWN_2153"/>
2249
+
2250
+
<!-- always 00000000: -->
2251
+
<reg32 offset="0x2154" name="UNKNOWN_2154"/>
2252
+
2253
+
<!-- always 00000000: -->
2254
+
<reg32 offset="0x2155" name="UNKNOWN_2155"/>
2255
+
2256
+
<!-- always 00000000: -->
2257
+
<reg32 offset="0x2156" name="UNKNOWN_2156"/>
2258
+
2259
+
<!-- always 00000000: -->
2260
+
<reg32 offset="0x2157" name="UNKNOWN_2157"/>
2261
+
2262
+
<!-- always 0000000b: -->
2263
+
<reg32 offset="0x21c3" name="UNKNOWN_21C3"/>
2264
+
2265
+
<!-- always 00000001: -->
2266
+
<reg32 offset="0x21e6" name="UNKNOWN_21E6"/>
2267
+
2268
+
<!-- always 00000000: -->
2269
+
<reg32 offset="0x2209" name="UNKNOWN_2209"/>
2270
+
2271
+
<!-- always 00000000: -->
2272
+
<reg32 offset="0x22d7" name="UNKNOWN_22D7"/>
2273
+
2274
+
<!-- always 00fcfc00: -->
2275
+
<reg32 offset="0x2352" name="UNKNOWN_2352"/>
2276
+
2277
+
</domain>
2278
+
2279
+
2280
+
<domain name="A4XX_TEX_SAMP" width="32">
2281
+
<doc>Texture sampler dwords</doc>
2282
+
<enum name="a4xx_tex_filter">
2283
+
<value name="A4XX_TEX_NEAREST" value="0"/>
2284
+
<value name="A4XX_TEX_LINEAR" value="1"/>
2285
+
<value name="A4XX_TEX_ANISO" value="2"/>
2286
+
</enum>
2287
+
<enum name="a4xx_tex_clamp">
2288
+
<value name="A4XX_TEX_REPEAT" value="0"/>
2289
+
<value name="A4XX_TEX_CLAMP_TO_EDGE" value="1"/>
2290
+
<value name="A4XX_TEX_MIRROR_REPEAT" value="2"/>
2291
+
<value name="A4XX_TEX_CLAMP_TO_BORDER" value="3"/>
2292
+
<value name="A4XX_TEX_MIRROR_CLAMP" value="4"/>
2293
+
</enum>
2294
+
<enum name="a4xx_tex_aniso">
2295
+
<value name="A4XX_TEX_ANISO_1" value="0"/>
2296
+
<value name="A4XX_TEX_ANISO_2" value="1"/>
2297
+
<value name="A4XX_TEX_ANISO_4" value="2"/>
2298
+
<value name="A4XX_TEX_ANISO_8" value="3"/>
2299
+
<value name="A4XX_TEX_ANISO_16" value="4"/>
2300
+
</enum>
2301
+
<reg32 offset="0" name="0">
2302
+
<bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
2303
+
<bitfield name="XY_MAG" low="1" high="2" type="a4xx_tex_filter"/>
2304
+
<bitfield name="XY_MIN" low="3" high="4" type="a4xx_tex_filter"/>
2305
+
<bitfield name="WRAP_S" low="5" high="7" type="a4xx_tex_clamp"/>
2306
+
<bitfield name="WRAP_T" low="8" high="10" type="a4xx_tex_clamp"/>
2307
+
<bitfield name="WRAP_R" low="11" high="13" type="a4xx_tex_clamp"/>
2308
+
<bitfield name="ANISO" low="14" high="16" type="a4xx_tex_aniso"/>
2309
+
<bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
2310
+
</reg32>
2311
+
<reg32 offset="1" name="1">
2312
+
<bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
2313
+
<bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
2314
+
<bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
2315
+
<bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
2316
+
<bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
2317
+
<bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
2318
+
</reg32>
2319
+
</domain>
2320
+
2321
+
<domain name="A4XX_TEX_CONST" width="32">
2322
+
<doc>Texture constant dwords</doc>
2323
+
<enum name="a4xx_tex_swiz">
2324
+
<!-- same as a2xx? -->
2325
+
<value name="A4XX_TEX_X" value="0"/>
2326
+
<value name="A4XX_TEX_Y" value="1"/>
2327
+
<value name="A4XX_TEX_Z" value="2"/>
2328
+
<value name="A4XX_TEX_W" value="3"/>
2329
+
<value name="A4XX_TEX_ZERO" value="4"/>
2330
+
<value name="A4XX_TEX_ONE" value="5"/>
2331
+
</enum>
2332
+
<enum name="a4xx_tex_type">
2333
+
<value name="A4XX_TEX_1D" value="0"/>
2334
+
<value name="A4XX_TEX_2D" value="1"/>
2335
+
<value name="A4XX_TEX_CUBE" value="2"/>
2336
+
<value name="A4XX_TEX_3D" value="3"/>
2337
+
<value name="A4XX_TEX_BUFFER" value="4"/>
2338
+
</enum>
2339
+
<reg32 offset="0" name="0">
2340
+
<bitfield name="TILED" pos="0" type="boolean"/>
2341
+
<bitfield name="SRGB" pos="2" type="boolean"/>
2342
+
<bitfield name="SWIZ_X" low="4" high="6" type="a4xx_tex_swiz"/>
2343
+
<bitfield name="SWIZ_Y" low="7" high="9" type="a4xx_tex_swiz"/>
2344
+
<bitfield name="SWIZ_Z" low="10" high="12" type="a4xx_tex_swiz"/>
2345
+
<bitfield name="SWIZ_W" low="13" high="15" type="a4xx_tex_swiz"/>
2346
+
<bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
2347
+
<bitfield name="FMT" low="22" high="28" type="a4xx_tex_fmt"/>
2348
+
<bitfield name="TYPE" low="29" high="31" type="a4xx_tex_type"/>
2349
+
</reg32>
2350
+
<reg32 offset="1" name="1">
2351
+
<bitfield name="HEIGHT" low="0" high="14" type="uint"/>
2352
+
<bitfield name="WIDTH" low="15" high="29" type="uint"/>
2353
+
</reg32>
2354
+
<reg32 offset="2" name="2">
2355
+
<!-- minimum pitch (for mipmap levels): log2(pitchalign / 32) -->
2356
+
<bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
2357
+
<bitfield name="BUFFER" pos="6" type="boolean"/>
2358
+
<doc>Pitch in bytes (so actually stride)</doc>
2359
+
<bitfield name="PITCH" low="9" high="29" type="uint"/>
2360
+
<bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
2361
+
</reg32>
2362
+
<reg32 offset="3" name="3">
2363
+
<bitfield name="LAYERSZ" low="0" high="13" shr="12" type="uint"/>
2364
+
<bitfield name="DEPTH" low="18" high="30" type="uint"/>
2365
+
</reg32>
2366
+
<reg32 offset="4" name="4">
2367
+
<!--
2368
+
like a3xx we seem to have two LAYERSZ's.. although this one
2369
+
seems too small to be useful, and when it overflows blob just
2370
+
sets it to zero..
2371
+
-->
2372
+
<bitfield name="LAYERSZ" low="0" high="3" shr="12" type="uint"/>
2373
+
<bitfield name="BASE" low="5" high="31" shr="5"/>
2374
+
</reg32>
2375
+
<reg32 offset="5" name="5"/>
2376
+
<reg32 offset="6" name="6"/>
2377
+
<reg32 offset="7" name="7"/>
2378
+
</domain>
2379
+
2380
+
<domain name="A4XX_SSBO_0" width="32">
2381
+
<reg32 offset="0" name="0">
2382
+
<bitfield name="BASE" low="5" high="31" shr="5"/>
2383
+
</reg32>
2384
+
<reg32 offset="1" name="1">
2385
+
<doc>Pitch in bytes (so actually stride)</doc>
2386
+
<bitfield name="PITCH" low="0" high="21" type="uint"/>
2387
+
</reg32>
2388
+
<reg32 offset="2" name="2">
2389
+
<bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
2390
+
</reg32>
2391
+
<reg32 offset="3" name="3">
2392
+
<!-- bytes per pixel: -->
2393
+
<bitfield name="CPP" low="0" high="5" type="uint"/>
2394
+
</reg32>
2395
+
</domain>
2396
+
2397
+
<domain name="A4XX_SSBO_1" width="32">
2398
+
<reg32 offset="0" name="0">
2399
+
<bitfield name="CPP" low="0" high="4" type="uint"/>
2400
+
<bitfield name="FMT" low="8" high="15" type="a4xx_color_fmt"/>
2401
+
<bitfield name="WIDTH" low="16" high="31" type="uint"/>
2402
+
</reg32>
2403
+
<reg32 offset="1" name="1">
2404
+
<bitfield name="HEIGHT" low="0" high="15" type="uint"/>
2405
+
<bitfield name="DEPTH" low="16" high="31" type="uint"/>
2406
+
</reg32>
2407
+
</domain>
2408
+
2409
+
</database>
+400
drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
+400
drivers/gpu/drm/msm/registers/adreno/adreno_common.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
7
+
<enum name="chip" bare="yes">
8
+
<value name="A2XX" value="2"/>
9
+
<value name="A3XX" value="3"/>
10
+
<value name="A4XX" value="4"/>
11
+
<value name="A5XX" value="5"/>
12
+
<value name="A6XX" value="6"/>
13
+
<value name="A7XX" value="7"/>
14
+
</enum>
15
+
16
+
<enum name="adreno_pa_su_sc_draw">
17
+
<value name="PC_DRAW_POINTS" value="0"/>
18
+
<value name="PC_DRAW_LINES" value="1"/>
19
+
<value name="PC_DRAW_TRIANGLES" value="2"/>
20
+
</enum>
21
+
22
+
<enum name="adreno_compare_func">
23
+
<value name="FUNC_NEVER" value="0"/>
24
+
<value name="FUNC_LESS" value="1"/>
25
+
<value name="FUNC_EQUAL" value="2"/>
26
+
<value name="FUNC_LEQUAL" value="3"/>
27
+
<value name="FUNC_GREATER" value="4"/>
28
+
<value name="FUNC_NOTEQUAL" value="5"/>
29
+
<value name="FUNC_GEQUAL" value="6"/>
30
+
<value name="FUNC_ALWAYS" value="7"/>
31
+
</enum>
32
+
33
+
<enum name="adreno_stencil_op">
34
+
<value name="STENCIL_KEEP" value="0"/>
35
+
<value name="STENCIL_ZERO" value="1"/>
36
+
<value name="STENCIL_REPLACE" value="2"/>
37
+
<value name="STENCIL_INCR_CLAMP" value="3"/>
38
+
<value name="STENCIL_DECR_CLAMP" value="4"/>
39
+
<value name="STENCIL_INVERT" value="5"/>
40
+
<value name="STENCIL_INCR_WRAP" value="6"/>
41
+
<value name="STENCIL_DECR_WRAP" value="7"/>
42
+
</enum>
43
+
44
+
<enum name="adreno_rb_blend_factor">
45
+
<value name="FACTOR_ZERO" value="0"/>
46
+
<value name="FACTOR_ONE" value="1"/>
47
+
<value name="FACTOR_SRC_COLOR" value="4"/>
48
+
<value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/>
49
+
<value name="FACTOR_SRC_ALPHA" value="6"/>
50
+
<value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/>
51
+
<value name="FACTOR_DST_COLOR" value="8"/>
52
+
<value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/>
53
+
<value name="FACTOR_DST_ALPHA" value="10"/>
54
+
<value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/>
55
+
<value name="FACTOR_CONSTANT_COLOR" value="12"/>
56
+
<value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/>
57
+
<value name="FACTOR_CONSTANT_ALPHA" value="14"/>
58
+
<value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/>
59
+
<value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/>
60
+
<value name="FACTOR_SRC1_COLOR" value="20"/>
61
+
<value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/>
62
+
<value name="FACTOR_SRC1_ALPHA" value="22"/>
63
+
<value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/>
64
+
</enum>
65
+
66
+
<bitset name="adreno_rb_stencilrefmask" inline="yes">
67
+
<bitfield name="STENCILREF" low="0" high="7" type="hex"/>
68
+
<bitfield name="STENCILMASK" low="8" high="15" type="hex"/>
69
+
<bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/>
70
+
</bitset>
71
+
72
+
<enum name="adreno_rb_surface_endian">
73
+
<value name="ENDIAN_NONE" value="0"/>
74
+
<value name="ENDIAN_8IN16" value="1"/>
75
+
<value name="ENDIAN_8IN32" value="2"/>
76
+
<value name="ENDIAN_16IN32" value="3"/>
77
+
<value name="ENDIAN_8IN64" value="4"/>
78
+
<value name="ENDIAN_8IN128" value="5"/>
79
+
</enum>
80
+
81
+
<enum name="adreno_rb_dither_mode">
82
+
<value name="DITHER_DISABLE" value="0"/>
83
+
<value name="DITHER_ALWAYS" value="1"/>
84
+
<value name="DITHER_IF_ALPHA_OFF" value="2"/>
85
+
</enum>
86
+
87
+
<enum name="adreno_rb_depth_format">
88
+
<value name="DEPTHX_16" value="0"/>
89
+
<value name="DEPTHX_24_8" value="1"/>
90
+
<value name="DEPTHX_32" value="2"/>
91
+
</enum>
92
+
93
+
<enum name="adreno_rb_copy_control_mode">
94
+
<value name="RB_COPY_RESOLVE" value="1"/>
95
+
<value name="RB_COPY_CLEAR" value="2"/>
96
+
<value name="RB_COPY_DEPTH_STENCIL" value="5"/> <!-- not sure if this is part of MODE or another bitfield?? -->
97
+
</enum>
98
+
99
+
<bitset name="adreno_reg_xy" inline="yes">
100
+
<bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/>
101
+
<bitfield name="X" low="0" high="14" type="uint"/>
102
+
<bitfield name="Y" low="16" high="30" type="uint"/>
103
+
</bitset>
104
+
105
+
<bitset name="adreno_cp_protect" inline="yes">
106
+
<bitfield name="BASE_ADDR" low="0" high="16"/>
107
+
<bitfield name="MASK_LEN" low="24" high="28"/>
108
+
<bitfield name="TRAP_WRITE" pos="29"/>
109
+
<bitfield name="TRAP_READ" pos="30"/>
110
+
</bitset>
111
+
112
+
<domain name="AXXX" width="32">
113
+
<brief>Registers in common between a2xx and a3xx</brief>
114
+
115
+
<reg32 offset="0x01c0" name="CP_RB_BASE"/>
116
+
<reg32 offset="0x01c1" name="CP_RB_CNTL">
117
+
<bitfield name="BUFSZ" low="0" high="5"/>
118
+
<bitfield name="BLKSZ" low="8" high="13"/>
119
+
<bitfield name="BUF_SWAP" low="16" high="17"/>
120
+
<bitfield name="POLL_EN" pos="20" type="boolean"/>
121
+
<bitfield name="NO_UPDATE" pos="27" type="boolean"/>
122
+
<bitfield name="RPTR_WR_EN" pos="31" type="boolean"/>
123
+
</reg32>
124
+
<reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR">
125
+
<bitfield name="SWAP" low="0" high="1" type="uint"/>
126
+
<bitfield name="ADDR" low="2" high="31" shr="2"/>
127
+
</reg32>
128
+
<reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/>
129
+
<reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/>
130
+
<reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/>
131
+
<reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/>
132
+
<reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/>
133
+
<reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS">
134
+
<bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/>
135
+
<bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/>
136
+
<bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/>
137
+
</reg32>
138
+
<reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS">
139
+
<bitfield name="MEQ_END" low="16" high="20" type="uint"/>
140
+
<bitfield name="ROQ_END" low="24" high="28" type="uint"/>
141
+
</reg32>
142
+
<reg32 offset="0x01d7" name="CP_CSQ_AVAIL">
143
+
<bitfield name="RING" low="0" high="6" type="uint"/>
144
+
<bitfield name="IB1" low="8" high="14" type="uint"/>
145
+
<bitfield name="IB2" low="16" high="22" type="uint"/>
146
+
</reg32>
147
+
<reg32 offset="0x01d8" name="CP_STQ_AVAIL">
148
+
<bitfield name="ST" low="0" high="6" type="uint"/>
149
+
</reg32>
150
+
<reg32 offset="0x01d9" name="CP_MEQ_AVAIL">
151
+
<bitfield name="MEQ" low="0" high="4" type="uint"/>
152
+
</reg32>
153
+
<reg32 offset="0x01dc" name="SCRATCH_UMSK">
154
+
<bitfield name="UMSK" low="0" high="7" type="uint"/>
155
+
<bitfield name="SWAP" low="16" high="17" type="uint"/>
156
+
</reg32>
157
+
<reg32 offset="0x01dd" name="SCRATCH_ADDR"/>
158
+
<reg32 offset="0x01ea" name="CP_ME_RDADDR"/>
159
+
160
+
<reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/>
161
+
<reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/>
162
+
<reg32 offset="0x01f2" name="CP_INT_CNTL">
163
+
<bitfield name="SW_INT_MASK" pos="19" type="boolean"/>
164
+
<bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/>
165
+
<bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/>
166
+
<bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/>
167
+
<bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/>
168
+
<bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/>
169
+
<bitfield name="IB2_INT_MASK" pos="29" type="boolean"/>
170
+
<bitfield name="IB1_INT_MASK" pos="30" type="boolean"/>
171
+
<bitfield name="RB_INT_MASK" pos="31" type="boolean"/>
172
+
</reg32>
173
+
<reg32 offset="0x01f3" name="CP_INT_STATUS"/>
174
+
<reg32 offset="0x01f4" name="CP_INT_ACK"/>
175
+
<reg32 offset="0x01f6" name="CP_ME_CNTL">
176
+
<bitfield name="BUSY" pos="29" type="boolean"/>
177
+
<bitfield name="HALT" pos="28" type="boolean"/>
178
+
</reg32>
179
+
<reg32 offset="0x01f7" name="CP_ME_STATUS"/>
180
+
<reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/>
181
+
<reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/>
182
+
<reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/>
183
+
<reg32 offset="0x01fc" name="CP_DEBUG">
184
+
<bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/>
185
+
<bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/>
186
+
<bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/>
187
+
<bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/>
188
+
<bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/>
189
+
<bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/>
190
+
<bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/>
191
+
<bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/>
192
+
</reg32>
193
+
<reg32 offset="0x01fd" name="CP_CSQ_RB_STAT">
194
+
<bitfield name="RPTR" low="0" high="6" type="uint"/>
195
+
<bitfield name="WPTR" low="16" high="22" type="uint"/>
196
+
</reg32>
197
+
<reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT">
198
+
<bitfield name="RPTR" low="0" high="6" type="uint"/>
199
+
<bitfield name="WPTR" low="16" high="22" type="uint"/>
200
+
</reg32>
201
+
<reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT">
202
+
<bitfield name="RPTR" low="0" high="6" type="uint"/>
203
+
<bitfield name="WPTR" low="16" high="22" type="uint"/>
204
+
</reg32>
205
+
206
+
<reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/>
207
+
<reg32 offset="0x0443" name="CP_STQ_ST_STAT"/>
208
+
<reg32 offset="0x044d" name="CP_ST_BASE"/>
209
+
<reg32 offset="0x044e" name="CP_ST_BUFSZ"/>
210
+
<reg32 offset="0x044f" name="CP_MEQ_STAT"/>
211
+
<reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/>
212
+
<reg32 offset="0x0454" name="CP_BIN_MASK_LO"/>
213
+
<reg32 offset="0x0455" name="CP_BIN_MASK_HI"/>
214
+
<reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/>
215
+
<reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/>
216
+
<reg32 offset="0x0458" name="CP_IB1_BASE"/>
217
+
<reg32 offset="0x0459" name="CP_IB1_BUFSZ"/>
218
+
<reg32 offset="0x045a" name="CP_IB2_BASE"/>
219
+
<reg32 offset="0x045b" name="CP_IB2_BUFSZ"/>
220
+
<reg32 offset="0x047f" name="CP_STAT">
221
+
<bitfield pos="31" name="CP_BUSY"/>
222
+
<bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/>
223
+
<bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/>
224
+
<bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/>
225
+
<bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/>
226
+
<bitfield pos="26" name="ME_BUSY"/>
227
+
<bitfield pos="25" name="MIU_WR_C_BUSY"/>
228
+
<bitfield pos="23" name="CP_3D_BUSY"/>
229
+
<bitfield pos="22" name="CP_NRT_BUSY"/>
230
+
<bitfield pos="21" name="RBIU_SCRATCH_BUSY"/>
231
+
<bitfield pos="20" name="RCIU_ME_BUSY"/>
232
+
<bitfield pos="19" name="RCIU_PFP_BUSY"/>
233
+
<bitfield pos="18" name="MEQ_RING_BUSY"/>
234
+
<bitfield pos="17" name="PFP_BUSY"/>
235
+
<bitfield pos="16" name="ST_QUEUE_BUSY"/>
236
+
<bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/>
237
+
<bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/>
238
+
<bitfield pos="11" name="RING_QUEUE_BUSY"/>
239
+
<bitfield pos="10" name="CSF_BUSY"/>
240
+
<bitfield pos="9" name="CSF_ST_BUSY"/>
241
+
<bitfield pos="8" name="EVENT_BUSY"/>
242
+
<bitfield pos="7" name="CSF_INDIRECT2_BUSY"/>
243
+
<bitfield pos="6" name="CSF_INDIRECTS_BUSY"/>
244
+
<bitfield pos="5" name="CSF_RING_BUSY"/>
245
+
<bitfield pos="4" name="RCIU_BUSY"/>
246
+
<bitfield pos="3" name="RBIU_BUSY"/>
247
+
<bitfield pos="2" name="MIU_RD_RETURN_BUSY"/>
248
+
<bitfield pos="1" name="MIU_RD_REQ_BUSY"/>
249
+
<bitfield pos="0" name="MIU_WR_BUSY"/>
250
+
</reg32>
251
+
<reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/>
252
+
<reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/>
253
+
<reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/>
254
+
<reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/>
255
+
<reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/>
256
+
<reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/>
257
+
<reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/>
258
+
<reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/>
259
+
260
+
<reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/>
261
+
<reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/>
262
+
<reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/>
263
+
<reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/>
264
+
<reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/>
265
+
<reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/>
266
+
<reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/>
267
+
<reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/>
268
+
<reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/>
269
+
<reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/>
270
+
<reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/>
271
+
<reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/>
272
+
<reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/>
273
+
<reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/>
274
+
<reg32 offset="0x060e" name="CP_ME_NRT_DATA"/>
275
+
<reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/>
276
+
<reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/>
277
+
<reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/>
278
+
279
+
</domain>
280
+
281
+
<!--
282
+
Common between A3xx and A4xx:
283
+
-->
284
+
285
+
<enum name="a3xx_rop_code">
286
+
<value name="ROP_CLEAR" value="0"/>
287
+
<value name="ROP_NOR" value="1"/>
288
+
<value name="ROP_AND_INVERTED" value="2"/>
289
+
<value name="ROP_COPY_INVERTED" value="3"/>
290
+
<value name="ROP_AND_REVERSE" value="4"/>
291
+
<value name="ROP_INVERT" value="5"/>
292
+
<value name="ROP_XOR" value="6"/>
293
+
<value name="ROP_NAND" value="7"/>
294
+
<value name="ROP_AND" value="8"/>
295
+
<value name="ROP_EQUIV" value="9"/>
296
+
<value name="ROP_NOOP" value="10"/>
297
+
<value name="ROP_OR_INVERTED" value="11"/>
298
+
<value name="ROP_COPY" value="12"/>
299
+
<value name="ROP_OR_REVERSE" value="13"/>
300
+
<value name="ROP_OR" value="14"/>
301
+
<value name="ROP_SET" value="15"/>
302
+
</enum>
303
+
304
+
<enum name="a3xx_render_mode">
305
+
<value name="RB_RENDERING_PASS" value="0"/>
306
+
<value name="RB_TILING_PASS" value="1"/>
307
+
<value name="RB_RESOLVE_PASS" value="2"/>
308
+
<value name="RB_COMPUTE_PASS" value="3"/>
309
+
</enum>
310
+
311
+
<enum name="a3xx_msaa_samples">
312
+
<value name="MSAA_ONE" value="0"/>
313
+
<value name="MSAA_TWO" value="1"/>
314
+
<value name="MSAA_FOUR" value="2"/>
315
+
<value name="MSAA_EIGHT" value="3"/>
316
+
</enum>
317
+
318
+
<enum name="a3xx_threadmode">
319
+
<value value="0" name="MULTI"/>
320
+
<value value="1" name="SINGLE"/>
321
+
</enum>
322
+
323
+
<enum name="a3xx_instrbuffermode">
324
+
<!--
325
+
When shader size goes above ~128 or so, blob switches to '0'
326
+
and doesn't emit shader in cmdstream. When either is '0' it
327
+
doesn't get emitted via CP_LOAD_STATE. When only one is
328
+
'0' the other gets size 256-others_size. So I think that:
329
+
BUFFER => execute out of state memory
330
+
CACHE => use available state memory as local cache
331
+
NOTE that when CACHE mode, also set CACHEINVALID flag!
332
+
333
+
TODO check if that 256 size is same for all a3xx
334
+
-->
335
+
<value value="0" name="CACHE"/>
336
+
<value value="1" name="BUFFER"/>
337
+
</enum>
338
+
339
+
<enum name="a3xx_threadsize">
340
+
<value value="0" name="TWO_QUADS"/>
341
+
<value value="1" name="FOUR_QUADS"/>
342
+
</enum>
343
+
344
+
<enum name="a3xx_color_swap">
345
+
<value name="WZYX" value="0"/>
346
+
<value name="WXYZ" value="1"/>
347
+
<value name="ZYXW" value="2"/>
348
+
<value name="XYZW" value="3"/>
349
+
</enum>
350
+
351
+
<enum name="a3xx_rb_blend_opcode">
352
+
<value name="BLEND_DST_PLUS_SRC" value="0"/>
353
+
<value name="BLEND_SRC_MINUS_DST" value="1"/>
354
+
<value name="BLEND_DST_MINUS_SRC" value="2"/>
355
+
<value name="BLEND_MIN_DST_SRC" value="3"/>
356
+
<value name="BLEND_MAX_DST_SRC" value="4"/>
357
+
</enum>
358
+
359
+
<enum name="a4xx_tess_spacing">
360
+
<value name="EQUAL_SPACING" value="0"/>
361
+
<value name="ODD_SPACING" value="2"/>
362
+
<value name="EVEN_SPACING" value="3"/>
363
+
</enum>
364
+
365
+
<doc>Address mode for a5xx+</doc>
366
+
<enum name="a5xx_address_mode">
367
+
<value name="ADDR_32B" value="0"/>
368
+
<value name="ADDR_64B" value="1"/>
369
+
</enum>
370
+
371
+
<doc>
372
+
Line mode for a5xx+
373
+
Note that Bresenham lines are only supported with MSAA disabled.
374
+
</doc>
375
+
<enum name="a5xx_line_mode">
376
+
<value value="0x0" name="BRESENHAM"/>
377
+
<value value="0x1" name="RECTANGULAR"/>
378
+
</enum>
379
+
380
+
<doc>
381
+
Blob (v615) seem to only use SAM and I wasn't able to coerce
382
+
it to produce any other command.
383
+
Probably valid for a4xx+ but not enabled or tested on anything
384
+
but a6xx.
385
+
</doc>
386
+
<enum name="a6xx_tex_prefetch_cmd">
387
+
<doc> Produces garbage </doc>
388
+
<value value="0x0" name="TEX_PREFETCH_UNK0"/>
389
+
<value value="0x1" name="TEX_PREFETCH_SAM"/>
390
+
<value value="0x2" name="TEX_PREFETCH_GATHER4R"/>
391
+
<value value="0x3" name="TEX_PREFETCH_GATHER4G"/>
392
+
<value value="0x4" name="TEX_PREFETCH_GATHER4B"/>
393
+
<value value="0x5" name="TEX_PREFETCH_GATHER4A"/>
394
+
<doc> Causes reads from an invalid address </doc>
395
+
<value value="0x6" name="TEX_PREFETCH_UNK6"/>
396
+
<doc> Results in color being zero </doc>
397
+
<value value="0x7" name="TEX_PREFETCH_UNK7"/>
398
+
</enum>
399
+
400
+
</database>
+2268
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
+2268
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
···
1
+
<?xml version="1.0" encoding="UTF-8"?>
2
+
<database xmlns="http://nouveau.freedesktop.org/"
3
+
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4
+
xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5
+
<import file="freedreno_copyright.xml"/>
6
+
<import file="adreno/adreno_common.xml"/>
7
+
8
+
<enum name="vgt_event_type" varset="chip">
9
+
<value name="VS_DEALLOC" value="0"/>
10
+
<value name="PS_DEALLOC" value="1" variants="A2XX-A6XX"/>
11
+
<value name="VS_DONE_TS" value="2"/>
12
+
<value name="PS_DONE_TS" value="3"/>
13
+
<doc>
14
+
Flushes dirty data from UCHE, and also writes a GPU timestamp to
15
+
the address if one is provided.
16
+
</doc>
17
+
<value name="CACHE_FLUSH_TS" value="4"/>
18
+
<value name="CONTEXT_DONE" value="5"/>
19
+
<value name="CACHE_FLUSH" value="6" variants="A2XX-A4XX"/>
20
+
<value name="VIZQUERY_START" value="7" variants="A2XX"/>
21
+
<value name="HLSQ_FLUSH" value="7" variants="A3XX-A4XX"/>
22
+
<value name="VIZQUERY_END" value="8" variants="A2XX"/>
23
+
<value name="SC_WAIT_WC" value="9" variants="A2XX"/>
24
+
<value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
25
+
<value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
26
+
<value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
27
+
<!-- Not sure that these 4 events don't have the same meaning as on A5XX+ -->
28
+
<value name="RST_PIX_CNT" value="13" variants="A2XX-A4XX"/>
29
+
<value name="RST_VTX_CNT" value="14" variants="A2XX-A4XX"/>
30
+
<value name="TILE_FLUSH" value="15" variants="A2XX-A4XX"/>
31
+
<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
32
+
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
33
+
<doc>
34
+
If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed
35
+
sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main
36
+
memory, skipping UCHE.
37
+
</doc>
38
+
<value name="ZPASS_DONE" value="21"/>
39
+
<value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
40
+
41
+
<doc>
42
+
Writes the GPU timestamp to the address that follows, once RB
43
+
access and flushes are complete.
44
+
</doc>
45
+
<value name="RB_DONE_TS" value="22" variants="A3XX-"/>
46
+
47
+
<value name="PERFCOUNTER_START" value="23" variants="A2XX-A4XX"/>
48
+
<value name="PERFCOUNTER_STOP" value="24" variants="A2XX-A4XX"/>
49
+
<value name="VS_FETCH_DONE" value="27"/>
50
+
<value name="FACENESS_FLUSH" value="28" variants="A2XX-A4XX"/>
51
+
52
+
<!-- a5xx events -->
53
+
<value name="WT_DONE_TS" value="8" variants="A5XX-"/>
54
+
<value name="START_FRAGMENT_CTRS" value="13" variants="A5XX-"/>
55
+
<value name="STOP_FRAGMENT_CTRS" value="14" variants="A5XX-"/>
56
+
<value name="START_COMPUTE_CTRS" value="15" variants="A5XX-"/>
57
+
<value name="STOP_COMPUTE_CTRS" value="16" variants="A5XX-"/>
58
+
<value name="FLUSH_SO_0" value="17" variants="A5XX-"/>
59
+
<value name="FLUSH_SO_1" value="18" variants="A5XX-"/>
60
+
<value name="FLUSH_SO_2" value="19" variants="A5XX-"/>
61
+
<value name="FLUSH_SO_3" value="20" variants="A5XX-"/>
62
+
63
+
<doc>
64
+
Invalidates depth attachment data from the CCU. We assume this
65
+
happens in the last stage.
66
+
</doc>
67
+
<value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX-"/>
68
+
69
+
<doc>
70
+
Invalidates color attachment data from the CCU. We assume this
71
+
happens in the last stage.
72
+
</doc>
73
+
<value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX-"/>
74
+
75
+
<doc>
76
+
Flushes the small cache used by CP_EVENT_WRITE::BLIT (which,
77
+
along with its registers, would be better named RESOLVE).
78
+
</doc>
79
+
<value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
80
+
81
+
<doc>
82
+
Flushes depth attachment data from the CCU. We assume this
83
+
happens in the last stage.
84
+
</doc>
85
+
<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX-"/>
86
+
87
+
<doc>
88
+
Flushes color attachment data from the CCU. We assume this
89
+
happens in the last stage.
90
+
</doc>
91
+
<value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX-"/>
92
+
93
+
<doc>
94
+
2D blit to resolve GMEM to system memory (skipping CCU) at the
95
+
end of a render pass. Compare to CP_BLIT's BLIT_OP_SCALE for
96
+
more general blitting.
97
+
</doc>
98
+
<value name="BLIT" value="30" variants="A5XX-"/>
99
+
100
+
<doc>
101
+
Clears based on GRAS_LRZ_CNTL configuration, could clear
102
+
fast-clear buffer or LRZ direction.
103
+
LRZ direction is stored at lrz_fc_offset + 0x200, has 1 byte which
104
+
could be expressed by enum:
105
+
CUR_DIR_DISABLED = 0x0
106
+
CUR_DIR_GE = 0x1
107
+
CUR_DIR_LE = 0x2
108
+
CUR_DIR_UNSET = 0x3
109
+
Clear of direction means setting the direction to CUR_DIR_UNSET.
110
+
</doc>
111
+
<value name="LRZ_CLEAR" value="37" variants="A5XX-"/>
112
+
113
+
<value name="LRZ_FLUSH" value="38" variants="A5XX-"/>
114
+
<value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/>
115
+
<value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/>
116
+
<value name="UNK_40" value="40" variants="A7XX"/>
117
+
<value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/>
118
+
<value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/>
119
+
<value name="UNK_2C" value="44" variants="A5XX-"/>
120
+
<value name="UNK_2D" value="45" variants="A5XX-"/>
121
+
122
+
<!-- a6xx events -->
123
+
<doc>
124
+
Invalidates UCHE.
125
+
</doc>
126
+
<value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
127
+
128
+
<value name="LABEL" value="63" variants="A6XX-"/>
129
+
130
+
<!-- note, some of these are the same as a6xx, just named differently -->
131
+
132
+
<doc> Doesn't seem to do anything </doc>
133
+
<value name="DUMMY_EVENT" value="1" variants="A7XX"/>
134
+
<value name="CCU_INVALIDATE_DEPTH" value="24" variants="A7XX"/>
135
+
<value name="CCU_INVALIDATE_COLOR" value="25" variants="A7XX"/>
136
+
<value name="CCU_RESOLVE_CLEAN" value="26" variants="A7XX"/>
137
+
<value name="CCU_FLUSH_DEPTH" value="28" variants="A7XX"/>
138
+
<value name="CCU_FLUSH_COLOR" value="29" variants="A7XX"/>
139
+
<value name="CCU_RESOLVE" value="30" variants="A7XX"/>
140
+
<value name="CCU_END_RESOLVE_GROUP" value="31" variants="A7XX"/>
141
+
<value name="CCU_CLEAN_DEPTH" value="32" variants="A7XX"/>
142
+
<value name="CCU_CLEAN_COLOR" value="33" variants="A7XX"/>
143
+
<value name="CACHE_RESET" value="48" variants="A7XX"/>
144
+
<value name="CACHE_CLEAN" value="49" variants="A7XX"/>
145
+
<!-- TODO: deal with name conflicts with other gens -->
146
+
<value name="CACHE_FLUSH7" value="50" variants="A7XX"/>
147
+
<value name="CACHE_INVALIDATE7" value="51" variants="A7XX"/>
148
+
</enum>
149
+
150
+
<enum name="pc_di_primtype">
151
+
<value name="DI_PT_NONE" value="0"/>
152
+
<!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
153
+
<value name="DI_PT_POINTLIST_PSIZE" value="1"/>
154
+
<value name="DI_PT_LINELIST" value="2"/>
155
+
<value name="DI_PT_LINESTRIP" value="3"/>
156
+
<value name="DI_PT_TRILIST" value="4"/>
157
+
<value name="DI_PT_TRIFAN" value="5"/>
158
+
<value name="DI_PT_TRISTRIP" value="6"/>
159
+
<value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
160
+
<value name="DI_PT_RECTLIST" value="8"/>
161
+
<value name="DI_PT_POINTLIST" value="9"/>
162
+
<value name="DI_PT_LINE_ADJ" value="0xa"/>
163
+
<value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
164
+
<value name="DI_PT_TRI_ADJ" value="0xc"/>
165
+
<value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
166
+
167
+
<value name="DI_PT_PATCHES0" value="0x1f"/>
168
+
<value name="DI_PT_PATCHES1" value="0x20"/>
169
+
<value name="DI_PT_PATCHES2" value="0x21"/>
170
+
<value name="DI_PT_PATCHES3" value="0x22"/>
171
+
<value name="DI_PT_PATCHES4" value="0x23"/>
172
+
<value name="DI_PT_PATCHES5" value="0x24"/>
173
+
<value name="DI_PT_PATCHES6" value="0x25"/>
174
+
<value name="DI_PT_PATCHES7" value="0x26"/>
175
+
<value name="DI_PT_PATCHES8" value="0x27"/>
176
+
<value name="DI_PT_PATCHES9" value="0x28"/>
177
+
<value name="DI_PT_PATCHES10" value="0x29"/>
178
+
<value name="DI_PT_PATCHES11" value="0x2a"/>
179
+
<value name="DI_PT_PATCHES12" value="0x2b"/>
180
+
<value name="DI_PT_PATCHES13" value="0x2c"/>
181
+
<value name="DI_PT_PATCHES14" value="0x2d"/>
182
+
<value name="DI_PT_PATCHES15" value="0x2e"/>
183
+
<value name="DI_PT_PATCHES16" value="0x2f"/>
184
+
<value name="DI_PT_PATCHES17" value="0x30"/>
185
+
<value name="DI_PT_PATCHES18" value="0x31"/>
186
+
<value name="DI_PT_PATCHES19" value="0x32"/>
187
+
<value name="DI_PT_PATCHES20" value="0x33"/>
188
+
<value name="DI_PT_PATCHES21" value="0x34"/>
189
+
<value name="DI_PT_PATCHES22" value="0x35"/>
190
+
<value name="DI_PT_PATCHES23" value="0x36"/>
191
+
<value name="DI_PT_PATCHES24" value="0x37"/>
192
+
<value name="DI_PT_PATCHES25" value="0x38"/>
193
+
<value name="DI_PT_PATCHES26" value="0x39"/>
194
+
<value name="DI_PT_PATCHES27" value="0x3a"/>
195
+
<value name="DI_PT_PATCHES28" value="0x3b"/>
196
+
<value name="DI_PT_PATCHES29" value="0x3c"/>
197
+
<value name="DI_PT_PATCHES30" value="0x3d"/>
198
+
<value name="DI_PT_PATCHES31" value="0x3e"/>
199
+
</enum>
200
+
201
+
<enum name="pc_di_src_sel">
202
+
<value name="DI_SRC_SEL_DMA" value="0"/>
203
+
<value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
204
+
<value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
205
+
<value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
206
+
</enum>
207
+
208
+
<enum name="pc_di_face_cull_sel">
209
+
<value name="DI_FACE_CULL_NONE" value="0"/>
210
+
<value name="DI_FACE_CULL_FETCH" value="1"/>
211
+
<value name="DI_FACE_BACKFACE_CULL" value="2"/>
212
+
<value name="DI_FACE_FRONTFACE_CULL" value="3"/>
213
+
</enum>
214
+
215
+
<enum name="pc_di_index_size">
216
+
<value name="INDEX_SIZE_IGN" value="0"/>
217
+
<value name="INDEX_SIZE_16_BIT" value="0"/>
218
+
<value name="INDEX_SIZE_32_BIT" value="1"/>
219
+
<value name="INDEX_SIZE_8_BIT" value="2"/>
220
+
<value name="INDEX_SIZE_INVALID"/>
221
+
</enum>
222
+
223
+
<enum name="pc_di_vis_cull_mode">
224
+
<value name="IGNORE_VISIBILITY" value="0"/>
225
+
<value name="USE_VISIBILITY" value="1"/>
226
+
</enum>
227
+
228
+
<enum name="adreno_pm4_packet_type">
229
+
<value name="CP_TYPE0_PKT" value="0x00000000"/>
230
+
<value name="CP_TYPE1_PKT" value="0x40000000"/>
231
+
<value name="CP_TYPE2_PKT" value="0x80000000"/>
232
+
<value name="CP_TYPE3_PKT" value="0xc0000000"/>
233
+
<value name="CP_TYPE4_PKT" value="0x40000000"/>
234
+
<value name="CP_TYPE7_PKT" value="0x70000000"/>
235
+
</enum>
236
+
237
+
<!--
238
+
Note that in some cases, the same packet id is recycled on a later
239
+
generation, so variants attribute is used to distinguish. They
240
+
may not be completely accurate, we would probably have to analyze
241
+
the pfp and me/pm4 firmware to verify the packet is actually
242
+
handled on a particular generation. But it is at least enough to
243
+
disambiguate the packet-id's that were re-used for different
244
+
packets starting with a5xx.
245
+
-->
246
+
<enum name="adreno_pm4_type3_packets" varset="chip">
247
+
<doc>initialize CP's micro-engine</doc>
248
+
<value name="CP_ME_INIT" value="0x48"/>
249
+
<doc>skip N 32-bit words to get to the next packet</doc>
250
+
<value name="CP_NOP" value="0x10"/>
251
+
<doc>
252
+
indirect buffer dispatch. prefetch parser uses this packet
253
+
type to determine whether to pre-fetch the IB
254
+
</doc>
255
+
<value name="CP_PREEMPT_ENABLE" value="0x1c" variants="A5XX"/>
256
+
<value name="CP_PREEMPT_TOKEN" value="0x1e" variants="A5XX"/>
257
+
<value name="CP_INDIRECT_BUFFER" value="0x3f"/>
258
+
<doc>
259
+
Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
260
+
another buffer at the same level. Must be at the end of IB, and
261
+
doesn't work with draw state IB's.
262
+
</doc>
263
+
<value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
264
+
<doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
265
+
<value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
266
+
<doc>
267
+
Waits for the IDLE state of the engine before further drawing.
268
+
This is pipelined, so the CP may continue.
269
+
</doc>
270
+
<value name="CP_WAIT_FOR_IDLE" value="0x26"/>
271
+
<doc>wait until a register or memory location is a specific value</doc>
272
+
<value name="CP_WAIT_REG_MEM" value="0x3c"/>
273
+
<doc>wait until a register location is equal to a specific value</doc>
274
+
<value name="CP_WAIT_REG_EQ" value="0x52"/>
275
+
<doc>wait until a register location is >= a specific value</doc>
276
+
<value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX-A4XX"/>
277
+
<doc>wait until a read completes</doc>
278
+
<value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX-A4XX"/>
279
+
<doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
280
+
<!--
281
+
NOTE: CP_WAIT_IB_PFD_COMPLETE unimplemented at least since a5xx fw, and
282
+
recycled for something new on a7xx
283
+
-->
284
+
<value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d" varset="chip" variants="A2XX-A4XX"/>
285
+
<doc>register read/modify/write</doc>
286
+
<value name="CP_REG_RMW" value="0x21"/>
287
+
<doc>Set binning configuration registers</doc>
288
+
<value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX-A4XX"/>
289
+
<value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX-"/>
290
+
<doc>reads register in chip and writes to memory</doc>
291
+
<value name="CP_REG_TO_MEM" value="0x3e"/>
292
+
<doc>write N 32-bit words to memory</doc>
293
+
<value name="CP_MEM_WRITE" value="0x3d"/>
294
+
<doc>write CP_PROG_COUNTER value to memory</doc>
295
+
<value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
296
+
<doc>conditional execution of a sequence of packets</doc>
297
+
<value name="CP_COND_EXEC" value="0x44"/>
298
+
<doc>conditional write to memory or register</doc>
299
+
<value name="CP_COND_WRITE" value="0x45" variants="A2XX-A4XX"/>
300
+
<value name="CP_COND_WRITE5" value="0x45" variants="A5XX-"/>
301
+
<doc>generate an event that creates a write to memory when completed</doc>
302
+
<value name="CP_EVENT_WRITE" value="0x46" variants="A2XX-A6XX"/>
303
+
<value name="CP_EVENT_WRITE7" value="0x46" variants="A7XX-"/>
304
+
<doc>generate a VS|PS_done event</doc>
305
+
<value name="CP_EVENT_WRITE_SHD" value="0x58"/>
306
+
<doc>generate a cache flush done event</doc>
307
+
<value name="CP_EVENT_WRITE_CFL" value="0x59"/>
308
+
<doc>generate a z_pass done event</doc>
309
+
<value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
310
+
<doc>
311
+
not sure the real name, but this seems to be what is used for
312
+
opencl, instead of CP_DRAW_INDX..
313
+
</doc>
314
+
<value name="CP_RUN_OPENCL" value="0x31"/>
315
+
<doc>initiate fetch of index buffer and draw</doc>
316
+
<value name="CP_DRAW_INDX" value="0x22"/>
317
+
<doc>draw using supplied indices in packet</doc>
318
+
<value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
319
+
<doc>initiate fetch of index buffer and binIDs and draw</doc>
320
+
<value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX-A4XX"/>
321
+
<doc>initiate fetch of bin IDs and draw using supplied indices</doc>
322
+
<value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX-A4XX"/>
323
+
<doc>begin/end initiator for viz query extent processing</doc>
324
+
<value name="CP_VIZ_QUERY" value="0x23" variants="A2XX-A4XX"/>
325
+
<doc>fetch state sub-blocks and initiate shader code DMAs</doc>
326
+
<value name="CP_SET_STATE" value="0x25"/>
327
+
<doc>load constant into chip and to memory</doc>
328
+
<value name="CP_SET_CONSTANT" value="0x2d" variants="A2XX"/>
329
+
<doc>load sequencer instruction memory (pointer-based)</doc>
330
+
<value name="CP_IM_LOAD" value="0x27"/>
331
+
<doc>load sequencer instruction memory (code embedded in packet)</doc>
332
+
<value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
333
+
<doc>load constants from a location in memory</doc>
334
+
<value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
335
+
<doc>selective invalidation of state pointers</doc>
336
+
<value name="CP_INVALIDATE_STATE" value="0x3b"/>
337
+
<doc>dynamically changes shader instruction memory partition</doc>
338
+
<value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX-A4XX"/>
339
+
<doc>sets the 64-bit BIN_MASK register in the PFP</doc>
340
+
<value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX-A4XX"/>
341
+
<doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
342
+
<value name="CP_SET_BIN_SELECT" value="0x51" variants="A2XX-A4XX"/>
343
+
<doc>updates the current context, if needed</doc>
344
+
<value name="CP_CONTEXT_UPDATE" value="0x5e"/>
345
+
<doc>generate interrupt from the command stream</doc>
346
+
<value name="CP_INTERRUPT" value="0x40"/>
347
+
<doc>copy sequencer instruction memory to system memory</doc>
348
+
<value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
349
+
350
+
<!-- For a20x -->
351
+
<!-- TODO handle variants..
352
+
<doc>
353
+
Program an offset that will added to the BIN_BASE value of
354
+
the 3D_DRAW_INDX_BIN packet
355
+
</doc>
356
+
<value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
357
+
-->
358
+
359
+
<!-- for a22x -->
360
+
<doc>
361
+
sets draw initiator flags register in PFP, gets bitwise-ORed into
362
+
every draw initiator
363
+
</doc>
364
+
<value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
365
+
<doc>sets the register protection mode</doc>
366
+
<value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
367
+
368
+
<value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
369
+
370
+
<!-- for a3xx -->
371
+
<doc>load high level sequencer command</doc>
372
+
<value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
373
+
<value name="CP_LOAD_STATE4" value="0x30" variants="A4XX-A5XX"/>
374
+
<doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
375
+
<value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
376
+
<doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
377
+
<value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
378
+
<doc>Load a buffer with pre-fetch enabled</doc>
379
+
<value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
380
+
<doc>Set bin (?)</doc>
381
+
<value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
382
+
383
+
<doc>test 2 memory locations to dword values specified</doc>
384
+
<value name="CP_TEST_TWO_MEMS" value="0x71"/>
385
+
386
+
<doc>Write register, ignoring context state for context sensitive registers</doc>
387
+
<value name="CP_REG_WR_NO_CTXT" value="0x78"/>
388
+
389
+
<doc>Record the real-time when this packet is processed by PFP</doc>
390
+
<value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
391
+
392
+
<!-- Used to switch GPU between secure and non-secure modes -->
393
+
<value name="CP_SET_SECURE_MODE" value="0x66"/>
394
+
395
+
<doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
396
+
<value name="CP_WAIT_FOR_ME" value="0x13"/>
397
+
398
+
<!-- for a4xx -->
399
+
<doc>
400
+
Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
401
+
groups of registers. Looks like it can be used to create state
402
+
objects in GPU memory, and on state change only emit pointer
403
+
(via CP_SET_DRAW_STATE), which should be nice for reducing CPU
404
+
overhead:
405
+
406
+
(A4x) save PM4 stream pointers to execute upon a visible draw
407
+
</doc>
408
+
<value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX-"/>
409
+
<value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
410
+
<value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX-"/>
411
+
<value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX-"/>
412
+
<value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX-"/>
413
+
<value name="CP_DRAW_AUTO" value="0x24"/>
414
+
415
+
<doc>
416
+
Enable or disable predication globally. Also resets the
417
+
predicate to "passing" and the local bit to enabled when
418
+
enabling global predication.
419
+
</doc>
420
+
<value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
421
+
422
+
<doc>
423
+
Enable or disable predication locally. Unlike globally enabling
424
+
predication, this packet doesn't touch any other state.
425
+
Predication only happens when enabled globally and locally and a
426
+
predicate has been set. This should be used for internal draws
427
+
which aren't supposed to use the predication state:
428
+
429
+
CP_DRAW_PRED_ENABLE_LOCAL(0)
430
+
... do draw...
431
+
CP_DRAW_PRED_ENABLE_LOCAL(1)
432
+
</doc>
433
+
<value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
434
+
435
+
<doc>
436
+
Latch a draw predicate into the internal register.
437
+
</doc>
438
+
<value name="CP_DRAW_PRED_SET" value="0x4e"/>
439
+
440
+
<doc>
441
+
for A4xx
442
+
Write to register with address that does not fit into type-0 pkt
443
+
</doc>
444
+
<value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
445
+
446
+
<doc>copy from ME scratch RAM to a register</doc>
447
+
<value name="CP_SCRATCH_TO_REG" value="0x4d"/>
448
+
449
+
<doc>Copy from REG to ME scratch RAM</doc>
450
+
<value name="CP_REG_TO_SCRATCH" value="0x4a"/>
451
+
452
+
<doc>Wait for memory writes to complete</doc>
453
+
<value name="CP_WAIT_MEM_WRITES" value="0x12"/>
454
+
455
+
<doc>Conditional execution based on register comparison</doc>
456
+
<value name="CP_COND_REG_EXEC" value="0x47"/>
457
+
458
+
<doc>Memory to REG copy</doc>
459
+
<value name="CP_MEM_TO_REG" value="0x42"/>
460
+
461
+
<value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX-"/>
462
+
<value name="CP_EXEC_CS" value="0x33"/>
463
+
464
+
<doc>
465
+
for a5xx
466
+
</doc>
467
+
<value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
468
+
<!-- switches SMMU pagetable, used on a5xx+ only -->
469
+
<value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX-"/>
470
+
<!-- for a6xx -->
471
+
<doc>Tells CP the current mode of GPU operation</doc>
472
+
<value name="CP_SET_MARKER" value="0x65" variants="A6XX-"/>
473
+
<doc>Instruct CP to set a few internal CP registers</doc>
474
+
<value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX-"/>
475
+
<!--
476
+
pairs of regid and value.. seems to be used to program some TF
477
+
related regs:
478
+
-->
479
+
<value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX-"/>
480
+
<!-- A5XX Enable yield in RB only -->
481
+
<value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
482
+
<doc>
483
+
Enables IB2 skipping. If both GLOBAL and LOCAL are 1 and
484
+
nothing is left in the visibility stream, then
485
+
CP_INDIRECT_BUFFER will be skipped, and draws will early return
486
+
from their IB.
487
+
</doc>
488
+
<value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX-"/>
489
+
<value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX-"/>
490
+
<value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX-"/>
491
+
<value name="CP_WHERE_AM_I" value="0x62" variants="A5XX-"/>
492
+
<value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX-"/>
493
+
<!-- Enable/Disable/Defer A5x global preemption model -->
494
+
<value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
495
+
<!-- Enable/Disable A5x local preemption model -->
496
+
<value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
497
+
<!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
498
+
<value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX-"/>
499
+
<!-- Inform CP about current render mode (needed for a5xx preemption) -->
500
+
<value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
501
+
<value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
502
+
<!-- check if this works on earlier.. -->
503
+
<value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX-"/>
504
+
505
+
<doc>
506
+
General purpose 2D blit engine for image transfers and mipmap
507
+
generation. Reads through UCHE, writes through the CCU cache in
508
+
the PS stage.
509
+
</doc>
510
+
<value name="CP_BLIT" value="0x2c" variants="A5XX-"/>
511
+
512
+
<!-- Test specified bit in specified register and set predicate -->
513
+
<value name="CP_REG_TEST" value="0x39" variants="A5XX-"/>
514
+
515
+
<!--
516
+
Seems to set the mode flags which control which CP_SET_DRAW_STATE
517
+
packets are executed, based on their ENABLE_MASK values
518
+
519
+
CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
520
+
packets w/ ENABLE_MASK & 0x6 to execute immediately
521
+
-->
522
+
<value name="CP_SET_MODE" value="0x63" variants="A6XX-"/>
523
+
524
+
<!--
525
+
Seems like there are now separate blocks of state for VS vs FS/CS
526
+
(probably these amounts to geometry vs fragments so that geometry
527
+
stage of the pipeline for next draw can start while fragment stage
528
+
of current draw is still running. The format of the payload of the
529
+
packets is the same, the only difference is the offsets of the regs
530
+
the firmware code that handles the packet writes.
531
+
532
+
Note that for CL, starting with a6xx, the preferred # of local
533
+
threads is no longer the same as the max, implying that the shader
534
+
core can now run warps from unrelated shaders (ie.
535
+
CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
536
+
CL_KERNEL_WORK_GROUP_SIZE)
537
+
-->
538
+
<value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX-"/>
539
+
<value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX-"/>
540
+
<!--
541
+
Note: For IBO state (Image/SSBOs) which have shared state across
542
+
shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
543
+
compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
544
+
interchangable.
545
+
-->
546
+
<value name="CP_LOAD_STATE6" value="0x36" variants="A6XX-"/>
547
+
548
+
<!-- internal packets: -->
549
+
<value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
550
+
<value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
551
+
<value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
552
+
<value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
553
+
<value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
554
+
<value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
555
+
<value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
556
+
<value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
557
+
558
+
<!-- internal jumptable entries on a6xx+, possibly a5xx: -->
559
+
560
+
<!-- jmptable entry used to handle type4 packet on a5xx+: -->
561
+
<value name="PKT4" value="0x04" variants="A5XX-"/>
562
+
<!-- called when ROQ is empty, "returns" from an IB or merged sequence of IBs -->
563
+
<value name="IN_IB_END" value="0x0a" variants="A6XX-"/>
564
+
<!-- handles IFPC save/restore -->
565
+
<value name="IN_GMU_INTERRUPT" value="0x0b" variants="A6XX-"/>
566
+
<!-- preemption/context-swtich routine -->
567
+
<value name="IN_PREEMPT" value="0x0f" variants="A6XX-"/>
568
+
569
+
<!-- TODO do these exist on A5xx? -->
570
+
<value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
571
+
<value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX-"/>
572
+
<value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX-"/>
573
+
<value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
574
+
<value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
575
+
<value name="CP_MEMCPY" value="0x75" variants="A6XX-"/>
576
+
<value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX-"/>
577
+
<!-- A750+, set in place of CP_SET_BIN_DATA5_OFFSET but has different values -->
578
+
<value name="CP_SET_UNK_BIN_DATA" value="0x2d" variants="A7XX-"/>
579
+
<doc>
580
+
Write CP_CONTEXT_SWITCH_*_INFO from CP to the following dwords,
581
+
and forcibly switch to the indicated context.
582
+
</doc>
583
+
<value name="CP_CONTEXT_SWITCH" value="0x54" variants="A6XX"/>
584
+
<!-- Note, kgsl calls this CP_SET_AMBLE: -->
585
+
<value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX-"/>
586
+
587
+
<!--
588
+
Seems to always have the payload:
589
+
00000002 00008801 00004010
590
+
or:
591
+
00000002 00008801 00004090
592
+
or:
593
+
00000002 00008801 00000010
594
+
00000002 00008801 00010010
595
+
00000002 00008801 00d64010
596
+
...
597
+
Note set for compute shaders..
598
+
Is 0x8801 a register offset?
599
+
This appears to be a special sort of register write packet
600
+
more or less, but the firmware has some special handling..
601
+
Seems like it intercepts/modifies certain register offsets,
602
+
but others are treated like a normal PKT4 reg write. I
603
+
guess there are some registers that the fw controls certain
604
+
bits.
605
+
-->
606
+
<value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
607
+
608
+
<doc>
609
+
These first appear in a650_sqe.bin. They can in theory be used
610
+
to loop any sequence of IB1 commands, but in practice they are
611
+
used to loop over bins. There is a fixed-size per-iteration
612
+
prefix, used to set per-bin state, and then the following IB1
613
+
commands are executed until CP_END_BIN which are always the same
614
+
for each iteration and usually contain a list of
615
+
CP_INDIRECT_BUFFER calls to IB2 commands which setup state and
616
+
execute restore/draw/save commands. This replaces the previous
617
+
technique of just repeating the CP_INDIRECT_BUFFER calls and
618
+
"unrolling" the loop.
619
+
</doc>
620
+
<value name="CP_START_BIN" value="0x50" variants="A6XX-"/>
621
+
<value name="CP_END_BIN" value="0x51" variants="A6XX-"/>
622
+
623
+
<doc> Make next dword 1 to disable preemption, 0 to re-enable it. </doc>
624
+
<value name="CP_PREEMPT_DISABLE" value="0x6c" variants="A6XX"/>
625
+
626
+
<value name="CP_WAIT_TIMESTAMP" value="0x14" variants="A7XX-"/>
627
+
<value name="CP_GLOBAL_TIMESTAMP" value="0x15" variants="A7XX-"/> <!-- payload 1 dword -->
628
+
<value name="CP_LOCAL_TIMESTAMP" value="0x16" variants="A7XX-"/> <!-- payload 1 dword, follows 0x15 -->
629
+
<value name="CP_THREAD_CONTROL" value="0x17" variants="A7XX-"/>
630
+
<!-- payload 4 dwords, last two could be render target addr (one pkt per MRT), possibly used for GMEM save/restore?-->
631
+
<value name="CP_RESOURCE_LIST" value="0x18" variants="A7XX-"/>
632
+
<doc> Can clear BV/BR counters, or wait until one catches up to another </doc>
633
+
<value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/>
634
+
<doc> Clears, adds to local, or adds to global timestamp </doc>
635
+
<value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/>
636
+
<!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? -->
637
+
<value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/>
638
+
<doc>
639
+
Write to a scratch memory that is read by CP_REG_TEST with
640
+
SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers.
641
+
However it uses the same memory space.
642
+
</doc>
643
+
<value name="CP_MEM_TO_SCRATCH_MEM" value="0x49" variants="A7XX-"/>
644
+
645
+
<doc>
646
+
Executes an array of fixed-size command buffers where each
647
+
buffer is assumed to have one draw call, skipping buffers with
648
+
non-visible draw calls.
649
+
</doc>
650
+
<value name="CP_FIXED_STRIDE_DRAW_TABLE" value="0x7f" variants="A7XX-"/>
651
+
652
+
<doc>Reset various on-chip state used for synchronization</doc>
653
+
<value name="CP_RESET_CONTEXT_STATE" value="0x1f" variants="A7XX-"/>
654
+
</enum>
655
+
656
+
657
+
<domain name="CP_LOAD_STATE" width="32">
658
+
<doc>Load state, a3xx (and later?)</doc>
659
+
<enum name="adreno_state_block">
660
+
<value name="SB_VERT_TEX" value="0"/>
661
+
<value name="SB_VERT_MIPADDR" value="1"/>
662
+
<value name="SB_FRAG_TEX" value="2"/>
663
+
<value name="SB_FRAG_MIPADDR" value="3"/>
664
+
<value name="SB_VERT_SHADER" value="4"/>
665
+
<value name="SB_GEOM_SHADER" value="5"/>
666
+
<value name="SB_FRAG_SHADER" value="6"/>
667
+
<value name="SB_COMPUTE_SHADER" value="7"/>
668
+
</enum>
669
+
<enum name="adreno_state_type">
670
+
<value name="ST_SHADER" value="0"/>
671
+
<value name="ST_CONSTANTS" value="1"/>
672
+
</enum>
673
+
<enum name="adreno_state_src">
674
+
<value name="SS_DIRECT" value="0">
675
+
<doc>inline with the CP_LOAD_STATE packet</doc>
676
+
</value>
677
+
<value name="SS_INVALID_ALL_IC" value="2"/>
678
+
<value name="SS_INVALID_PART_IC" value="3"/>
679
+
<value name="SS_INDIRECT" value="4">
680
+
<doc>in buffer pointed to by EXT_SRC_ADDR</doc>
681
+
</value>
682
+
<value name="SS_INDIRECT_TCM" value="5"/>
683
+
<value name="SS_INDIRECT_STM" value="6"/>
684
+
</enum>
685
+
<reg32 offset="0" name="0">
686
+
<bitfield name="DST_OFF" low="0" high="15" type="uint"/>
687
+
<bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
688
+
<bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
689
+
<bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
690
+
</reg32>
691
+
<reg32 offset="1" name="1">
692
+
<bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
693
+
<bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
694
+
</reg32>
695
+
</domain>
696
+
697
+
<domain name="CP_LOAD_STATE4" width="32" varset="chip">
698
+
<doc>Load state, a4xx+</doc>
699
+
<enum name="a4xx_state_block">
700
+
<!--
701
+
unknown: 0x7 and 0xf <- seen in compute shader
702
+
703
+
STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
704
+
Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
705
+
the gpuaddr of the following shader constants block. DST_OFF seems
706
+
to specify which shader stage:
707
+
708
+
16 -> vert
709
+
36 -> tcs
710
+
56 -> tes
711
+
76 -> geom
712
+
96 -> frag
713
+
714
+
Example:
715
+
716
+
opcode: CP_LOAD_STATE4 (30) (12 dwords)
717
+
{ DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
718
+
{ STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
719
+
{ EXT_SRC_ADDR_HI = 0 }
720
+
0000: c0264100 00000000 00000000 00000000
721
+
0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
722
+
723
+
opcode: CP_LOAD_STATE4 (30) (4 dwords)
724
+
{ DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
725
+
{ STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
726
+
{ EXT_SRC_ADDR_HI = 0 }
727
+
0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
728
+
0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
729
+
0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
730
+
731
+
STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
732
+
733
+
-->
734
+
<value name="SB4_VS_TEX" value="0x0"/>
735
+
<value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
736
+
<value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
737
+
<value name="SB4_GS_TEX" value="0x3"/>
738
+
<value name="SB4_FS_TEX" value="0x4"/>
739
+
<value name="SB4_CS_TEX" value="0x5"/>
740
+
<value name="SB4_VS_SHADER" value="0x8"/>
741
+
<value name="SB4_HS_SHADER" value="0x9"/>
742
+
<value name="SB4_DS_SHADER" value="0xa"/>
743
+
<value name="SB4_GS_SHADER" value="0xb"/>
744
+
<value name="SB4_FS_SHADER" value="0xc"/>
745
+
<value name="SB4_CS_SHADER" value="0xd"/>
746
+
<!--
747
+
for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
748
+
STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
749
+
750
+
Compute has it's own dedicated SSBO state, it seems, but the rest
751
+
of the stages share state
752
+
-->
753
+
<value name="SB4_SSBO" value="0xe"/>
754
+
<value name="SB4_CS_SSBO" value="0xf"/>
755
+
</enum>
756
+
<enum name="a4xx_state_type">
757
+
<value name="ST4_SHADER" value="0"/>
758
+
<value name="ST4_CONSTANTS" value="1"/>
759
+
<value name="ST4_UBO" value="2"/>
760
+
</enum>
761
+
<enum name="a4xx_state_src">
762
+
<value name="SS4_DIRECT" value="0"/>
763
+
<value name="SS4_INDIRECT" value="2"/>
764
+
</enum>
765
+
<reg32 offset="0" name="0">
766
+
<bitfield name="DST_OFF" low="0" high="13" type="uint"/>
767
+
<bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
768
+
<bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
769
+
<bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
770
+
</reg32>
771
+
<reg32 offset="1" name="1">
772
+
<bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
773
+
<bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
774
+
</reg32>
775
+
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
776
+
<bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
777
+
</reg32>
778
+
</domain>
779
+
780
+
<!-- looks basically same CP_LOAD_STATE4 -->
781
+
<domain name="CP_LOAD_STATE6" width="32" varset="chip">
782
+
<doc>Load state, a6xx+</doc>
783
+
<enum name="a6xx_state_block">
784
+
<value name="SB6_VS_TEX" value="0x0"/>
785
+
<value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
786
+
<value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
787
+
<value name="SB6_GS_TEX" value="0x3"/>
788
+
<value name="SB6_FS_TEX" value="0x4"/>
789
+
<value name="SB6_CS_TEX" value="0x5"/>
790
+
<value name="SB6_VS_SHADER" value="0x8"/>
791
+
<value name="SB6_HS_SHADER" value="0x9"/>
792
+
<value name="SB6_DS_SHADER" value="0xa"/>
793
+
<value name="SB6_GS_SHADER" value="0xb"/>
794
+
<value name="SB6_FS_SHADER" value="0xc"/>
795
+
<value name="SB6_CS_SHADER" value="0xd"/>
796
+
<value name="SB6_IBO" value="0xe"/>
797
+
<value name="SB6_CS_IBO" value="0xf"/>
798
+
</enum>
799
+
<enum name="a6xx_state_type">
800
+
<value name="ST6_SHADER" value="0"/>
801
+
<value name="ST6_CONSTANTS" value="1"/>
802
+
<value name="ST6_UBO" value="2"/>
803
+
<value name="ST6_IBO" value="3"/>
804
+
</enum>
805
+
<enum name="a6xx_state_src">
806
+
<value name="SS6_DIRECT" value="0"/>
807
+
<value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
808
+
<value name="SS6_INDIRECT" value="2"/>
809
+
<doc>
810
+
SS6_UBO used by the a6xx vulkan blob with tesselation constants
811
+
in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset)
812
+
to load constants from a UBO loaded with DST_OFF = 14 and offset 0,
813
+
EXT_SRC_ADDR = 0xe0000
814
+
(offset is a guess, should be in bytes given that maxUniformBufferRange=64k)
815
+
</doc>
816
+
<value name="SS6_UBO" value="3"/>
817
+
</enum>
818
+
<reg32 offset="0" name="0">
819
+
<bitfield name="DST_OFF" low="0" high="13" type="uint"/>
820
+
<bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
821
+
<bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
822
+
<bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
823
+
<bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
824
+
</reg32>
825
+
<reg32 offset="1" name="1">
826
+
<bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
827
+
</reg32>
828
+
<reg32 offset="2" name="2">
829
+
<bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
830
+
</reg32>
831
+
<reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
832
+
</domain>
833
+
834
+
<bitset name="vgt_draw_initiator" inline="yes">
835
+
<bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
836
+
<bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
837
+
<bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
838
+
<bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
839
+
<bitfield name="NOT_EOP" pos="12" type="boolean"/>
840
+
<bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
841
+
<bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
842
+
<bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
843
+
</bitset>
844
+
845
+
<!-- changed on a4xx: -->
846
+
<enum name="a4xx_index_size">
847
+
<value name="INDEX4_SIZE_8_BIT" value="0"/>
848
+
<value name="INDEX4_SIZE_16_BIT" value="1"/>
849
+
<value name="INDEX4_SIZE_32_BIT" value="2"/>
850
+
</enum>
851
+
852
+
<enum name="a6xx_patch_type">
853
+
<value name="TESS_QUADS" value="0"/>
854
+
<value name="TESS_TRIANGLES" value="1"/>
855
+
<value name="TESS_ISOLINES" value="2"/>
856
+
</enum>
857
+
858
+
<bitset name="vgt_draw_initiator_a4xx" inline="yes">
859
+
<!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
860
+
<bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
861
+
<bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
862
+
<bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
863
+
<bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
864
+
<bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
865
+
<bitfield name="GS_ENABLE" pos="16" type="boolean"/>
866
+
<bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
867
+
</bitset>
868
+
869
+
<domain name="CP_DRAW_INDX" width="32">
870
+
<reg32 offset="0" name="0">
871
+
<bitfield name="VIZ_QUERY" low="0" high="31"/>
872
+
</reg32>
873
+
<reg32 offset="1" name="1" type="vgt_draw_initiator"/>
874
+
<reg32 offset="2" name="2">
875
+
<bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
876
+
</reg32>
877
+
<reg32 offset="3" name="3">
878
+
<bitfield name="INDX_BASE" low="0" high="31"/>
879
+
</reg32>
880
+
<reg32 offset="4" name="4">
881
+
<bitfield name="INDX_SIZE" low="0" high="31"/>
882
+
</reg32>
883
+
</domain>
884
+
885
+
<domain name="CP_DRAW_INDX_2" width="32">
886
+
<reg32 offset="0" name="0">
887
+
<bitfield name="VIZ_QUERY" low="0" high="31"/>
888
+
</reg32>
889
+
<reg32 offset="1" name="1" type="vgt_draw_initiator"/>
890
+
<reg32 offset="2" name="2">
891
+
<bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
892
+
</reg32>
893
+
<!-- followed by NUM_INDICES indices.. -->
894
+
</domain>
895
+
896
+
<domain name="CP_DRAW_INDX_OFFSET" width="32">
897
+
<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
898
+
<reg32 offset="1" name="1">
899
+
<bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
900
+
</reg32>
901
+
<reg32 offset="2" name="2">
902
+
<bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
903
+
</reg32>
904
+
<reg32 offset="3" name="3">
905
+
<bitfield name="FIRST_INDX" low="0" high="31"/>
906
+
</reg32>
907
+
908
+
<stripe varset="chip" variants="A5XX-">
909
+
<reg32 offset="4" name="4">
910
+
<bitfield name="INDX_BASE_LO" low="0" high="31"/>
911
+
</reg32>
912
+
<reg32 offset="5" name="5">
913
+
<bitfield name="INDX_BASE_HI" low="0" high="31"/>
914
+
</reg32>
915
+
<reg64 offset="4" name="INDX_BASE" type="address"/>
916
+
<reg32 offset="6" name="6">
917
+
<!-- max # of elements in index buffer -->
918
+
<bitfield name="MAX_INDICES" low="0" high="31"/>
919
+
</reg32>
920
+
</stripe>
921
+
922
+
<reg32 offset="4" name="4">
923
+
<bitfield name="INDX_BASE" low="0" high="31" type="address"/>
924
+
</reg32>
925
+
926
+
<reg32 offset="5" name="5">
927
+
<bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
928
+
</reg32>
929
+
</domain>
930
+
931
+
<domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
932
+
<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
933
+
<stripe varset="chip" variants="A4XX">
934
+
<reg32 offset="1" name="1">
935
+
<bitfield name="INDIRECT" low="0" high="31"/>
936
+
</reg32>
937
+
</stripe>
938
+
<stripe varset="chip" variants="A5XX-">
939
+
<reg32 offset="1" name="1">
940
+
<bitfield name="INDIRECT_LO" low="0" high="31"/>
941
+
</reg32>
942
+
<reg32 offset="2" name="2">
943
+
<bitfield name="INDIRECT_HI" low="0" high="31"/>
944
+
</reg32>
945
+
<reg64 offset="1" name="INDIRECT" type="address"/>
946
+
</stripe>
947
+
</domain>
948
+
949
+
<domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
950
+
<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
951
+
<stripe varset="chip" variants="A4XX">
952
+
<reg32 offset="1" name="1">
953
+
<bitfield name="INDX_BASE" low="0" high="31"/>
954
+
</reg32>
955
+
<reg32 offset="2" name="2">
956
+
<!-- max # of bytes in index buffer -->
957
+
<bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
958
+
</reg32>
959
+
<reg32 offset="3" name="3">
960
+
<bitfield name="INDIRECT" low="0" high="31"/>
961
+
</reg32>
962
+
</stripe>
963
+
<stripe varset="chip" variants="A5XX-">
964
+
<reg32 offset="1" name="1">
965
+
<bitfield name="INDX_BASE_LO" low="0" high="31"/>
966
+
</reg32>
967
+
<reg32 offset="2" name="2">
968
+
<bitfield name="INDX_BASE_HI" low="0" high="31"/>
969
+
</reg32>
970
+
<reg64 offset="1" name="INDX_BASE" type="address"/>
971
+
<reg32 offset="3" name="3">
972
+
<!-- max # of elements in index buffer -->
973
+
<bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
974
+
</reg32>
975
+
<reg32 offset="4" name="4">
976
+
<bitfield name="INDIRECT_LO" low="0" high="31"/>
977
+
</reg32>
978
+
<reg32 offset="5" name="5">
979
+
<bitfield name="INDIRECT_HI" low="0" high="31"/>
980
+
</reg32>
981
+
<reg64 offset="4" name="INDIRECT" type="address"/>
982
+
</stripe>
983
+
</domain>
984
+
985
+
<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
986
+
<enum name="a6xx_draw_indirect_opcode">
987
+
<value name="INDIRECT_OP_NORMAL" value="0x2"/>
988
+
<value name="INDIRECT_OP_INDEXED" value="0x4"/>
989
+
<value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/>
990
+
<value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/>
991
+
</enum>
992
+
<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
993
+
<reg32 offset="1" name="1">
994
+
<bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
995
+
<doc>
996
+
DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
997
+
be updated for each draw to {draw_id, first_vertex, first_instance, 0}
998
+
value of 0 disables it
999
+
</doc>
1000
+
<bitfield name="DST_OFF" low="8" high="21" type="hex"/>
1001
+
</reg32>
1002
+
<reg32 offset="2" name="DRAW_COUNT" type="uint"/>
1003
+
<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL">
1004
+
<reg64 offset="3" name="INDIRECT" type="address"/>
1005
+
<reg32 offset="5" name="STRIDE" type="uint"/>
1006
+
</stripe>
1007
+
<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED" prefix="INDEXED">
1008
+
<reg64 offset="3" name="INDEX" type="address"/>
1009
+
<reg32 offset="5" name="MAX_INDICES" type="uint"/>
1010
+
<reg64 offset="6" name="INDIRECT" type="address"/>
1011
+
<reg32 offset="8" name="STRIDE" type="uint"/>
1012
+
</stripe>
1013
+
<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT" prefix="INDIRECT">
1014
+
<reg64 offset="3" name="INDIRECT" type="address"/>
1015
+
<reg64 offset="5" name="INDIRECT_COUNT" type="address"/>
1016
+
<reg32 offset="7" name="STRIDE" type="uint"/>
1017
+
</stripe>
1018
+
<stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED" prefix="INDIRECT_INDEXED">
1019
+
<reg64 offset="3" name="INDEX" type="address"/>
1020
+
<reg32 offset="5" name="MAX_INDICES" type="uint"/>
1021
+
<reg64 offset="6" name="INDIRECT" type="address"/>
1022
+
<reg64 offset="8" name="INDIRECT_COUNT" type="address"/>
1023
+
<reg32 offset="10" name="STRIDE" type="uint"/>
1024
+
</stripe>
1025
+
</domain>
1026
+
1027
+
<domain name="CP_DRAW_AUTO" width="32">
1028
+
<reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
1029
+
<reg32 offset="1" name="1">
1030
+
<bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
1031
+
</reg32>
1032
+
<reg64 offset="2" name="NUM_VERTICES_BASE" type="address"/>
1033
+
<reg32 offset="4" name="4">
1034
+
<bitfield name="NUM_VERTICES_OFFSET" low="0" high="31" type="uint"/>
1035
+
</reg32>
1036
+
<reg32 offset="5" name="5">
1037
+
<bitfield name="STRIDE" low="0" high="31" type="uint"/>
1038
+
</reg32>
1039
+
</domain>
1040
+
1041
+
<domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip">
1042
+
<reg32 offset="0" name="0">
1043
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
1044
+
</reg32>
1045
+
</domain>
1046
+
1047
+
<domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip">
1048
+
<reg32 offset="0" name="0">
1049
+
<bitfield name="ENABLE" pos="0" type="boolean"/>
1050
+
</reg32>
1051
+
</domain>
1052
+
1053
+
<domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
1054
+
<enum name="cp_draw_pred_src">
1055
+
<!--
1056
+
Sources 1-4 seem to be about combining reading
1057
+
SO/primitive queries and setting the predicate, which is
1058
+
a DX11-specific optimization (since in DX11 you can only
1059
+
predicate on the result of queries).
1060
+
-->
1061
+
<value name="PRED_SRC_MEM" value="5">
1062
+
<doc>
1063
+
Read a 64-bit value at the given address and
1064
+
test if it equals/doesn't equal 0.
1065
+
</doc>
1066
+
</value>
1067
+
</enum>
1068
+
<enum name="cp_draw_pred_test">
1069
+
<value name="NE_0_PASS" value="0"/>
1070
+
<value name="EQ_0_PASS" value="1"/>
1071
+
</enum>
1072
+
<reg32 offset="0" name="0">
1073
+
<bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
1074
+
<bitfield name="TEST" pos="8" type="cp_draw_pred_test"/>
1075
+
</reg32>
1076
+
<reg64 offset="1" name="MEM_ADDR" type="address"/>
1077
+
</domain>
1078
+
1079
+
<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
1080
+
<array offset="0" stride="3" length="100">
1081
+
<reg32 offset="0" name="0">
1082
+
<bitfield name="COUNT" low="0" high="15" type="uint"/>
1083
+
<bitfield name="DIRTY" pos="16" type="boolean"/>
1084
+
<bitfield name="DISABLE" pos="17" type="boolean"/>
1085
+
<bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
1086
+
<bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
1087
+
<bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
1088
+
<bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
1089
+
<bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
1090
+
<bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
1091
+
</reg32>
1092
+
<reg32 offset="1" name="1">
1093
+
<bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
1094
+
</reg32>
1095
+
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1096
+
<bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
1097
+
</reg32>
1098
+
</array>
1099
+
</domain>
1100
+
1101
+
<domain name="CP_SET_BIN" width="32">
1102
+
<doc>value at offset 0 always seems to be 0x00000000..</doc>
1103
+
<reg32 offset="0" name="0"/>
1104
+
<reg32 offset="1" name="1">
1105
+
<bitfield name="X1" low="0" high="15" type="uint"/>
1106
+
<bitfield name="Y1" low="16" high="31" type="uint"/>
1107
+
</reg32>
1108
+
<reg32 offset="2" name="2">
1109
+
<bitfield name="X2" low="0" high="15" type="uint"/>
1110
+
<bitfield name="Y2" low="16" high="31" type="uint"/>
1111
+
</reg32>
1112
+
</domain>
1113
+
1114
+
<domain name="CP_SET_BIN_DATA" width="32">
1115
+
<reg32 offset="0" name="0">
1116
+
<!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
1117
+
<bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
1118
+
</reg32>
1119
+
<reg32 offset="1" name="1">
1120
+
<!-- seesm to correspond to VSC_SIZE_ADDRESS -->
1121
+
<bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
1122
+
</reg32>
1123
+
</domain>
1124
+
1125
+
<domain name="CP_SET_BIN_DATA5" width="32">
1126
+
<reg32 offset="0" name="0">
1127
+
<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1128
+
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
1129
+
<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
1130
+
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
1131
+
</reg32>
1132
+
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
1133
+
<reg32 offset="1" name="1">
1134
+
<bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
1135
+
</reg32>
1136
+
<reg32 offset="2" name="2">
1137
+
<bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
1138
+
</reg32>
1139
+
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
1140
+
<reg32 offset="3" name="3">
1141
+
<bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
1142
+
</reg32>
1143
+
<reg32 offset="4" name="4">
1144
+
<bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
1145
+
</reg32>
1146
+
<!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
1147
+
<reg32 offset="5" name="5">
1148
+
<bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
1149
+
</reg32>
1150
+
<reg32 offset="6" name="6">
1151
+
<bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
1152
+
</reg32>
1153
+
<!--
1154
+
a7xx adds a few more addresses to the end of the pkt
1155
+
-->
1156
+
<reg64 offset="7" name="7"/>
1157
+
<reg64 offset="9" name="9"/>
1158
+
</domain>
1159
+
1160
+
<domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
1161
+
<doc>
1162
+
Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
1163
+
pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
1164
+
for Vulkan where these values aren't known when the command
1165
+
stream is recorded.
1166
+
</doc>
1167
+
<reg32 offset="0" name="0">
1168
+
<!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
1169
+
<bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
1170
+
<!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
1171
+
<bitfield name="VSC_N" low="22" high="26" type="uint"/>
1172
+
</reg32>
1173
+
<!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
1174
+
<reg32 offset="1" name="1">
1175
+
<bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
1176
+
</reg32>
1177
+
<!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
1178
+
<reg32 offset="2" name="2">
1179
+
<bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
1180
+
</reg32>
1181
+
<!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
1182
+
<reg32 offset="3" name="3">
1183
+
<bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
1184
+
</reg32>
1185
+
</domain>
1186
+
1187
+
<domain name="CP_REG_RMW" width="32">
1188
+
<doc>
1189
+
Modifies DST_REG using two sources that can either be registers
1190
+
or immediates. If SRC1_ADD is set, then do the following:
1191
+
1192
+
$dst = (($dst & $src0) rot $rotate) + $src1
1193
+
1194
+
Otherwise:
1195
+
1196
+
$dst = (($dst & $src0) rot $rotate) | $src1
1197
+
1198
+
Here "rot" means rotate left.
1199
+
</doc>
1200
+
<reg32 offset="0" name="0">
1201
+
<bitfield name="DST_REG" low="0" high="17" type="hex"/>
1202
+
<bitfield name="ROTATE" low="24" high="28" type="uint"/>
1203
+
<bitfield name="SRC1_ADD" pos="29" type="boolean"/>
1204
+
<bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
1205
+
<bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
1206
+
</reg32>
1207
+
<reg32 offset="1" name="1">
1208
+
<bitfield name="SRC0" low="0" high="31" type="uint"/>
1209
+
</reg32>
1210
+
<reg32 offset="2" name="2">
1211
+
<bitfield name="SRC1" low="0" high="31" type="uint"/>
1212
+
</reg32>
1213
+
</domain>
1214
+
1215
+
<domain name="CP_REG_TO_MEM" width="32">
1216
+
<reg32 offset="0" name="0">
1217
+
<bitfield name="REG" low="0" high="17" type="hex"/>
1218
+
<!-- number of registers/dwords copied is max(CNT, 1). -->
1219
+
<bitfield name="CNT" low="18" high="29" type="uint"/>
1220
+
<bitfield name="64B" pos="30" type="boolean"/>
1221
+
<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1222
+
</reg32>
1223
+
<reg32 offset="1" name="1">
1224
+
<bitfield name="DEST" low="0" high="31"/>
1225
+
</reg32>
1226
+
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1227
+
<bitfield name="DEST_HI" low="0" high="31"/>
1228
+
</reg32>
1229
+
</domain>
1230
+
1231
+
<domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
1232
+
<doc>
1233
+
Like CP_REG_TO_MEM, but the memory address to write to can be
1234
+
offsetted using either one or two registers or scratch
1235
+
registers.
1236
+
</doc>
1237
+
<reg32 offset="0" name="0">
1238
+
<bitfield name="REG" low="0" high="17" type="hex"/>
1239
+
<!-- number of registers/dwords copied is max(CNT, 1). -->
1240
+
<bitfield name="CNT" low="18" high="29" type="uint"/>
1241
+
<bitfield name="64B" pos="30" type="boolean"/>
1242
+
<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1243
+
</reg32>
1244
+
<reg32 offset="1" name="1">
1245
+
<bitfield name="DEST" low="0" high="31"/>
1246
+
</reg32>
1247
+
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1248
+
<bitfield name="DEST_HI" low="0" high="31"/>
1249
+
</reg32>
1250
+
<reg32 offset="3" name="3">
1251
+
<bitfield name="OFFSET0" low="0" high="17" type="hex"/>
1252
+
<bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
1253
+
</reg32>
1254
+
<!-- followed by an optional identical OFFSET1 dword -->
1255
+
</domain>
1256
+
1257
+
<domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
1258
+
<doc>
1259
+
Like CP_REG_TO_MEM, but the memory address to write to can be
1260
+
offsetted using a DWORD in memory.
1261
+
</doc>
1262
+
<reg32 offset="0" name="0">
1263
+
<bitfield name="REG" low="0" high="17" type="hex"/>
1264
+
<!-- number of registers/dwords copied is max(CNT, 1). -->
1265
+
<bitfield name="CNT" low="18" high="29" type="uint"/>
1266
+
<bitfield name="64B" pos="30" type="boolean"/>
1267
+
<bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1268
+
</reg32>
1269
+
<reg32 offset="1" name="1">
1270
+
<bitfield name="DEST" low="0" high="31"/>
1271
+
</reg32>
1272
+
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1273
+
<bitfield name="DEST_HI" low="0" high="31"/>
1274
+
</reg32>
1275
+
<reg32 offset="3" name="3">
1276
+
<bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1277
+
</reg32>
1278
+
<reg32 offset="4" name="4">
1279
+
<bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1280
+
</reg32>
1281
+
</domain>
1282
+
1283
+
<domain name="CP_MEM_TO_REG" width="32">
1284
+
<reg32 offset="0" name="0">
1285
+
<bitfield name="REG" low="0" high="17" type="hex"/>
1286
+
<!-- number of registers/dwords copied is max(CNT, 1). -->
1287
+
<bitfield name="CNT" low="19" high="29" type="uint"/>
1288
+
<!-- shift each DWORD left by 2 while copying -->
1289
+
<bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
1290
+
<!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1291
+
<bitfield name="UNK31" pos="31" type="boolean"/>
1292
+
</reg32>
1293
+
<reg32 offset="1" name="1">
1294
+
<bitfield name="SRC" low="0" high="31"/>
1295
+
</reg32>
1296
+
<reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1297
+
<bitfield name="SRC_HI" low="0" high="31"/>
1298
+
</reg32>
1299
+
</domain>
1300
+
1301
+
<domain name="CP_MEM_TO_MEM" width="32">
1302
+
<reg32 offset="0" name="0">
1303
+
<!--
1304
+
not sure how many src operands we have, but the low
1305
+
bits negate the n'th src argument.
1306
+
-->
1307
+
<bitfield name="NEG_A" pos="0" type="boolean"/>
1308
+
<bitfield name="NEG_B" pos="1" type="boolean"/>
1309
+
<bitfield name="NEG_C" pos="2" type="boolean"/>
1310
+
1311
+
<!-- if set treat src/dst as 64bit values -->
1312
+
<bitfield name="DOUBLE" pos="29" type="boolean"/>
1313
+
<!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1314
+
<bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
1315
+
<!-- some other kind of wait -->
1316
+
<bitfield name="UNK31" pos="31" type="boolean"/>
1317
+
</reg32>
1318
+
<!--
1319
+
followed by sequence of addresses.. the first is the
1320
+
destination and the rest are N src addresses which are
1321
+
summed (after being negated if NEG_x bit set) allowing
1322
+
to do things like 'result += end - start' (which turns
1323
+
out to be useful for queries and accumulating results
1324
+
across multiple tiles)
1325
+
-->
1326
+
</domain>
1327
+
1328
+
<domain name="CP_MEMCPY" width="32">
1329
+
<reg32 offset="0" name="0">
1330
+
<bitfield name="DWORDS" low="0" high="31" type="uint"/>
1331
+
</reg32>
1332
+
<reg32 offset="1" name="1">
1333
+
<bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1334
+
</reg32>
1335
+
<reg32 offset="2" name="2">
1336
+
<bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1337
+
</reg32>
1338
+
<reg32 offset="3" name="3">
1339
+
<bitfield name="DST_LO" low="0" high="31" type="hex"/>
1340
+
</reg32>
1341
+
<reg32 offset="4" name="4">
1342
+
<bitfield name="DST_HI" low="0" high="31" type="hex"/>
1343
+
</reg32>
1344
+
</domain>
1345
+
1346
+
<domain name="CP_REG_TO_SCRATCH" width="32">
1347
+
<reg32 offset="0" name="0">
1348
+
<bitfield name="REG" low="0" high="17" type="hex"/>
1349
+
<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1350
+
<!-- number of registers/dwords copied is CNT + 1. -->
1351
+
<bitfield name="CNT" low="24" high="26" type="uint"/>
1352
+
</reg32>
1353
+
</domain>
1354
+
1355
+
<domain name="CP_SCRATCH_TO_REG" width="32">
1356
+
<reg32 offset="0" name="0">
1357
+
<bitfield name="REG" low="0" high="17" type="hex"/>
1358
+
<!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1359
+
<bitfield name="UNK18" pos="18" type="boolean"/>
1360
+
<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1361
+
<!-- number of registers/dwords copied is CNT + 1. -->
1362
+
<bitfield name="CNT" low="24" high="26" type="uint"/>
1363
+
</reg32>
1364
+
</domain>
1365
+
1366
+
<domain name="CP_SCRATCH_WRITE" width="32">
1367
+
<reg32 offset="0" name="0">
1368
+
<bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1369
+
</reg32>
1370
+
<!-- followed by one or more DWORDs to write to scratch registers -->
1371
+
</domain>
1372
+
1373
+
<domain name="CP_MEM_WRITE" width="32">
1374
+
<reg32 offset="0" name="0">
1375
+
<bitfield name="ADDR_LO" low="0" high="31"/>
1376
+
</reg32>
1377
+
<reg32 offset="1" name="1">
1378
+
<bitfield name="ADDR_HI" low="0" high="31"/>
1379
+
</reg32>
1380
+
<!-- followed by the DWORDs to write -->
1381
+
</domain>
1382
+
1383
+
<enum name="cp_cond_function">
1384
+
<value value="0" name="WRITE_ALWAYS"/>
1385
+
<value value="1" name="WRITE_LT"/>
1386
+
<value value="2" name="WRITE_LE"/>
1387
+
<value value="3" name="WRITE_EQ"/>
1388
+
<value value="4" name="WRITE_NE"/>
1389
+
<value value="5" name="WRITE_GE"/>
1390
+
<value value="6" name="WRITE_GT"/>
1391
+
</enum>
1392
+
1393
+
<domain name="CP_COND_WRITE" width="32">
1394
+
<reg32 offset="0" name="0">
1395
+
<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1396
+
<bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1397
+
<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1398
+
</reg32>
1399
+
<reg32 offset="1" name="1">
1400
+
<bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1401
+
</reg32>
1402
+
<reg32 offset="2" name="2">
1403
+
<bitfield name="REF" low="0" high="31"/>
1404
+
</reg32>
1405
+
<reg32 offset="3" name="3">
1406
+
<bitfield name="MASK" low="0" high="31"/>
1407
+
</reg32>
1408
+
<reg32 offset="4" name="4">
1409
+
<bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1410
+
</reg32>
1411
+
<reg32 offset="5" name="5">
1412
+
<bitfield name="WRITE_DATA" low="0" high="31"/>
1413
+
</reg32>
1414
+
</domain>
1415
+
1416
+
<enum name="poll_memory_type">
1417
+
<value value="0" name="POLL_REGISTER"/>
1418
+
<value value="1" name="POLL_MEMORY"/>
1419
+
<value value="2" name="POLL_SCRATCH"/>
1420
+
<value value="3" name="POLL_ON_CHIP" varset="chip" variants="A7XX-"/>
1421
+
</enum>
1422
+
1423
+
<domain name="CP_COND_WRITE5" width="32">
1424
+
<reg32 offset="0" name="0">
1425
+
<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1426
+
<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1427
+
<!-- POLL_REGISTER polls a register at POLL_ADDR_LO. -->
1428
+
<bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
1429
+
<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1430
+
</reg32>
1431
+
<reg32 offset="1" name="1">
1432
+
<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1433
+
</reg32>
1434
+
<reg32 offset="2" name="2">
1435
+
<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1436
+
</reg32>
1437
+
<reg32 offset="3" name="3">
1438
+
<bitfield name="REF" low="0" high="31"/>
1439
+
</reg32>
1440
+
<reg32 offset="4" name="4">
1441
+
<bitfield name="MASK" low="0" high="31"/>
1442
+
</reg32>
1443
+
<reg32 offset="5" name="5">
1444
+
<bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1445
+
</reg32>
1446
+
<reg32 offset="6" name="6">
1447
+
<bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1448
+
</reg32>
1449
+
<reg32 offset="7" name="7">
1450
+
<bitfield name="WRITE_DATA" low="0" high="31"/>
1451
+
</reg32>
1452
+
</domain>
1453
+
1454
+
<domain name="CP_WAIT_MEM_GTE" width="32">
1455
+
<doc>
1456
+
Wait until a memory value is greater than or equal to the
1457
+
reference, using signed comparison.
1458
+
</doc>
1459
+
<reg32 offset="0" name="0">
1460
+
<!-- Reserved for flags, presumably? Unused in FW -->
1461
+
<bitfield name="RESERVED" low="0" high="31" type="hex"/>
1462
+
</reg32>
1463
+
<reg32 offset="1" name="1">
1464
+
<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1465
+
</reg32>
1466
+
<reg32 offset="2" name="2">
1467
+
<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1468
+
</reg32>
1469
+
<reg32 offset="3" name="3">
1470
+
<bitfield name="REF" low="0" high="31"/>
1471
+
</reg32>
1472
+
</domain>
1473
+
1474
+
<domain name="CP_WAIT_REG_MEM" width="32">
1475
+
<doc>
1476
+
This uses the same internal comparison as CP_COND_WRITE,
1477
+
but waits until the comparison is true instead. It busy-loops in
1478
+
the CP for the given number of cycles before trying again.
1479
+
</doc>
1480
+
<reg32 offset="0" name="0">
1481
+
<bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1482
+
<bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1483
+
<bitfield name="POLL" low="4" high="5" type="poll_memory_type"/>
1484
+
<bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1485
+
</reg32>
1486
+
<reg32 offset="1" name="1">
1487
+
<bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1488
+
</reg32>
1489
+
<reg32 offset="2" name="2">
1490
+
<bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1491
+
</reg32>
1492
+
<reg32 offset="3" name="3">
1493
+
<bitfield name="REF" low="0" high="31"/>
1494
+
</reg32>
1495
+
<reg32 offset="4" name="4">
1496
+
<bitfield name="MASK" low="0" high="31"/>
1497
+
</reg32>
1498
+
<reg32 offset="5" name="5">
1499
+
<bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1500
+
</reg32>
1501
+
</domain>
1502
+
1503
+
<domain name="CP_WAIT_TWO_REGS" width="32">
1504
+
<doc>
1505
+
Waits for REG0 to not be 0 or REG1 to not equal REF
1506
+
</doc>
1507
+
<reg32 offset="0" name="0">
1508
+
<bitfield name="REG0" low="0" high="17" type="hex"/>
1509
+
</reg32>
1510
+
<reg32 offset="1" name="1">
1511
+
<bitfield name="REG1" low="0" high="17" type="hex"/>
1512
+
</reg32>
1513
+
<reg32 offset="2" name="2">
1514
+
<bitfield name="REF" low="0" high="31" type="uint"/>
1515
+
</reg32>
1516
+
</domain>
1517
+
1518
+
<domain name="CP_DISPATCH_COMPUTE" width="32">
1519
+
<reg32 offset="0" name="0"/>
1520
+
<reg32 offset="1" name="1">
1521
+
<bitfield name="X" low="0" high="31"/>
1522
+
</reg32>
1523
+
<reg32 offset="2" name="2">
1524
+
<bitfield name="Y" low="0" high="31"/>
1525
+
</reg32>
1526
+
<reg32 offset="3" name="3">
1527
+
<bitfield name="Z" low="0" high="31"/>
1528
+
</reg32>
1529
+
</domain>
1530
+
1531
+
<domain name="CP_SET_RENDER_MODE" width="32">
1532
+
<enum name="render_mode_cmd">
1533
+
<value value="1" name="BYPASS"/>
1534
+
<value value="2" name="BINNING"/>
1535
+
<value value="3" name="GMEM"/>
1536
+
<value value="5" name="BLIT2D"/>
1537
+
<!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1538
+
<value value="7" name="BLIT2DSCALE"/>
1539
+
<!-- 8 set before going back to BYPASS exiting 2D -->
1540
+
<value value="8" name="END2D"/>
1541
+
</enum>
1542
+
<reg32 offset="0" name="0">
1543
+
<bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1544
+
<!--
1545
+
normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1546
+
0x21xx range.. possibly (at least some) a5xx variants have a
1547
+
2d core?
1548
+
-->
1549
+
</reg32>
1550
+
<!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1551
+
<reg32 offset="1" name="1">
1552
+
<bitfield name="ADDR_0_LO" low="0" high="31"/>
1553
+
</reg32>
1554
+
<reg32 offset="2" name="2">
1555
+
<bitfield name="ADDR_0_HI" low="0" high="31"/>
1556
+
</reg32>
1557
+
<reg32 offset="3" name="3">
1558
+
<!--
1559
+
set when in GMEM.. maybe indicates GMEM contents need to be
1560
+
preserved on ctx switch?
1561
+
-->
1562
+
<bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1563
+
<bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1564
+
</reg32>
1565
+
<reg32 offset="4" name="4"/>
1566
+
<!-- second buffer looks like some cmdstream.. length in dwords: -->
1567
+
<reg32 offset="5" name="5">
1568
+
<bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1569
+
</reg32>
1570
+
<reg32 offset="6" name="6">
1571
+
<bitfield name="ADDR_1_LO" low="0" high="31"/>
1572
+
</reg32>
1573
+
<reg32 offset="7" name="7">
1574
+
<bitfield name="ADDR_1_HI" low="0" high="31"/>
1575
+
</reg32>
1576
+
</domain>
1577
+
1578
+
<!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1579
+
<domain name="CP_COMPUTE_CHECKPOINT" width="32">
1580
+
<!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1581
+
<reg32 offset="0" name="0">
1582
+
<bitfield name="ADDR_0_LO" low="0" high="31"/>
1583
+
</reg32>
1584
+
<reg32 offset="1" name="1">
1585
+
<bitfield name="ADDR_0_HI" low="0" high="31"/>
1586
+
</reg32>
1587
+
<reg32 offset="2" name="2">
1588
+
</reg32>
1589
+
<reg32 offset="3" name="3"/>
1590
+
<!-- second buffer looks like some cmdstream.. length in dwords: -->
1591
+
<reg32 offset="4" name="4">
1592
+
<bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1593
+
</reg32>
1594
+
<reg32 offset="5" name="5">
1595
+
<bitfield name="ADDR_1_LO" low="0" high="31"/>
1596
+
</reg32>
1597
+
<reg32 offset="6" name="6">
1598
+
<bitfield name="ADDR_1_HI" low="0" high="31"/>
1599
+
</reg32>
1600
+
<reg32 offset="7" name="7"/>
1601
+
</domain>
1602
+
1603
+
<domain name="CP_PERFCOUNTER_ACTION" width="32">
1604
+
<reg32 offset="0" name="0">
1605
+
</reg32>
1606
+
<reg32 offset="1" name="1">
1607
+
<bitfield name="ADDR_0_LO" low="0" high="31"/>
1608
+
</reg32>
1609
+
<reg32 offset="2" name="2">
1610
+
<bitfield name="ADDR_0_HI" low="0" high="31"/>
1611
+
</reg32>
1612
+
</domain>
1613
+
1614
+
<domain varset="chip" name="CP_EVENT_WRITE" width="32">
1615
+
<reg32 offset="0" name="0">
1616
+
<bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1617
+
<!-- when set, write back timestamp instead of value from packet: -->
1618
+
<bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1619
+
<bitfield name="IRQ" pos="31" type="boolean"/>
1620
+
</reg32>
1621
+
<!--
1622
+
TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1623
+
context switch?
1624
+
-->
1625
+
<reg32 offset="1" name="1">
1626
+
<bitfield name="ADDR_0_LO" low="0" high="31"/>
1627
+
</reg32>
1628
+
<reg32 offset="2" name="2">
1629
+
<bitfield name="ADDR_0_HI" low="0" high="31"/>
1630
+
</reg32>
1631
+
<reg32 offset="3" name="3">
1632
+
<!-- ??? -->
1633
+
</reg32>
1634
+
</domain>
1635
+
1636
+
<domain varset="chip" name="CP_EVENT_WRITE7" width="32">
1637
+
<enum name="event_write_src">
1638
+
<!-- Write payload[0] -->
1639
+
<value value="0" name="EV_WRITE_USER_32B"/>
1640
+
<!-- Write payload[0] payload[1] -->
1641
+
<value value="1" name="EV_WRITE_USER_64B"/>
1642
+
<!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
1643
+
<value value="2" name="EV_WRITE_TIMESTAMP_SUM"/>
1644
+
<value value="3" name="EV_WRITE_ALWAYSON"/>
1645
+
<!-- Write payload[1] regs starting at payload[0] offset -->
1646
+
<value value="4" name="EV_WRITE_REGS_CONTENT"/>
1647
+
</enum>
1648
+
1649
+
<enum name="event_write_dst">
1650
+
<value value="0" name="EV_DST_RAM"/>
1651
+
<value value="1" name="EV_DST_ONCHIP"/>
1652
+
</enum>
1653
+
1654
+
<reg32 offset="0" name="0">
1655
+
<bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1656
+
<bitfield name="WRITE_SAMPLE_COUNT" pos="12" type="boolean"/>
1657
+
<!-- Write sample count at (iova + 16) -->
1658
+
<bitfield name="SAMPLE_COUNT_END_OFFSET" pos="13" type="boolean"/>
1659
+
<!-- *(iova + 8) = *(iova + 16) - *iova -->
1660
+
<bitfield name="WRITE_SAMPLE_COUNT_DIFF" pos="14" type="boolean"/>
1661
+
1662
+
<!-- Next 4 flags are valid to set only when concurrent binning is enabled -->
1663
+
<!-- Increment 16b BV counter. Valid only in BV pipe -->
1664
+
<bitfield name="INC_BV_COUNT" pos="16" type="boolean"/>
1665
+
<!-- Increment 16b BR counter. Valid only in BR pipe -->
1666
+
<bitfield name="INC_BR_COUNT" pos="17" type="boolean"/>
1667
+
<bitfield name="CLEAR_RENDER_RESOURCE" pos="18" type="boolean"/>
1668
+
<bitfield name="CLEAR_LRZ_RESOURCE" pos="19" type="boolean"/>
1669
+
1670
+
<bitfield name="WRITE_SRC" low="20" high="22" type="event_write_src"/>
1671
+
<bitfield name="WRITE_DST" pos="24" type="event_write_dst" addvariant="yes"/>
1672
+
<!-- Writes into WRITE_DST from WRITE_SRC. RB_DONE_TS requires WRITE_ENABLED. -->
1673
+
<bitfield name="WRITE_ENABLED" pos="27" type="boolean"/>
1674
+
</reg32>
1675
+
1676
+
<stripe varset="event_write_dst" variants="EV_DST_RAM">
1677
+
<reg32 offset="1" name="1">
1678
+
<bitfield name="ADDR_0_LO" low="0" high="31"/>
1679
+
</reg32>
1680
+
<reg32 offset="2" name="2">
1681
+
<bitfield name="ADDR_0_HI" low="0" high="31"/>
1682
+
</reg32>
1683
+
<reg32 offset="3" name="3">
1684
+
<bitfield name="PAYLOAD_0" low="0" high="31"/>
1685
+
</reg32>
1686
+
<reg32 offset="4" name="4">
1687
+
<bitfield name="PAYLOAD_1" low="0" high="31"/>
1688
+
</reg32>
1689
+
</stripe>
1690
+
1691
+
<stripe varset="event_write_dst" variants="EV_DST_ONCHIP">
1692
+
<reg32 offset="1" name="1">
1693
+
<bitfield name="ONCHIP_ADDR_0" low="0" high="31"/>
1694
+
</reg32>
1695
+
<reg32 offset="3" name="3">
1696
+
<bitfield name="PAYLOAD_0" low="0" high="31"/>
1697
+
</reg32>
1698
+
<reg32 offset="4" name="4">
1699
+
<bitfield name="PAYLOAD_1" low="0" high="31"/>
1700
+
</reg32>
1701
+
</stripe>
1702
+
</domain>
1703
+
1704
+
<domain name="CP_BLIT" width="32">
1705
+
<enum name="cp_blit_cmd">
1706
+
<value value="0" name="BLIT_OP_FILL"/>
1707
+
<value value="1" name="BLIT_OP_COPY"/>
1708
+
<value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1709
+
</enum>
1710
+
<reg32 offset="0" name="0">
1711
+
<bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1712
+
</reg32>
1713
+
<reg32 offset="1" name="1">
1714
+
<bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1715
+
<bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1716
+
</reg32>
1717
+
<reg32 offset="2" name="2">
1718
+
<bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1719
+
<bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1720
+
</reg32>
1721
+
<reg32 offset="3" name="3">
1722
+
<bitfield name="DST_X1" low="0" high="13" type="uint"/>
1723
+
<bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1724
+
</reg32>
1725
+
<reg32 offset="4" name="4">
1726
+
<bitfield name="DST_X2" low="0" high="13" type="uint"/>
1727
+
<bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1728
+
</reg32>
1729
+
</domain>
1730
+
1731
+
<domain name="CP_EXEC_CS" width="32">
1732
+
<reg32 offset="0" name="0">
1733
+
</reg32>
1734
+
<reg32 offset="1" name="1">
1735
+
<bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1736
+
</reg32>
1737
+
<reg32 offset="2" name="2">
1738
+
<bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1739
+
</reg32>
1740
+
<reg32 offset="3" name="3">
1741
+
<bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1742
+
</reg32>
1743
+
</domain>
1744
+
1745
+
<domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1746
+
<reg32 offset="0" name="0">
1747
+
</reg32>
1748
+
<stripe varset="chip" variants="A4XX">
1749
+
<reg32 offset="1" name="1">
1750
+
<bitfield name="ADDR" low="0" high="31"/>
1751
+
</reg32>
1752
+
<reg32 offset="2" name="2">
1753
+
<!-- localsize is value minus one: -->
1754
+
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1755
+
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1756
+
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1757
+
</reg32>
1758
+
</stripe>
1759
+
<stripe varset="chip" variants="A5XX-">
1760
+
<reg32 offset="1" name="1">
1761
+
<bitfield name="ADDR_LO" low="0" high="31"/>
1762
+
</reg32>
1763
+
<reg32 offset="2" name="2">
1764
+
<bitfield name="ADDR_HI" low="0" high="31"/>
1765
+
</reg32>
1766
+
<reg32 offset="3" name="3">
1767
+
<!-- localsize is value minus one: -->
1768
+
<bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1769
+
<bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1770
+
<bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1771
+
</reg32>
1772
+
</stripe>
1773
+
</domain>
1774
+
1775
+
<domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1776
+
<doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1777
+
<enum name="a6xx_marker">
1778
+
<value value="1" name="RM6_BYPASS"/>
1779
+
<value value="2" name="RM6_BINNING"/>
1780
+
<value value="4" name="RM6_GMEM"/>
1781
+
<value value="5" name="RM6_ENDVIS"/>
1782
+
<value value="6" name="RM6_RESOLVE"/>
1783
+
<value value="7" name="RM6_YIELD"/>
1784
+
<value value="8" name="RM6_COMPUTE"/>
1785
+
<value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1786
+
1787
+
<!--
1788
+
These values come from a6xx_set_marker() in the
1789
+
downstream kernel, and they can only be set by the kernel
1790
+
-->
1791
+
<value value="0xd" name="RM6_IB1LIST_START"/>
1792
+
<value value="0xe" name="RM6_IB1LIST_END"/>
1793
+
<!-- IFPC - inter-frame power collapse -->
1794
+
<value value="0x100" name="RM6_IFPC_ENABLE"/>
1795
+
<value value="0x101" name="RM6_IFPC_DISABLE"/>
1796
+
</enum>
1797
+
<reg32 offset="0" name="0">
1798
+
<!--
1799
+
NOTE: blob driver and some versions of freedreno/turnip set
1800
+
b4, which is unused (at least by current sqe fw), but interferes
1801
+
with parsing if we extend the size of the bitfield to include
1802
+
b8 (only sent by kernel mode driver). Really, the way the
1803
+
parsing works in the firmware, only b0-b3 are considered, but
1804
+
if b8 is set, the low bits are interpreted differently. To
1805
+
model this, without getting confused by spurious b4, this is
1806
+
described as two overlapping bitfields:
1807
+
-->
1808
+
<bitfield name="MODE" low="0" high="8" type="a6xx_marker"/>
1809
+
<bitfield name="MARKER" low="0" high="3" type="a6xx_marker"/>
1810
+
</reg32>
1811
+
</domain>
1812
+
1813
+
<domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1814
+
<doc>Set internal CP registers, used to indicate context save data addresses</doc>
1815
+
<enum name="pseudo_reg">
1816
+
<value value="0" name="SMMU_INFO"/>
1817
+
<value value="1" name="NON_SECURE_SAVE_ADDR"/>
1818
+
<value value="2" name="SECURE_SAVE_ADDR"/>
1819
+
<value value="3" name="NON_PRIV_SAVE_ADDR"/>
1820
+
<value value="4" name="COUNTER"/>
1821
+
1822
+
<!--
1823
+
On a6xx the registers are set directly and CP_SET_BIN_DATA5_OFFSET reads them,
1824
+
but that doesn't work with concurrent binning because BR will be reading from
1825
+
a different set of streams than BV is writing, so on a7xx we have these
1826
+
pseudo-regs instead, which do the right thing.
1827
+
1828
+
The corresponding VSC registers exist, and they're written by BV when it
1829
+
encounters CP_SET_PSEUDO_REG. When BR later encounters the same CP_SET_PSEUDO_REG
1830
+
it will only write some private scratch registers which are read by
1831
+
CP_SET_BIN_DATA5_OFFSET.
1832
+
1833
+
If concurrent binning is disabled then BR also does binning so it will also
1834
+
write the "real" registers in BR.
1835
+
-->
1836
+
<value value="8" name="DRAW_STRM_ADDRESS"/>
1837
+
<value value="9" name="DRAW_STRM_SIZE_ADDRESS"/>
1838
+
<value value="10" name="PRIM_STRM_ADDRESS"/>
1839
+
<value value="11" name="UNK_STRM_ADDRESS"/>
1840
+
<value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
1841
+
1842
+
<value value="16" name="BINDLESS_BASE_0_ADDR"/>
1843
+
<value value="17" name="BINDLESS_BASE_1_ADDR"/>
1844
+
<value value="18" name="BINDLESS_BASE_2_ADDR"/>
1845
+
<value value="19" name="BINDLESS_BASE_3_ADDR"/>
1846
+
<value value="20" name="BINDLESS_BASE_4_ADDR"/>
1847
+
<value value="21" name="BINDLESS_BASE_5_ADDR"/>
1848
+
<value value="22" name="BINDLESS_BASE_6_ADDR"/>
1849
+
</enum>
1850
+
<array offset="0" stride="3" length="100">
1851
+
<reg32 offset="0" name="0">
1852
+
<bitfield name="PSEUDO_REG" low="0" high="10" type="pseudo_reg"/>
1853
+
</reg32>
1854
+
<reg32 offset="1" name="1">
1855
+
<bitfield name="LO" low="0" high="31"/>
1856
+
</reg32>
1857
+
<reg32 offset="2" name="2">
1858
+
<bitfield name="HI" low="0" high="31"/>
1859
+
</reg32>
1860
+
</array>
1861
+
</domain>
1862
+
1863
+
<domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1864
+
<doc>
1865
+
Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1866
+
So:
1867
+
1868
+
opcode: CP_REG_TEST (39) (2 dwords)
1869
+
{ REG = 0xc10 | BIT = 0 }
1870
+
0000: 70b90001 00000c10
1871
+
opcode: CP_COND_REG_EXEC (47) (3 dwords)
1872
+
0000: 70c70002 10000000 00000004
1873
+
opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1874
+
1875
+
Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1876
+
offset 0x0c10 is 1
1877
+
</doc>
1878
+
<enum name="source_type">
1879
+
<value value="0" name="SOURCE_REG"/>
1880
+
<!-- Don't confuse with scratch registers, this is a separate memory
1881
+
written into by CP_MEM_TO_SCRATCH_MEM. -->
1882
+
<value value="1" name="SOURCE_SCRATCH_MEM" varset="chip" variants="A7XX-"/>
1883
+
</enum>
1884
+
<reg32 offset="0" name="0">
1885
+
<!-- the register to test -->
1886
+
<bitfield name="REG" low="0" high="17" varset="source_type" variants="SOURCE_REG"/>
1887
+
<bitfield name="SCRATCH_MEM_OFFSET" low="0" high="17" varset="source_type" variants="SOURCE_SCRATCH_MEM"/>
1888
+
<bitfield name="SOURCE" pos="18" type="source_type" addvariant="yes"/>
1889
+
<!-- the bit to test -->
1890
+
<bitfield name="BIT" low="20" high="24" type="uint"/>
1891
+
<!-- skip implied CP_WAIT_FOR_ME -->
1892
+
<bitfield name="SKIP_WAIT_FOR_ME" pos="25" type="boolean"/>
1893
+
<!-- the predicate bit to set (new in gen3+) -->
1894
+
<bitfield name="PRED_BIT" low="26" high="30" type="uint"/>
1895
+
<!-- update the predicate reg directly (new in gen3+) -->
1896
+
<bitfield name="PRED_UPDATE" pos="31" type="boolean"/>
1897
+
</reg32>
1898
+
1899
+
<!--
1900
+
In PRED_UPDATE mode, the predicate reg is updated directly using two
1901
+
more dwords, ignoring other bits:
1902
+
1903
+
PRED_REG = (PRED_REG & ~PRED_MASK) | (PRED_VAL & PRED_MASK);
1904
+
-->
1905
+
<reg32 offset="1" name="PRED_MASK" type="hex"/>
1906
+
<reg32 offset="2" name="PRED_VAL" type="hex"/>
1907
+
</domain>
1908
+
1909
+
<!-- I *think* this existed at least as far back as a4xx -->
1910
+
<domain name="CP_COND_REG_EXEC" width="32">
1911
+
<enum name="compare_mode">
1912
+
<!-- use the predicate bit set by CP_REG_TEST -->
1913
+
<value value="1" name="PRED_TEST"/>
1914
+
<!-- compare two registers directly for equality -->
1915
+
<value value="2" name="REG_COMPARE"/>
1916
+
<!-- test if certain render modes are set via CP_SET_MARKER -->
1917
+
<value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
1918
+
<!-- compare REG0 for equality with immediate -->
1919
+
<value value="4" name="REG_COMPARE_IMM" varset="chip" variants="A7XX-"/>
1920
+
<!-- test which of BR/BV are enabled -->
1921
+
<value value="5" name="THREAD_MODE" varset="chip" variants="A7XX-"/>
1922
+
</enum>
1923
+
<reg32 offset="0" name="0" varset="compare_mode">
1924
+
<bitfield name="REG0" low="0" high="17" variants="REG_COMPARE" type="hex"/>
1925
+
1926
+
<!-- the predicate bit to test (new in gen3+) -->
1927
+
<bitfield name="PRED_BIT" low="18" high="22" variants="PRED_TEST" type="uint"/>
1928
+
<bitfield name="SKIP_WAIT_FOR_ME" pos="23" varset="chip" variants="A7XX-" type="boolean"/>
1929
+
<!-- With REG_COMPARE instead of register read from ONCHIP memory -->
1930
+
<bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
1931
+
1932
+
<!--
1933
+
Note: these bits have the same meaning, and use the same
1934
+
internal mechanism as the bits in CP_SET_DRAW_STATE.
1935
+
When RENDER_MODE is selected, they're used as
1936
+
a bitmask of which modes pass the test.
1937
+
-->
1938
+
1939
+
<!-- RM6_BINNING -->
1940
+
<bitfield name="BINNING" pos="25" variants="RENDER_MODE" type="boolean"/>
1941
+
<!-- all others -->
1942
+
<bitfield name="GMEM" pos="26" variants="RENDER_MODE" type="boolean"/>
1943
+
<!-- RM6_BYPASS -->
1944
+
<bitfield name="SYSMEM" pos="27" variants="RENDER_MODE" type="boolean"/>
1945
+
1946
+
<bitfield name="BV" pos="25" variants="THREAD_MODE" type="boolean"/>
1947
+
<bitfield name="BR" pos="26" variants="THREAD_MODE" type="boolean"/>
1948
+
<bitfield name="LPAC" pos="27" variants="THREAD_MODE" type="boolean"/>
1949
+
1950
+
<bitfield name="MODE" low="28" high="31" type="compare_mode" addvariant="yes"/>
1951
+
</reg32>
1952
+
1953
+
<stripe varset="compare_mode" variants="PRED_TEST">
1954
+
<reg32 offset="1" name="1">
1955
+
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
1956
+
</reg32>
1957
+
</stripe>
1958
+
1959
+
<stripe varset="compare_mode" variants="REG_COMPARE">
1960
+
<reg32 offset="1" name="1">
1961
+
<bitfield name="REG1" low="0" high="17" type="hex"/>
1962
+
<!-- Instead of register read from ONCHIP memory -->
1963
+
<bitfield name="ONCHIP_MEM" pos="24" varset="chip" variants="A7XX-" type="boolean"/>
1964
+
</reg32>
1965
+
</stripe>
1966
+
1967
+
<stripe varset="compare_mode" variants="RENDER_MODE">
1968
+
<reg32 offset="1" name="1">
1969
+
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
1970
+
</reg32>
1971
+
</stripe>
1972
+
1973
+
<stripe varset="compare_mode" variants="REG_COMPARE_IMM">
1974
+
<reg32 offset="1" name="1">
1975
+
<bitfield name="IMM" low="0" high="31"/>
1976
+
</reg32>
1977
+
</stripe>
1978
+
1979
+
<stripe varset="compare_mode" variants="THREAD_MODE">
1980
+
<reg32 offset="1" name="1">
1981
+
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
1982
+
</reg32>
1983
+
</stripe>
1984
+
1985
+
<reg32 offset="2" name="2">
1986
+
<bitfield name="DWORDS" low="0" high="23" type="uint"/>
1987
+
</reg32>
1988
+
</domain>
1989
+
1990
+
<domain name="CP_COND_EXEC" width="32">
1991
+
<doc>
1992
+
Executes the following DWORDs of commands if the dword at ADDR0
1993
+
is not equal to 0 and the dword at ADDR1 is less than REF
1994
+
(signed comparison).
1995
+
</doc>
1996
+
<reg32 offset="0" name="0">
1997
+
<bitfield name="ADDR0_LO" low="0" high="31"/>
1998
+
</reg32>
1999
+
<reg32 offset="1" name="1">
2000
+
<bitfield name="ADDR0_HI" low="0" high="31"/>
2001
+
</reg32>
2002
+
<reg32 offset="2" name="2">
2003
+
<bitfield name="ADDR1_LO" low="0" high="31"/>
2004
+
</reg32>
2005
+
<reg32 offset="3" name="3">
2006
+
<bitfield name="ADDR1_HI" low="0" high="31"/>
2007
+
</reg32>
2008
+
<reg32 offset="4" name="4">
2009
+
<bitfield name="REF" low="0" high="31"/>
2010
+
</reg32>
2011
+
<reg32 offset="5" name="5">
2012
+
<bitfield name="DWORDS" low="0" high="31" type="uint"/>
2013
+
</reg32>
2014
+
</domain>
2015
+
2016
+
<domain name="CP_SET_CTXSWITCH_IB" width="32">
2017
+
<doc>
2018
+
Used by the userspace driver to set various IB's which are
2019
+
executed during context save/restore for handling
2020
+
state that isn't restored by the
2021
+
context switch routine itself.
2022
+
</doc>
2023
+
<enum name="ctxswitch_ib">
2024
+
<value name="RESTORE_IB" value="0">
2025
+
<doc>Executed unconditionally when switching back to the context.</doc>
2026
+
</value>
2027
+
<value name="YIELD_RESTORE_IB" value="1">
2028
+
<doc>
2029
+
Executed when switching back after switching
2030
+
away during execution of
2031
+
a CP_SET_MARKER packet with RM6_YIELD as the
2032
+
payload *and* the normal save routine was
2033
+
bypassed for a shorter one. I think this is
2034
+
connected to the "skipsaverestore" bit set by
2035
+
the kernel when preempting.
2036
+
</doc>
2037
+
</value>
2038
+
<value name="SAVE_IB" value="2">
2039
+
<doc>
2040
+
Executed when switching away from the context,
2041
+
except for context switches initiated via
2042
+
CP_YIELD.
2043
+
</doc>
2044
+
</value>
2045
+
<value name="RB_SAVE_IB" value="3">
2046
+
<doc>
2047
+
This can only be set by the RB (i.e. the kernel)
2048
+
and executes with protected mode off, but
2049
+
is otherwise similar to SAVE_IB.
2050
+
2051
+
Note, kgsl calls this CP_KMD_AMBLE_TYPE
2052
+
</doc>
2053
+
</value>
2054
+
</enum>
2055
+
<reg32 offset="0" name="0">
2056
+
<bitfield name="ADDR_LO" low="0" high="31"/>
2057
+
</reg32>
2058
+
<reg32 offset="1" name="1">
2059
+
<bitfield name="ADDR_HI" low="0" high="31"/>
2060
+
</reg32>
2061
+
<reg32 offset="2" name="2">
2062
+
<bitfield name="DWORDS" low="0" high="19" type="uint"/>
2063
+
<bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
2064
+
</reg32>
2065
+
</domain>
2066
+
2067
+
<domain name="CP_REG_WRITE" width="32">
2068
+
<enum name="reg_tracker">
2069
+
<doc>
2070
+
Keep shadow copies of these registers and only set them
2071
+
when drawing, avoiding redundant writes:
2072
+
- VPC_CNTL_0
2073
+
- HLSQ_CONTROL_1_REG
2074
+
- HLSQ_UNKNOWN_B980
2075
+
</doc>
2076
+
<value name="TRACK_CNTL_REG" value="0x1"/>
2077
+
<doc>
2078
+
Track RB_RENDER_CNTL, and insert a WFI in the following
2079
+
situation:
2080
+
- There is a write that disables binning
2081
+
- There was a draw with binning left enabled, but in
2082
+
BYPASS mode
2083
+
Presumably this is a hang workaround?
2084
+
</doc>
2085
+
<value name="TRACK_RENDER_CNTL" value="0x2"/>
2086
+
<doc>
2087
+
Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
2088
+
the data to write is 0. Used by the Vulkan blob with
2089
+
PC_MULTIVIEW_CNTL, but this isn't predicated on particular
2090
+
register(s) like the others.
2091
+
</doc>
2092
+
<value name="UNK_EVENT_WRITE" value="0x4"/>
2093
+
<doc>
2094
+
Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
2095
+
GRAS_LRZ_DEPTH_VIEW with previous values, and if one of
2096
+
the following is true:
2097
+
- GRAS_LRZ_CNTL::GREATER has changed
2098
+
- GRAS_LRZ_CNTL::DIR has changed, the old value is not
2099
+
CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
2100
+
- GRAS_LRZ_DEPTH_VIEW has changed
2101
+
then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
2102
+
forced to 1.
2103
+
Only exists in a650_sqe.fw.
2104
+
</doc>
2105
+
<value name="TRACK_LRZ" value="0x8"/>
2106
+
</enum>
2107
+
<reg32 offset="0" name="0">
2108
+
<bitfield name="TRACKER" low="0" high="3" type="reg_tracker"/>
2109
+
</reg32>
2110
+
<reg32 offset="1" name="1"/>
2111
+
<reg32 offset="2" name="2"/>
2112
+
</domain>
2113
+
2114
+
<domain name="CP_SMMU_TABLE_UPDATE" width="32">
2115
+
<doc>
2116
+
Note that the SMMU's definition of TTBRn can take different forms
2117
+
depending on the pgtable format. But a5xx+ only uses aarch64
2118
+
format.
2119
+
</doc>
2120
+
<reg32 offset="0" name="0">
2121
+
<bitfield name="TTBR0_LO" low="0" high="31"/>
2122
+
</reg32>
2123
+
<reg32 offset="1" name="1">
2124
+
<bitfield name="TTBR0_HI" low="0" high="15"/>
2125
+
<bitfield name="ASID" low="16" high="31"/>
2126
+
</reg32>
2127
+
<reg32 offset="2" name="2">
2128
+
<doc>Unused, does not apply to aarch64 pgtable format</doc>
2129
+
<bitfield name="CONTEXTIDR" low="0" high="31"/>
2130
+
</reg32>
2131
+
<reg32 offset="3" name="3">
2132
+
<bitfield name="CONTEXTBANK" low="0" high="31"/>
2133
+
</reg32>
2134
+
</domain>
2135
+
2136
+
<domain name="CP_START_BIN" width="32">
2137
+
<reg32 offset="0" name="BIN_COUNT" type="uint"/>
2138
+
<reg64 offset="1" name="PREFIX_ADDR" type="address"/>
2139
+
<reg32 offset="3" name="PREFIX_DWORDS">
2140
+
<doc>
2141
+
Size of prefix for each bin. For each bin index i, the
2142
+
prefix commands at PREFIX_ADDR + i * PREFIX_DWORDS are
2143
+
executed in an IB2 before the IB1 commands following
2144
+
this packet.
2145
+
</doc>
2146
+
</reg32>
2147
+
<reg32 offset="4" name="BODY_DWORDS">
2148
+
<doc>Number of dwords after this packet until CP_END_BIN</doc>
2149
+
</reg32>
2150
+
</domain>
2151
+
2152
+
<domain name="CP_WAIT_TIMESTAMP" width="32">
2153
+
<enum name="ts_wait_value_src">
2154
+
<!-- Wait for value at memory address to be >= SRC_0 (signed comparison) -->
2155
+
<value value="0" name="TS_WAIT_GE_32B"/>
2156
+
<!-- Wait for value at memory address to be >= SRC_0 (unsigned) -->
2157
+
<value value="1" name="TS_WAIT_GE_64B"/>
2158
+
<!-- Write (TIMESTAMP_GLOBAL + TIMESTAMP_LOCAL) -->
2159
+
<value value="2" name="TS_WAIT_GE_TIMESTAMP_SUM"/>
2160
+
</enum>
2161
+
2162
+
<enum name="ts_wait_type">
2163
+
<value value="0" name="TS_WAIT_RAM"/>
2164
+
<value value="1" name="TS_WAIT_ONCHIP"/>
2165
+
</enum>
2166
+
2167
+
<reg32 offset="0" name="0">
2168
+
<bitfield name="WAIT_VALUE_SRC" low="0" high="1" type="ts_wait_value_src"/>
2169
+
<bitfield name="WAIT_DST" pos="4" type="ts_wait_type" addvariant="yes"/>
2170
+
</reg32>
2171
+
2172
+
<stripe varset="ts_wait_type" variants="TS_WAIT_RAM">
2173
+
<reg64 offset="1" name="ADDR" type="address"/>
2174
+
</stripe>
2175
+
2176
+
<stripe varset="ts_wait_type" variants="TS_WAIT_ONCHIP">
2177
+
<reg32 offset="1" name="ONCHIP_ADDR_0" low="0" high="31"/>
2178
+
</stripe>
2179
+
2180
+
<reg32 offset="3" name="SRC_0"/>
2181
+
<reg32 offset="4" name="SRC_1"/>
2182
+
</domain>
2183
+
2184
+
<domain name="CP_BV_BR_COUNT_OPS" width="32">
2185
+
<enum name="pipe_count_op">
2186
+
<value name="PIPE_CLEAR_BV_BR" value="0x1"/>
2187
+
<value name="PIPE_SET_BR_OFFSET" value="0x2"/>
2188
+
<!-- Wait until for BV_counter > BR_counter -->
2189
+
<value name="PIPE_BR_WAIT_FOR_BV" value="0x3"/>
2190
+
<!-- Wait until (BR_counter + BR_OFFSET) > BV_counter -->
2191
+
<value name="PIPE_BV_WAIT_FOR_BR" value="0x4"/>
2192
+
</enum>
2193
+
<reg32 offset="0" name="0">
2194
+
<bitfield name="OP" low="0" high="3" type="pipe_count_op"/>
2195
+
</reg32>
2196
+
<reg32 offset="1" name="1">
2197
+
<bitfield name="BR_OFFSET" low="0" high="15" type="uint"/>
2198
+
</reg32>
2199
+
</domain>
2200
+
2201
+
<domain name="CP_MODIFY_TIMESTAMP" width="32">
2202
+
<enum name="timestamp_op">
2203
+
<value name="MODIFY_TIMESTAMP_CLEAR" value="0"/>
2204
+
<value name="MODIFY_TIMESTAMP_ADD_GLOBAL" value="1"/>
2205
+
<value name="MODIFY_TIMESTAMP_ADD_LOCAL" value="2"/>
2206
+
</enum>
2207
+
<reg32 offset="0" name="0">
2208
+
<bitfield name="ADD" low="0" high="7" type="uint"/>
2209
+
<bitfield name="OP" low="28" high="31" type="timestamp_op"/>
2210
+
</reg32>
2211
+
</domain>
2212
+
2213
+
<domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
2214
+
<doc>
2215
+
Best guess is that it is a faster way to fetch all the VSC_STATE registers
2216
+
and keep them in a local scratch memory instead of fetching every time
2217
+
when skipping IBs.
2218
+
</doc>
2219
+
<reg32 offset="0" name="0">
2220
+
<bitfield name="CNT" low="0" high="5" type="uint"/>
2221
+
</reg32>
2222
+
<reg32 offset="1" name="1">
2223
+
<doc>Scratch memory size is 48 dwords`</doc>
2224
+
<bitfield name="OFFSET" low="0" high="5" type="uint"/>
2225
+
</reg32>
2226
+
<reg32 offset="2" name="2">
2227
+
<bitfield name="SRC" low="0" high="31"/>
2228
+
</reg32>
2229
+
<reg32 offset="3" name="3">
2230
+
<bitfield name="SRC_HI" low="0" high="31"/>
2231
+
</reg32>
2232
+
</domain>
2233
+
2234
+
<domain name="CP_THREAD_CONTROL" width="32">
2235
+
<enum name="cp_thread">
2236
+
<value name="CP_SET_THREAD_BR" value="1"/> <!-- Render -->
2237
+
<value name="CP_SET_THREAD_BV" value="2"/> <!-- Visibility -->
2238
+
<value name="CP_SET_THREAD_BOTH" value="3"/>
2239
+
</enum>
2240
+
<reg32 offset="0" name="0">
2241
+
<bitfield low="0" high="1" name="THREAD" type="cp_thread"/>
2242
+
<bitfield pos="27" name="CONCURRENT_BIN_DISABLE" type="boolean"/>
2243
+
<bitfield pos="31" name="SYNC_THREADS" type="boolean"/>
2244
+
</reg32>
2245
+
</domain>
2246
+
2247
+
<domain name="CP_FIXED_STRIDE_DRAW_TABLE" width="32">
2248
+
<reg64 offset="0" name="IB_BASE"/>
2249
+
<reg32 offset="2" name="2">
2250
+
<!-- STRIDE * COUNT -->
2251
+
<bitfield name="IB_SIZE" low="0" high="11"/>
2252
+
<bitfield name="STRIDE" low="20" high="31"/>
2253
+
</reg32>
2254
+
<reg32 offset="3" name="3">
2255
+
<bitfield name="COUNT" low="0" high="31"/>
2256
+
</reg32>
2257
+
</domain>
2258
+
2259
+
<domain name="CP_RESET_CONTEXT_STATE" width="32">
2260
+
<reg32 offset="0" name="0">
2261
+
<bitfield name="CLEAR_ON_CHIP_TS" pos="0" type="boolean"/>
2262
+
<bitfield name="CLEAR_RESOURCE_TABLE" pos="1" type="boolean"/>
2263
+
<bitfield name="CLEAR_GLOBAL_LOCAL_TS" pos="2" type="boolean"/>
2264
+
</reg32>
2265
+
</domain>
2266
+
2267
+
</database>
2268
+