drm/msm/adreno: Implement gx_is_on() for A8x

+38 -4

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

··· 91 91 } 92 92 93 93 /* Check to see if the GX rail is still powered */ 94 - bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu) 94 + bool a6xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) 95 95 { 96 - struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); 97 - struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; 96 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 97 + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 98 98 u32 val; 99 99 100 100 /* This can be called from gpu state code so make sure GMU is valid */ ··· 115 115 return !(val & 116 116 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 117 117 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 118 + } 119 + 120 + bool a7xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) 121 + { 122 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 123 + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 124 + u32 val; 125 + 126 + /* This can be called from gpu state code so make sure GMU is valid */ 127 + if (!gmu->initialized) 128 + return false; 129 + 130 + val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS); 131 + 132 + return !(val & 133 + (A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 134 + A7XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 135 + } 136 + 137 + bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu) 138 + { 139 + struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); 140 + struct a6xx_gmu *gmu = &a6xx_gpu->gmu; 141 + u32 val; 142 + 143 + /* This can be called from gpu state code so make sure GMU is valid */ 144 + if (!gmu->initialized) 145 + return false; 146 + 147 + val = gmu_read(gmu, REG_A8XX_GMU_PWR_CLK_STATUS); 148 + 149 + return !(val & 150 + (A8XX_GMU_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF | 151 + A8XX_GMU_PWR_CLK_STATUS_GX_HM_CLK_OFF)); 118 152 } 119 153 120 154 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp, ··· 274 240 275 241 if (val == local) { 276 242 if (gmu->idle_level != GMU_IDLE_STATE_IFPC || 277 - !a6xx_gmu_gx_is_on(gmu)) 243 + !adreno_gpu->funcs->gx_is_on(adreno_gpu)) 278 244 return true; 279 245 } 280 246

+4 -1

drivers/gpu/drm/msm/adreno/a6xx_gmu.h

··· 10 10 #include <linux/notifier.h> 11 11 #include <linux/soc/qcom/qcom_aoss.h> 12 12 #include "msm_drv.h" 13 + #include "adreno_gpu.h" 13 14 #include "a6xx_hfi.h" 14 15 15 16 struct a6xx_gmu_bo { ··· 232 231 int a6xx_hfi_send_prep_slumber(struct a6xx_gmu *gmu); 233 232 int a6xx_hfi_set_freq(struct a6xx_gmu *gmu, u32 perf_index, u32 bw_index); 234 233 235 - bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu); 234 + bool a6xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu); 235 + bool a7xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu); 236 + bool a8xx_gmu_gx_is_on(struct adreno_gpu *adreno_gpu); 236 237 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu); 237 238 void a6xx_sptprac_disable(struct a6xx_gmu *gmu); 238 239 int a6xx_sptprac_enable(struct a6xx_gmu *gmu);

+5 -1

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

··· 1643 1643 1644 1644 adreno_dump_info(gpu); 1645 1645 1646 - if (a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) { 1646 + if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) { 1647 1647 /* Sometimes crashstate capture is skipped, so SQE should be halted here again */ 1648 1648 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3); 1649 1649 ··· 2763 2763 .get_timestamp = a6xx_gmu_get_timestamp, 2764 2764 .bus_halt = a6xx_bus_clear_pending_transactions, 2765 2765 .mmu_fault_handler = a6xx_fault_handler, 2766 + .gx_is_on = a6xx_gmu_gx_is_on, 2766 2767 }; 2767 2768 2768 2769 const struct adreno_gpu_funcs a6xx_gmuwrapper_funcs = { ··· 2796 2795 .get_timestamp = a6xx_get_timestamp, 2797 2796 .bus_halt = a6xx_bus_clear_pending_transactions, 2798 2797 .mmu_fault_handler = a6xx_fault_handler, 2798 + .gx_is_on = a6xx_gmu_gx_is_on, 2799 2799 }; 2800 2800 2801 2801 const struct adreno_gpu_funcs a7xx_gpu_funcs = { ··· 2831 2829 .get_timestamp = a6xx_gmu_get_timestamp, 2832 2830 .bus_halt = a6xx_bus_clear_pending_transactions, 2833 2831 .mmu_fault_handler = a6xx_fault_handler, 2832 + .gx_is_on = a7xx_gmu_gx_is_on, 2834 2833 }; 2835 2834 2836 2835 const struct adreno_gpu_funcs a8xx_gpu_funcs = { ··· 2859 2856 .get_timestamp = a8xx_gmu_get_timestamp, 2860 2857 .bus_halt = a8xx_bus_clear_pending_transactions, 2861 2858 .mmu_fault_handler = a8xx_fault_handler, 2859 + .gx_is_on = a8xx_gmu_gx_is_on, 2862 2860 };

+2 -2

drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c

··· 1251 1251 _a6xx_get_gmu_registers(gpu, a6xx_state, &a6xx_gpucc_reg, 1252 1252 &a6xx_state->gmu_registers[2], false); 1253 1253 1254 - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) 1254 + if (!adreno_gpu->funcs->gx_is_on(adreno_gpu)) 1255 1255 return; 1256 1256 1257 1257 /* Set the fence to ALLOW mode so we can access the registers */ ··· 1608 1608 } 1609 1609 1610 1610 /* If GX isn't on the rest of the data isn't going to be accessible */ 1611 - if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) 1611 + if (!adreno_gpu->funcs->gx_is_on(adreno_gpu)) 1612 1612 return &a6xx_state->base; 1613 1613 1614 1614 /* Halt SQE first */

+1

drivers/gpu/drm/msm/adreno/adreno_gpu.h

··· 78 78 u64 (*get_timestamp)(struct msm_gpu *gpu); 79 79 void (*bus_halt)(struct adreno_gpu *adreno_gpu, bool gx_off); 80 80 int (*mmu_fault_handler)(void *arg, unsigned long iova, int flags, void *data); 81 + bool (*gx_is_on)(struct adreno_gpu *adreno_gpu); 81 82 }; 82 83 83 84 struct adreno_reglist {

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