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drm/msm/a6xx: Correct OOB usage

During the GMU resume sequence, using another OOB other than OOB_GPU may
confuse the internal state of GMU firmware. To align more strictly with
the downstream sequence, move the sysprof related OOB setup after the
OOB_GPU is cleared.

Fixes: 62cd0fa6990b ("drm/msm/adreno: Disable IFPC when sysprof is active")
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/714659/
Message-ID: <20260327-a8xx-gpu-batch2-v2-4-2b53c38d2101@oss.qualcomm.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>

authored by

Akhil P Oommen and committed by
Rob Clark d34b6919 0c59f258

+12 -5
-5
drivers/gpu/drm/msm/adreno/a6xx_gmu.c
··· 1236 1236 /* Set the GPU to the current freq */ 1237 1237 a6xx_gmu_set_initial_freq(gpu, gmu); 1238 1238 1239 - if (refcount_read(&gpu->sysprof_active) > 1) { 1240 - ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1241 - if (!ret) 1242 - set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); 1243 - } 1244 1239 out: 1245 1240 /* On failure, shut down the GMU to leave it in a good state */ 1246 1241 if (ret) {
+6
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 1605 1605 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER); 1606 1606 } 1607 1607 1608 + if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { 1609 + ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 1610 + if (!ret) 1611 + set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); 1612 + } 1613 + 1608 1614 return ret; 1609 1615 } 1610 1616
+6
drivers/gpu/drm/msm/adreno/a8xx_gpu.c
··· 721 721 */ 722 722 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); 723 723 724 + if (!ret && (refcount_read(&gpu->sysprof_active) > 1)) { 725 + ret = a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET); 726 + if (!ret) 727 + set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status); 728 + } 729 + 724 730 return ret; 725 731 } 726 732