Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'mediatek-drm-next-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux into drm-next
Mediatek DRM Next for Linux 6.14
1. dp: Add sdp path reset
2. dp: Support flexible length of DP calibration data
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20250104125538.111118-1-chunkuang.hu@kernel.org
+29
-5
+28
-5
drivers/gpu/drm/mediatek/mtk_dp.c
+28
-5
drivers/gpu/drm/mediatek/mtk_dp.c
···
1135
1135
0, DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);
1136
1136
}
1137
1137
1138
+
static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp)
1139
+
{
1140
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
1141
+
SDP_RESET_SW_DP_ENC0_P0,
1142
+
SDP_RESET_SW_DP_ENC0_P0);
1143
+
1144
+
/* Wait for sdp path reset to complete */
1145
+
usleep_range(1000, 5000);
1146
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
1147
+
0, SDP_RESET_SW_DP_ENC0_P0);
1148
+
}
1149
+
1138
1150
static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)
1139
1151
{
1140
1152
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,
···
1177
1165
buf = (u32 *)nvmem_cell_read(cell, &len);
1178
1166
nvmem_cell_put(cell);
1179
1167
1180
-
if (IS_ERR(buf) || ((len / sizeof(u32)) != 4)) {
1168
+
if (IS_ERR(buf)) {
1181
1169
dev_warn(dev, "Failed to read nvmem_cell_read\n");
1182
-
1183
-
if (!IS_ERR(buf))
1184
-
kfree(buf);
1185
-
1186
1170
goto use_default_val;
1187
1171
}
1188
1172
1173
+
/* The cell length is in bytes. Convert it to be compatible with u32 buffer. */
1174
+
len /= sizeof(u32);
1175
+
1189
1176
for (i = 0; i < MTK_DP_CAL_MAX; i++) {
1190
1177
fmt = &mtk_dp->data->efuse_fmt[i];
1178
+
1179
+
if (fmt->idx >= len) {
1180
+
dev_warn(mtk_dp->dev,
1181
+
"Out-of-bound efuse data access, fmt idx = %d, buf len = %zu\n",
1182
+
fmt->idx, len);
1183
+
kfree(buf);
1184
+
goto use_default_val;
1185
+
}
1186
+
1191
1187
cal_data[i] = (buf[fmt->idx] >> fmt->shift) & fmt->mask;
1192
1188
1193
1189
if (cal_data[i] < fmt->min_val || cal_data[i] > fmt->max_val) {
···
2416
2396
mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
2417
2397
DP_PWR_STATE_BANDGAP_TPLL,
2418
2398
DP_PWR_STATE_MASK);
2399
+
2400
+
/* SDP path reset sw*/
2401
+
mtk_dp_sdp_path_reset(mtk_dp);
2419
2402
2420
2403
/* Ensure the sink is muted */
2421
2404
msleep(20);
+1
drivers/gpu/drm/mediatek/mtk_dp_reg.h
+1
drivers/gpu/drm/mediatek/mtk_dp_reg.h
···
86
86
#define MTK_DP_ENC0_P0_3004 0x3004
87
87
#define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8)
88
88
#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0 BIT(9)
89
+
#define SDP_RESET_SW_DP_ENC0_P0 BIT(13)
89
90
#define MTK_DP_ENC0_P0_3010 0x3010
90
91
#define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
91
92
#define MTK_DP_ENC0_P0_3014 0x3014