drm/msm: drop A2xx and common headers · tjh.dev/kernel@aed6c8d

-3251

drivers/gpu/drm/msm/adreno/a2xx.xml.h

··· 1 - #ifndef A2XX_XML 2 - #define A2XX_XML 3 - 4 - /* Autogenerated file, DO NOT EDIT manually! 5 - 6 - This file was generated by the rules-ng-ng gen_header.py tool in this git repository: 7 - http://gitlab.freedesktop.org/mesa/mesa/ 8 - git clone https://gitlab.freedesktop.org/mesa/mesa.git 9 - 10 - The rules-ng-ng source files this header was generated from are: 11 - 12 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from Fri Jun 2 14:59:26 2023) 13 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) 14 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) 15 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) 16 - 17 - Copyright (C) 2013-2024 by the following authors: 18 - - Rob Clark <robdclark@gmail.com> Rob Clark 19 - - Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin 20 - 21 - Permission is hereby granted, free of charge, to any person obtaining 22 - a copy of this software and associated documentation files (the 23 - "Software"), to deal in the Software without restriction, including 24 - without limitation the rights to use, copy, modify, merge, publish, 25 - distribute, sublicense, and/or sell copies of the Software, and to 26 - permit persons to whom the Software is furnished to do so, subject to 27 - the following conditions: 28 - 29 - The above copyright notice and this permission notice (including the 30 - next paragraph) shall be included in all copies or substantial 31 - portions of the Software. 32 - 33 - THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 - EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 35 - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 36 - IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 37 - LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 38 - OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 39 - WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 40 - 41 - */ 42 - 43 - #ifdef __KERNEL__ 44 - #include <linux/bug.h> 45 - #define assert(x) BUG_ON(!(x)) 46 - #else 47 - #include <assert.h> 48 - #endif 49 - 50 - #ifdef __cplusplus 51 - #define __struct_cast(X) 52 - #else 53 - #define __struct_cast(X) (struct X) 54 - #endif 55 - 56 - enum a2xx_rb_dither_type { 57 - DITHER_PIXEL = 0, 58 - DITHER_SUBPIXEL = 1, 59 - }; 60 - 61 - enum a2xx_colorformatx { 62 - COLORX_4_4_4_4 = 0, 63 - COLORX_1_5_5_5 = 1, 64 - COLORX_5_6_5 = 2, 65 - COLORX_8 = 3, 66 - COLORX_8_8 = 4, 67 - COLORX_8_8_8_8 = 5, 68 - COLORX_S8_8_8_8 = 6, 69 - COLORX_16_FLOAT = 7, 70 - COLORX_16_16_FLOAT = 8, 71 - COLORX_16_16_16_16_FLOAT = 9, 72 - COLORX_32_FLOAT = 10, 73 - COLORX_32_32_FLOAT = 11, 74 - COLORX_32_32_32_32_FLOAT = 12, 75 - COLORX_2_3_3 = 13, 76 - COLORX_8_8_8 = 14, 77 - }; 78 - 79 - enum a2xx_sq_surfaceformat { 80 - FMT_1_REVERSE = 0, 81 - FMT_1 = 1, 82 - FMT_8 = 2, 83 - FMT_1_5_5_5 = 3, 84 - FMT_5_6_5 = 4, 85 - FMT_6_5_5 = 5, 86 - FMT_8_8_8_8 = 6, 87 - FMT_2_10_10_10 = 7, 88 - FMT_8_A = 8, 89 - FMT_8_B = 9, 90 - FMT_8_8 = 10, 91 - FMT_Cr_Y1_Cb_Y0 = 11, 92 - FMT_Y1_Cr_Y0_Cb = 12, 93 - FMT_5_5_5_1 = 13, 94 - FMT_8_8_8_8_A = 14, 95 - FMT_4_4_4_4 = 15, 96 - FMT_8_8_8 = 16, 97 - FMT_DXT1 = 18, 98 - FMT_DXT2_3 = 19, 99 - FMT_DXT4_5 = 20, 100 - FMT_10_10_10_2 = 21, 101 - FMT_24_8 = 22, 102 - FMT_16 = 24, 103 - FMT_16_16 = 25, 104 - FMT_16_16_16_16 = 26, 105 - FMT_16_EXPAND = 27, 106 - FMT_16_16_EXPAND = 28, 107 - FMT_16_16_16_16_EXPAND = 29, 108 - FMT_16_FLOAT = 30, 109 - FMT_16_16_FLOAT = 31, 110 - FMT_16_16_16_16_FLOAT = 32, 111 - FMT_32 = 33, 112 - FMT_32_32 = 34, 113 - FMT_32_32_32_32 = 35, 114 - FMT_32_FLOAT = 36, 115 - FMT_32_32_FLOAT = 37, 116 - FMT_32_32_32_32_FLOAT = 38, 117 - FMT_ATI_TC_RGB = 39, 118 - FMT_ATI_TC_RGBA = 40, 119 - FMT_ATI_TC_555_565_RGB = 41, 120 - FMT_ATI_TC_555_565_RGBA = 42, 121 - FMT_ATI_TC_RGBA_INTERP = 43, 122 - FMT_ATI_TC_555_565_RGBA_INTERP = 44, 123 - FMT_ETC1_RGBA_INTERP = 46, 124 - FMT_ETC1_RGB = 47, 125 - FMT_ETC1_RGBA = 48, 126 - FMT_DXN = 49, 127 - FMT_2_3_3 = 51, 128 - FMT_2_10_10_10_AS_16_16_16_16 = 54, 129 - FMT_10_10_10_2_AS_16_16_16_16 = 55, 130 - FMT_32_32_32_FLOAT = 57, 131 - FMT_DXT3A = 58, 132 - FMT_DXT5A = 59, 133 - FMT_CTX1 = 60, 134 - }; 135 - 136 - enum a2xx_sq_ps_vtx_mode { 137 - POSITION_1_VECTOR = 0, 138 - POSITION_2_VECTORS_UNUSED = 1, 139 - POSITION_2_VECTORS_SPRITE = 2, 140 - POSITION_2_VECTORS_EDGE = 3, 141 - POSITION_2_VECTORS_KILL = 4, 142 - POSITION_2_VECTORS_SPRITE_KILL = 5, 143 - POSITION_2_VECTORS_EDGE_KILL = 6, 144 - MULTIPASS = 7, 145 - }; 146 - 147 - enum a2xx_sq_sample_cntl { 148 - CENTROIDS_ONLY = 0, 149 - CENTERS_ONLY = 1, 150 - CENTROIDS_AND_CENTERS = 2, 151 - }; 152 - 153 - enum a2xx_dx_clip_space { 154 - DXCLIP_OPENGL = 0, 155 - DXCLIP_DIRECTX = 1, 156 - }; 157 - 158 - enum a2xx_pa_su_sc_polymode { 159 - POLY_DISABLED = 0, 160 - POLY_DUALMODE = 1, 161 - }; 162 - 163 - enum a2xx_rb_edram_mode { 164 - EDRAM_NOP = 0, 165 - COLOR_DEPTH = 4, 166 - DEPTH_ONLY = 5, 167 - EDRAM_COPY = 6, 168 - }; 169 - 170 - enum a2xx_pa_sc_pattern_bit_order { 171 - LITTLE = 0, 172 - BIG = 1, 173 - }; 174 - 175 - enum a2xx_pa_sc_auto_reset_cntl { 176 - NEVER = 0, 177 - EACH_PRIMITIVE = 1, 178 - EACH_PACKET = 2, 179 - }; 180 - 181 - enum a2xx_pa_pixcenter { 182 - PIXCENTER_D3D = 0, 183 - PIXCENTER_OGL = 1, 184 - }; 185 - 186 - enum a2xx_pa_roundmode { 187 - TRUNCATE = 0, 188 - ROUND = 1, 189 - ROUNDTOEVEN = 2, 190 - ROUNDTOODD = 3, 191 - }; 192 - 193 - enum a2xx_pa_quantmode { 194 - ONE_SIXTEENTH = 0, 195 - ONE_EIGTH = 1, 196 - ONE_QUARTER = 2, 197 - ONE_HALF = 3, 198 - ONE = 4, 199 - }; 200 - 201 - enum a2xx_rb_copy_sample_select { 202 - SAMPLE_0 = 0, 203 - SAMPLE_1 = 1, 204 - SAMPLE_2 = 2, 205 - SAMPLE_3 = 3, 206 - SAMPLE_01 = 4, 207 - SAMPLE_23 = 5, 208 - SAMPLE_0123 = 6, 209 - }; 210 - 211 - enum a2xx_rb_blend_opcode { 212 - BLEND2_DST_PLUS_SRC = 0, 213 - BLEND2_SRC_MINUS_DST = 1, 214 - BLEND2_MIN_DST_SRC = 2, 215 - BLEND2_MAX_DST_SRC = 3, 216 - BLEND2_DST_MINUS_SRC = 4, 217 - BLEND2_DST_PLUS_SRC_BIAS = 5, 218 - }; 219 - 220 - enum a2xx_su_perfcnt_select { 221 - PERF_PAPC_PASX_REQ = 0, 222 - PERF_PAPC_PASX_FIRST_VECTOR = 2, 223 - PERF_PAPC_PASX_SECOND_VECTOR = 3, 224 - PERF_PAPC_PASX_FIRST_DEAD = 4, 225 - PERF_PAPC_PASX_SECOND_DEAD = 5, 226 - PERF_PAPC_PASX_VTX_KILL_DISCARD = 6, 227 - PERF_PAPC_PASX_VTX_NAN_DISCARD = 7, 228 - PERF_PAPC_PA_INPUT_PRIM = 8, 229 - PERF_PAPC_PA_INPUT_NULL_PRIM = 9, 230 - PERF_PAPC_PA_INPUT_EVENT_FLAG = 10, 231 - PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11, 232 - PERF_PAPC_PA_INPUT_END_OF_PACKET = 12, 233 - PERF_PAPC_CLPR_CULL_PRIM = 13, 234 - PERF_PAPC_CLPR_VV_CULL_PRIM = 15, 235 - PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17, 236 - PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18, 237 - PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19, 238 - PERF_PAPC_CLPR_VV_CLIP_PRIM = 21, 239 - PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23, 240 - PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24, 241 - PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25, 242 - PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26, 243 - PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27, 244 - PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28, 245 - PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29, 246 - PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30, 247 - PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31, 248 - PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32, 249 - PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33, 250 - PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34, 251 - PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35, 252 - PERF_PAPC_CLSM_NULL_PRIM = 36, 253 - PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37, 254 - PERF_PAPC_CLSM_CLIP_PRIM = 38, 255 - PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39, 256 - PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40, 257 - PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41, 258 - PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42, 259 - PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43, 260 - PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44, 261 - PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45, 262 - PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46, 263 - PERF_PAPC_SU_INPUT_PRIM = 47, 264 - PERF_PAPC_SU_INPUT_CLIP_PRIM = 48, 265 - PERF_PAPC_SU_INPUT_NULL_PRIM = 49, 266 - PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50, 267 - PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51, 268 - PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52, 269 - PERF_PAPC_SU_POLYMODE_FACE_CULL = 53, 270 - PERF_PAPC_SU_POLYMODE_BACK_CULL = 54, 271 - PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55, 272 - PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56, 273 - PERF_PAPC_SU_OUTPUT_PRIM = 57, 274 - PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58, 275 - PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59, 276 - PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60, 277 - PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61, 278 - PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62, 279 - PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63, 280 - PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64, 281 - PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65, 282 - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66, 283 - PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67, 284 - PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68, 285 - PERF_PAPC_PASX_REQ_IDLE = 69, 286 - PERF_PAPC_PASX_REQ_BUSY = 70, 287 - PERF_PAPC_PASX_REQ_STALLED = 71, 288 - PERF_PAPC_PASX_REC_IDLE = 72, 289 - PERF_PAPC_PASX_REC_BUSY = 73, 290 - PERF_PAPC_PASX_REC_STARVED_SX = 74, 291 - PERF_PAPC_PASX_REC_STALLED = 75, 292 - PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76, 293 - PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77, 294 - PERF_PAPC_CCGSM_IDLE = 78, 295 - PERF_PAPC_CCGSM_BUSY = 79, 296 - PERF_PAPC_CCGSM_STALLED = 80, 297 - PERF_PAPC_CLPRIM_IDLE = 81, 298 - PERF_PAPC_CLPRIM_BUSY = 82, 299 - PERF_PAPC_CLPRIM_STALLED = 83, 300 - PERF_PAPC_CLPRIM_STARVED_CCGSM = 84, 301 - PERF_PAPC_CLIPSM_IDLE = 85, 302 - PERF_PAPC_CLIPSM_BUSY = 86, 303 - PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87, 304 - PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88, 305 - PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89, 306 - PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90, 307 - PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91, 308 - PERF_PAPC_CLIPGA_IDLE = 92, 309 - PERF_PAPC_CLIPGA_BUSY = 93, 310 - PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94, 311 - PERF_PAPC_CLIPGA_STALLED = 95, 312 - PERF_PAPC_CLIP_IDLE = 96, 313 - PERF_PAPC_CLIP_BUSY = 97, 314 - PERF_PAPC_SU_IDLE = 98, 315 - PERF_PAPC_SU_BUSY = 99, 316 - PERF_PAPC_SU_STARVED_CLIP = 100, 317 - PERF_PAPC_SU_STALLED_SC = 101, 318 - PERF_PAPC_SU_FACENESS_CULL = 102, 319 - }; 320 - 321 - enum a2xx_sc_perfcnt_select { 322 - SC_SR_WINDOW_VALID = 0, 323 - SC_CW_WINDOW_VALID = 1, 324 - SC_QM_WINDOW_VALID = 2, 325 - SC_FW_WINDOW_VALID = 3, 326 - SC_EZ_WINDOW_VALID = 4, 327 - SC_IT_WINDOW_VALID = 5, 328 - SC_STARVED_BY_PA = 6, 329 - SC_STALLED_BY_RB_TILE = 7, 330 - SC_STALLED_BY_RB_SAMP = 8, 331 - SC_STARVED_BY_RB_EZ = 9, 332 - SC_STALLED_BY_SAMPLE_FF = 10, 333 - SC_STALLED_BY_SQ = 11, 334 - SC_STALLED_BY_SP = 12, 335 - SC_TOTAL_NO_PRIMS = 13, 336 - SC_NON_EMPTY_PRIMS = 14, 337 - SC_NO_TILES_PASSING_QM = 15, 338 - SC_NO_PIXELS_PRE_EZ = 16, 339 - SC_NO_PIXELS_POST_EZ = 17, 340 - }; 341 - 342 - enum a2xx_vgt_perfcount_select { 343 - VGT_SQ_EVENT_WINDOW_ACTIVE = 0, 344 - VGT_SQ_SEND = 1, 345 - VGT_SQ_STALLED = 2, 346 - VGT_SQ_STARVED_BUSY = 3, 347 - VGT_SQ_STARVED_IDLE = 4, 348 - VGT_SQ_STATIC = 5, 349 - VGT_PA_EVENT_WINDOW_ACTIVE = 6, 350 - VGT_PA_CLIP_V_SEND = 7, 351 - VGT_PA_CLIP_V_STALLED = 8, 352 - VGT_PA_CLIP_V_STARVED_BUSY = 9, 353 - VGT_PA_CLIP_V_STARVED_IDLE = 10, 354 - VGT_PA_CLIP_V_STATIC = 11, 355 - VGT_PA_CLIP_P_SEND = 12, 356 - VGT_PA_CLIP_P_STALLED = 13, 357 - VGT_PA_CLIP_P_STARVED_BUSY = 14, 358 - VGT_PA_CLIP_P_STARVED_IDLE = 15, 359 - VGT_PA_CLIP_P_STATIC = 16, 360 - VGT_PA_CLIP_S_SEND = 17, 361 - VGT_PA_CLIP_S_STALLED = 18, 362 - VGT_PA_CLIP_S_STARVED_BUSY = 19, 363 - VGT_PA_CLIP_S_STARVED_IDLE = 20, 364 - VGT_PA_CLIP_S_STATIC = 21, 365 - RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22, 366 - RBIU_IMMED_DATA_FIFO_STARVED = 23, 367 - RBIU_IMMED_DATA_FIFO_STALLED = 24, 368 - RBIU_DMA_REQUEST_FIFO_STARVED = 25, 369 - RBIU_DMA_REQUEST_FIFO_STALLED = 26, 370 - RBIU_DRAW_INITIATOR_FIFO_STARVED = 27, 371 - RBIU_DRAW_INITIATOR_FIFO_STALLED = 28, 372 - BIN_PRIM_NEAR_CULL = 29, 373 - BIN_PRIM_ZERO_CULL = 30, 374 - BIN_PRIM_FAR_CULL = 31, 375 - BIN_PRIM_BIN_CULL = 32, 376 - BIN_PRIM_FACE_CULL = 33, 377 - SPARE34 = 34, 378 - SPARE35 = 35, 379 - SPARE36 = 36, 380 - SPARE37 = 37, 381 - SPARE38 = 38, 382 - SPARE39 = 39, 383 - TE_SU_IN_VALID = 40, 384 - TE_SU_IN_READ = 41, 385 - TE_SU_IN_PRIM = 42, 386 - TE_SU_IN_EOP = 43, 387 - TE_SU_IN_NULL_PRIM = 44, 388 - TE_WK_IN_VALID = 45, 389 - TE_WK_IN_READ = 46, 390 - TE_OUT_PRIM_VALID = 47, 391 - TE_OUT_PRIM_READ = 48, 392 - }; 393 - 394 - enum a2xx_tcr_perfcount_select { 395 - DGMMPD_IPMUX0_STALL = 0, 396 - DGMMPD_IPMUX_ALL_STALL = 4, 397 - OPMUX0_L2_WRITES = 5, 398 - }; 399 - 400 - enum a2xx_tp_perfcount_select { 401 - POINT_QUADS = 0, 402 - BILIN_QUADS = 1, 403 - ANISO_QUADS = 2, 404 - MIP_QUADS = 3, 405 - VOL_QUADS = 4, 406 - MIP_VOL_QUADS = 5, 407 - MIP_ANISO_QUADS = 6, 408 - VOL_ANISO_QUADS = 7, 409 - ANISO_2_1_QUADS = 8, 410 - ANISO_4_1_QUADS = 9, 411 - ANISO_6_1_QUADS = 10, 412 - ANISO_8_1_QUADS = 11, 413 - ANISO_10_1_QUADS = 12, 414 - ANISO_12_1_QUADS = 13, 415 - ANISO_14_1_QUADS = 14, 416 - ANISO_16_1_QUADS = 15, 417 - MIP_VOL_ANISO_QUADS = 16, 418 - ALIGN_2_QUADS = 17, 419 - ALIGN_4_QUADS = 18, 420 - PIX_0_QUAD = 19, 421 - PIX_1_QUAD = 20, 422 - PIX_2_QUAD = 21, 423 - PIX_3_QUAD = 22, 424 - PIX_4_QUAD = 23, 425 - TP_MIPMAP_LOD0 = 24, 426 - TP_MIPMAP_LOD1 = 25, 427 - TP_MIPMAP_LOD2 = 26, 428 - TP_MIPMAP_LOD3 = 27, 429 - TP_MIPMAP_LOD4 = 28, 430 - TP_MIPMAP_LOD5 = 29, 431 - TP_MIPMAP_LOD6 = 30, 432 - TP_MIPMAP_LOD7 = 31, 433 - TP_MIPMAP_LOD8 = 32, 434 - TP_MIPMAP_LOD9 = 33, 435 - TP_MIPMAP_LOD10 = 34, 436 - TP_MIPMAP_LOD11 = 35, 437 - TP_MIPMAP_LOD12 = 36, 438 - TP_MIPMAP_LOD13 = 37, 439 - TP_MIPMAP_LOD14 = 38, 440 - }; 441 - 442 - enum a2xx_tcm_perfcount_select { 443 - QUAD0_RD_LAT_FIFO_EMPTY = 0, 444 - QUAD0_RD_LAT_FIFO_4TH_FULL = 3, 445 - QUAD0_RD_LAT_FIFO_HALF_FULL = 4, 446 - QUAD0_RD_LAT_FIFO_FULL = 5, 447 - QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6, 448 - READ_STARVED_QUAD0 = 28, 449 - READ_STARVED = 32, 450 - READ_STALLED_QUAD0 = 33, 451 - READ_STALLED = 37, 452 - VALID_READ_QUAD0 = 38, 453 - TC_TP_STARVED_QUAD0 = 42, 454 - TC_TP_STARVED = 46, 455 - }; 456 - 457 - enum a2xx_tcf_perfcount_select { 458 - VALID_CYCLES = 0, 459 - SINGLE_PHASES = 1, 460 - ANISO_PHASES = 2, 461 - MIP_PHASES = 3, 462 - VOL_PHASES = 4, 463 - MIP_VOL_PHASES = 5, 464 - MIP_ANISO_PHASES = 6, 465 - VOL_ANISO_PHASES = 7, 466 - ANISO_2_1_PHASES = 8, 467 - ANISO_4_1_PHASES = 9, 468 - ANISO_6_1_PHASES = 10, 469 - ANISO_8_1_PHASES = 11, 470 - ANISO_10_1_PHASES = 12, 471 - ANISO_12_1_PHASES = 13, 472 - ANISO_14_1_PHASES = 14, 473 - ANISO_16_1_PHASES = 15, 474 - MIP_VOL_ANISO_PHASES = 16, 475 - ALIGN_2_PHASES = 17, 476 - ALIGN_4_PHASES = 18, 477 - TPC_BUSY = 19, 478 - TPC_STALLED = 20, 479 - TPC_STARVED = 21, 480 - TPC_WORKING = 22, 481 - TPC_WALKER_BUSY = 23, 482 - TPC_WALKER_STALLED = 24, 483 - TPC_WALKER_WORKING = 25, 484 - TPC_ALIGNER_BUSY = 26, 485 - TPC_ALIGNER_STALLED = 27, 486 - TPC_ALIGNER_STALLED_BY_BLEND = 28, 487 - TPC_ALIGNER_STALLED_BY_CACHE = 29, 488 - TPC_ALIGNER_WORKING = 30, 489 - TPC_BLEND_BUSY = 31, 490 - TPC_BLEND_SYNC = 32, 491 - TPC_BLEND_STARVED = 33, 492 - TPC_BLEND_WORKING = 34, 493 - OPCODE_0x00 = 35, 494 - OPCODE_0x01 = 36, 495 - OPCODE_0x04 = 37, 496 - OPCODE_0x10 = 38, 497 - OPCODE_0x11 = 39, 498 - OPCODE_0x12 = 40, 499 - OPCODE_0x13 = 41, 500 - OPCODE_0x18 = 42, 501 - OPCODE_0x19 = 43, 502 - OPCODE_0x1A = 44, 503 - OPCODE_OTHER = 45, 504 - IN_FIFO_0_EMPTY = 56, 505 - IN_FIFO_0_LT_HALF_FULL = 57, 506 - IN_FIFO_0_HALF_FULL = 58, 507 - IN_FIFO_0_FULL = 59, 508 - IN_FIFO_TPC_EMPTY = 72, 509 - IN_FIFO_TPC_LT_HALF_FULL = 73, 510 - IN_FIFO_TPC_HALF_FULL = 74, 511 - IN_FIFO_TPC_FULL = 75, 512 - TPC_TC_XFC = 76, 513 - TPC_TC_STATE = 77, 514 - TC_STALL = 78, 515 - QUAD0_TAPS = 79, 516 - QUADS = 83, 517 - TCA_SYNC_STALL = 84, 518 - TAG_STALL = 85, 519 - TCB_SYNC_STALL = 88, 520 - TCA_VALID = 89, 521 - PROBES_VALID = 90, 522 - MISS_STALL = 91, 523 - FETCH_FIFO_STALL = 92, 524 - TCO_STALL = 93, 525 - ANY_STALL = 94, 526 - TAG_MISSES = 95, 527 - TAG_HITS = 96, 528 - SUB_TAG_MISSES = 97, 529 - SET0_INVALIDATES = 98, 530 - SET1_INVALIDATES = 99, 531 - SET2_INVALIDATES = 100, 532 - SET3_INVALIDATES = 101, 533 - SET0_TAG_MISSES = 102, 534 - SET1_TAG_MISSES = 103, 535 - SET2_TAG_MISSES = 104, 536 - SET3_TAG_MISSES = 105, 537 - SET0_TAG_HITS = 106, 538 - SET1_TAG_HITS = 107, 539 - SET2_TAG_HITS = 108, 540 - SET3_TAG_HITS = 109, 541 - SET0_SUB_TAG_MISSES = 110, 542 - SET1_SUB_TAG_MISSES = 111, 543 - SET2_SUB_TAG_MISSES = 112, 544 - SET3_SUB_TAG_MISSES = 113, 545 - SET0_EVICT1 = 114, 546 - SET0_EVICT2 = 115, 547 - SET0_EVICT3 = 116, 548 - SET0_EVICT4 = 117, 549 - SET0_EVICT5 = 118, 550 - SET0_EVICT6 = 119, 551 - SET0_EVICT7 = 120, 552 - SET0_EVICT8 = 121, 553 - SET1_EVICT1 = 130, 554 - SET1_EVICT2 = 131, 555 - SET1_EVICT3 = 132, 556 - SET1_EVICT4 = 133, 557 - SET1_EVICT5 = 134, 558 - SET1_EVICT6 = 135, 559 - SET1_EVICT7 = 136, 560 - SET1_EVICT8 = 137, 561 - SET2_EVICT1 = 146, 562 - SET2_EVICT2 = 147, 563 - SET2_EVICT3 = 148, 564 - SET2_EVICT4 = 149, 565 - SET2_EVICT5 = 150, 566 - SET2_EVICT6 = 151, 567 - SET2_EVICT7 = 152, 568 - SET2_EVICT8 = 153, 569 - SET3_EVICT1 = 162, 570 - SET3_EVICT2 = 163, 571 - SET3_EVICT3 = 164, 572 - SET3_EVICT4 = 165, 573 - SET3_EVICT5 = 166, 574 - SET3_EVICT6 = 167, 575 - SET3_EVICT7 = 168, 576 - SET3_EVICT8 = 169, 577 - FF_EMPTY = 178, 578 - FF_LT_HALF_FULL = 179, 579 - FF_HALF_FULL = 180, 580 - FF_FULL = 181, 581 - FF_XFC = 182, 582 - FF_STALLED = 183, 583 - FG_MASKS = 184, 584 - FG_LEFT_MASKS = 185, 585 - FG_LEFT_MASK_STALLED = 186, 586 - FG_LEFT_NOT_DONE_STALL = 187, 587 - FG_LEFT_FG_STALL = 188, 588 - FG_LEFT_SECTORS = 189, 589 - FG0_REQUESTS = 195, 590 - FG0_STALLED = 196, 591 - MEM_REQ512 = 199, 592 - MEM_REQ_SENT = 200, 593 - MEM_LOCAL_READ_REQ = 202, 594 - TC0_MH_STALLED = 203, 595 - }; 596 - 597 - enum a2xx_sq_perfcnt_select { 598 - SQ_PIXEL_VECTORS_SUB = 0, 599 - SQ_VERTEX_VECTORS_SUB = 1, 600 - SQ_ALU0_ACTIVE_VTX_SIMD0 = 2, 601 - SQ_ALU1_ACTIVE_VTX_SIMD0 = 3, 602 - SQ_ALU0_ACTIVE_PIX_SIMD0 = 4, 603 - SQ_ALU1_ACTIVE_PIX_SIMD0 = 5, 604 - SQ_ALU0_ACTIVE_VTX_SIMD1 = 6, 605 - SQ_ALU1_ACTIVE_VTX_SIMD1 = 7, 606 - SQ_ALU0_ACTIVE_PIX_SIMD1 = 8, 607 - SQ_ALU1_ACTIVE_PIX_SIMD1 = 9, 608 - SQ_EXPORT_CYCLES = 10, 609 - SQ_ALU_CST_WRITTEN = 11, 610 - SQ_TEX_CST_WRITTEN = 12, 611 - SQ_ALU_CST_STALL = 13, 612 - SQ_ALU_TEX_STALL = 14, 613 - SQ_INST_WRITTEN = 15, 614 - SQ_BOOLEAN_WRITTEN = 16, 615 - SQ_LOOPS_WRITTEN = 17, 616 - SQ_PIXEL_SWAP_IN = 18, 617 - SQ_PIXEL_SWAP_OUT = 19, 618 - SQ_VERTEX_SWAP_IN = 20, 619 - SQ_VERTEX_SWAP_OUT = 21, 620 - SQ_ALU_VTX_INST_ISSUED = 22, 621 - SQ_TEX_VTX_INST_ISSUED = 23, 622 - SQ_VC_VTX_INST_ISSUED = 24, 623 - SQ_CF_VTX_INST_ISSUED = 25, 624 - SQ_ALU_PIX_INST_ISSUED = 26, 625 - SQ_TEX_PIX_INST_ISSUED = 27, 626 - SQ_VC_PIX_INST_ISSUED = 28, 627 - SQ_CF_PIX_INST_ISSUED = 29, 628 - SQ_ALU0_FIFO_EMPTY_SIMD0 = 30, 629 - SQ_ALU1_FIFO_EMPTY_SIMD0 = 31, 630 - SQ_ALU0_FIFO_EMPTY_SIMD1 = 32, 631 - SQ_ALU1_FIFO_EMPTY_SIMD1 = 33, 632 - SQ_ALU_NOPS = 34, 633 - SQ_PRED_SKIP = 35, 634 - SQ_SYNC_ALU_STALL_SIMD0_VTX = 36, 635 - SQ_SYNC_ALU_STALL_SIMD1_VTX = 37, 636 - SQ_SYNC_TEX_STALL_VTX = 38, 637 - SQ_SYNC_VC_STALL_VTX = 39, 638 - SQ_CONSTANTS_USED_SIMD0 = 40, 639 - SQ_CONSTANTS_SENT_SP_SIMD0 = 41, 640 - SQ_GPR_STALL_VTX = 42, 641 - SQ_GPR_STALL_PIX = 43, 642 - SQ_VTX_RS_STALL = 44, 643 - SQ_PIX_RS_STALL = 45, 644 - SQ_SX_PC_FULL = 46, 645 - SQ_SX_EXP_BUFF_FULL = 47, 646 - SQ_SX_POS_BUFF_FULL = 48, 647 - SQ_INTERP_QUADS = 49, 648 - SQ_INTERP_ACTIVE = 50, 649 - SQ_IN_PIXEL_STALL = 51, 650 - SQ_IN_VTX_STALL = 52, 651 - SQ_VTX_CNT = 53, 652 - SQ_VTX_VECTOR2 = 54, 653 - SQ_VTX_VECTOR3 = 55, 654 - SQ_VTX_VECTOR4 = 56, 655 - SQ_PIXEL_VECTOR1 = 57, 656 - SQ_PIXEL_VECTOR23 = 58, 657 - SQ_PIXEL_VECTOR4 = 59, 658 - SQ_CONSTANTS_USED_SIMD1 = 60, 659 - SQ_CONSTANTS_SENT_SP_SIMD1 = 61, 660 - SQ_SX_MEM_EXP_FULL = 62, 661 - SQ_ALU0_ACTIVE_VTX_SIMD2 = 63, 662 - SQ_ALU1_ACTIVE_VTX_SIMD2 = 64, 663 - SQ_ALU0_ACTIVE_PIX_SIMD2 = 65, 664 - SQ_ALU1_ACTIVE_PIX_SIMD2 = 66, 665 - SQ_ALU0_ACTIVE_VTX_SIMD3 = 67, 666 - SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68, 667 - SQ_ALU0_ACTIVE_PIX_SIMD3 = 69, 668 - SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70, 669 - SQ_ALU0_FIFO_EMPTY_SIMD2 = 71, 670 - SQ_ALU1_FIFO_EMPTY_SIMD2 = 72, 671 - SQ_ALU0_FIFO_EMPTY_SIMD3 = 73, 672 - SQ_ALU1_FIFO_EMPTY_SIMD3 = 74, 673 - SQ_SYNC_ALU_STALL_SIMD2_VTX = 75, 674 - SQ_PERFCOUNT_VTX_POP_THREAD = 76, 675 - SQ_SYNC_ALU_STALL_SIMD0_PIX = 77, 676 - SQ_SYNC_ALU_STALL_SIMD1_PIX = 78, 677 - SQ_SYNC_ALU_STALL_SIMD2_PIX = 79, 678 - SQ_PERFCOUNT_PIX_POP_THREAD = 80, 679 - SQ_SYNC_TEX_STALL_PIX = 81, 680 - SQ_SYNC_VC_STALL_PIX = 82, 681 - SQ_CONSTANTS_USED_SIMD2 = 83, 682 - SQ_CONSTANTS_SENT_SP_SIMD2 = 84, 683 - SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85, 684 - SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86, 685 - SQ_ALU0_FIFO_FULL_SIMD0 = 87, 686 - SQ_ALU1_FIFO_FULL_SIMD0 = 88, 687 - SQ_ALU0_FIFO_FULL_SIMD1 = 89, 688 - SQ_ALU1_FIFO_FULL_SIMD1 = 90, 689 - SQ_ALU0_FIFO_FULL_SIMD2 = 91, 690 - SQ_ALU1_FIFO_FULL_SIMD2 = 92, 691 - SQ_ALU0_FIFO_FULL_SIMD3 = 93, 692 - SQ_ALU1_FIFO_FULL_SIMD3 = 94, 693 - VC_PERF_STATIC = 95, 694 - VC_PERF_STALLED = 96, 695 - VC_PERF_STARVED = 97, 696 - VC_PERF_SEND = 98, 697 - VC_PERF_ACTUAL_STARVED = 99, 698 - PIXEL_THREAD_0_ACTIVE = 100, 699 - VERTEX_THREAD_0_ACTIVE = 101, 700 - PIXEL_THREAD_0_NUMBER = 102, 701 - VERTEX_THREAD_0_NUMBER = 103, 702 - VERTEX_EVENT_NUMBER = 104, 703 - PIXEL_EVENT_NUMBER = 105, 704 - PTRBUFF_EF_PUSH = 106, 705 - PTRBUFF_EF_POP_EVENT = 107, 706 - PTRBUFF_EF_POP_NEW_VTX = 108, 707 - PTRBUFF_EF_POP_DEALLOC = 109, 708 - PTRBUFF_EF_POP_PVECTOR = 110, 709 - PTRBUFF_EF_POP_PVECTOR_X = 111, 710 - PTRBUFF_EF_POP_PVECTOR_VNZ = 112, 711 - PTRBUFF_PB_DEALLOC = 113, 712 - PTRBUFF_PI_STATE_PPB_POP = 114, 713 - PTRBUFF_PI_RTR = 115, 714 - PTRBUFF_PI_READ_EN = 116, 715 - PTRBUFF_PI_BUFF_SWAP = 117, 716 - PTRBUFF_SQ_FREE_BUFF = 118, 717 - PTRBUFF_SQ_DEC = 119, 718 - PTRBUFF_SC_VALID_CNTL_EVENT = 120, 719 - PTRBUFF_SC_VALID_IJ_XFER = 121, 720 - PTRBUFF_SC_NEW_VECTOR_1_Q = 122, 721 - PTRBUFF_QUAL_NEW_VECTOR = 123, 722 - PTRBUFF_QUAL_EVENT = 124, 723 - PTRBUFF_END_BUFFER = 125, 724 - PTRBUFF_FILL_QUAD = 126, 725 - VERTS_WRITTEN_SPI = 127, 726 - TP_FETCH_INSTR_EXEC = 128, 727 - TP_FETCH_INSTR_REQ = 129, 728 - TP_DATA_RETURN = 130, 729 - SPI_WRITE_CYCLES_SP = 131, 730 - SPI_WRITES_SP = 132, 731 - SP_ALU_INSTR_EXEC = 133, 732 - SP_CONST_ADDR_TO_SQ = 134, 733 - SP_PRED_KILLS_TO_SQ = 135, 734 - SP_EXPORT_CYCLES_TO_SX = 136, 735 - SP_EXPORTS_TO_SX = 137, 736 - SQ_CYCLES_ELAPSED = 138, 737 - SQ_TCFS_OPT_ALLOC_EXEC = 139, 738 - SQ_TCFS_NO_OPT_ALLOC = 140, 739 - SQ_ALU0_NO_OPT_ALLOC = 141, 740 - SQ_ALU1_NO_OPT_ALLOC = 142, 741 - SQ_TCFS_ARB_XFC_CNT = 143, 742 - SQ_ALU0_ARB_XFC_CNT = 144, 743 - SQ_ALU1_ARB_XFC_CNT = 145, 744 - SQ_TCFS_CFS_UPDATE_CNT = 146, 745 - SQ_ALU0_CFS_UPDATE_CNT = 147, 746 - SQ_ALU1_CFS_UPDATE_CNT = 148, 747 - SQ_VTX_PUSH_THREAD_CNT = 149, 748 - SQ_VTX_POP_THREAD_CNT = 150, 749 - SQ_PIX_PUSH_THREAD_CNT = 151, 750 - SQ_PIX_POP_THREAD_CNT = 152, 751 - SQ_PIX_TOTAL = 153, 752 - SQ_PIX_KILLED = 154, 753 - }; 754 - 755 - enum a2xx_sx_perfcnt_select { 756 - SX_EXPORT_VECTORS = 0, 757 - SX_DUMMY_QUADS = 1, 758 - SX_ALPHA_FAIL = 2, 759 - SX_RB_QUAD_BUSY = 3, 760 - SX_RB_COLOR_BUSY = 4, 761 - SX_RB_QUAD_STALL = 5, 762 - SX_RB_COLOR_STALL = 6, 763 - }; 764 - 765 - enum a2xx_rbbm_perfcount1_sel { 766 - RBBM1_COUNT = 0, 767 - RBBM1_NRT_BUSY = 1, 768 - RBBM1_RB_BUSY = 2, 769 - RBBM1_SQ_CNTX0_BUSY = 3, 770 - RBBM1_SQ_CNTX17_BUSY = 4, 771 - RBBM1_VGT_BUSY = 5, 772 - RBBM1_VGT_NODMA_BUSY = 6, 773 - RBBM1_PA_BUSY = 7, 774 - RBBM1_SC_CNTX_BUSY = 8, 775 - RBBM1_TPC_BUSY = 9, 776 - RBBM1_TC_BUSY = 10, 777 - RBBM1_SX_BUSY = 11, 778 - RBBM1_CP_COHER_BUSY = 12, 779 - RBBM1_CP_NRT_BUSY = 13, 780 - RBBM1_GFX_IDLE_STALL = 14, 781 - RBBM1_INTERRUPT = 15, 782 - }; 783 - 784 - enum a2xx_cp_perfcount_sel { 785 - ALWAYS_COUNT = 0, 786 - TRANS_FIFO_FULL = 1, 787 - TRANS_FIFO_AF = 2, 788 - RCIU_PFPTRANS_WAIT = 3, 789 - RCIU_NRTTRANS_WAIT = 6, 790 - CSF_NRT_READ_WAIT = 8, 791 - CSF_I1_FIFO_FULL = 9, 792 - CSF_I2_FIFO_FULL = 10, 793 - CSF_ST_FIFO_FULL = 11, 794 - CSF_RING_ROQ_FULL = 13, 795 - CSF_I1_ROQ_FULL = 14, 796 - CSF_I2_ROQ_FULL = 15, 797 - CSF_ST_ROQ_FULL = 16, 798 - MIU_TAG_MEM_FULL = 18, 799 - MIU_WRITECLEAN = 19, 800 - MIU_NRT_WRITE_STALLED = 22, 801 - MIU_NRT_READ_STALLED = 23, 802 - ME_WRITE_CONFIRM_FIFO_FULL = 24, 803 - ME_VS_DEALLOC_FIFO_FULL = 25, 804 - ME_PS_DEALLOC_FIFO_FULL = 26, 805 - ME_REGS_VS_EVENT_FIFO_FULL = 27, 806 - ME_REGS_PS_EVENT_FIFO_FULL = 28, 807 - ME_REGS_CF_EVENT_FIFO_FULL = 29, 808 - ME_MICRO_RB_STARVED = 30, 809 - ME_MICRO_I1_STARVED = 31, 810 - ME_MICRO_I2_STARVED = 32, 811 - ME_MICRO_ST_STARVED = 33, 812 - RCIU_RBBM_DWORD_SENT = 40, 813 - ME_BUSY_CLOCKS = 41, 814 - ME_WAIT_CONTEXT_AVAIL = 42, 815 - PFP_TYPE0_PACKET = 43, 816 - PFP_TYPE3_PACKET = 44, 817 - CSF_RB_WPTR_NEQ_RPTR = 45, 818 - CSF_I1_SIZE_NEQ_ZERO = 46, 819 - CSF_I2_SIZE_NEQ_ZERO = 47, 820 - CSF_RBI1I2_FETCHING = 48, 821 - }; 822 - 823 - enum a2xx_rb_perfcnt_select { 824 - RBPERF_CNTX_BUSY = 0, 825 - RBPERF_CNTX_BUSY_MAX = 1, 826 - RBPERF_SX_QUAD_STARVED = 2, 827 - RBPERF_SX_QUAD_STARVED_MAX = 3, 828 - RBPERF_GA_GC_CH0_SYS_REQ = 4, 829 - RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5, 830 - RBPERF_GA_GC_CH1_SYS_REQ = 6, 831 - RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7, 832 - RBPERF_MH_STARVED = 8, 833 - RBPERF_MH_STARVED_MAX = 9, 834 - RBPERF_AZ_BC_COLOR_BUSY = 10, 835 - RBPERF_AZ_BC_COLOR_BUSY_MAX = 11, 836 - RBPERF_AZ_BC_Z_BUSY = 12, 837 - RBPERF_AZ_BC_Z_BUSY_MAX = 13, 838 - RBPERF_RB_SC_TILE_RTR_N = 14, 839 - RBPERF_RB_SC_TILE_RTR_N_MAX = 15, 840 - RBPERF_RB_SC_SAMP_RTR_N = 16, 841 - RBPERF_RB_SC_SAMP_RTR_N_MAX = 17, 842 - RBPERF_RB_SX_QUAD_RTR_N = 18, 843 - RBPERF_RB_SX_QUAD_RTR_N_MAX = 19, 844 - RBPERF_RB_SX_COLOR_RTR_N = 20, 845 - RBPERF_RB_SX_COLOR_RTR_N_MAX = 21, 846 - RBPERF_RB_SC_SAMP_LZ_BUSY = 22, 847 - RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23, 848 - RBPERF_ZXP_STALL = 24, 849 - RBPERF_ZXP_STALL_MAX = 25, 850 - RBPERF_EVENT_PENDING = 26, 851 - RBPERF_EVENT_PENDING_MAX = 27, 852 - RBPERF_RB_MH_VALID = 28, 853 - RBPERF_RB_MH_VALID_MAX = 29, 854 - RBPERF_SX_RB_QUAD_SEND = 30, 855 - RBPERF_SX_RB_COLOR_SEND = 31, 856 - RBPERF_SC_RB_TILE_SEND = 32, 857 - RBPERF_SC_RB_SAMPLE_SEND = 33, 858 - RBPERF_SX_RB_MEM_EXPORT = 34, 859 - RBPERF_SX_RB_QUAD_EVENT = 35, 860 - RBPERF_SC_RB_TILE_EVENT_FILTERED = 36, 861 - RBPERF_SC_RB_TILE_EVENT_ALL = 37, 862 - RBPERF_RB_SC_EZ_SEND = 38, 863 - RBPERF_RB_SX_INDEX_SEND = 39, 864 - RBPERF_GMEM_INTFO_RD = 40, 865 - RBPERF_GMEM_INTF1_RD = 41, 866 - RBPERF_GMEM_INTFO_WR = 42, 867 - RBPERF_GMEM_INTF1_WR = 43, 868 - RBPERF_RB_CP_CONTEXT_DONE = 44, 869 - RBPERF_RB_CP_CACHE_FLUSH = 45, 870 - RBPERF_ZPASS_DONE = 46, 871 - RBPERF_ZCMD_VALID = 47, 872 - RBPERF_CCMD_VALID = 48, 873 - RBPERF_ACCUM_GRANT = 49, 874 - RBPERF_ACCUM_C0_GRANT = 50, 875 - RBPERF_ACCUM_C1_GRANT = 51, 876 - RBPERF_ACCUM_FULL_BE_WR = 52, 877 - RBPERF_ACCUM_REQUEST_NO_GRANT = 53, 878 - RBPERF_ACCUM_TIMEOUT_PULSE = 54, 879 - RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55, 880 - RBPERF_ACCUM_CAM_HIT_FLUSHING = 56, 881 - }; 882 - 883 - enum a2xx_mh_perfcnt_select { 884 - CP_R0_REQUESTS = 0, 885 - CP_R1_REQUESTS = 1, 886 - CP_R2_REQUESTS = 2, 887 - CP_R3_REQUESTS = 3, 888 - CP_R4_REQUESTS = 4, 889 - CP_TOTAL_READ_REQUESTS = 5, 890 - CP_TOTAL_WRITE_REQUESTS = 6, 891 - CP_TOTAL_REQUESTS = 7, 892 - CP_DATA_BYTES_WRITTEN = 8, 893 - CP_WRITE_CLEAN_RESPONSES = 9, 894 - CP_R0_READ_BURSTS_RECEIVED = 10, 895 - CP_R1_READ_BURSTS_RECEIVED = 11, 896 - CP_R2_READ_BURSTS_RECEIVED = 12, 897 - CP_R3_READ_BURSTS_RECEIVED = 13, 898 - CP_R4_READ_BURSTS_RECEIVED = 14, 899 - CP_TOTAL_READ_BURSTS_RECEIVED = 15, 900 - CP_R0_DATA_BEATS_READ = 16, 901 - CP_R1_DATA_BEATS_READ = 17, 902 - CP_R2_DATA_BEATS_READ = 18, 903 - CP_R3_DATA_BEATS_READ = 19, 904 - CP_R4_DATA_BEATS_READ = 20, 905 - CP_TOTAL_DATA_BEATS_READ = 21, 906 - VGT_R0_REQUESTS = 22, 907 - VGT_R1_REQUESTS = 23, 908 - VGT_TOTAL_REQUESTS = 24, 909 - VGT_R0_READ_BURSTS_RECEIVED = 25, 910 - VGT_R1_READ_BURSTS_RECEIVED = 26, 911 - VGT_TOTAL_READ_BURSTS_RECEIVED = 27, 912 - VGT_R0_DATA_BEATS_READ = 28, 913 - VGT_R1_DATA_BEATS_READ = 29, 914 - VGT_TOTAL_DATA_BEATS_READ = 30, 915 - TC_TOTAL_REQUESTS = 31, 916 - TC_ROQ_REQUESTS = 32, 917 - TC_INFO_SENT = 33, 918 - TC_READ_BURSTS_RECEIVED = 34, 919 - TC_DATA_BEATS_READ = 35, 920 - TCD_BURSTS_READ = 36, 921 - RB_REQUESTS = 37, 922 - RB_DATA_BYTES_WRITTEN = 38, 923 - RB_WRITE_CLEAN_RESPONSES = 39, 924 - AXI_READ_REQUESTS_ID_0 = 40, 925 - AXI_READ_REQUESTS_ID_1 = 41, 926 - AXI_READ_REQUESTS_ID_2 = 42, 927 - AXI_READ_REQUESTS_ID_3 = 43, 928 - AXI_READ_REQUESTS_ID_4 = 44, 929 - AXI_READ_REQUESTS_ID_5 = 45, 930 - AXI_READ_REQUESTS_ID_6 = 46, 931 - AXI_READ_REQUESTS_ID_7 = 47, 932 - AXI_TOTAL_READ_REQUESTS = 48, 933 - AXI_WRITE_REQUESTS_ID_0 = 49, 934 - AXI_WRITE_REQUESTS_ID_1 = 50, 935 - AXI_WRITE_REQUESTS_ID_2 = 51, 936 - AXI_WRITE_REQUESTS_ID_3 = 52, 937 - AXI_WRITE_REQUESTS_ID_4 = 53, 938 - AXI_WRITE_REQUESTS_ID_5 = 54, 939 - AXI_WRITE_REQUESTS_ID_6 = 55, 940 - AXI_WRITE_REQUESTS_ID_7 = 56, 941 - AXI_TOTAL_WRITE_REQUESTS = 57, 942 - AXI_TOTAL_REQUESTS_ID_0 = 58, 943 - AXI_TOTAL_REQUESTS_ID_1 = 59, 944 - AXI_TOTAL_REQUESTS_ID_2 = 60, 945 - AXI_TOTAL_REQUESTS_ID_3 = 61, 946 - AXI_TOTAL_REQUESTS_ID_4 = 62, 947 - AXI_TOTAL_REQUESTS_ID_5 = 63, 948 - AXI_TOTAL_REQUESTS_ID_6 = 64, 949 - AXI_TOTAL_REQUESTS_ID_7 = 65, 950 - AXI_TOTAL_REQUESTS = 66, 951 - AXI_READ_CHANNEL_BURSTS_ID_0 = 67, 952 - AXI_READ_CHANNEL_BURSTS_ID_1 = 68, 953 - AXI_READ_CHANNEL_BURSTS_ID_2 = 69, 954 - AXI_READ_CHANNEL_BURSTS_ID_3 = 70, 955 - AXI_READ_CHANNEL_BURSTS_ID_4 = 71, 956 - AXI_READ_CHANNEL_BURSTS_ID_5 = 72, 957 - AXI_READ_CHANNEL_BURSTS_ID_6 = 73, 958 - AXI_READ_CHANNEL_BURSTS_ID_7 = 74, 959 - AXI_READ_CHANNEL_TOTAL_BURSTS = 75, 960 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76, 961 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77, 962 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78, 963 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79, 964 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80, 965 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81, 966 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82, 967 - AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83, 968 - AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84, 969 - AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85, 970 - AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86, 971 - AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87, 972 - AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88, 973 - AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89, 974 - AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90, 975 - AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91, 976 - AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92, 977 - AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93, 978 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94, 979 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95, 980 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96, 981 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97, 982 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98, 983 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99, 984 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100, 985 - AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101, 986 - AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102, 987 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103, 988 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104, 989 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105, 990 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106, 991 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107, 992 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108, 993 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109, 994 - AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110, 995 - AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111, 996 - TOTAL_MMU_MISSES = 112, 997 - MMU_READ_MISSES = 113, 998 - MMU_WRITE_MISSES = 114, 999 - TOTAL_MMU_HITS = 115, 1000 - MMU_READ_HITS = 116, 1001 - MMU_WRITE_HITS = 117, 1002 - SPLIT_MODE_TC_HITS = 118, 1003 - SPLIT_MODE_TC_MISSES = 119, 1004 - SPLIT_MODE_NON_TC_HITS = 120, 1005 - SPLIT_MODE_NON_TC_MISSES = 121, 1006 - STALL_AWAITING_TLB_MISS_FETCH = 122, 1007 - MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123, 1008 - MMU_TLB_MISS_DATA_BEATS_READ = 124, 1009 - CP_CYCLES_HELD_OFF = 125, 1010 - VGT_CYCLES_HELD_OFF = 126, 1011 - TC_CYCLES_HELD_OFF = 127, 1012 - TC_ROQ_CYCLES_HELD_OFF = 128, 1013 - TC_CYCLES_HELD_OFF_TCD_FULL = 129, 1014 - RB_CYCLES_HELD_OFF = 130, 1015 - TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131, 1016 - TLB_MISS_CYCLES_HELD_OFF = 132, 1017 - AXI_READ_REQUEST_HELD_OFF = 133, 1018 - AXI_WRITE_REQUEST_HELD_OFF = 134, 1019 - AXI_REQUEST_HELD_OFF = 135, 1020 - AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136, 1021 - AXI_WRITE_DATA_HELD_OFF = 137, 1022 - CP_SAME_PAGE_BANK_REQUESTS = 138, 1023 - VGT_SAME_PAGE_BANK_REQUESTS = 139, 1024 - TC_SAME_PAGE_BANK_REQUESTS = 140, 1025 - TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141, 1026 - RB_SAME_PAGE_BANK_REQUESTS = 142, 1027 - TOTAL_SAME_PAGE_BANK_REQUESTS = 143, 1028 - CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144, 1029 - VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145, 1030 - TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146, 1031 - RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147, 1032 - TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148, 1033 - TOTAL_MH_READ_REQUESTS = 149, 1034 - TOTAL_MH_WRITE_REQUESTS = 150, 1035 - TOTAL_MH_REQUESTS = 151, 1036 - MH_BUSY = 152, 1037 - CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153, 1038 - VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154, 1039 - TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155, 1040 - RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156, 1041 - TC_ROQ_N_VALID_ENTRIES = 157, 1042 - ARQ_N_ENTRIES = 158, 1043 - WDB_N_ENTRIES = 159, 1044 - MH_READ_LATENCY_OUTST_REQ_SUM = 160, 1045 - MC_READ_LATENCY_OUTST_REQ_SUM = 161, 1046 - MC_TOTAL_READ_REQUESTS = 162, 1047 - ELAPSED_CYCLES_MH_GATED_CLK = 163, 1048 - ELAPSED_CLK_CYCLES = 164, 1049 - CP_W_16B_REQUESTS = 165, 1050 - CP_W_32B_REQUESTS = 166, 1051 - TC_16B_REQUESTS = 167, 1052 - TC_32B_REQUESTS = 168, 1053 - PA_REQUESTS = 169, 1054 - PA_DATA_BYTES_WRITTEN = 170, 1055 - PA_WRITE_CLEAN_RESPONSES = 171, 1056 - PA_CYCLES_HELD_OFF = 172, 1057 - AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173, 1058 - AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174, 1059 - AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175, 1060 - AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176, 1061 - AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177, 1062 - AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178, 1063 - AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179, 1064 - AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180, 1065 - AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181, 1066 - }; 1067 - 1068 - enum perf_mode_cnt { 1069 - PERF_STATE_RESET = 0, 1070 - PERF_STATE_ENABLE = 1, 1071 - PERF_STATE_FREEZE = 2, 1072 - }; 1073 - 1074 - enum adreno_mmu_clnt_beh { 1075 - BEH_NEVR = 0, 1076 - BEH_TRAN_RNG = 1, 1077 - BEH_TRAN_FLT = 2, 1078 - }; 1079 - 1080 - enum sq_tex_clamp { 1081 - SQ_TEX_WRAP = 0, 1082 - SQ_TEX_MIRROR = 1, 1083 - SQ_TEX_CLAMP_LAST_TEXEL = 2, 1084 - SQ_TEX_MIRROR_ONCE_LAST_TEXEL = 3, 1085 - SQ_TEX_CLAMP_HALF_BORDER = 4, 1086 - SQ_TEX_MIRROR_ONCE_HALF_BORDER = 5, 1087 - SQ_TEX_CLAMP_BORDER = 6, 1088 - SQ_TEX_MIRROR_ONCE_BORDER = 7, 1089 - }; 1090 - 1091 - enum sq_tex_swiz { 1092 - SQ_TEX_X = 0, 1093 - SQ_TEX_Y = 1, 1094 - SQ_TEX_Z = 2, 1095 - SQ_TEX_W = 3, 1096 - SQ_TEX_ZERO = 4, 1097 - SQ_TEX_ONE = 5, 1098 - }; 1099 - 1100 - enum sq_tex_filter { 1101 - SQ_TEX_FILTER_POINT = 0, 1102 - SQ_TEX_FILTER_BILINEAR = 1, 1103 - SQ_TEX_FILTER_BASEMAP = 2, 1104 - SQ_TEX_FILTER_USE_FETCH_CONST = 3, 1105 - }; 1106 - 1107 - enum sq_tex_aniso_filter { 1108 - SQ_TEX_ANISO_FILTER_DISABLED = 0, 1109 - SQ_TEX_ANISO_FILTER_MAX_1_1 = 1, 1110 - SQ_TEX_ANISO_FILTER_MAX_2_1 = 2, 1111 - SQ_TEX_ANISO_FILTER_MAX_4_1 = 3, 1112 - SQ_TEX_ANISO_FILTER_MAX_8_1 = 4, 1113 - SQ_TEX_ANISO_FILTER_MAX_16_1 = 5, 1114 - SQ_TEX_ANISO_FILTER_USE_FETCH_CONST = 7, 1115 - }; 1116 - 1117 - enum sq_tex_dimension { 1118 - SQ_TEX_DIMENSION_1D = 0, 1119 - SQ_TEX_DIMENSION_2D = 1, 1120 - SQ_TEX_DIMENSION_3D = 2, 1121 - SQ_TEX_DIMENSION_CUBE = 3, 1122 - }; 1123 - 1124 - enum sq_tex_border_color { 1125 - SQ_TEX_BORDER_COLOR_BLACK = 0, 1126 - SQ_TEX_BORDER_COLOR_WHITE = 1, 1127 - SQ_TEX_BORDER_COLOR_ACBYCR_BLACK = 2, 1128 - SQ_TEX_BORDER_COLOR_ACBCRY_BLACK = 3, 1129 - }; 1130 - 1131 - enum sq_tex_sign { 1132 - SQ_TEX_SIGN_UNSIGNED = 0, 1133 - SQ_TEX_SIGN_SIGNED = 1, 1134 - SQ_TEX_SIGN_UNSIGNED_BIASED = 2, 1135 - SQ_TEX_SIGN_GAMMA = 3, 1136 - }; 1137 - 1138 - enum sq_tex_endian { 1139 - SQ_TEX_ENDIAN_NONE = 0, 1140 - SQ_TEX_ENDIAN_8IN16 = 1, 1141 - SQ_TEX_ENDIAN_8IN32 = 2, 1142 - SQ_TEX_ENDIAN_16IN32 = 3, 1143 - }; 1144 - 1145 - enum sq_tex_clamp_policy { 1146 - SQ_TEX_CLAMP_POLICY_D3D = 0, 1147 - SQ_TEX_CLAMP_POLICY_OGL = 1, 1148 - }; 1149 - 1150 - enum sq_tex_num_format { 1151 - SQ_TEX_NUM_FORMAT_FRAC = 0, 1152 - SQ_TEX_NUM_FORMAT_INT = 1, 1153 - }; 1154 - 1155 - enum sq_tex_type { 1156 - SQ_TEX_TYPE_0 = 0, 1157 - SQ_TEX_TYPE_1 = 1, 1158 - SQ_TEX_TYPE_2 = 2, 1159 - SQ_TEX_TYPE_3 = 3, 1160 - }; 1161 - 1162 - #define REG_A2XX_RBBM_PATCH_RELEASE 0x00000001 1163 - 1164 - #define REG_A2XX_RBBM_CNTL 0x0000003b 1165 - 1166 - #define REG_A2XX_RBBM_SOFT_RESET 0x0000003c 1167 - 1168 - #define REG_A2XX_CP_PFP_UCODE_ADDR 0x000000c0 1169 - 1170 - #define REG_A2XX_CP_PFP_UCODE_DATA 0x000000c1 1171 - 1172 - #define REG_A2XX_MH_MMU_CONFIG 0x00000040 1173 - #define A2XX_MH_MMU_CONFIG_MMU_ENABLE 0x00000001 1174 - #define A2XX_MH_MMU_CONFIG_SPLIT_MODE_ENABLE 0x00000002 1175 - #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK 0x00000030 1176 - #define A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT 4 1177 - static inline uint32_t A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1178 - { 1179 - return ((val) << A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_RB_W_CLNT_BEHAVIOR__MASK; 1180 - } 1181 - #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK 0x000000c0 1182 - #define A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT 6 1183 - static inline uint32_t A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1184 - { 1185 - return ((val) << A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_W_CLNT_BEHAVIOR__MASK; 1186 - } 1187 - #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK 0x00000300 1188 - #define A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT 8 1189 - static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1190 - { 1191 - return ((val) << A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R0_CLNT_BEHAVIOR__MASK; 1192 - } 1193 - #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK 0x00000c00 1194 - #define A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT 10 1195 - static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1196 - { 1197 - return ((val) << A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R1_CLNT_BEHAVIOR__MASK; 1198 - } 1199 - #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK 0x00003000 1200 - #define A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT 12 1201 - static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1202 - { 1203 - return ((val) << A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R2_CLNT_BEHAVIOR__MASK; 1204 - } 1205 - #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK 0x0000c000 1206 - #define A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT 14 1207 - static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1208 - { 1209 - return ((val) << A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R3_CLNT_BEHAVIOR__MASK; 1210 - } 1211 - #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK 0x00030000 1212 - #define A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT 16 1213 - static inline uint32_t A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1214 - { 1215 - return ((val) << A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_CP_R4_CLNT_BEHAVIOR__MASK; 1216 - } 1217 - #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK 0x000c0000 1218 - #define A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT 18 1219 - static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1220 - { 1221 - return ((val) << A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R0_CLNT_BEHAVIOR__MASK; 1222 - } 1223 - #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK 0x00300000 1224 - #define A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT 20 1225 - static inline uint32_t A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1226 - { 1227 - return ((val) << A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_VGT_R1_CLNT_BEHAVIOR__MASK; 1228 - } 1229 - #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK 0x00c00000 1230 - #define A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT 22 1231 - static inline uint32_t A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1232 - { 1233 - return ((val) << A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_TC_R_CLNT_BEHAVIOR__MASK; 1234 - } 1235 - #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK 0x03000000 1236 - #define A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT 24 1237 - static inline uint32_t A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR(enum adreno_mmu_clnt_beh val) 1238 - { 1239 - return ((val) << A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__SHIFT) & A2XX_MH_MMU_CONFIG_PA_W_CLNT_BEHAVIOR__MASK; 1240 - } 1241 - 1242 - #define REG_A2XX_MH_MMU_VA_RANGE 0x00000041 1243 - #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK 0x00000fff 1244 - #define A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT 0 1245 - static inline uint32_t A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS(uint32_t val) 1246 - { 1247 - return ((val) << A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__SHIFT) & A2XX_MH_MMU_VA_RANGE_NUM_64KB_REGIONS__MASK; 1248 - } 1249 - #define A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK 0xfffff000 1250 - #define A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT 12 1251 - static inline uint32_t A2XX_MH_MMU_VA_RANGE_VA_BASE(uint32_t val) 1252 - { 1253 - return ((val) << A2XX_MH_MMU_VA_RANGE_VA_BASE__SHIFT) & A2XX_MH_MMU_VA_RANGE_VA_BASE__MASK; 1254 - } 1255 - 1256 - #define REG_A2XX_MH_MMU_PT_BASE 0x00000042 1257 - 1258 - #define REG_A2XX_MH_MMU_PAGE_FAULT 0x00000043 1259 - 1260 - #define REG_A2XX_MH_MMU_TRAN_ERROR 0x00000044 1261 - 1262 - #define REG_A2XX_MH_MMU_INVALIDATE 0x00000045 1263 - #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_ALL 0x00000001 1264 - #define A2XX_MH_MMU_INVALIDATE_INVALIDATE_TC 0x00000002 1265 - 1266 - #define REG_A2XX_MH_MMU_MPU_BASE 0x00000046 1267 - 1268 - #define REG_A2XX_MH_MMU_MPU_END 0x00000047 1269 - 1270 - #define REG_A2XX_NQWAIT_UNTIL 0x00000394 1271 - 1272 - #define REG_A2XX_RBBM_PERFCOUNTER0_SELECT 0x00000395 1273 - 1274 - #define REG_A2XX_RBBM_PERFCOUNTER1_SELECT 0x00000396 1275 - 1276 - #define REG_A2XX_RBBM_PERFCOUNTER0_LO 0x00000397 1277 - 1278 - #define REG_A2XX_RBBM_PERFCOUNTER0_HI 0x00000398 1279 - 1280 - #define REG_A2XX_RBBM_PERFCOUNTER1_LO 0x00000399 1281 - 1282 - #define REG_A2XX_RBBM_PERFCOUNTER1_HI 0x0000039a 1283 - 1284 - #define REG_A2XX_RBBM_DEBUG 0x0000039b 1285 - 1286 - #define REG_A2XX_RBBM_PM_OVERRIDE1 0x0000039c 1287 - #define A2XX_RBBM_PM_OVERRIDE1_RBBM_AHBCLK_PM_OVERRIDE 0x00000001 1288 - #define A2XX_RBBM_PM_OVERRIDE1_SC_REG_SCLK_PM_OVERRIDE 0x00000002 1289 - #define A2XX_RBBM_PM_OVERRIDE1_SC_SCLK_PM_OVERRIDE 0x00000004 1290 - #define A2XX_RBBM_PM_OVERRIDE1_SP_TOP_SCLK_PM_OVERRIDE 0x00000008 1291 - #define A2XX_RBBM_PM_OVERRIDE1_SP_V0_SCLK_PM_OVERRIDE 0x00000010 1292 - #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_SCLK_PM_OVERRIDE 0x00000020 1293 - #define A2XX_RBBM_PM_OVERRIDE1_SQ_REG_FIFOS_SCLK_PM_OVERRIDE 0x00000040 1294 - #define A2XX_RBBM_PM_OVERRIDE1_SQ_CONST_MEM_SCLK_PM_OVERRIDE 0x00000080 1295 - #define A2XX_RBBM_PM_OVERRIDE1_SQ_SQ_SCLK_PM_OVERRIDE 0x00000100 1296 - #define A2XX_RBBM_PM_OVERRIDE1_SX_SCLK_PM_OVERRIDE 0x00000200 1297 - #define A2XX_RBBM_PM_OVERRIDE1_SX_REG_SCLK_PM_OVERRIDE 0x00000400 1298 - #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCO_SCLK_PM_OVERRIDE 0x00000800 1299 - #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCM_SCLK_PM_OVERRIDE 0x00001000 1300 - #define A2XX_RBBM_PM_OVERRIDE1_TCM_TCD_SCLK_PM_OVERRIDE 0x00002000 1301 - #define A2XX_RBBM_PM_OVERRIDE1_TCM_REG_SCLK_PM_OVERRIDE 0x00004000 1302 - #define A2XX_RBBM_PM_OVERRIDE1_TPC_TPC_SCLK_PM_OVERRIDE 0x00008000 1303 - #define A2XX_RBBM_PM_OVERRIDE1_TPC_REG_SCLK_PM_OVERRIDE 0x00010000 1304 - #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCA_SCLK_PM_OVERRIDE 0x00020000 1305 - #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_SCLK_PM_OVERRIDE 0x00040000 1306 - #define A2XX_RBBM_PM_OVERRIDE1_TCF_TCB_READ_SCLK_PM_OVERRIDE 0x00080000 1307 - #define A2XX_RBBM_PM_OVERRIDE1_TP_TP_SCLK_PM_OVERRIDE 0x00100000 1308 - #define A2XX_RBBM_PM_OVERRIDE1_TP_REG_SCLK_PM_OVERRIDE 0x00200000 1309 - #define A2XX_RBBM_PM_OVERRIDE1_CP_G_SCLK_PM_OVERRIDE 0x00400000 1310 - #define A2XX_RBBM_PM_OVERRIDE1_CP_REG_SCLK_PM_OVERRIDE 0x00800000 1311 - #define A2XX_RBBM_PM_OVERRIDE1_CP_G_REG_SCLK_PM_OVERRIDE 0x01000000 1312 - #define A2XX_RBBM_PM_OVERRIDE1_SPI_SCLK_PM_OVERRIDE 0x02000000 1313 - #define A2XX_RBBM_PM_OVERRIDE1_RB_REG_SCLK_PM_OVERRIDE 0x04000000 1314 - #define A2XX_RBBM_PM_OVERRIDE1_RB_SCLK_PM_OVERRIDE 0x08000000 1315 - #define A2XX_RBBM_PM_OVERRIDE1_MH_MH_SCLK_PM_OVERRIDE 0x10000000 1316 - #define A2XX_RBBM_PM_OVERRIDE1_MH_REG_SCLK_PM_OVERRIDE 0x20000000 1317 - #define A2XX_RBBM_PM_OVERRIDE1_MH_MMU_SCLK_PM_OVERRIDE 0x40000000 1318 - #define A2XX_RBBM_PM_OVERRIDE1_MH_TCROQ_SCLK_PM_OVERRIDE 0x80000000 1319 - 1320 - #define REG_A2XX_RBBM_PM_OVERRIDE2 0x0000039d 1321 - #define A2XX_RBBM_PM_OVERRIDE2_PA_REG_SCLK_PM_OVERRIDE 0x00000001 1322 - #define A2XX_RBBM_PM_OVERRIDE2_PA_PA_SCLK_PM_OVERRIDE 0x00000002 1323 - #define A2XX_RBBM_PM_OVERRIDE2_PA_AG_SCLK_PM_OVERRIDE 0x00000004 1324 - #define A2XX_RBBM_PM_OVERRIDE2_VGT_REG_SCLK_PM_OVERRIDE 0x00000008 1325 - #define A2XX_RBBM_PM_OVERRIDE2_VGT_FIFOS_SCLK_PM_OVERRIDE 0x00000010 1326 - #define A2XX_RBBM_PM_OVERRIDE2_VGT_VGT_SCLK_PM_OVERRIDE 0x00000020 1327 - #define A2XX_RBBM_PM_OVERRIDE2_DEBUG_PERF_SCLK_PM_OVERRIDE 0x00000040 1328 - #define A2XX_RBBM_PM_OVERRIDE2_PERM_SCLK_PM_OVERRIDE 0x00000080 1329 - #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM0_PM_OVERRIDE 0x00000100 1330 - #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM1_PM_OVERRIDE 0x00000200 1331 - #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM2_PM_OVERRIDE 0x00000400 1332 - #define A2XX_RBBM_PM_OVERRIDE2_GC_GA_GMEM3_PM_OVERRIDE 0x00000800 1333 - 1334 - #define REG_A2XX_RBBM_DEBUG_OUT 0x000003a0 1335 - 1336 - #define REG_A2XX_RBBM_DEBUG_CNTL 0x000003a1 1337 - 1338 - #define REG_A2XX_RBBM_READ_ERROR 0x000003b3 1339 - 1340 - #define REG_A2XX_RBBM_INT_CNTL 0x000003b4 1341 - #define A2XX_RBBM_INT_CNTL_RDERR_INT_MASK 0x00000001 1342 - #define A2XX_RBBM_INT_CNTL_DISPLAY_UPDATE_INT_MASK 0x00000002 1343 - #define A2XX_RBBM_INT_CNTL_GUI_IDLE_INT_MASK 0x00080000 1344 - 1345 - #define REG_A2XX_RBBM_INT_STATUS 0x000003b5 1346 - 1347 - #define REG_A2XX_RBBM_INT_ACK 0x000003b6 1348 - 1349 - #define REG_A2XX_MASTER_INT_SIGNAL 0x000003b7 1350 - #define A2XX_MASTER_INT_SIGNAL_MH_INT_STAT 0x00000020 1351 - #define A2XX_MASTER_INT_SIGNAL_SQ_INT_STAT 0x04000000 1352 - #define A2XX_MASTER_INT_SIGNAL_CP_INT_STAT 0x40000000 1353 - #define A2XX_MASTER_INT_SIGNAL_RBBM_INT_STAT 0x80000000 1354 - 1355 - #define REG_A2XX_RBBM_PERIPHID1 0x000003f9 1356 - 1357 - #define REG_A2XX_RBBM_PERIPHID2 0x000003fa 1358 - 1359 - #define REG_A2XX_CP_PERFMON_CNTL 0x00000444 1360 - #define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK 0x00000007 1361 - #define A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT 0 1362 - static inline uint32_t A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT(enum perf_mode_cnt val) 1363 - { 1364 - return ((val) << A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__SHIFT) & A2XX_CP_PERFMON_CNTL_PERF_MODE_CNT__MASK; 1365 - } 1366 - 1367 - #define REG_A2XX_CP_PERFCOUNTER_SELECT 0x00000445 1368 - 1369 - #define REG_A2XX_CP_PERFCOUNTER_LO 0x00000446 1370 - 1371 - #define REG_A2XX_CP_PERFCOUNTER_HI 0x00000447 1372 - 1373 - #define REG_A2XX_RBBM_STATUS 0x000005d0 1374 - #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK 0x0000001f 1375 - #define A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT 0 1376 - static inline uint32_t A2XX_RBBM_STATUS_CMDFIFO_AVAIL(uint32_t val) 1377 - { 1378 - return ((val) << A2XX_RBBM_STATUS_CMDFIFO_AVAIL__SHIFT) & A2XX_RBBM_STATUS_CMDFIFO_AVAIL__MASK; 1379 - } 1380 - #define A2XX_RBBM_STATUS_TC_BUSY 0x00000020 1381 - #define A2XX_RBBM_STATUS_HIRQ_PENDING 0x00000100 1382 - #define A2XX_RBBM_STATUS_CPRQ_PENDING 0x00000200 1383 - #define A2XX_RBBM_STATUS_CFRQ_PENDING 0x00000400 1384 - #define A2XX_RBBM_STATUS_PFRQ_PENDING 0x00000800 1385 - #define A2XX_RBBM_STATUS_VGT_BUSY_NO_DMA 0x00001000 1386 - #define A2XX_RBBM_STATUS_RBBM_WU_BUSY 0x00004000 1387 - #define A2XX_RBBM_STATUS_CP_NRT_BUSY 0x00010000 1388 - #define A2XX_RBBM_STATUS_MH_BUSY 0x00040000 1389 - #define A2XX_RBBM_STATUS_MH_COHERENCY_BUSY 0x00080000 1390 - #define A2XX_RBBM_STATUS_SX_BUSY 0x00200000 1391 - #define A2XX_RBBM_STATUS_TPC_BUSY 0x00400000 1392 - #define A2XX_RBBM_STATUS_SC_CNTX_BUSY 0x01000000 1393 - #define A2XX_RBBM_STATUS_PA_BUSY 0x02000000 1394 - #define A2XX_RBBM_STATUS_VGT_BUSY 0x04000000 1395 - #define A2XX_RBBM_STATUS_SQ_CNTX17_BUSY 0x08000000 1396 - #define A2XX_RBBM_STATUS_SQ_CNTX0_BUSY 0x10000000 1397 - #define A2XX_RBBM_STATUS_RB_CNTX_BUSY 0x40000000 1398 - #define A2XX_RBBM_STATUS_GUI_ACTIVE 0x80000000 1399 - 1400 - #define REG_A2XX_MH_ARBITER_CONFIG 0x00000a40 1401 - #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK 0x0000003f 1402 - #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT 0 1403 - static inline uint32_t A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT(uint32_t val) 1404 - { 1405 - return ((val) << A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_SAME_PAGE_LIMIT__MASK; 1406 - } 1407 - #define A2XX_MH_ARBITER_CONFIG_SAME_PAGE_GRANULARITY 0x00000040 1408 - #define A2XX_MH_ARBITER_CONFIG_L1_ARB_ENABLE 0x00000080 1409 - #define A2XX_MH_ARBITER_CONFIG_L1_ARB_HOLD_ENABLE 0x00000100 1410 - #define A2XX_MH_ARBITER_CONFIG_L2_ARB_CONTROL 0x00000200 1411 - #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK 0x00001c00 1412 - #define A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT 10 1413 - static inline uint32_t A2XX_MH_ARBITER_CONFIG_PAGE_SIZE(uint32_t val) 1414 - { 1415 - return ((val) << A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__SHIFT) & A2XX_MH_ARBITER_CONFIG_PAGE_SIZE__MASK; 1416 - } 1417 - #define A2XX_MH_ARBITER_CONFIG_TC_REORDER_ENABLE 0x00002000 1418 - #define A2XX_MH_ARBITER_CONFIG_TC_ARB_HOLD_ENABLE 0x00004000 1419 - #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT_ENABLE 0x00008000 1420 - #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK 0x003f0000 1421 - #define A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT 16 1422 - static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) 1423 - { 1424 - return ((val) << A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__SHIFT) & A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT__MASK; 1425 - } 1426 - #define A2XX_MH_ARBITER_CONFIG_CP_CLNT_ENABLE 0x00400000 1427 - #define A2XX_MH_ARBITER_CONFIG_VGT_CLNT_ENABLE 0x00800000 1428 - #define A2XX_MH_ARBITER_CONFIG_TC_CLNT_ENABLE 0x01000000 1429 - #define A2XX_MH_ARBITER_CONFIG_RB_CLNT_ENABLE 0x02000000 1430 - #define A2XX_MH_ARBITER_CONFIG_PA_CLNT_ENABLE 0x04000000 1431 - 1432 - #define REG_A2XX_MH_INTERRUPT_MASK 0x00000a42 1433 - #define A2XX_MH_INTERRUPT_MASK_AXI_READ_ERROR 0x00000001 1434 - #define A2XX_MH_INTERRUPT_MASK_AXI_WRITE_ERROR 0x00000002 1435 - #define A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT 0x00000004 1436 - 1437 - #define REG_A2XX_MH_INTERRUPT_STATUS 0x00000a43 1438 - 1439 - #define REG_A2XX_MH_INTERRUPT_CLEAR 0x00000a44 1440 - 1441 - #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG1 0x00000a54 1442 - 1443 - #define REG_A2XX_MH_CLNT_INTF_CTRL_CONFIG2 0x00000a55 1444 - 1445 - #define REG_A2XX_A220_VSC_BIN_SIZE 0x00000c01 1446 - #define A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f 1447 - #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 1448 - static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) 1449 - { 1450 - assert(!(val & 0x1f)); 1451 - return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; 1452 - } 1453 - #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 1454 - #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 1455 - static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) 1456 - { 1457 - assert(!(val & 0x1f)); 1458 - return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; 1459 - } 1460 - 1461 - #define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) 1462 - 1463 - static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } 1464 - 1465 - static inline uint32_t REG_A2XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; } 1466 - 1467 - static inline uint32_t REG_A2XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; } 1468 - 1469 - #define REG_A2XX_PC_DEBUG_CNTL 0x00000c38 1470 - 1471 - #define REG_A2XX_PC_DEBUG_DATA 0x00000c39 1472 - 1473 - #define REG_A2XX_PA_SC_VIZ_QUERY_STATUS 0x00000c44 1474 - 1475 - #define REG_A2XX_GRAS_DEBUG_CNTL 0x00000c80 1476 - 1477 - #define REG_A2XX_PA_SU_DEBUG_CNTL 0x00000c80 1478 - 1479 - #define REG_A2XX_GRAS_DEBUG_DATA 0x00000c81 1480 - 1481 - #define REG_A2XX_PA_SU_DEBUG_DATA 0x00000c81 1482 - 1483 - #define REG_A2XX_PA_SU_FACE_DATA 0x00000c86 1484 - #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK 0xffffffe0 1485 - #define A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT 5 1486 - static inline uint32_t A2XX_PA_SU_FACE_DATA_BASE_ADDR(uint32_t val) 1487 - { 1488 - return ((val) << A2XX_PA_SU_FACE_DATA_BASE_ADDR__SHIFT) & A2XX_PA_SU_FACE_DATA_BASE_ADDR__MASK; 1489 - } 1490 - 1491 - #define REG_A2XX_SQ_GPR_MANAGEMENT 0x00000d00 1492 - #define A2XX_SQ_GPR_MANAGEMENT_REG_DYNAMIC 0x00000001 1493 - #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK 0x00000ff0 1494 - #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT 4 1495 - static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX(uint32_t val) 1496 - { 1497 - return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_PIX__MASK; 1498 - } 1499 - #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK 0x000ff000 1500 - #define A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT 12 1501 - static inline uint32_t A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX(uint32_t val) 1502 - { 1503 - return ((val) << A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__SHIFT) & A2XX_SQ_GPR_MANAGEMENT_REG_SIZE_VTX__MASK; 1504 - } 1505 - 1506 - #define REG_A2XX_SQ_FLOW_CONTROL 0x00000d01 1507 - 1508 - #define REG_A2XX_SQ_INST_STORE_MANAGMENT 0x00000d02 1509 - #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK 0x00000fff 1510 - #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT 0 1511 - static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX(uint32_t val) 1512 - { 1513 - return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_PIX__MASK; 1514 - } 1515 - #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK 0x0fff0000 1516 - #define A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT 16 1517 - static inline uint32_t A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX(uint32_t val) 1518 - { 1519 - return ((val) << A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__SHIFT) & A2XX_SQ_INST_STORE_MANAGMENT_INST_BASE_VTX__MASK; 1520 - } 1521 - 1522 - #define REG_A2XX_SQ_DEBUG_MISC 0x00000d05 1523 - 1524 - #define REG_A2XX_SQ_INT_CNTL 0x00000d34 1525 - 1526 - #define REG_A2XX_SQ_INT_STATUS 0x00000d35 1527 - 1528 - #define REG_A2XX_SQ_INT_ACK 0x00000d36 1529 - 1530 - #define REG_A2XX_SQ_DEBUG_INPUT_FSM 0x00000dae 1531 - 1532 - #define REG_A2XX_SQ_DEBUG_CONST_MGR_FSM 0x00000daf 1533 - 1534 - #define REG_A2XX_SQ_DEBUG_TP_FSM 0x00000db0 1535 - 1536 - #define REG_A2XX_SQ_DEBUG_FSM_ALU_0 0x00000db1 1537 - 1538 - #define REG_A2XX_SQ_DEBUG_FSM_ALU_1 0x00000db2 1539 - 1540 - #define REG_A2XX_SQ_DEBUG_EXP_ALLOC 0x00000db3 1541 - 1542 - #define REG_A2XX_SQ_DEBUG_PTR_BUFF 0x00000db4 1543 - 1544 - #define REG_A2XX_SQ_DEBUG_GPR_VTX 0x00000db5 1545 - 1546 - #define REG_A2XX_SQ_DEBUG_GPR_PIX 0x00000db6 1547 - 1548 - #define REG_A2XX_SQ_DEBUG_TB_STATUS_SEL 0x00000db7 1549 - 1550 - #define REG_A2XX_SQ_DEBUG_VTX_TB_0 0x00000db8 1551 - 1552 - #define REG_A2XX_SQ_DEBUG_VTX_TB_1 0x00000db9 1553 - 1554 - #define REG_A2XX_SQ_DEBUG_VTX_TB_STATUS_REG 0x00000dba 1555 - 1556 - #define REG_A2XX_SQ_DEBUG_VTX_TB_STATE_MEM 0x00000dbb 1557 - 1558 - #define REG_A2XX_SQ_DEBUG_PIX_TB_0 0x00000dbc 1559 - 1560 - #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_0 0x00000dbd 1561 - 1562 - #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_1 0x00000dbe 1563 - 1564 - #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_2 0x00000dbf 1565 - 1566 - #define REG_A2XX_SQ_DEBUG_PIX_TB_STATUS_REG_3 0x00000dc0 1567 - 1568 - #define REG_A2XX_SQ_DEBUG_PIX_TB_STATE_MEM 0x00000dc1 1569 - 1570 - #define REG_A2XX_TC_CNTL_STATUS 0x00000e00 1571 - #define A2XX_TC_CNTL_STATUS_L2_INVALIDATE 0x00000001 1572 - 1573 - #define REG_A2XX_TP0_CHICKEN 0x00000e1e 1574 - 1575 - #define REG_A2XX_RB_BC_CONTROL 0x00000f01 1576 - #define A2XX_RB_BC_CONTROL_ACCUM_LINEAR_MODE_ENABLE 0x00000001 1577 - #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK 0x00000006 1578 - #define A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT 1 1579 - static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT(uint32_t val) 1580 - { 1581 - return ((val) << A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_TIMEOUT_SELECT__MASK; 1582 - } 1583 - #define A2XX_RB_BC_CONTROL_DISABLE_EDRAM_CAM 0x00000008 1584 - #define A2XX_RB_BC_CONTROL_DISABLE_EZ_FAST_CONTEXT_SWITCH 0x00000010 1585 - #define A2XX_RB_BC_CONTROL_DISABLE_EZ_NULL_ZCMD_DROP 0x00000020 1586 - #define A2XX_RB_BC_CONTROL_DISABLE_LZ_NULL_ZCMD_DROP 0x00000040 1587 - #define A2XX_RB_BC_CONTROL_ENABLE_AZ_THROTTLE 0x00000080 1588 - #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK 0x00001f00 1589 - #define A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT 8 1590 - static inline uint32_t A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT(uint32_t val) 1591 - { 1592 - return ((val) << A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__SHIFT) & A2XX_RB_BC_CONTROL_AZ_THROTTLE_COUNT__MASK; 1593 - } 1594 - #define A2XX_RB_BC_CONTROL_ENABLE_CRC_UPDATE 0x00004000 1595 - #define A2XX_RB_BC_CONTROL_CRC_MODE 0x00008000 1596 - #define A2XX_RB_BC_CONTROL_DISABLE_SAMPLE_COUNTERS 0x00010000 1597 - #define A2XX_RB_BC_CONTROL_DISABLE_ACCUM 0x00020000 1598 - #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK 0x003c0000 1599 - #define A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT 18 1600 - static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK(uint32_t val) 1601 - { 1602 - return ((val) << A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_ALLOC_MASK__MASK; 1603 - } 1604 - #define A2XX_RB_BC_CONTROL_LINEAR_PERFORMANCE_ENABLE 0x00400000 1605 - #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK 0x07800000 1606 - #define A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT 23 1607 - static inline uint32_t A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT(uint32_t val) 1608 - { 1609 - return ((val) << A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__SHIFT) & A2XX_RB_BC_CONTROL_ACCUM_DATA_FIFO_LIMIT__MASK; 1610 - } 1611 - #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK 0x18000000 1612 - #define A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT 27 1613 - static inline uint32_t A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT(uint32_t val) 1614 - { 1615 - return ((val) << A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__SHIFT) & A2XX_RB_BC_CONTROL_MEM_EXPORT_TIMEOUT_SELECT__MASK; 1616 - } 1617 - #define A2XX_RB_BC_CONTROL_MEM_EXPORT_LINEAR_MODE_ENABLE 0x20000000 1618 - #define A2XX_RB_BC_CONTROL_CRC_SYSTEM 0x40000000 1619 - #define A2XX_RB_BC_CONTROL_RESERVED6 0x80000000 1620 - 1621 - #define REG_A2XX_RB_EDRAM_INFO 0x00000f02 1622 - 1623 - #define REG_A2XX_RB_DEBUG_CNTL 0x00000f26 1624 - 1625 - #define REG_A2XX_RB_DEBUG_DATA 0x00000f27 1626 - 1627 - #define REG_A2XX_RB_SURFACE_INFO 0x00002000 1628 - #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK 0x00003fff 1629 - #define A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT 0 1630 - static inline uint32_t A2XX_RB_SURFACE_INFO_SURFACE_PITCH(uint32_t val) 1631 - { 1632 - return ((val) << A2XX_RB_SURFACE_INFO_SURFACE_PITCH__SHIFT) & A2XX_RB_SURFACE_INFO_SURFACE_PITCH__MASK; 1633 - } 1634 - #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK 0x0000c000 1635 - #define A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT 14 1636 - static inline uint32_t A2XX_RB_SURFACE_INFO_MSAA_SAMPLES(uint32_t val) 1637 - { 1638 - return ((val) << A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__SHIFT) & A2XX_RB_SURFACE_INFO_MSAA_SAMPLES__MASK; 1639 - } 1640 - 1641 - #define REG_A2XX_RB_COLOR_INFO 0x00002001 1642 - #define A2XX_RB_COLOR_INFO_FORMAT__MASK 0x0000000f 1643 - #define A2XX_RB_COLOR_INFO_FORMAT__SHIFT 0 1644 - static inline uint32_t A2XX_RB_COLOR_INFO_FORMAT(enum a2xx_colorformatx val) 1645 - { 1646 - return ((val) << A2XX_RB_COLOR_INFO_FORMAT__SHIFT) & A2XX_RB_COLOR_INFO_FORMAT__MASK; 1647 - } 1648 - #define A2XX_RB_COLOR_INFO_ROUND_MODE__MASK 0x00000030 1649 - #define A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT 4 1650 - static inline uint32_t A2XX_RB_COLOR_INFO_ROUND_MODE(uint32_t val) 1651 - { 1652 - return ((val) << A2XX_RB_COLOR_INFO_ROUND_MODE__SHIFT) & A2XX_RB_COLOR_INFO_ROUND_MODE__MASK; 1653 - } 1654 - #define A2XX_RB_COLOR_INFO_LINEAR 0x00000040 1655 - #define A2XX_RB_COLOR_INFO_ENDIAN__MASK 0x00000180 1656 - #define A2XX_RB_COLOR_INFO_ENDIAN__SHIFT 7 1657 - static inline uint32_t A2XX_RB_COLOR_INFO_ENDIAN(uint32_t val) 1658 - { 1659 - return ((val) << A2XX_RB_COLOR_INFO_ENDIAN__SHIFT) & A2XX_RB_COLOR_INFO_ENDIAN__MASK; 1660 - } 1661 - #define A2XX_RB_COLOR_INFO_SWAP__MASK 0x00000600 1662 - #define A2XX_RB_COLOR_INFO_SWAP__SHIFT 9 1663 - static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) 1664 - { 1665 - return ((val) << A2XX_RB_COLOR_INFO_SWAP__SHIFT) & A2XX_RB_COLOR_INFO_SWAP__MASK; 1666 - } 1667 - #define A2XX_RB_COLOR_INFO_BASE__MASK 0xfffff000 1668 - #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 1669 - static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) 1670 - { 1671 - assert(!(val & 0xfff)); 1672 - return (((val >> 12)) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; 1673 - } 1674 - 1675 - #define REG_A2XX_RB_DEPTH_INFO 0x00002002 1676 - #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000001 1677 - #define A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0 1678 - static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val) 1679 - { 1680 - return ((val) << A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK; 1681 - } 1682 - #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff000 1683 - #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 1684 - static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) 1685 - { 1686 - assert(!(val & 0xfff)); 1687 - return (((val >> 12)) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; 1688 - } 1689 - 1690 - #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 1691 - 1692 - #define REG_A2XX_COHER_DEST_BASE_0 0x00002006 1693 - 1694 - #define REG_A2XX_PA_SC_SCREEN_SCISSOR_TL 0x0000200e 1695 - #define A2XX_PA_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1696 - #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff 1697 - #define A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT 0 1698 - static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_X(uint32_t val) 1699 - { 1700 - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_X__MASK; 1701 - } 1702 - #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000 1703 - #define A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16 1704 - static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_TL_Y(uint32_t val) 1705 - { 1706 - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_TL_Y__MASK; 1707 - } 1708 - 1709 - #define REG_A2XX_PA_SC_SCREEN_SCISSOR_BR 0x0000200f 1710 - #define A2XX_PA_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1711 - #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff 1712 - #define A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT 0 1713 - static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_X(uint32_t val) 1714 - { 1715 - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_X__MASK; 1716 - } 1717 - #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000 1718 - #define A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16 1719 - static inline uint32_t A2XX_PA_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) 1720 - { 1721 - return ((val) << A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_SCREEN_SCISSOR_BR_Y__MASK; 1722 - } 1723 - 1724 - #define REG_A2XX_PA_SC_WINDOW_OFFSET 0x00002080 1725 - #define A2XX_PA_SC_WINDOW_OFFSET_X__MASK 0x00007fff 1726 - #define A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT 0 1727 - static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_X(int32_t val) 1728 - { 1729 - return ((val) << A2XX_PA_SC_WINDOW_OFFSET_X__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_X__MASK; 1730 - } 1731 - #define A2XX_PA_SC_WINDOW_OFFSET_Y__MASK 0x7fff0000 1732 - #define A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT 16 1733 - static inline uint32_t A2XX_PA_SC_WINDOW_OFFSET_Y(int32_t val) 1734 - { 1735 - return ((val) << A2XX_PA_SC_WINDOW_OFFSET_Y__SHIFT) & A2XX_PA_SC_WINDOW_OFFSET_Y__MASK; 1736 - } 1737 - #define A2XX_PA_SC_WINDOW_OFFSET_DISABLE 0x80000000 1738 - 1739 - #define REG_A2XX_PA_SC_WINDOW_SCISSOR_TL 0x00002081 1740 - #define A2XX_PA_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000 1741 - #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff 1742 - #define A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT 0 1743 - static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_X(uint32_t val) 1744 - { 1745 - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_X__MASK; 1746 - } 1747 - #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000 1748 - #define A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16 1749 - static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_TL_Y(uint32_t val) 1750 - { 1751 - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_TL_Y__MASK; 1752 - } 1753 - 1754 - #define REG_A2XX_PA_SC_WINDOW_SCISSOR_BR 0x00002082 1755 - #define A2XX_PA_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000 1756 - #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff 1757 - #define A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT 0 1758 - static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_X(uint32_t val) 1759 - { 1760 - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_X__MASK; 1761 - } 1762 - #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000 1763 - #define A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16 1764 - static inline uint32_t A2XX_PA_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) 1765 - { 1766 - return ((val) << A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A2XX_PA_SC_WINDOW_SCISSOR_BR_Y__MASK; 1767 - } 1768 - 1769 - #define REG_A2XX_UNKNOWN_2010 0x00002010 1770 - 1771 - #define REG_A2XX_VGT_MAX_VTX_INDX 0x00002100 1772 - 1773 - #define REG_A2XX_VGT_MIN_VTX_INDX 0x00002101 1774 - 1775 - #define REG_A2XX_VGT_INDX_OFFSET 0x00002102 1776 - 1777 - #define REG_A2XX_A225_PC_MULTI_PRIM_IB_RESET_INDX 0x00002103 1778 - 1779 - #define REG_A2XX_RB_COLOR_MASK 0x00002104 1780 - #define A2XX_RB_COLOR_MASK_WRITE_RED 0x00000001 1781 - #define A2XX_RB_COLOR_MASK_WRITE_GREEN 0x00000002 1782 - #define A2XX_RB_COLOR_MASK_WRITE_BLUE 0x00000004 1783 - #define A2XX_RB_COLOR_MASK_WRITE_ALPHA 0x00000008 1784 - 1785 - #define REG_A2XX_RB_BLEND_RED 0x00002105 1786 - 1787 - #define REG_A2XX_RB_BLEND_GREEN 0x00002106 1788 - 1789 - #define REG_A2XX_RB_BLEND_BLUE 0x00002107 1790 - 1791 - #define REG_A2XX_RB_BLEND_ALPHA 0x00002108 1792 - 1793 - #define REG_A2XX_RB_FOG_COLOR 0x00002109 1794 - #define A2XX_RB_FOG_COLOR_FOG_RED__MASK 0x000000ff 1795 - #define A2XX_RB_FOG_COLOR_FOG_RED__SHIFT 0 1796 - static inline uint32_t A2XX_RB_FOG_COLOR_FOG_RED(uint32_t val) 1797 - { 1798 - return ((val) << A2XX_RB_FOG_COLOR_FOG_RED__SHIFT) & A2XX_RB_FOG_COLOR_FOG_RED__MASK; 1799 - } 1800 - #define A2XX_RB_FOG_COLOR_FOG_GREEN__MASK 0x0000ff00 1801 - #define A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT 8 1802 - static inline uint32_t A2XX_RB_FOG_COLOR_FOG_GREEN(uint32_t val) 1803 - { 1804 - return ((val) << A2XX_RB_FOG_COLOR_FOG_GREEN__SHIFT) & A2XX_RB_FOG_COLOR_FOG_GREEN__MASK; 1805 - } 1806 - #define A2XX_RB_FOG_COLOR_FOG_BLUE__MASK 0x00ff0000 1807 - #define A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT 16 1808 - static inline uint32_t A2XX_RB_FOG_COLOR_FOG_BLUE(uint32_t val) 1809 - { 1810 - return ((val) << A2XX_RB_FOG_COLOR_FOG_BLUE__SHIFT) & A2XX_RB_FOG_COLOR_FOG_BLUE__MASK; 1811 - } 1812 - 1813 - #define REG_A2XX_RB_STENCILREFMASK_BF 0x0000210c 1814 - #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff 1815 - #define A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0 1816 - static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val) 1817 - { 1818 - return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILREF__MASK; 1819 - } 1820 - #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00 1821 - #define A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8 1822 - static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val) 1823 - { 1824 - return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK; 1825 - } 1826 - #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000 1827 - #define A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16 1828 - static inline uint32_t A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val) 1829 - { 1830 - return ((val) << A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK; 1831 - } 1832 - 1833 - #define REG_A2XX_RB_STENCILREFMASK 0x0000210d 1834 - #define A2XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff 1835 - #define A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0 1836 - static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILREF(uint32_t val) 1837 - { 1838 - return ((val) << A2XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILREF__MASK; 1839 - } 1840 - #define A2XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00 1841 - #define A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8 1842 - static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val) 1843 - { 1844 - return ((val) << A2XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILMASK__MASK; 1845 - } 1846 - #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000 1847 - #define A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16 1848 - static inline uint32_t A2XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val) 1849 - { 1850 - return ((val) << A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A2XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK; 1851 - } 1852 - 1853 - #define REG_A2XX_RB_ALPHA_REF 0x0000210e 1854 - 1855 - #define REG_A2XX_PA_CL_VPORT_XSCALE 0x0000210f 1856 - #define A2XX_PA_CL_VPORT_XSCALE__MASK 0xffffffff 1857 - #define A2XX_PA_CL_VPORT_XSCALE__SHIFT 0 1858 - static inline uint32_t A2XX_PA_CL_VPORT_XSCALE(float val) 1859 - { 1860 - return ((fui(val)) << A2XX_PA_CL_VPORT_XSCALE__SHIFT) & A2XX_PA_CL_VPORT_XSCALE__MASK; 1861 - } 1862 - 1863 - #define REG_A2XX_PA_CL_VPORT_XOFFSET 0x00002110 1864 - #define A2XX_PA_CL_VPORT_XOFFSET__MASK 0xffffffff 1865 - #define A2XX_PA_CL_VPORT_XOFFSET__SHIFT 0 1866 - static inline uint32_t A2XX_PA_CL_VPORT_XOFFSET(float val) 1867 - { 1868 - return ((fui(val)) << A2XX_PA_CL_VPORT_XOFFSET__SHIFT) & A2XX_PA_CL_VPORT_XOFFSET__MASK; 1869 - } 1870 - 1871 - #define REG_A2XX_PA_CL_VPORT_YSCALE 0x00002111 1872 - #define A2XX_PA_CL_VPORT_YSCALE__MASK 0xffffffff 1873 - #define A2XX_PA_CL_VPORT_YSCALE__SHIFT 0 1874 - static inline uint32_t A2XX_PA_CL_VPORT_YSCALE(float val) 1875 - { 1876 - return ((fui(val)) << A2XX_PA_CL_VPORT_YSCALE__SHIFT) & A2XX_PA_CL_VPORT_YSCALE__MASK; 1877 - } 1878 - 1879 - #define REG_A2XX_PA_CL_VPORT_YOFFSET 0x00002112 1880 - #define A2XX_PA_CL_VPORT_YOFFSET__MASK 0xffffffff 1881 - #define A2XX_PA_CL_VPORT_YOFFSET__SHIFT 0 1882 - static inline uint32_t A2XX_PA_CL_VPORT_YOFFSET(float val) 1883 - { 1884 - return ((fui(val)) << A2XX_PA_CL_VPORT_YOFFSET__SHIFT) & A2XX_PA_CL_VPORT_YOFFSET__MASK; 1885 - } 1886 - 1887 - #define REG_A2XX_PA_CL_VPORT_ZSCALE 0x00002113 1888 - #define A2XX_PA_CL_VPORT_ZSCALE__MASK 0xffffffff 1889 - #define A2XX_PA_CL_VPORT_ZSCALE__SHIFT 0 1890 - static inline uint32_t A2XX_PA_CL_VPORT_ZSCALE(float val) 1891 - { 1892 - return ((fui(val)) << A2XX_PA_CL_VPORT_ZSCALE__SHIFT) & A2XX_PA_CL_VPORT_ZSCALE__MASK; 1893 - } 1894 - 1895 - #define REG_A2XX_PA_CL_VPORT_ZOFFSET 0x00002114 1896 - #define A2XX_PA_CL_VPORT_ZOFFSET__MASK 0xffffffff 1897 - #define A2XX_PA_CL_VPORT_ZOFFSET__SHIFT 0 1898 - static inline uint32_t A2XX_PA_CL_VPORT_ZOFFSET(float val) 1899 - { 1900 - return ((fui(val)) << A2XX_PA_CL_VPORT_ZOFFSET__SHIFT) & A2XX_PA_CL_VPORT_ZOFFSET__MASK; 1901 - } 1902 - 1903 - #define REG_A2XX_SQ_PROGRAM_CNTL 0x00002180 1904 - #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK 0x000000ff 1905 - #define A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT 0 1906 - static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_REGS(uint32_t val) 1907 - { 1908 - return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_REGS__MASK; 1909 - } 1910 - #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK 0x0000ff00 1911 - #define A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT 8 1912 - static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_REGS(uint32_t val) 1913 - { 1914 - return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_REGS__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_REGS__MASK; 1915 - } 1916 - #define A2XX_SQ_PROGRAM_CNTL_VS_RESOURCE 0x00010000 1917 - #define A2XX_SQ_PROGRAM_CNTL_PS_RESOURCE 0x00020000 1918 - #define A2XX_SQ_PROGRAM_CNTL_PARAM_GEN 0x00040000 1919 - #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_PIX 0x00080000 1920 - #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK 0x00f00000 1921 - #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT 20 1922 - static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT(uint32_t val) 1923 - { 1924 - return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_COUNT__MASK; 1925 - } 1926 - #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK 0x07000000 1927 - #define A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT 24 1928 - static inline uint32_t A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE(enum a2xx_sq_ps_vtx_mode val) 1929 - { 1930 - return ((val) << A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_VS_EXPORT_MODE__MASK; 1931 - } 1932 - #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK 0x78000000 1933 - #define A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT 27 1934 - static inline uint32_t A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE(uint32_t val) 1935 - { 1936 - return ((val) << A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__SHIFT) & A2XX_SQ_PROGRAM_CNTL_PS_EXPORT_MODE__MASK; 1937 - } 1938 - #define A2XX_SQ_PROGRAM_CNTL_GEN_INDEX_VTX 0x80000000 1939 - 1940 - #define REG_A2XX_SQ_CONTEXT_MISC 0x00002181 1941 - #define A2XX_SQ_CONTEXT_MISC_INST_PRED_OPTIMIZE 0x00000001 1942 - #define A2XX_SQ_CONTEXT_MISC_SC_OUTPUT_SCREEN_XY 0x00000002 1943 - #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK 0x0000000c 1944 - #define A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT 2 1945 - static inline uint32_t A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL(enum a2xx_sq_sample_cntl val) 1946 - { 1947 - return ((val) << A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__SHIFT) & A2XX_SQ_CONTEXT_MISC_SC_SAMPLE_CNTL__MASK; 1948 - } 1949 - #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK 0x0000ff00 1950 - #define A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT 8 1951 - static inline uint32_t A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS(uint32_t val) 1952 - { 1953 - return ((val) << A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__SHIFT) & A2XX_SQ_CONTEXT_MISC_PARAM_GEN_POS__MASK; 1954 - } 1955 - #define A2XX_SQ_CONTEXT_MISC_PERFCOUNTER_REF 0x00010000 1956 - #define A2XX_SQ_CONTEXT_MISC_YEILD_OPTIMIZE 0x00020000 1957 - #define A2XX_SQ_CONTEXT_MISC_TX_CACHE_SEL 0x00040000 1958 - 1959 - #define REG_A2XX_SQ_INTERPOLATOR_CNTL 0x00002182 1960 - #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK 0x0000ffff 1961 - #define A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT 0 1962 - static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE(uint32_t val) 1963 - { 1964 - return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_PARAM_SHADE__MASK; 1965 - } 1966 - #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK 0xffff0000 1967 - #define A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT 16 1968 - static inline uint32_t A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN(uint32_t val) 1969 - { 1970 - return ((val) << A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__SHIFT) & A2XX_SQ_INTERPOLATOR_CNTL_SAMPLING_PATTERN__MASK; 1971 - } 1972 - 1973 - #define REG_A2XX_SQ_WRAPPING_0 0x00002183 1974 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK 0x0000000f 1975 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT 0 1976 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_0(uint32_t val) 1977 - { 1978 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_0__MASK; 1979 - } 1980 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK 0x000000f0 1981 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT 4 1982 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_1(uint32_t val) 1983 - { 1984 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_1__MASK; 1985 - } 1986 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK 0x00000f00 1987 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT 8 1988 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_2(uint32_t val) 1989 - { 1990 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_2__MASK; 1991 - } 1992 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK 0x0000f000 1993 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT 12 1994 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_3(uint32_t val) 1995 - { 1996 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_3__MASK; 1997 - } 1998 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK 0x000f0000 1999 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT 16 2000 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_4(uint32_t val) 2001 - { 2002 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_4__MASK; 2003 - } 2004 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK 0x00f00000 2005 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT 20 2006 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_5(uint32_t val) 2007 - { 2008 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_5__MASK; 2009 - } 2010 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK 0x0f000000 2011 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT 24 2012 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_6(uint32_t val) 2013 - { 2014 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_6__MASK; 2015 - } 2016 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK 0xf0000000 2017 - #define A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT 28 2018 - static inline uint32_t A2XX_SQ_WRAPPING_0_PARAM_WRAP_7(uint32_t val) 2019 - { 2020 - return ((val) << A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__SHIFT) & A2XX_SQ_WRAPPING_0_PARAM_WRAP_7__MASK; 2021 - } 2022 - 2023 - #define REG_A2XX_SQ_WRAPPING_1 0x00002184 2024 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK 0x0000000f 2025 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT 0 2026 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_8(uint32_t val) 2027 - { 2028 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_8__MASK; 2029 - } 2030 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK 0x000000f0 2031 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT 4 2032 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_9(uint32_t val) 2033 - { 2034 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_9__MASK; 2035 - } 2036 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK 0x00000f00 2037 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT 8 2038 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_10(uint32_t val) 2039 - { 2040 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_10__MASK; 2041 - } 2042 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK 0x0000f000 2043 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT 12 2044 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_11(uint32_t val) 2045 - { 2046 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_11__MASK; 2047 - } 2048 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK 0x000f0000 2049 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT 16 2050 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_12(uint32_t val) 2051 - { 2052 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_12__MASK; 2053 - } 2054 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK 0x00f00000 2055 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT 20 2056 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_13(uint32_t val) 2057 - { 2058 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_13__MASK; 2059 - } 2060 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK 0x0f000000 2061 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT 24 2062 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_14(uint32_t val) 2063 - { 2064 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_14__MASK; 2065 - } 2066 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK 0xf0000000 2067 - #define A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT 28 2068 - static inline uint32_t A2XX_SQ_WRAPPING_1_PARAM_WRAP_15(uint32_t val) 2069 - { 2070 - return ((val) << A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__SHIFT) & A2XX_SQ_WRAPPING_1_PARAM_WRAP_15__MASK; 2071 - } 2072 - 2073 - #define REG_A2XX_SQ_PS_PROGRAM 0x000021f6 2074 - #define A2XX_SQ_PS_PROGRAM_BASE__MASK 0x00000fff 2075 - #define A2XX_SQ_PS_PROGRAM_BASE__SHIFT 0 2076 - static inline uint32_t A2XX_SQ_PS_PROGRAM_BASE(uint32_t val) 2077 - { 2078 - return ((val) << A2XX_SQ_PS_PROGRAM_BASE__SHIFT) & A2XX_SQ_PS_PROGRAM_BASE__MASK; 2079 - } 2080 - #define A2XX_SQ_PS_PROGRAM_SIZE__MASK 0x00fff000 2081 - #define A2XX_SQ_PS_PROGRAM_SIZE__SHIFT 12 2082 - static inline uint32_t A2XX_SQ_PS_PROGRAM_SIZE(uint32_t val) 2083 - { 2084 - return ((val) << A2XX_SQ_PS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_PS_PROGRAM_SIZE__MASK; 2085 - } 2086 - 2087 - #define REG_A2XX_SQ_VS_PROGRAM 0x000021f7 2088 - #define A2XX_SQ_VS_PROGRAM_BASE__MASK 0x00000fff 2089 - #define A2XX_SQ_VS_PROGRAM_BASE__SHIFT 0 2090 - static inline uint32_t A2XX_SQ_VS_PROGRAM_BASE(uint32_t val) 2091 - { 2092 - return ((val) << A2XX_SQ_VS_PROGRAM_BASE__SHIFT) & A2XX_SQ_VS_PROGRAM_BASE__MASK; 2093 - } 2094 - #define A2XX_SQ_VS_PROGRAM_SIZE__MASK 0x00fff000 2095 - #define A2XX_SQ_VS_PROGRAM_SIZE__SHIFT 12 2096 - static inline uint32_t A2XX_SQ_VS_PROGRAM_SIZE(uint32_t val) 2097 - { 2098 - return ((val) << A2XX_SQ_VS_PROGRAM_SIZE__SHIFT) & A2XX_SQ_VS_PROGRAM_SIZE__MASK; 2099 - } 2100 - 2101 - #define REG_A2XX_VGT_EVENT_INITIATOR 0x000021f9 2102 - 2103 - #define REG_A2XX_VGT_DRAW_INITIATOR 0x000021fc 2104 - #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f 2105 - #define A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0 2106 - static inline uint32_t A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val) 2107 - { 2108 - return ((val) << A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK; 2109 - } 2110 - #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0 2111 - #define A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6 2112 - static inline uint32_t A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val) 2113 - { 2114 - return ((val) << A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A2XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK; 2115 - } 2116 - #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600 2117 - #define A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9 2118 - static inline uint32_t A2XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val) 2119 - { 2120 - return ((val) << A2XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A2XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK; 2121 - } 2122 - #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800 2123 - #define A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11 2124 - static inline uint32_t A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val) 2125 - { 2126 - return ((val) << A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A2XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK; 2127 - } 2128 - #define A2XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000 2129 - #define A2XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000 2130 - #define A2XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000 2131 - #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000 2132 - #define A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24 2133 - static inline uint32_t A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val) 2134 - { 2135 - return ((val) << A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A2XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK; 2136 - } 2137 - 2138 - #define REG_A2XX_VGT_IMMED_DATA 0x000021fd 2139 - 2140 - #define REG_A2XX_RB_DEPTHCONTROL 0x00002200 2141 - #define A2XX_RB_DEPTHCONTROL_STENCIL_ENABLE 0x00000001 2142 - #define A2XX_RB_DEPTHCONTROL_Z_ENABLE 0x00000002 2143 - #define A2XX_RB_DEPTHCONTROL_Z_WRITE_ENABLE 0x00000004 2144 - #define A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE 0x00000008 2145 - #define A2XX_RB_DEPTHCONTROL_ZFUNC__MASK 0x00000070 2146 - #define A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT 4 2147 - static inline uint32_t A2XX_RB_DEPTHCONTROL_ZFUNC(enum adreno_compare_func val) 2148 - { 2149 - return ((val) << A2XX_RB_DEPTHCONTROL_ZFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_ZFUNC__MASK; 2150 - } 2151 - #define A2XX_RB_DEPTHCONTROL_BACKFACE_ENABLE 0x00000080 2152 - #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK 0x00000700 2153 - #define A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT 8 2154 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC(enum adreno_compare_func val) 2155 - { 2156 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC__MASK; 2157 - } 2158 - #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK 0x00003800 2159 - #define A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT 11 2160 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL(enum adreno_stencil_op val) 2161 - { 2162 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL__MASK; 2163 - } 2164 - #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK 0x0001c000 2165 - #define A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT 14 2166 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS(enum adreno_stencil_op val) 2167 - { 2168 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS__MASK; 2169 - } 2170 - #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK 0x000e0000 2171 - #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT 17 2172 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL(enum adreno_stencil_op val) 2173 - { 2174 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL__MASK; 2175 - } 2176 - #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK 0x00700000 2177 - #define A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT 20 2178 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF(enum adreno_compare_func val) 2179 - { 2180 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFUNC_BF__MASK; 2181 - } 2182 - #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK 0x03800000 2183 - #define A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT 23 2184 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF(enum adreno_stencil_op val) 2185 - { 2186 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILFAIL_BF__MASK; 2187 - } 2188 - #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK 0x1c000000 2189 - #define A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT 26 2190 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF(enum adreno_stencil_op val) 2191 - { 2192 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZPASS_BF__MASK; 2193 - } 2194 - #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK 0xe0000000 2195 - #define A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT 29 2196 - static inline uint32_t A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF(enum adreno_stencil_op val) 2197 - { 2198 - return ((val) << A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__SHIFT) & A2XX_RB_DEPTHCONTROL_STENCILZFAIL_BF__MASK; 2199 - } 2200 - 2201 - #define REG_A2XX_RB_BLEND_CONTROL 0x00002201 2202 - #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK 0x0000001f 2203 - #define A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT 0 2204 - static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(enum adreno_rb_blend_factor val) 2205 - { 2206 - return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND__MASK; 2207 - } 2208 - #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK 0x000000e0 2209 - #define A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT 5 2210 - static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(enum a2xx_rb_blend_opcode val) 2211 - { 2212 - return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN__MASK; 2213 - } 2214 - #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK 0x00001f00 2215 - #define A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT 8 2216 - static inline uint32_t A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(enum adreno_rb_blend_factor val) 2217 - { 2218 - return ((val) << A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND__MASK; 2219 - } 2220 - #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK 0x001f0000 2221 - #define A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT 16 2222 - static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(enum adreno_rb_blend_factor val) 2223 - { 2224 - return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND__MASK; 2225 - } 2226 - #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK 0x00e00000 2227 - #define A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT 21 2228 - static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(enum a2xx_rb_blend_opcode val) 2229 - { 2230 - return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN__MASK; 2231 - } 2232 - #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK 0x1f000000 2233 - #define A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT 24 2234 - static inline uint32_t A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(enum adreno_rb_blend_factor val) 2235 - { 2236 - return ((val) << A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__SHIFT) & A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND__MASK; 2237 - } 2238 - #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE_ENABLE 0x20000000 2239 - #define A2XX_RB_BLEND_CONTROL_BLEND_FORCE 0x40000000 2240 - 2241 - #define REG_A2XX_RB_COLORCONTROL 0x00002202 2242 - #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK 0x00000007 2243 - #define A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT 0 2244 - static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_FUNC(enum adreno_compare_func val) 2245 - { 2246 - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_FUNC__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_FUNC__MASK; 2247 - } 2248 - #define A2XX_RB_COLORCONTROL_ALPHA_TEST_ENABLE 0x00000008 2249 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_ENABLE 0x00000010 2250 - #define A2XX_RB_COLORCONTROL_BLEND_DISABLE 0x00000020 2251 - #define A2XX_RB_COLORCONTROL_VOB_ENABLE 0x00000040 2252 - #define A2XX_RB_COLORCONTROL_VS_EXPORTS_FOG 0x00000080 2253 - #define A2XX_RB_COLORCONTROL_ROP_CODE__MASK 0x00000f00 2254 - #define A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT 8 2255 - static inline uint32_t A2XX_RB_COLORCONTROL_ROP_CODE(uint32_t val) 2256 - { 2257 - return ((val) << A2XX_RB_COLORCONTROL_ROP_CODE__SHIFT) & A2XX_RB_COLORCONTROL_ROP_CODE__MASK; 2258 - } 2259 - #define A2XX_RB_COLORCONTROL_DITHER_MODE__MASK 0x00003000 2260 - #define A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT 12 2261 - static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_MODE(enum adreno_rb_dither_mode val) 2262 - { 2263 - return ((val) << A2XX_RB_COLORCONTROL_DITHER_MODE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_MODE__MASK; 2264 - } 2265 - #define A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK 0x0000c000 2266 - #define A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT 14 2267 - static inline uint32_t A2XX_RB_COLORCONTROL_DITHER_TYPE(enum a2xx_rb_dither_type val) 2268 - { 2269 - return ((val) << A2XX_RB_COLORCONTROL_DITHER_TYPE__SHIFT) & A2XX_RB_COLORCONTROL_DITHER_TYPE__MASK; 2270 - } 2271 - #define A2XX_RB_COLORCONTROL_PIXEL_FOG 0x00010000 2272 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK 0x03000000 2273 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT 24 2274 - static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0(uint32_t val) 2275 - { 2276 - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET0__MASK; 2277 - } 2278 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK 0x0c000000 2279 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT 26 2280 - static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1(uint32_t val) 2281 - { 2282 - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET1__MASK; 2283 - } 2284 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK 0x30000000 2285 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT 28 2286 - static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2(uint32_t val) 2287 - { 2288 - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET2__MASK; 2289 - } 2290 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK 0xc0000000 2291 - #define A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT 30 2292 - static inline uint32_t A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3(uint32_t val) 2293 - { 2294 - return ((val) << A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__SHIFT) & A2XX_RB_COLORCONTROL_ALPHA_TO_MASK_OFFSET3__MASK; 2295 - } 2296 - 2297 - #define REG_A2XX_VGT_CURRENT_BIN_ID_MAX 0x00002203 2298 - #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK 0x00000007 2299 - #define A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT 0 2300 - static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN(uint32_t val) 2301 - { 2302 - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_COLUMN__MASK; 2303 - } 2304 - #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK 0x00000038 2305 - #define A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT 3 2306 - static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_ROW(uint32_t val) 2307 - { 2308 - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_ROW__MASK; 2309 - } 2310 - #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK 0x000001c0 2311 - #define A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT 6 2312 - static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK(uint32_t val) 2313 - { 2314 - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MAX_GUARD_BAND_MASK__MASK; 2315 - } 2316 - 2317 - #define REG_A2XX_PA_CL_CLIP_CNTL 0x00002204 2318 - #define A2XX_PA_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000 2319 - #define A2XX_PA_CL_CLIP_CNTL_BOUNDARY_EDGE_FLAG_ENA 0x00040000 2320 - #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK 0x00080000 2321 - #define A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT 19 2322 - static inline uint32_t A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF(enum a2xx_dx_clip_space val) 2323 - { 2324 - return ((val) << A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__SHIFT) & A2XX_PA_CL_CLIP_CNTL_DX_CLIP_SPACE_DEF__MASK; 2325 - } 2326 - #define A2XX_PA_CL_CLIP_CNTL_DIS_CLIP_ERR_DETECT 0x00100000 2327 - #define A2XX_PA_CL_CLIP_CNTL_VTX_KILL_OR 0x00200000 2328 - #define A2XX_PA_CL_CLIP_CNTL_XY_NAN_RETAIN 0x00400000 2329 - #define A2XX_PA_CL_CLIP_CNTL_Z_NAN_RETAIN 0x00800000 2330 - #define A2XX_PA_CL_CLIP_CNTL_W_NAN_RETAIN 0x01000000 2331 - 2332 - #define REG_A2XX_PA_SU_SC_MODE_CNTL 0x00002205 2333 - #define A2XX_PA_SU_SC_MODE_CNTL_CULL_FRONT 0x00000001 2334 - #define A2XX_PA_SU_SC_MODE_CNTL_CULL_BACK 0x00000002 2335 - #define A2XX_PA_SU_SC_MODE_CNTL_FACE 0x00000004 2336 - #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK 0x00000018 2337 - #define A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT 3 2338 - static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_POLYMODE(enum a2xx_pa_su_sc_polymode val) 2339 - { 2340 - return ((val) << A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_POLYMODE__MASK; 2341 - } 2342 - #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK 0x000000e0 2343 - #define A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT 5 2344 - static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(enum adreno_pa_su_sc_draw val) 2345 - { 2346 - return ((val) << A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE__MASK; 2347 - } 2348 - #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK 0x00000700 2349 - #define A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT 8 2350 - static inline uint32_t A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(enum adreno_pa_su_sc_draw val) 2351 - { 2352 - return ((val) << A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__SHIFT) & A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE__MASK; 2353 - } 2354 - #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_FRONT_ENABLE 0x00000800 2355 - #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_BACK_ENABLE 0x00001000 2356 - #define A2XX_PA_SU_SC_MODE_CNTL_POLY_OFFSET_PARA_ENABLE 0x00002000 2357 - #define A2XX_PA_SU_SC_MODE_CNTL_MSAA_ENABLE 0x00008000 2358 - #define A2XX_PA_SU_SC_MODE_CNTL_VTX_WINDOW_OFFSET_ENABLE 0x00010000 2359 - #define A2XX_PA_SU_SC_MODE_CNTL_LINE_STIPPLE_ENABLE 0x00040000 2360 - #define A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST 0x00080000 2361 - #define A2XX_PA_SU_SC_MODE_CNTL_PERSP_CORR_DIS 0x00100000 2362 - #define A2XX_PA_SU_SC_MODE_CNTL_MULTI_PRIM_IB_ENA 0x00200000 2363 - #define A2XX_PA_SU_SC_MODE_CNTL_QUAD_ORDER_ENABLE 0x00800000 2364 - #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_ALL_TRI 0x02000000 2365 - #define A2XX_PA_SU_SC_MODE_CNTL_WAIT_RB_IDLE_FIRST_TRI_NEW_STATE 0x04000000 2366 - #define A2XX_PA_SU_SC_MODE_CNTL_CLAMPED_FACENESS 0x10000000 2367 - #define A2XX_PA_SU_SC_MODE_CNTL_ZERO_AREA_FACENESS 0x20000000 2368 - #define A2XX_PA_SU_SC_MODE_CNTL_FACE_KILL_ENABLE 0x40000000 2369 - #define A2XX_PA_SU_SC_MODE_CNTL_FACE_WRITE_ENABLE 0x80000000 2370 - 2371 - #define REG_A2XX_PA_CL_VTE_CNTL 0x00002206 2372 - #define A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA 0x00000001 2373 - #define A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA 0x00000002 2374 - #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA 0x00000004 2375 - #define A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA 0x00000008 2376 - #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_SCALE_ENA 0x00000010 2377 - #define A2XX_PA_CL_VTE_CNTL_VPORT_Z_OFFSET_ENA 0x00000020 2378 - #define A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT 0x00000100 2379 - #define A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT 0x00000200 2380 - #define A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT 0x00000400 2381 - #define A2XX_PA_CL_VTE_CNTL_PERFCOUNTER_REF 0x00000800 2382 - 2383 - #define REG_A2XX_VGT_CURRENT_BIN_ID_MIN 0x00002207 2384 - #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK 0x00000007 2385 - #define A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT 0 2386 - static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN(uint32_t val) 2387 - { 2388 - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_COLUMN__MASK; 2389 - } 2390 - #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK 0x00000038 2391 - #define A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT 3 2392 - static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_ROW(uint32_t val) 2393 - { 2394 - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_ROW__MASK; 2395 - } 2396 - #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK 0x000001c0 2397 - #define A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT 6 2398 - static inline uint32_t A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK(uint32_t val) 2399 - { 2400 - return ((val) << A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__SHIFT) & A2XX_VGT_CURRENT_BIN_ID_MIN_GUARD_BAND_MASK__MASK; 2401 - } 2402 - 2403 - #define REG_A2XX_RB_MODECONTROL 0x00002208 2404 - #define A2XX_RB_MODECONTROL_EDRAM_MODE__MASK 0x00000007 2405 - #define A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT 0 2406 - static inline uint32_t A2XX_RB_MODECONTROL_EDRAM_MODE(enum a2xx_rb_edram_mode val) 2407 - { 2408 - return ((val) << A2XX_RB_MODECONTROL_EDRAM_MODE__SHIFT) & A2XX_RB_MODECONTROL_EDRAM_MODE__MASK; 2409 - } 2410 - 2411 - #define REG_A2XX_A220_RB_LRZ_VSC_CONTROL 0x00002209 2412 - 2413 - #define REG_A2XX_RB_SAMPLE_POS 0x0000220a 2414 - 2415 - #define REG_A2XX_CLEAR_COLOR 0x0000220b 2416 - #define A2XX_CLEAR_COLOR_RED__MASK 0x000000ff 2417 - #define A2XX_CLEAR_COLOR_RED__SHIFT 0 2418 - static inline uint32_t A2XX_CLEAR_COLOR_RED(uint32_t val) 2419 - { 2420 - return ((val) << A2XX_CLEAR_COLOR_RED__SHIFT) & A2XX_CLEAR_COLOR_RED__MASK; 2421 - } 2422 - #define A2XX_CLEAR_COLOR_GREEN__MASK 0x0000ff00 2423 - #define A2XX_CLEAR_COLOR_GREEN__SHIFT 8 2424 - static inline uint32_t A2XX_CLEAR_COLOR_GREEN(uint32_t val) 2425 - { 2426 - return ((val) << A2XX_CLEAR_COLOR_GREEN__SHIFT) & A2XX_CLEAR_COLOR_GREEN__MASK; 2427 - } 2428 - #define A2XX_CLEAR_COLOR_BLUE__MASK 0x00ff0000 2429 - #define A2XX_CLEAR_COLOR_BLUE__SHIFT 16 2430 - static inline uint32_t A2XX_CLEAR_COLOR_BLUE(uint32_t val) 2431 - { 2432 - return ((val) << A2XX_CLEAR_COLOR_BLUE__SHIFT) & A2XX_CLEAR_COLOR_BLUE__MASK; 2433 - } 2434 - #define A2XX_CLEAR_COLOR_ALPHA__MASK 0xff000000 2435 - #define A2XX_CLEAR_COLOR_ALPHA__SHIFT 24 2436 - static inline uint32_t A2XX_CLEAR_COLOR_ALPHA(uint32_t val) 2437 - { 2438 - return ((val) << A2XX_CLEAR_COLOR_ALPHA__SHIFT) & A2XX_CLEAR_COLOR_ALPHA__MASK; 2439 - } 2440 - 2441 - #define REG_A2XX_A220_GRAS_CONTROL 0x00002210 2442 - 2443 - #define REG_A2XX_PA_SU_POINT_SIZE 0x00002280 2444 - #define A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK 0x0000ffff 2445 - #define A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT 0 2446 - static inline uint32_t A2XX_PA_SU_POINT_SIZE_HEIGHT(float val) 2447 - { 2448 - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_HEIGHT__SHIFT) & A2XX_PA_SU_POINT_SIZE_HEIGHT__MASK; 2449 - } 2450 - #define A2XX_PA_SU_POINT_SIZE_WIDTH__MASK 0xffff0000 2451 - #define A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT 16 2452 - static inline uint32_t A2XX_PA_SU_POINT_SIZE_WIDTH(float val) 2453 - { 2454 - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_SIZE_WIDTH__SHIFT) & A2XX_PA_SU_POINT_SIZE_WIDTH__MASK; 2455 - } 2456 - 2457 - #define REG_A2XX_PA_SU_POINT_MINMAX 0x00002281 2458 - #define A2XX_PA_SU_POINT_MINMAX_MIN__MASK 0x0000ffff 2459 - #define A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT 0 2460 - static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MIN(float val) 2461 - { 2462 - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MIN__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MIN__MASK; 2463 - } 2464 - #define A2XX_PA_SU_POINT_MINMAX_MAX__MASK 0xffff0000 2465 - #define A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT 16 2466 - static inline uint32_t A2XX_PA_SU_POINT_MINMAX_MAX(float val) 2467 - { 2468 - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_POINT_MINMAX_MAX__SHIFT) & A2XX_PA_SU_POINT_MINMAX_MAX__MASK; 2469 - } 2470 - 2471 - #define REG_A2XX_PA_SU_LINE_CNTL 0x00002282 2472 - #define A2XX_PA_SU_LINE_CNTL_WIDTH__MASK 0x0000ffff 2473 - #define A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT 0 2474 - static inline uint32_t A2XX_PA_SU_LINE_CNTL_WIDTH(float val) 2475 - { 2476 - return ((((uint32_t)(val * 16.0))) << A2XX_PA_SU_LINE_CNTL_WIDTH__SHIFT) & A2XX_PA_SU_LINE_CNTL_WIDTH__MASK; 2477 - } 2478 - 2479 - #define REG_A2XX_PA_SC_LINE_STIPPLE 0x00002283 2480 - #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK 0x0000ffff 2481 - #define A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT 0 2482 - static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN(uint32_t val) 2483 - { 2484 - return ((val) << A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_LINE_PATTERN__MASK; 2485 - } 2486 - #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK 0x00ff0000 2487 - #define A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT 16 2488 - static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT(uint32_t val) 2489 - { 2490 - return ((val) << A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_REPEAT_COUNT__MASK; 2491 - } 2492 - #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK 0x10000000 2493 - #define A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT 28 2494 - static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER(enum a2xx_pa_sc_pattern_bit_order val) 2495 - { 2496 - return ((val) << A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_PATTERN_BIT_ORDER__MASK; 2497 - } 2498 - #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK 0x60000000 2499 - #define A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT 29 2500 - static inline uint32_t A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL(enum a2xx_pa_sc_auto_reset_cntl val) 2501 - { 2502 - return ((val) << A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__SHIFT) & A2XX_PA_SC_LINE_STIPPLE_AUTO_RESET_CNTL__MASK; 2503 - } 2504 - 2505 - #define REG_A2XX_PA_SC_VIZ_QUERY 0x00002293 2506 - #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ENA 0x00000001 2507 - #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK 0x0000007e 2508 - #define A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT 1 2509 - static inline uint32_t A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID(uint32_t val) 2510 - { 2511 - return ((val) << A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__SHIFT) & A2XX_PA_SC_VIZ_QUERY_VIZ_QUERY_ID__MASK; 2512 - } 2513 - #define A2XX_PA_SC_VIZ_QUERY_KILL_PIX_POST_EARLY_Z 0x00000100 2514 - 2515 - #define REG_A2XX_VGT_ENHANCE 0x00002294 2516 - 2517 - #define REG_A2XX_PA_SC_LINE_CNTL 0x00002300 2518 - #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK 0x0000ffff 2519 - #define A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT 0 2520 - static inline uint32_t A2XX_PA_SC_LINE_CNTL_BRES_CNTL(uint32_t val) 2521 - { 2522 - return ((val) << A2XX_PA_SC_LINE_CNTL_BRES_CNTL__SHIFT) & A2XX_PA_SC_LINE_CNTL_BRES_CNTL__MASK; 2523 - } 2524 - #define A2XX_PA_SC_LINE_CNTL_USE_BRES_CNTL 0x00000100 2525 - #define A2XX_PA_SC_LINE_CNTL_EXPAND_LINE_WIDTH 0x00000200 2526 - #define A2XX_PA_SC_LINE_CNTL_LAST_PIXEL 0x00000400 2527 - 2528 - #define REG_A2XX_PA_SC_AA_CONFIG 0x00002301 2529 - #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK 0x00000007 2530 - #define A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT 0 2531 - static inline uint32_t A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES(uint32_t val) 2532 - { 2533 - return ((val) << A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__SHIFT) & A2XX_PA_SC_AA_CONFIG_MSAA_NUM_SAMPLES__MASK; 2534 - } 2535 - #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK 0x0001e000 2536 - #define A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT 13 2537 - static inline uint32_t A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST(uint32_t val) 2538 - { 2539 - return ((val) << A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__SHIFT) & A2XX_PA_SC_AA_CONFIG_MAX_SAMPLE_DIST__MASK; 2540 - } 2541 - 2542 - #define REG_A2XX_PA_SU_VTX_CNTL 0x00002302 2543 - #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK 0x00000001 2544 - #define A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT 0 2545 - static inline uint32_t A2XX_PA_SU_VTX_CNTL_PIX_CENTER(enum a2xx_pa_pixcenter val) 2546 - { 2547 - return ((val) << A2XX_PA_SU_VTX_CNTL_PIX_CENTER__SHIFT) & A2XX_PA_SU_VTX_CNTL_PIX_CENTER__MASK; 2548 - } 2549 - #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK 0x00000006 2550 - #define A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT 1 2551 - static inline uint32_t A2XX_PA_SU_VTX_CNTL_ROUND_MODE(enum a2xx_pa_roundmode val) 2552 - { 2553 - return ((val) << A2XX_PA_SU_VTX_CNTL_ROUND_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_ROUND_MODE__MASK; 2554 - } 2555 - #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK 0x00000380 2556 - #define A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT 7 2557 - static inline uint32_t A2XX_PA_SU_VTX_CNTL_QUANT_MODE(enum a2xx_pa_quantmode val) 2558 - { 2559 - return ((val) << A2XX_PA_SU_VTX_CNTL_QUANT_MODE__SHIFT) & A2XX_PA_SU_VTX_CNTL_QUANT_MODE__MASK; 2560 - } 2561 - 2562 - #define REG_A2XX_PA_CL_GB_VERT_CLIP_ADJ 0x00002303 2563 - #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK 0xffffffff 2564 - #define A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT 0 2565 - static inline uint32_t A2XX_PA_CL_GB_VERT_CLIP_ADJ(float val) 2566 - { 2567 - return ((fui(val)) << A2XX_PA_CL_GB_VERT_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_CLIP_ADJ__MASK; 2568 - } 2569 - 2570 - #define REG_A2XX_PA_CL_GB_VERT_DISC_ADJ 0x00002304 2571 - #define A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK 0xffffffff 2572 - #define A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT 0 2573 - static inline uint32_t A2XX_PA_CL_GB_VERT_DISC_ADJ(float val) 2574 - { 2575 - return ((fui(val)) << A2XX_PA_CL_GB_VERT_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_VERT_DISC_ADJ__MASK; 2576 - } 2577 - 2578 - #define REG_A2XX_PA_CL_GB_HORZ_CLIP_ADJ 0x00002305 2579 - #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK 0xffffffff 2580 - #define A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT 0 2581 - static inline uint32_t A2XX_PA_CL_GB_HORZ_CLIP_ADJ(float val) 2582 - { 2583 - return ((fui(val)) << A2XX_PA_CL_GB_HORZ_CLIP_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_CLIP_ADJ__MASK; 2584 - } 2585 - 2586 - #define REG_A2XX_PA_CL_GB_HORZ_DISC_ADJ 0x00002306 2587 - #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK 0xffffffff 2588 - #define A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT 0 2589 - static inline uint32_t A2XX_PA_CL_GB_HORZ_DISC_ADJ(float val) 2590 - { 2591 - return ((fui(val)) << A2XX_PA_CL_GB_HORZ_DISC_ADJ__SHIFT) & A2XX_PA_CL_GB_HORZ_DISC_ADJ__MASK; 2592 - } 2593 - 2594 - #define REG_A2XX_SQ_VS_CONST 0x00002307 2595 - #define A2XX_SQ_VS_CONST_BASE__MASK 0x000001ff 2596 - #define A2XX_SQ_VS_CONST_BASE__SHIFT 0 2597 - static inline uint32_t A2XX_SQ_VS_CONST_BASE(uint32_t val) 2598 - { 2599 - return ((val) << A2XX_SQ_VS_CONST_BASE__SHIFT) & A2XX_SQ_VS_CONST_BASE__MASK; 2600 - } 2601 - #define A2XX_SQ_VS_CONST_SIZE__MASK 0x001ff000 2602 - #define A2XX_SQ_VS_CONST_SIZE__SHIFT 12 2603 - static inline uint32_t A2XX_SQ_VS_CONST_SIZE(uint32_t val) 2604 - { 2605 - return ((val) << A2XX_SQ_VS_CONST_SIZE__SHIFT) & A2XX_SQ_VS_CONST_SIZE__MASK; 2606 - } 2607 - 2608 - #define REG_A2XX_SQ_PS_CONST 0x00002308 2609 - #define A2XX_SQ_PS_CONST_BASE__MASK 0x000001ff 2610 - #define A2XX_SQ_PS_CONST_BASE__SHIFT 0 2611 - static inline uint32_t A2XX_SQ_PS_CONST_BASE(uint32_t val) 2612 - { 2613 - return ((val) << A2XX_SQ_PS_CONST_BASE__SHIFT) & A2XX_SQ_PS_CONST_BASE__MASK; 2614 - } 2615 - #define A2XX_SQ_PS_CONST_SIZE__MASK 0x001ff000 2616 - #define A2XX_SQ_PS_CONST_SIZE__SHIFT 12 2617 - static inline uint32_t A2XX_SQ_PS_CONST_SIZE(uint32_t val) 2618 - { 2619 - return ((val) << A2XX_SQ_PS_CONST_SIZE__SHIFT) & A2XX_SQ_PS_CONST_SIZE__MASK; 2620 - } 2621 - 2622 - #define REG_A2XX_SQ_DEBUG_MISC_0 0x00002309 2623 - 2624 - #define REG_A2XX_SQ_DEBUG_MISC_1 0x0000230a 2625 - 2626 - #define REG_A2XX_PA_SC_AA_MASK 0x00002312 2627 - 2628 - #define REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL 0x00002316 2629 - #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK 0x00000007 2630 - #define A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT 0 2631 - static inline uint32_t A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH(uint32_t val) 2632 - { 2633 - return ((val) << A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__SHIFT) & A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL_VTX_REUSE_DEPTH__MASK; 2634 - } 2635 - 2636 - #define REG_A2XX_VGT_OUT_DEALLOC_CNTL 0x00002317 2637 - #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK 0x00000003 2638 - #define A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT 0 2639 - static inline uint32_t A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST(uint32_t val) 2640 - { 2641 - return ((val) << A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__SHIFT) & A2XX_VGT_OUT_DEALLOC_CNTL_DEALLOC_DIST__MASK; 2642 - } 2643 - 2644 - #define REG_A2XX_RB_COPY_CONTROL 0x00002318 2645 - #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK 0x00000007 2646 - #define A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT 0 2647 - static inline uint32_t A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT(enum a2xx_rb_copy_sample_select val) 2648 - { 2649 - return ((val) << A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__SHIFT) & A2XX_RB_COPY_CONTROL_COPY_SAMPLE_SELECT__MASK; 2650 - } 2651 - #define A2XX_RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE 0x00000008 2652 - #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK 0x000000f0 2653 - #define A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT 4 2654 - static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) 2655 - { 2656 - return ((val) << A2XX_RB_COPY_CONTROL_CLEAR_MASK__SHIFT) & A2XX_RB_COPY_CONTROL_CLEAR_MASK__MASK; 2657 - } 2658 - 2659 - #define REG_A2XX_RB_COPY_DEST_BASE 0x00002319 2660 - 2661 - #define REG_A2XX_RB_COPY_DEST_PITCH 0x0000231a 2662 - #define A2XX_RB_COPY_DEST_PITCH__MASK 0xffffffff 2663 - #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 2664 - static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) 2665 - { 2666 - assert(!(val & 0x1f)); 2667 - return (((val >> 5)) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; 2668 - } 2669 - 2670 - #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b 2671 - #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK 0x00000007 2672 - #define A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT 0 2673 - static inline uint32_t A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN(enum adreno_rb_surface_endian val) 2674 - { 2675 - return ((val) << A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__SHIFT) & A2XX_RB_COPY_DEST_INFO_DEST_ENDIAN__MASK; 2676 - } 2677 - #define A2XX_RB_COPY_DEST_INFO_LINEAR 0x00000008 2678 - #define A2XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000f0 2679 - #define A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 4 2680 - static inline uint32_t A2XX_RB_COPY_DEST_INFO_FORMAT(enum a2xx_colorformatx val) 2681 - { 2682 - return ((val) << A2XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A2XX_RB_COPY_DEST_INFO_FORMAT__MASK; 2683 - } 2684 - #define A2XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300 2685 - #define A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8 2686 - static inline uint32_t A2XX_RB_COPY_DEST_INFO_SWAP(uint32_t val) 2687 - { 2688 - return ((val) << A2XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A2XX_RB_COPY_DEST_INFO_SWAP__MASK; 2689 - } 2690 - #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00 2691 - #define A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10 2692 - static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val) 2693 - { 2694 - return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK; 2695 - } 2696 - #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK 0x00003000 2697 - #define A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT 12 2698 - static inline uint32_t A2XX_RB_COPY_DEST_INFO_DITHER_TYPE(enum a2xx_rb_dither_type val) 2699 - { 2700 - return ((val) << A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__SHIFT) & A2XX_RB_COPY_DEST_INFO_DITHER_TYPE__MASK; 2701 - } 2702 - #define A2XX_RB_COPY_DEST_INFO_WRITE_RED 0x00004000 2703 - #define A2XX_RB_COPY_DEST_INFO_WRITE_GREEN 0x00008000 2704 - #define A2XX_RB_COPY_DEST_INFO_WRITE_BLUE 0x00010000 2705 - #define A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA 0x00020000 2706 - 2707 - #define REG_A2XX_RB_COPY_DEST_OFFSET 0x0000231c 2708 - #define A2XX_RB_COPY_DEST_OFFSET_X__MASK 0x00001fff 2709 - #define A2XX_RB_COPY_DEST_OFFSET_X__SHIFT 0 2710 - static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_X(uint32_t val) 2711 - { 2712 - return ((val) << A2XX_RB_COPY_DEST_OFFSET_X__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_X__MASK; 2713 - } 2714 - #define A2XX_RB_COPY_DEST_OFFSET_Y__MASK 0x03ffe000 2715 - #define A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT 13 2716 - static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val) 2717 - { 2718 - return ((val) << A2XX_RB_COPY_DEST_OFFSET_Y__SHIFT) & A2XX_RB_COPY_DEST_OFFSET_Y__MASK; 2719 - } 2720 - 2721 - #define REG_A2XX_RB_DEPTH_CLEAR 0x0000231d 2722 - 2723 - #define REG_A2XX_RB_SAMPLE_COUNT_CTL 0x00002324 2724 - 2725 - #define REG_A2XX_RB_COLOR_DEST_MASK 0x00002326 2726 - 2727 - #define REG_A2XX_A225_GRAS_UCP0X 0x00002340 2728 - 2729 - #define REG_A2XX_A225_GRAS_UCP5W 0x00002357 2730 - 2731 - #define REG_A2XX_A225_GRAS_UCP_ENABLED 0x00002360 2732 - 2733 - #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE 0x00002380 2734 - 2735 - #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET 0x00002381 2736 - 2737 - #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE 0x00002382 2738 - 2739 - #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET 0x00002383 2740 - 2741 - #define REG_A2XX_SQ_CONSTANT_0 0x00004000 2742 - 2743 - #define REG_A2XX_SQ_FETCH_0 0x00004800 2744 - 2745 - #define REG_A2XX_SQ_CF_BOOLEANS 0x00004900 2746 - 2747 - #define REG_A2XX_SQ_CF_LOOP 0x00004908 2748 - 2749 - #define REG_A2XX_COHER_SIZE_PM4 0x00000a29 2750 - 2751 - #define REG_A2XX_COHER_BASE_PM4 0x00000a2a 2752 - 2753 - #define REG_A2XX_COHER_STATUS_PM4 0x00000a2b 2754 - 2755 - #define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT 0x00000c88 2756 - 2757 - #define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT 0x00000c89 2758 - 2759 - #define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT 0x00000c8a 2760 - 2761 - #define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT 0x00000c8b 2762 - 2763 - #define REG_A2XX_PA_SU_PERFCOUNTER0_LOW 0x00000c8c 2764 - 2765 - #define REG_A2XX_PA_SU_PERFCOUNTER0_HI 0x00000c8d 2766 - 2767 - #define REG_A2XX_PA_SU_PERFCOUNTER1_LOW 0x00000c8e 2768 - 2769 - #define REG_A2XX_PA_SU_PERFCOUNTER1_HI 0x00000c8f 2770 - 2771 - #define REG_A2XX_PA_SU_PERFCOUNTER2_LOW 0x00000c90 2772 - 2773 - #define REG_A2XX_PA_SU_PERFCOUNTER2_HI 0x00000c91 2774 - 2775 - #define REG_A2XX_PA_SU_PERFCOUNTER3_LOW 0x00000c92 2776 - 2777 - #define REG_A2XX_PA_SU_PERFCOUNTER3_HI 0x00000c93 2778 - 2779 - #define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT 0x00000c98 2780 - 2781 - #define REG_A2XX_PA_SC_PERFCOUNTER0_LOW 0x00000c99 2782 - 2783 - #define REG_A2XX_PA_SC_PERFCOUNTER0_HI 0x00000c9a 2784 - 2785 - #define REG_A2XX_VGT_PERFCOUNTER0_SELECT 0x00000c48 2786 - 2787 - #define REG_A2XX_VGT_PERFCOUNTER1_SELECT 0x00000c49 2788 - 2789 - #define REG_A2XX_VGT_PERFCOUNTER2_SELECT 0x00000c4a 2790 - 2791 - #define REG_A2XX_VGT_PERFCOUNTER3_SELECT 0x00000c4b 2792 - 2793 - #define REG_A2XX_VGT_PERFCOUNTER0_LOW 0x00000c4c 2794 - 2795 - #define REG_A2XX_VGT_PERFCOUNTER1_LOW 0x00000c4e 2796 - 2797 - #define REG_A2XX_VGT_PERFCOUNTER2_LOW 0x00000c50 2798 - 2799 - #define REG_A2XX_VGT_PERFCOUNTER3_LOW 0x00000c52 2800 - 2801 - #define REG_A2XX_VGT_PERFCOUNTER0_HI 0x00000c4d 2802 - 2803 - #define REG_A2XX_VGT_PERFCOUNTER1_HI 0x00000c4f 2804 - 2805 - #define REG_A2XX_VGT_PERFCOUNTER2_HI 0x00000c51 2806 - 2807 - #define REG_A2XX_VGT_PERFCOUNTER3_HI 0x00000c53 2808 - 2809 - #define REG_A2XX_TCR_PERFCOUNTER0_SELECT 0x00000e05 2810 - 2811 - #define REG_A2XX_TCR_PERFCOUNTER1_SELECT 0x00000e08 2812 - 2813 - #define REG_A2XX_TCR_PERFCOUNTER0_HI 0x00000e06 2814 - 2815 - #define REG_A2XX_TCR_PERFCOUNTER1_HI 0x00000e09 2816 - 2817 - #define REG_A2XX_TCR_PERFCOUNTER0_LOW 0x00000e07 2818 - 2819 - #define REG_A2XX_TCR_PERFCOUNTER1_LOW 0x00000e0a 2820 - 2821 - #define REG_A2XX_TP0_PERFCOUNTER0_SELECT 0x00000e1f 2822 - 2823 - #define REG_A2XX_TP0_PERFCOUNTER0_HI 0x00000e20 2824 - 2825 - #define REG_A2XX_TP0_PERFCOUNTER0_LOW 0x00000e21 2826 - 2827 - #define REG_A2XX_TP0_PERFCOUNTER1_SELECT 0x00000e22 2828 - 2829 - #define REG_A2XX_TP0_PERFCOUNTER1_HI 0x00000e23 2830 - 2831 - #define REG_A2XX_TP0_PERFCOUNTER1_LOW 0x00000e24 2832 - 2833 - #define REG_A2XX_TCM_PERFCOUNTER0_SELECT 0x00000e54 2834 - 2835 - #define REG_A2XX_TCM_PERFCOUNTER1_SELECT 0x00000e57 2836 - 2837 - #define REG_A2XX_TCM_PERFCOUNTER0_HI 0x00000e55 2838 - 2839 - #define REG_A2XX_TCM_PERFCOUNTER1_HI 0x00000e58 2840 - 2841 - #define REG_A2XX_TCM_PERFCOUNTER0_LOW 0x00000e56 2842 - 2843 - #define REG_A2XX_TCM_PERFCOUNTER1_LOW 0x00000e59 2844 - 2845 - #define REG_A2XX_TCF_PERFCOUNTER0_SELECT 0x00000e5a 2846 - 2847 - #define REG_A2XX_TCF_PERFCOUNTER1_SELECT 0x00000e5d 2848 - 2849 - #define REG_A2XX_TCF_PERFCOUNTER2_SELECT 0x00000e60 2850 - 2851 - #define REG_A2XX_TCF_PERFCOUNTER3_SELECT 0x00000e63 2852 - 2853 - #define REG_A2XX_TCF_PERFCOUNTER4_SELECT 0x00000e66 2854 - 2855 - #define REG_A2XX_TCF_PERFCOUNTER5_SELECT 0x00000e69 2856 - 2857 - #define REG_A2XX_TCF_PERFCOUNTER6_SELECT 0x00000e6c 2858 - 2859 - #define REG_A2XX_TCF_PERFCOUNTER7_SELECT 0x00000e6f 2860 - 2861 - #define REG_A2XX_TCF_PERFCOUNTER8_SELECT 0x00000e72 2862 - 2863 - #define REG_A2XX_TCF_PERFCOUNTER9_SELECT 0x00000e75 2864 - 2865 - #define REG_A2XX_TCF_PERFCOUNTER10_SELECT 0x00000e78 2866 - 2867 - #define REG_A2XX_TCF_PERFCOUNTER11_SELECT 0x00000e7b 2868 - 2869 - #define REG_A2XX_TCF_PERFCOUNTER0_HI 0x00000e5b 2870 - 2871 - #define REG_A2XX_TCF_PERFCOUNTER1_HI 0x00000e5e 2872 - 2873 - #define REG_A2XX_TCF_PERFCOUNTER2_HI 0x00000e61 2874 - 2875 - #define REG_A2XX_TCF_PERFCOUNTER3_HI 0x00000e64 2876 - 2877 - #define REG_A2XX_TCF_PERFCOUNTER4_HI 0x00000e67 2878 - 2879 - #define REG_A2XX_TCF_PERFCOUNTER5_HI 0x00000e6a 2880 - 2881 - #define REG_A2XX_TCF_PERFCOUNTER6_HI 0x00000e6d 2882 - 2883 - #define REG_A2XX_TCF_PERFCOUNTER7_HI 0x00000e70 2884 - 2885 - #define REG_A2XX_TCF_PERFCOUNTER8_HI 0x00000e73 2886 - 2887 - #define REG_A2XX_TCF_PERFCOUNTER9_HI 0x00000e76 2888 - 2889 - #define REG_A2XX_TCF_PERFCOUNTER10_HI 0x00000e79 2890 - 2891 - #define REG_A2XX_TCF_PERFCOUNTER11_HI 0x00000e7c 2892 - 2893 - #define REG_A2XX_TCF_PERFCOUNTER0_LOW 0x00000e5c 2894 - 2895 - #define REG_A2XX_TCF_PERFCOUNTER1_LOW 0x00000e5f 2896 - 2897 - #define REG_A2XX_TCF_PERFCOUNTER2_LOW 0x00000e62 2898 - 2899 - #define REG_A2XX_TCF_PERFCOUNTER3_LOW 0x00000e65 2900 - 2901 - #define REG_A2XX_TCF_PERFCOUNTER4_LOW 0x00000e68 2902 - 2903 - #define REG_A2XX_TCF_PERFCOUNTER5_LOW 0x00000e6b 2904 - 2905 - #define REG_A2XX_TCF_PERFCOUNTER6_LOW 0x00000e6e 2906 - 2907 - #define REG_A2XX_TCF_PERFCOUNTER7_LOW 0x00000e71 2908 - 2909 - #define REG_A2XX_TCF_PERFCOUNTER8_LOW 0x00000e74 2910 - 2911 - #define REG_A2XX_TCF_PERFCOUNTER9_LOW 0x00000e77 2912 - 2913 - #define REG_A2XX_TCF_PERFCOUNTER10_LOW 0x00000e7a 2914 - 2915 - #define REG_A2XX_TCF_PERFCOUNTER11_LOW 0x00000e7d 2916 - 2917 - #define REG_A2XX_SQ_PERFCOUNTER0_SELECT 0x00000dc8 2918 - 2919 - #define REG_A2XX_SQ_PERFCOUNTER1_SELECT 0x00000dc9 2920 - 2921 - #define REG_A2XX_SQ_PERFCOUNTER2_SELECT 0x00000dca 2922 - 2923 - #define REG_A2XX_SQ_PERFCOUNTER3_SELECT 0x00000dcb 2924 - 2925 - #define REG_A2XX_SQ_PERFCOUNTER0_LOW 0x00000dcc 2926 - 2927 - #define REG_A2XX_SQ_PERFCOUNTER0_HI 0x00000dcd 2928 - 2929 - #define REG_A2XX_SQ_PERFCOUNTER1_LOW 0x00000dce 2930 - 2931 - #define REG_A2XX_SQ_PERFCOUNTER1_HI 0x00000dcf 2932 - 2933 - #define REG_A2XX_SQ_PERFCOUNTER2_LOW 0x00000dd0 2934 - 2935 - #define REG_A2XX_SQ_PERFCOUNTER2_HI 0x00000dd1 2936 - 2937 - #define REG_A2XX_SQ_PERFCOUNTER3_LOW 0x00000dd2 2938 - 2939 - #define REG_A2XX_SQ_PERFCOUNTER3_HI 0x00000dd3 2940 - 2941 - #define REG_A2XX_SX_PERFCOUNTER0_SELECT 0x00000dd4 2942 - 2943 - #define REG_A2XX_SX_PERFCOUNTER0_LOW 0x00000dd8 2944 - 2945 - #define REG_A2XX_SX_PERFCOUNTER0_HI 0x00000dd9 2946 - 2947 - #define REG_A2XX_MH_PERFCOUNTER0_SELECT 0x00000a46 2948 - 2949 - #define REG_A2XX_MH_PERFCOUNTER1_SELECT 0x00000a4a 2950 - 2951 - #define REG_A2XX_MH_PERFCOUNTER0_CONFIG 0x00000a47 2952 - 2953 - #define REG_A2XX_MH_PERFCOUNTER1_CONFIG 0x00000a4b 2954 - 2955 - #define REG_A2XX_MH_PERFCOUNTER0_LOW 0x00000a48 2956 - 2957 - #define REG_A2XX_MH_PERFCOUNTER1_LOW 0x00000a4c 2958 - 2959 - #define REG_A2XX_MH_PERFCOUNTER0_HI 0x00000a49 2960 - 2961 - #define REG_A2XX_MH_PERFCOUNTER1_HI 0x00000a4d 2962 - 2963 - #define REG_A2XX_RB_PERFCOUNTER0_SELECT 0x00000f04 2964 - 2965 - #define REG_A2XX_RB_PERFCOUNTER1_SELECT 0x00000f05 2966 - 2967 - #define REG_A2XX_RB_PERFCOUNTER2_SELECT 0x00000f06 2968 - 2969 - #define REG_A2XX_RB_PERFCOUNTER3_SELECT 0x00000f07 2970 - 2971 - #define REG_A2XX_RB_PERFCOUNTER0_LOW 0x00000f08 2972 - 2973 - #define REG_A2XX_RB_PERFCOUNTER0_HI 0x00000f09 2974 - 2975 - #define REG_A2XX_RB_PERFCOUNTER1_LOW 0x00000f0a 2976 - 2977 - #define REG_A2XX_RB_PERFCOUNTER1_HI 0x00000f0b 2978 - 2979 - #define REG_A2XX_RB_PERFCOUNTER2_LOW 0x00000f0c 2980 - 2981 - #define REG_A2XX_RB_PERFCOUNTER2_HI 0x00000f0d 2982 - 2983 - #define REG_A2XX_RB_PERFCOUNTER3_LOW 0x00000f0e 2984 - 2985 - #define REG_A2XX_RB_PERFCOUNTER3_HI 0x00000f0f 2986 - 2987 - #define REG_A2XX_SQ_TEX_0 0x00000000 2988 - #define A2XX_SQ_TEX_0_TYPE__MASK 0x00000003 2989 - #define A2XX_SQ_TEX_0_TYPE__SHIFT 0 2990 - static inline uint32_t A2XX_SQ_TEX_0_TYPE(enum sq_tex_type val) 2991 - { 2992 - return ((val) << A2XX_SQ_TEX_0_TYPE__SHIFT) & A2XX_SQ_TEX_0_TYPE__MASK; 2993 - } 2994 - #define A2XX_SQ_TEX_0_SIGN_X__MASK 0x0000000c 2995 - #define A2XX_SQ_TEX_0_SIGN_X__SHIFT 2 2996 - static inline uint32_t A2XX_SQ_TEX_0_SIGN_X(enum sq_tex_sign val) 2997 - { 2998 - return ((val) << A2XX_SQ_TEX_0_SIGN_X__SHIFT) & A2XX_SQ_TEX_0_SIGN_X__MASK; 2999 - } 3000 - #define A2XX_SQ_TEX_0_SIGN_Y__MASK 0x00000030 3001 - #define A2XX_SQ_TEX_0_SIGN_Y__SHIFT 4 3002 - static inline uint32_t A2XX_SQ_TEX_0_SIGN_Y(enum sq_tex_sign val) 3003 - { 3004 - return ((val) << A2XX_SQ_TEX_0_SIGN_Y__SHIFT) & A2XX_SQ_TEX_0_SIGN_Y__MASK; 3005 - } 3006 - #define A2XX_SQ_TEX_0_SIGN_Z__MASK 0x000000c0 3007 - #define A2XX_SQ_TEX_0_SIGN_Z__SHIFT 6 3008 - static inline uint32_t A2XX_SQ_TEX_0_SIGN_Z(enum sq_tex_sign val) 3009 - { 3010 - return ((val) << A2XX_SQ_TEX_0_SIGN_Z__SHIFT) & A2XX_SQ_TEX_0_SIGN_Z__MASK; 3011 - } 3012 - #define A2XX_SQ_TEX_0_SIGN_W__MASK 0x00000300 3013 - #define A2XX_SQ_TEX_0_SIGN_W__SHIFT 8 3014 - static inline uint32_t A2XX_SQ_TEX_0_SIGN_W(enum sq_tex_sign val) 3015 - { 3016 - return ((val) << A2XX_SQ_TEX_0_SIGN_W__SHIFT) & A2XX_SQ_TEX_0_SIGN_W__MASK; 3017 - } 3018 - #define A2XX_SQ_TEX_0_CLAMP_X__MASK 0x00001c00 3019 - #define A2XX_SQ_TEX_0_CLAMP_X__SHIFT 10 3020 - static inline uint32_t A2XX_SQ_TEX_0_CLAMP_X(enum sq_tex_clamp val) 3021 - { 3022 - return ((val) << A2XX_SQ_TEX_0_CLAMP_X__SHIFT) & A2XX_SQ_TEX_0_CLAMP_X__MASK; 3023 - } 3024 - #define A2XX_SQ_TEX_0_CLAMP_Y__MASK 0x0000e000 3025 - #define A2XX_SQ_TEX_0_CLAMP_Y__SHIFT 13 3026 - static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Y(enum sq_tex_clamp val) 3027 - { 3028 - return ((val) << A2XX_SQ_TEX_0_CLAMP_Y__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Y__MASK; 3029 - } 3030 - #define A2XX_SQ_TEX_0_CLAMP_Z__MASK 0x00070000 3031 - #define A2XX_SQ_TEX_0_CLAMP_Z__SHIFT 16 3032 - static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) 3033 - { 3034 - return ((val) << A2XX_SQ_TEX_0_CLAMP_Z__SHIFT) & A2XX_SQ_TEX_0_CLAMP_Z__MASK; 3035 - } 3036 - #define A2XX_SQ_TEX_0_PITCH__MASK 0x7fc00000 3037 - #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 3038 - static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) 3039 - { 3040 - assert(!(val & 0x1f)); 3041 - return (((val >> 5)) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; 3042 - } 3043 - #define A2XX_SQ_TEX_0_TILED 0x80000000 3044 - 3045 - #define REG_A2XX_SQ_TEX_1 0x00000001 3046 - #define A2XX_SQ_TEX_1_FORMAT__MASK 0x0000003f 3047 - #define A2XX_SQ_TEX_1_FORMAT__SHIFT 0 3048 - static inline uint32_t A2XX_SQ_TEX_1_FORMAT(enum a2xx_sq_surfaceformat val) 3049 - { 3050 - return ((val) << A2XX_SQ_TEX_1_FORMAT__SHIFT) & A2XX_SQ_TEX_1_FORMAT__MASK; 3051 - } 3052 - #define A2XX_SQ_TEX_1_ENDIANNESS__MASK 0x000000c0 3053 - #define A2XX_SQ_TEX_1_ENDIANNESS__SHIFT 6 3054 - static inline uint32_t A2XX_SQ_TEX_1_ENDIANNESS(enum sq_tex_endian val) 3055 - { 3056 - return ((val) << A2XX_SQ_TEX_1_ENDIANNESS__SHIFT) & A2XX_SQ_TEX_1_ENDIANNESS__MASK; 3057 - } 3058 - #define A2XX_SQ_TEX_1_REQUEST_SIZE__MASK 0x00000300 3059 - #define A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT 8 3060 - static inline uint32_t A2XX_SQ_TEX_1_REQUEST_SIZE(uint32_t val) 3061 - { 3062 - return ((val) << A2XX_SQ_TEX_1_REQUEST_SIZE__SHIFT) & A2XX_SQ_TEX_1_REQUEST_SIZE__MASK; 3063 - } 3064 - #define A2XX_SQ_TEX_1_STACKED 0x00000400 3065 - #define A2XX_SQ_TEX_1_CLAMP_POLICY__MASK 0x00000800 3066 - #define A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT 11 3067 - static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) 3068 - { 3069 - return ((val) << A2XX_SQ_TEX_1_CLAMP_POLICY__SHIFT) & A2XX_SQ_TEX_1_CLAMP_POLICY__MASK; 3070 - } 3071 - #define A2XX_SQ_TEX_1_BASE_ADDRESS__MASK 0xfffff000 3072 - #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 3073 - static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) 3074 - { 3075 - assert(!(val & 0xfff)); 3076 - return (((val >> 12)) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; 3077 - } 3078 - 3079 - #define REG_A2XX_SQ_TEX_2 0x00000002 3080 - #define A2XX_SQ_TEX_2_WIDTH__MASK 0x00001fff 3081 - #define A2XX_SQ_TEX_2_WIDTH__SHIFT 0 3082 - static inline uint32_t A2XX_SQ_TEX_2_WIDTH(uint32_t val) 3083 - { 3084 - return ((val) << A2XX_SQ_TEX_2_WIDTH__SHIFT) & A2XX_SQ_TEX_2_WIDTH__MASK; 3085 - } 3086 - #define A2XX_SQ_TEX_2_HEIGHT__MASK 0x03ffe000 3087 - #define A2XX_SQ_TEX_2_HEIGHT__SHIFT 13 3088 - static inline uint32_t A2XX_SQ_TEX_2_HEIGHT(uint32_t val) 3089 - { 3090 - return ((val) << A2XX_SQ_TEX_2_HEIGHT__SHIFT) & A2XX_SQ_TEX_2_HEIGHT__MASK; 3091 - } 3092 - #define A2XX_SQ_TEX_2_DEPTH__MASK 0xfc000000 3093 - #define A2XX_SQ_TEX_2_DEPTH__SHIFT 26 3094 - static inline uint32_t A2XX_SQ_TEX_2_DEPTH(uint32_t val) 3095 - { 3096 - return ((val) << A2XX_SQ_TEX_2_DEPTH__SHIFT) & A2XX_SQ_TEX_2_DEPTH__MASK; 3097 - } 3098 - 3099 - #define REG_A2XX_SQ_TEX_3 0x00000003 3100 - #define A2XX_SQ_TEX_3_NUM_FORMAT__MASK 0x00000001 3101 - #define A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT 0 3102 - static inline uint32_t A2XX_SQ_TEX_3_NUM_FORMAT(enum sq_tex_num_format val) 3103 - { 3104 - return ((val) << A2XX_SQ_TEX_3_NUM_FORMAT__SHIFT) & A2XX_SQ_TEX_3_NUM_FORMAT__MASK; 3105 - } 3106 - #define A2XX_SQ_TEX_3_SWIZ_X__MASK 0x0000000e 3107 - #define A2XX_SQ_TEX_3_SWIZ_X__SHIFT 1 3108 - static inline uint32_t A2XX_SQ_TEX_3_SWIZ_X(enum sq_tex_swiz val) 3109 - { 3110 - return ((val) << A2XX_SQ_TEX_3_SWIZ_X__SHIFT) & A2XX_SQ_TEX_3_SWIZ_X__MASK; 3111 - } 3112 - #define A2XX_SQ_TEX_3_SWIZ_Y__MASK 0x00000070 3113 - #define A2XX_SQ_TEX_3_SWIZ_Y__SHIFT 4 3114 - static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Y(enum sq_tex_swiz val) 3115 - { 3116 - return ((val) << A2XX_SQ_TEX_3_SWIZ_Y__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Y__MASK; 3117 - } 3118 - #define A2XX_SQ_TEX_3_SWIZ_Z__MASK 0x00000380 3119 - #define A2XX_SQ_TEX_3_SWIZ_Z__SHIFT 7 3120 - static inline uint32_t A2XX_SQ_TEX_3_SWIZ_Z(enum sq_tex_swiz val) 3121 - { 3122 - return ((val) << A2XX_SQ_TEX_3_SWIZ_Z__SHIFT) & A2XX_SQ_TEX_3_SWIZ_Z__MASK; 3123 - } 3124 - #define A2XX_SQ_TEX_3_SWIZ_W__MASK 0x00001c00 3125 - #define A2XX_SQ_TEX_3_SWIZ_W__SHIFT 10 3126 - static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val) 3127 - { 3128 - return ((val) << A2XX_SQ_TEX_3_SWIZ_W__SHIFT) & A2XX_SQ_TEX_3_SWIZ_W__MASK; 3129 - } 3130 - #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK 0x0007e000 3131 - #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT 13 3132 - static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val) 3133 - { 3134 - return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK; 3135 - } 3136 - #define A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK 0x00180000 3137 - #define A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT 19 3138 - static inline uint32_t A2XX_SQ_TEX_3_XY_MAG_FILTER(enum sq_tex_filter val) 3139 - { 3140 - return ((val) << A2XX_SQ_TEX_3_XY_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MAG_FILTER__MASK; 3141 - } 3142 - #define A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK 0x00600000 3143 - #define A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT 21 3144 - static inline uint32_t A2XX_SQ_TEX_3_XY_MIN_FILTER(enum sq_tex_filter val) 3145 - { 3146 - return ((val) << A2XX_SQ_TEX_3_XY_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_3_XY_MIN_FILTER__MASK; 3147 - } 3148 - #define A2XX_SQ_TEX_3_MIP_FILTER__MASK 0x01800000 3149 - #define A2XX_SQ_TEX_3_MIP_FILTER__SHIFT 23 3150 - static inline uint32_t A2XX_SQ_TEX_3_MIP_FILTER(enum sq_tex_filter val) 3151 - { 3152 - return ((val) << A2XX_SQ_TEX_3_MIP_FILTER__SHIFT) & A2XX_SQ_TEX_3_MIP_FILTER__MASK; 3153 - } 3154 - #define A2XX_SQ_TEX_3_ANISO_FILTER__MASK 0x0e000000 3155 - #define A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT 25 3156 - static inline uint32_t A2XX_SQ_TEX_3_ANISO_FILTER(enum sq_tex_aniso_filter val) 3157 - { 3158 - return ((val) << A2XX_SQ_TEX_3_ANISO_FILTER__SHIFT) & A2XX_SQ_TEX_3_ANISO_FILTER__MASK; 3159 - } 3160 - #define A2XX_SQ_TEX_3_BORDER_SIZE__MASK 0x80000000 3161 - #define A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT 31 3162 - static inline uint32_t A2XX_SQ_TEX_3_BORDER_SIZE(uint32_t val) 3163 - { 3164 - return ((val) << A2XX_SQ_TEX_3_BORDER_SIZE__SHIFT) & A2XX_SQ_TEX_3_BORDER_SIZE__MASK; 3165 - } 3166 - 3167 - #define REG_A2XX_SQ_TEX_4 0x00000004 3168 - #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK 0x00000001 3169 - #define A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT 0 3170 - static inline uint32_t A2XX_SQ_TEX_4_VOL_MAG_FILTER(enum sq_tex_filter val) 3171 - { 3172 - return ((val) << A2XX_SQ_TEX_4_VOL_MAG_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MAG_FILTER__MASK; 3173 - } 3174 - #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK 0x00000002 3175 - #define A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT 1 3176 - static inline uint32_t A2XX_SQ_TEX_4_VOL_MIN_FILTER(enum sq_tex_filter val) 3177 - { 3178 - return ((val) << A2XX_SQ_TEX_4_VOL_MIN_FILTER__SHIFT) & A2XX_SQ_TEX_4_VOL_MIN_FILTER__MASK; 3179 - } 3180 - #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK 0x0000003c 3181 - #define A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT 2 3182 - static inline uint32_t A2XX_SQ_TEX_4_MIP_MIN_LEVEL(uint32_t val) 3183 - { 3184 - return ((val) << A2XX_SQ_TEX_4_MIP_MIN_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MIN_LEVEL__MASK; 3185 - } 3186 - #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK 0x000003c0 3187 - #define A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT 6 3188 - static inline uint32_t A2XX_SQ_TEX_4_MIP_MAX_LEVEL(uint32_t val) 3189 - { 3190 - return ((val) << A2XX_SQ_TEX_4_MIP_MAX_LEVEL__SHIFT) & A2XX_SQ_TEX_4_MIP_MAX_LEVEL__MASK; 3191 - } 3192 - #define A2XX_SQ_TEX_4_MAX_ANISO_WALK 0x00000400 3193 - #define A2XX_SQ_TEX_4_MIN_ANISO_WALK 0x00000800 3194 - #define A2XX_SQ_TEX_4_LOD_BIAS__MASK 0x003ff000 3195 - #define A2XX_SQ_TEX_4_LOD_BIAS__SHIFT 12 3196 - static inline uint32_t A2XX_SQ_TEX_4_LOD_BIAS(float val) 3197 - { 3198 - return ((((int32_t)(val * 32.0))) << A2XX_SQ_TEX_4_LOD_BIAS__SHIFT) & A2XX_SQ_TEX_4_LOD_BIAS__MASK; 3199 - } 3200 - #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK 0x07c00000 3201 - #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT 22 3202 - static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H(uint32_t val) 3203 - { 3204 - return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_H__MASK; 3205 - } 3206 - #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK 0xf8000000 3207 - #define A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT 27 3208 - static inline uint32_t A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V(uint32_t val) 3209 - { 3210 - return ((val) << A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__SHIFT) & A2XX_SQ_TEX_4_GRAD_EXP_ADJUST_V__MASK; 3211 - } 3212 - 3213 - #define REG_A2XX_SQ_TEX_5 0x00000005 3214 - #define A2XX_SQ_TEX_5_BORDER_COLOR__MASK 0x00000003 3215 - #define A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT 0 3216 - static inline uint32_t A2XX_SQ_TEX_5_BORDER_COLOR(enum sq_tex_border_color val) 3217 - { 3218 - return ((val) << A2XX_SQ_TEX_5_BORDER_COLOR__SHIFT) & A2XX_SQ_TEX_5_BORDER_COLOR__MASK; 3219 - } 3220 - #define A2XX_SQ_TEX_5_FORCE_BCW_MAX 0x00000004 3221 - #define A2XX_SQ_TEX_5_TRI_CLAMP__MASK 0x00000018 3222 - #define A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT 3 3223 - static inline uint32_t A2XX_SQ_TEX_5_TRI_CLAMP(uint32_t val) 3224 - { 3225 - return ((val) << A2XX_SQ_TEX_5_TRI_CLAMP__SHIFT) & A2XX_SQ_TEX_5_TRI_CLAMP__MASK; 3226 - } 3227 - #define A2XX_SQ_TEX_5_ANISO_BIAS__MASK 0x000001e0 3228 - #define A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT 5 3229 - static inline uint32_t A2XX_SQ_TEX_5_ANISO_BIAS(float val) 3230 - { 3231 - return ((((int32_t)(val * 1.0))) << A2XX_SQ_TEX_5_ANISO_BIAS__SHIFT) & A2XX_SQ_TEX_5_ANISO_BIAS__MASK; 3232 - } 3233 - #define A2XX_SQ_TEX_5_DIMENSION__MASK 0x00000600 3234 - #define A2XX_SQ_TEX_5_DIMENSION__SHIFT 9 3235 - static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) 3236 - { 3237 - return ((val) << A2XX_SQ_TEX_5_DIMENSION__SHIFT) & A2XX_SQ_TEX_5_DIMENSION__MASK; 3238 - } 3239 - #define A2XX_SQ_TEX_5_PACKED_MIPS 0x00000800 3240 - #define A2XX_SQ_TEX_5_MIP_ADDRESS__MASK 0xfffff000 3241 - #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 3242 - static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) 3243 - { 3244 - assert(!(val & 0xfff)); 3245 - return (((val >> 12)) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; 3246 - } 3247 - 3248 - #ifdef __cplusplus 3249 - #endif 3250 - 3251 - #endif /* A2XX_XML */

-539

drivers/gpu/drm/msm/adreno/adreno_common.xml.h

··· 1 - #ifndef ADRENO_COMMON_XML 2 - #define ADRENO_COMMON_XML 3 - 4 - /* Autogenerated file, DO NOT EDIT manually! 5 - 6 - This file was generated by the rules-ng-ng gen_header.py tool in this git repository: 7 - http://gitlab.freedesktop.org/mesa/mesa/ 8 - git clone https://gitlab.freedesktop.org/mesa/mesa.git 9 - 10 - The rules-ng-ng source files this header was generated from are: 11 - 12 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) 13 - */ 14 - 15 - #ifdef __KERNEL__ 16 - #include <linux/bug.h> 17 - #define assert(x) BUG_ON(!(x)) 18 - #else 19 - #include <assert.h> 20 - #endif 21 - 22 - #ifdef __cplusplus 23 - #define __struct_cast(X) 24 - #else 25 - #define __struct_cast(X) (struct X) 26 - #endif 27 - 28 - enum chip { 29 - A2XX = 2, 30 - A3XX = 3, 31 - A4XX = 4, 32 - A5XX = 5, 33 - A6XX = 6, 34 - A7XX = 7, 35 - }; 36 - 37 - enum adreno_pa_su_sc_draw { 38 - PC_DRAW_POINTS = 0, 39 - PC_DRAW_LINES = 1, 40 - PC_DRAW_TRIANGLES = 2, 41 - }; 42 - 43 - enum adreno_compare_func { 44 - FUNC_NEVER = 0, 45 - FUNC_LESS = 1, 46 - FUNC_EQUAL = 2, 47 - FUNC_LEQUAL = 3, 48 - FUNC_GREATER = 4, 49 - FUNC_NOTEQUAL = 5, 50 - FUNC_GEQUAL = 6, 51 - FUNC_ALWAYS = 7, 52 - }; 53 - 54 - enum adreno_stencil_op { 55 - STENCIL_KEEP = 0, 56 - STENCIL_ZERO = 1, 57 - STENCIL_REPLACE = 2, 58 - STENCIL_INCR_CLAMP = 3, 59 - STENCIL_DECR_CLAMP = 4, 60 - STENCIL_INVERT = 5, 61 - STENCIL_INCR_WRAP = 6, 62 - STENCIL_DECR_WRAP = 7, 63 - }; 64 - 65 - enum adreno_rb_blend_factor { 66 - FACTOR_ZERO = 0, 67 - FACTOR_ONE = 1, 68 - FACTOR_SRC_COLOR = 4, 69 - FACTOR_ONE_MINUS_SRC_COLOR = 5, 70 - FACTOR_SRC_ALPHA = 6, 71 - FACTOR_ONE_MINUS_SRC_ALPHA = 7, 72 - FACTOR_DST_COLOR = 8, 73 - FACTOR_ONE_MINUS_DST_COLOR = 9, 74 - FACTOR_DST_ALPHA = 10, 75 - FACTOR_ONE_MINUS_DST_ALPHA = 11, 76 - FACTOR_CONSTANT_COLOR = 12, 77 - FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 78 - FACTOR_CONSTANT_ALPHA = 14, 79 - FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 80 - FACTOR_SRC_ALPHA_SATURATE = 16, 81 - FACTOR_SRC1_COLOR = 20, 82 - FACTOR_ONE_MINUS_SRC1_COLOR = 21, 83 - FACTOR_SRC1_ALPHA = 22, 84 - FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 85 - }; 86 - 87 - enum adreno_rb_surface_endian { 88 - ENDIAN_NONE = 0, 89 - ENDIAN_8IN16 = 1, 90 - ENDIAN_8IN32 = 2, 91 - ENDIAN_16IN32 = 3, 92 - ENDIAN_8IN64 = 4, 93 - ENDIAN_8IN128 = 5, 94 - }; 95 - 96 - enum adreno_rb_dither_mode { 97 - DITHER_DISABLE = 0, 98 - DITHER_ALWAYS = 1, 99 - DITHER_IF_ALPHA_OFF = 2, 100 - }; 101 - 102 - enum adreno_rb_depth_format { 103 - DEPTHX_16 = 0, 104 - DEPTHX_24_8 = 1, 105 - DEPTHX_32 = 2, 106 - }; 107 - 108 - enum adreno_rb_copy_control_mode { 109 - RB_COPY_RESOLVE = 1, 110 - RB_COPY_CLEAR = 2, 111 - RB_COPY_DEPTH_STENCIL = 5, 112 - }; 113 - 114 - enum a3xx_rop_code { 115 - ROP_CLEAR = 0, 116 - ROP_NOR = 1, 117 - ROP_AND_INVERTED = 2, 118 - ROP_COPY_INVERTED = 3, 119 - ROP_AND_REVERSE = 4, 120 - ROP_INVERT = 5, 121 - ROP_XOR = 6, 122 - ROP_NAND = 7, 123 - ROP_AND = 8, 124 - ROP_EQUIV = 9, 125 - ROP_NOOP = 10, 126 - ROP_OR_INVERTED = 11, 127 - ROP_COPY = 12, 128 - ROP_OR_REVERSE = 13, 129 - ROP_OR = 14, 130 - ROP_SET = 15, 131 - }; 132 - 133 - enum a3xx_render_mode { 134 - RB_RENDERING_PASS = 0, 135 - RB_TILING_PASS = 1, 136 - RB_RESOLVE_PASS = 2, 137 - RB_COMPUTE_PASS = 3, 138 - }; 139 - 140 - enum a3xx_msaa_samples { 141 - MSAA_ONE = 0, 142 - MSAA_TWO = 1, 143 - MSAA_FOUR = 2, 144 - MSAA_EIGHT = 3, 145 - }; 146 - 147 - enum a3xx_threadmode { 148 - MULTI = 0, 149 - SINGLE = 1, 150 - }; 151 - 152 - enum a3xx_instrbuffermode { 153 - CACHE = 0, 154 - BUFFER = 1, 155 - }; 156 - 157 - enum a3xx_threadsize { 158 - TWO_QUADS = 0, 159 - FOUR_QUADS = 1, 160 - }; 161 - 162 - enum a3xx_color_swap { 163 - WZYX = 0, 164 - WXYZ = 1, 165 - ZYXW = 2, 166 - XYZW = 3, 167 - }; 168 - 169 - enum a3xx_rb_blend_opcode { 170 - BLEND_DST_PLUS_SRC = 0, 171 - BLEND_SRC_MINUS_DST = 1, 172 - BLEND_DST_MINUS_SRC = 2, 173 - BLEND_MIN_DST_SRC = 3, 174 - BLEND_MAX_DST_SRC = 4, 175 - }; 176 - 177 - enum a4xx_tess_spacing { 178 - EQUAL_SPACING = 0, 179 - ODD_SPACING = 2, 180 - EVEN_SPACING = 3, 181 - }; 182 - 183 - enum a5xx_address_mode { 184 - ADDR_32B = 0, 185 - ADDR_64B = 1, 186 - }; 187 - 188 - enum a5xx_line_mode { 189 - BRESENHAM = 0, 190 - RECTANGULAR = 1, 191 - }; 192 - 193 - enum a6xx_tex_prefetch_cmd { 194 - TEX_PREFETCH_UNK0 = 0, 195 - TEX_PREFETCH_SAM = 1, 196 - TEX_PREFETCH_GATHER4R = 2, 197 - TEX_PREFETCH_GATHER4G = 3, 198 - TEX_PREFETCH_GATHER4B = 4, 199 - TEX_PREFETCH_GATHER4A = 5, 200 - TEX_PREFETCH_UNK6 = 6, 201 - TEX_PREFETCH_UNK7 = 7, 202 - }; 203 - 204 - #define REG_AXXX_CP_RB_BASE 0x000001c0 205 - 206 - #define REG_AXXX_CP_RB_CNTL 0x000001c1 207 - #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 208 - #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 209 - static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 210 - { 211 - return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 212 - } 213 - #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 214 - #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 215 - static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 216 - { 217 - return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 218 - } 219 - #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 220 - #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 221 - static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 222 - { 223 - return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 224 - } 225 - #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 226 - #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 227 - #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 228 - 229 - #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 230 - #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 231 - #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 232 - static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 233 - { 234 - return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 235 - } 236 - #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 237 - #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 238 - static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 239 - { 240 - assert(!(val & 0x3)); 241 - return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 242 - } 243 - 244 - #define REG_AXXX_CP_RB_RPTR 0x000001c4 245 - 246 - #define REG_AXXX_CP_RB_WPTR 0x000001c5 247 - 248 - #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 249 - 250 - #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 251 - 252 - #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 253 - 254 - #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 255 - #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 256 - #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 257 - static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 258 - { 259 - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 260 - } 261 - #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 262 - #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 263 - static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 264 - { 265 - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 266 - } 267 - #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 268 - #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 269 - static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 270 - { 271 - return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 272 - } 273 - 274 - #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 275 - #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 276 - #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 277 - static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 278 - { 279 - return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 280 - } 281 - #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 282 - #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 283 - static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 284 - { 285 - return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 286 - } 287 - 288 - #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 289 - #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 290 - #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 291 - static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 292 - { 293 - return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 294 - } 295 - #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 296 - #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 297 - static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 298 - { 299 - return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 300 - } 301 - #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 302 - #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 303 - static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 304 - { 305 - return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 306 - } 307 - 308 - #define REG_AXXX_CP_STQ_AVAIL 0x000001d8 309 - #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 310 - #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 311 - static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 312 - { 313 - return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 314 - } 315 - 316 - #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 317 - #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 318 - #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 319 - static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 320 - { 321 - return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 322 - } 323 - 324 - #define REG_AXXX_SCRATCH_UMSK 0x000001dc 325 - #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 326 - #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 327 - static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 328 - { 329 - return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 330 - } 331 - #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 332 - #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 333 - static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 334 - { 335 - return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 336 - } 337 - 338 - #define REG_AXXX_SCRATCH_ADDR 0x000001dd 339 - 340 - #define REG_AXXX_CP_ME_RDADDR 0x000001ea 341 - 342 - #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 343 - 344 - #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 345 - 346 - #define REG_AXXX_CP_INT_CNTL 0x000001f2 347 - #define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 348 - #define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 349 - #define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 350 - #define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 351 - #define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 352 - #define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 353 - #define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 354 - #define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 355 - #define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 356 - 357 - #define REG_AXXX_CP_INT_STATUS 0x000001f3 358 - 359 - #define REG_AXXX_CP_INT_ACK 0x000001f4 360 - 361 - #define REG_AXXX_CP_ME_CNTL 0x000001f6 362 - #define AXXX_CP_ME_CNTL_BUSY 0x20000000 363 - #define AXXX_CP_ME_CNTL_HALT 0x10000000 364 - 365 - #define REG_AXXX_CP_ME_STATUS 0x000001f7 366 - 367 - #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 368 - 369 - #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 370 - 371 - #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 372 - 373 - #define REG_AXXX_CP_DEBUG 0x000001fc 374 - #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 375 - #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 376 - #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 377 - #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 378 - #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 379 - #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 380 - #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 381 - #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 382 - 383 - #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 384 - #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 385 - #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 386 - static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 387 - { 388 - return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 389 - } 390 - #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 391 - #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 392 - static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 393 - { 394 - return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 395 - } 396 - 397 - #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 398 - #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 399 - #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 400 - static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 401 - { 402 - return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 403 - } 404 - #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 405 - #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 406 - static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 407 - { 408 - return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 409 - } 410 - 411 - #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 412 - #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 413 - #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 414 - static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 415 - { 416 - return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 417 - } 418 - #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 419 - #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 420 - static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 421 - { 422 - return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 423 - } 424 - 425 - #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 426 - 427 - #define REG_AXXX_CP_STQ_ST_STAT 0x00000443 428 - 429 - #define REG_AXXX_CP_ST_BASE 0x0000044d 430 - 431 - #define REG_AXXX_CP_ST_BUFSZ 0x0000044e 432 - 433 - #define REG_AXXX_CP_MEQ_STAT 0x0000044f 434 - 435 - #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 436 - 437 - #define REG_AXXX_CP_BIN_MASK_LO 0x00000454 438 - 439 - #define REG_AXXX_CP_BIN_MASK_HI 0x00000455 440 - 441 - #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 442 - 443 - #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 444 - 445 - #define REG_AXXX_CP_IB1_BASE 0x00000458 446 - 447 - #define REG_AXXX_CP_IB1_BUFSZ 0x00000459 448 - 449 - #define REG_AXXX_CP_IB2_BASE 0x0000045a 450 - 451 - #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 452 - 453 - #define REG_AXXX_CP_STAT 0x0000047f 454 - #define AXXX_CP_STAT_CP_BUSY 0x80000000 455 - #define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 456 - #define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 457 - #define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 458 - #define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 459 - #define AXXX_CP_STAT_ME_BUSY 0x04000000 460 - #define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 461 - #define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 462 - #define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 463 - #define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 464 - #define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 465 - #define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 466 - #define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 467 - #define AXXX_CP_STAT_PFP_BUSY 0x00020000 468 - #define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 469 - #define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 470 - #define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 471 - #define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 472 - #define AXXX_CP_STAT_CSF_BUSY 0x00000400 473 - #define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 474 - #define AXXX_CP_STAT_EVENT_BUSY 0x00000100 475 - #define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 476 - #define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 477 - #define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 478 - #define AXXX_CP_STAT_RCIU_BUSY 0x00000010 479 - #define AXXX_CP_STAT_RBIU_BUSY 0x00000008 480 - #define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 481 - #define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 482 - #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 483 - 484 - #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 485 - 486 - #define REG_AXXX_CP_SCRATCH_REG1 0x00000579 487 - 488 - #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 489 - 490 - #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 491 - 492 - #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 493 - 494 - #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 495 - 496 - #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 497 - 498 - #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 499 - 500 - #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 501 - 502 - #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 503 - 504 - #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 505 - 506 - #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 507 - 508 - #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 509 - 510 - #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 511 - 512 - #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 513 - 514 - #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 515 - 516 - #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 517 - 518 - #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 519 - 520 - #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 521 - 522 - #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 523 - 524 - #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 525 - 526 - #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 527 - 528 - #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 529 - 530 - #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 531 - 532 - #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 533 - 534 - #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 535 - 536 - #ifdef __cplusplus 537 - #endif 538 - 539 - #endif /* ADRENO_COMMON_XML */

-2803

drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h

··· 1 - #ifndef ADRENO_PM4_XML 2 - #define ADRENO_PM4_XML 3 - 4 - /* Autogenerated file, DO NOT EDIT manually! 5 - 6 - This file was generated by the rules-ng-ng gen_header.py tool in this git repository: 7 - http://gitlab.freedesktop.org/mesa/mesa/ 8 - git clone https://gitlab.freedesktop.org/mesa/mesa.git 9 - 10 - The rules-ng-ng source files this header was generated from are: 11 - 12 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024) 13 - - /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) 14 - */ 15 - 16 - #ifdef __KERNEL__ 17 - #include <linux/bug.h> 18 - #define assert(x) BUG_ON(!(x)) 19 - #else 20 - #include <assert.h> 21 - #endif 22 - 23 - #ifdef __cplusplus 24 - #define __struct_cast(X) 25 - #else 26 - #define __struct_cast(X) (struct X) 27 - #endif 28 - 29 - enum vgt_event_type { 30 - VS_DEALLOC = 0, 31 - PS_DEALLOC = 1, 32 - VS_DONE_TS = 2, 33 - PS_DONE_TS = 3, 34 - CACHE_FLUSH_TS = 4, 35 - CONTEXT_DONE = 5, 36 - CACHE_FLUSH = 6, 37 - VIZQUERY_START = 7, 38 - HLSQ_FLUSH = 7, 39 - VIZQUERY_END = 8, 40 - SC_WAIT_WC = 9, 41 - WRITE_PRIMITIVE_COUNTS = 9, 42 - START_PRIMITIVE_CTRS = 11, 43 - STOP_PRIMITIVE_CTRS = 12, 44 - RST_PIX_CNT = 13, 45 - RST_VTX_CNT = 14, 46 - TILE_FLUSH = 15, 47 - STAT_EVENT = 16, 48 - CACHE_FLUSH_AND_INV_TS_EVENT = 20, 49 - ZPASS_DONE = 21, 50 - CACHE_FLUSH_AND_INV_EVENT = 22, 51 - RB_DONE_TS = 22, 52 - PERFCOUNTER_START = 23, 53 - PERFCOUNTER_STOP = 24, 54 - VS_FETCH_DONE = 27, 55 - FACENESS_FLUSH = 28, 56 - WT_DONE_TS = 8, 57 - START_FRAGMENT_CTRS = 13, 58 - STOP_FRAGMENT_CTRS = 14, 59 - START_COMPUTE_CTRS = 15, 60 - STOP_COMPUTE_CTRS = 16, 61 - FLUSH_SO_0 = 17, 62 - FLUSH_SO_1 = 18, 63 - FLUSH_SO_2 = 19, 64 - FLUSH_SO_3 = 20, 65 - PC_CCU_INVALIDATE_DEPTH = 24, 66 - PC_CCU_INVALIDATE_COLOR = 25, 67 - PC_CCU_RESOLVE_TS = 26, 68 - PC_CCU_FLUSH_DEPTH_TS = 28, 69 - PC_CCU_FLUSH_COLOR_TS = 29, 70 - BLIT = 30, 71 - LRZ_CLEAR = 37, 72 - LRZ_FLUSH = 38, 73 - BLIT_OP_FILL_2D = 39, 74 - BLIT_OP_COPY_2D = 40, 75 - UNK_40 = 40, 76 - BLIT_OP_SCALE_2D = 42, 77 - CONTEXT_DONE_2D = 43, 78 - UNK_2C = 44, 79 - UNK_2D = 45, 80 - CACHE_INVALIDATE = 49, 81 - LABEL = 63, 82 - DUMMY_EVENT = 1, 83 - CCU_INVALIDATE_DEPTH = 24, 84 - CCU_INVALIDATE_COLOR = 25, 85 - CCU_RESOLVE_CLEAN = 26, 86 - CCU_FLUSH_DEPTH = 28, 87 - CCU_FLUSH_COLOR = 29, 88 - CCU_RESOLVE = 30, 89 - CCU_END_RESOLVE_GROUP = 31, 90 - CCU_CLEAN_DEPTH = 32, 91 - CCU_CLEAN_COLOR = 33, 92 - CACHE_RESET = 48, 93 - CACHE_CLEAN = 49, 94 - CACHE_FLUSH7 = 50, 95 - CACHE_INVALIDATE7 = 51, 96 - }; 97 - 98 - enum pc_di_primtype { 99 - DI_PT_NONE = 0, 100 - DI_PT_POINTLIST_PSIZE = 1, 101 - DI_PT_LINELIST = 2, 102 - DI_PT_LINESTRIP = 3, 103 - DI_PT_TRILIST = 4, 104 - DI_PT_TRIFAN = 5, 105 - DI_PT_TRISTRIP = 6, 106 - DI_PT_LINELOOP = 7, 107 - DI_PT_RECTLIST = 8, 108 - DI_PT_POINTLIST = 9, 109 - DI_PT_LINE_ADJ = 10, 110 - DI_PT_LINESTRIP_ADJ = 11, 111 - DI_PT_TRI_ADJ = 12, 112 - DI_PT_TRISTRIP_ADJ = 13, 113 - DI_PT_PATCHES0 = 31, 114 - DI_PT_PATCHES1 = 32, 115 - DI_PT_PATCHES2 = 33, 116 - DI_PT_PATCHES3 = 34, 117 - DI_PT_PATCHES4 = 35, 118 - DI_PT_PATCHES5 = 36, 119 - DI_PT_PATCHES6 = 37, 120 - DI_PT_PATCHES7 = 38, 121 - DI_PT_PATCHES8 = 39, 122 - DI_PT_PATCHES9 = 40, 123 - DI_PT_PATCHES10 = 41, 124 - DI_PT_PATCHES11 = 42, 125 - DI_PT_PATCHES12 = 43, 126 - DI_PT_PATCHES13 = 44, 127 - DI_PT_PATCHES14 = 45, 128 - DI_PT_PATCHES15 = 46, 129 - DI_PT_PATCHES16 = 47, 130 - DI_PT_PATCHES17 = 48, 131 - DI_PT_PATCHES18 = 49, 132 - DI_PT_PATCHES19 = 50, 133 - DI_PT_PATCHES20 = 51, 134 - DI_PT_PATCHES21 = 52, 135 - DI_PT_PATCHES22 = 53, 136 - DI_PT_PATCHES23 = 54, 137 - DI_PT_PATCHES24 = 55, 138 - DI_PT_PATCHES25 = 56, 139 - DI_PT_PATCHES26 = 57, 140 - DI_PT_PATCHES27 = 58, 141 - DI_PT_PATCHES28 = 59, 142 - DI_PT_PATCHES29 = 60, 143 - DI_PT_PATCHES30 = 61, 144 - DI_PT_PATCHES31 = 62, 145 - }; 146 - 147 - enum pc_di_src_sel { 148 - DI_SRC_SEL_DMA = 0, 149 - DI_SRC_SEL_IMMEDIATE = 1, 150 - DI_SRC_SEL_AUTO_INDEX = 2, 151 - DI_SRC_SEL_AUTO_XFB = 3, 152 - }; 153 - 154 - enum pc_di_face_cull_sel { 155 - DI_FACE_CULL_NONE = 0, 156 - DI_FACE_CULL_FETCH = 1, 157 - DI_FACE_BACKFACE_CULL = 2, 158 - DI_FACE_FRONTFACE_CULL = 3, 159 - }; 160 - 161 - enum pc_di_index_size { 162 - INDEX_SIZE_IGN = 0, 163 - INDEX_SIZE_16_BIT = 0, 164 - INDEX_SIZE_32_BIT = 1, 165 - INDEX_SIZE_8_BIT = 2, 166 - INDEX_SIZE_INVALID = 0, 167 - }; 168 - 169 - enum pc_di_vis_cull_mode { 170 - IGNORE_VISIBILITY = 0, 171 - USE_VISIBILITY = 1, 172 - }; 173 - 174 - enum adreno_pm4_packet_type { 175 - CP_TYPE0_PKT = 0x00000000, 176 - CP_TYPE1_PKT = 0x40000000, 177 - CP_TYPE2_PKT = 0x80000000, 178 - CP_TYPE3_PKT = 0xc0000000, 179 - CP_TYPE4_PKT = 0x40000000, 180 - CP_TYPE7_PKT = 0x70000000, 181 - }; 182 - 183 - enum adreno_pm4_type3_packets { 184 - CP_ME_INIT = 72, 185 - CP_NOP = 16, 186 - CP_PREEMPT_ENABLE = 28, 187 - CP_PREEMPT_TOKEN = 30, 188 - CP_INDIRECT_BUFFER = 63, 189 - CP_INDIRECT_BUFFER_CHAIN = 87, 190 - CP_INDIRECT_BUFFER_PFD = 55, 191 - CP_WAIT_FOR_IDLE = 38, 192 - CP_WAIT_REG_MEM = 60, 193 - CP_WAIT_REG_EQ = 82, 194 - CP_WAIT_REG_GTE = 83, 195 - CP_WAIT_UNTIL_READ = 92, 196 - CP_WAIT_IB_PFD_COMPLETE = 93, 197 - CP_REG_RMW = 33, 198 - CP_SET_BIN_DATA = 47, 199 - CP_SET_BIN_DATA5 = 47, 200 - CP_REG_TO_MEM = 62, 201 - CP_MEM_WRITE = 61, 202 - CP_MEM_WRITE_CNTR = 79, 203 - CP_COND_EXEC = 68, 204 - CP_COND_WRITE = 69, 205 - CP_COND_WRITE5 = 69, 206 - CP_EVENT_WRITE = 70, 207 - CP_EVENT_WRITE7 = 70, 208 - CP_EVENT_WRITE_SHD = 88, 209 - CP_EVENT_WRITE_CFL = 89, 210 - CP_EVENT_WRITE_ZPD = 91, 211 - CP_RUN_OPENCL = 49, 212 - CP_DRAW_INDX = 34, 213 - CP_DRAW_INDX_2 = 54, 214 - CP_DRAW_INDX_BIN = 52, 215 - CP_DRAW_INDX_2_BIN = 53, 216 - CP_VIZ_QUERY = 35, 217 - CP_SET_STATE = 37, 218 - CP_SET_CONSTANT = 45, 219 - CP_IM_LOAD = 39, 220 - CP_IM_LOAD_IMMEDIATE = 43, 221 - CP_LOAD_CONSTANT_CONTEXT = 46, 222 - CP_INVALIDATE_STATE = 59, 223 - CP_SET_SHADER_BASES = 74, 224 - CP_SET_BIN_MASK = 80, 225 - CP_SET_BIN_SELECT = 81, 226 - CP_CONTEXT_UPDATE = 94, 227 - CP_INTERRUPT = 64, 228 - CP_IM_STORE = 44, 229 - CP_SET_DRAW_INIT_FLAGS = 75, 230 - CP_SET_PROTECTED_MODE = 95, 231 - CP_BOOTSTRAP_UCODE = 111, 232 - CP_LOAD_STATE = 48, 233 - CP_LOAD_STATE4 = 48, 234 - CP_COND_INDIRECT_BUFFER_PFE = 58, 235 - CP_COND_INDIRECT_BUFFER_PFD = 50, 236 - CP_INDIRECT_BUFFER_PFE = 63, 237 - CP_SET_BIN = 76, 238 - CP_TEST_TWO_MEMS = 113, 239 - CP_REG_WR_NO_CTXT = 120, 240 - CP_RECORD_PFP_TIMESTAMP = 17, 241 - CP_SET_SECURE_MODE = 102, 242 - CP_WAIT_FOR_ME = 19, 243 - CP_SET_DRAW_STATE = 67, 244 - CP_DRAW_INDX_OFFSET = 56, 245 - CP_DRAW_INDIRECT = 40, 246 - CP_DRAW_INDX_INDIRECT = 41, 247 - CP_DRAW_INDIRECT_MULTI = 42, 248 - CP_DRAW_AUTO = 36, 249 - CP_DRAW_PRED_ENABLE_GLOBAL = 25, 250 - CP_DRAW_PRED_ENABLE_LOCAL = 26, 251 - CP_DRAW_PRED_SET = 78, 252 - CP_WIDE_REG_WRITE = 116, 253 - CP_SCRATCH_TO_REG = 77, 254 - CP_REG_TO_SCRATCH = 74, 255 - CP_WAIT_MEM_WRITES = 18, 256 - CP_COND_REG_EXEC = 71, 257 - CP_MEM_TO_REG = 66, 258 - CP_EXEC_CS_INDIRECT = 65, 259 - CP_EXEC_CS = 51, 260 - CP_PERFCOUNTER_ACTION = 80, 261 - CP_SMMU_TABLE_UPDATE = 83, 262 - CP_SET_MARKER = 101, 263 - CP_SET_PSEUDO_REG = 86, 264 - CP_CONTEXT_REG_BUNCH = 92, 265 - CP_YIELD_ENABLE = 28, 266 - CP_SKIP_IB2_ENABLE_GLOBAL = 29, 267 - CP_SKIP_IB2_ENABLE_LOCAL = 35, 268 - CP_SET_SUBDRAW_SIZE = 53, 269 - CP_WHERE_AM_I = 98, 270 - CP_SET_VISIBILITY_OVERRIDE = 100, 271 - CP_PREEMPT_ENABLE_GLOBAL = 105, 272 - CP_PREEMPT_ENABLE_LOCAL = 106, 273 - CP_CONTEXT_SWITCH_YIELD = 107, 274 - CP_SET_RENDER_MODE = 108, 275 - CP_COMPUTE_CHECKPOINT = 110, 276 - CP_MEM_TO_MEM = 115, 277 - CP_BLIT = 44, 278 - CP_REG_TEST = 57, 279 - CP_SET_MODE = 99, 280 - CP_LOAD_STATE6_GEOM = 50, 281 - CP_LOAD_STATE6_FRAG = 52, 282 - CP_LOAD_STATE6 = 54, 283 - IN_IB_PREFETCH_END = 23, 284 - IN_SUBBLK_PREFETCH = 31, 285 - IN_INSTR_PREFETCH = 32, 286 - IN_INSTR_MATCH = 71, 287 - IN_CONST_PREFETCH = 73, 288 - IN_INCR_UPDT_STATE = 85, 289 - IN_INCR_UPDT_CONST = 86, 290 - IN_INCR_UPDT_INSTR = 87, 291 - PKT4 = 4, 292 - IN_IB_END = 10, 293 - IN_GMU_INTERRUPT = 11, 294 - IN_PREEMPT = 15, 295 - CP_SCRATCH_WRITE = 76, 296 - CP_REG_TO_MEM_OFFSET_MEM = 116, 297 - CP_REG_TO_MEM_OFFSET_REG = 114, 298 - CP_WAIT_MEM_GTE = 20, 299 - CP_WAIT_TWO_REGS = 112, 300 - CP_MEMCPY = 117, 301 - CP_SET_BIN_DATA5_OFFSET = 46, 302 - CP_SET_UNK_BIN_DATA = 45, 303 - CP_CONTEXT_SWITCH = 84, 304 - CP_SET_CTXSWITCH_IB = 85, 305 - CP_REG_WRITE = 109, 306 - CP_START_BIN = 80, 307 - CP_END_BIN = 81, 308 - CP_PREEMPT_DISABLE = 108, 309 - CP_WAIT_TIMESTAMP = 20, 310 - CP_GLOBAL_TIMESTAMP = 21, 311 - CP_LOCAL_TIMESTAMP = 22, 312 - CP_THREAD_CONTROL = 23, 313 - CP_RESOURCE_LIST = 24, 314 - CP_BV_BR_COUNT_OPS = 27, 315 - CP_MODIFY_TIMESTAMP = 28, 316 - CP_CONTEXT_REG_BUNCH2 = 93, 317 - CP_MEM_TO_SCRATCH_MEM = 73, 318 - CP_FIXED_STRIDE_DRAW_TABLE = 127, 319 - CP_RESET_CONTEXT_STATE = 31, 320 - }; 321 - 322 - enum adreno_state_block { 323 - SB_VERT_TEX = 0, 324 - SB_VERT_MIPADDR = 1, 325 - SB_FRAG_TEX = 2, 326 - SB_FRAG_MIPADDR = 3, 327 - SB_VERT_SHADER = 4, 328 - SB_GEOM_SHADER = 5, 329 - SB_FRAG_SHADER = 6, 330 - SB_COMPUTE_SHADER = 7, 331 - }; 332 - 333 - enum adreno_state_type { 334 - ST_SHADER = 0, 335 - ST_CONSTANTS = 1, 336 - }; 337 - 338 - enum adreno_state_src { 339 - SS_DIRECT = 0, 340 - SS_INVALID_ALL_IC = 2, 341 - SS_INVALID_PART_IC = 3, 342 - SS_INDIRECT = 4, 343 - SS_INDIRECT_TCM = 5, 344 - SS_INDIRECT_STM = 6, 345 - }; 346 - 347 - enum a4xx_state_block { 348 - SB4_VS_TEX = 0, 349 - SB4_HS_TEX = 1, 350 - SB4_DS_TEX = 2, 351 - SB4_GS_TEX = 3, 352 - SB4_FS_TEX = 4, 353 - SB4_CS_TEX = 5, 354 - SB4_VS_SHADER = 8, 355 - SB4_HS_SHADER = 9, 356 - SB4_DS_SHADER = 10, 357 - SB4_GS_SHADER = 11, 358 - SB4_FS_SHADER = 12, 359 - SB4_CS_SHADER = 13, 360 - SB4_SSBO = 14, 361 - SB4_CS_SSBO = 15, 362 - }; 363 - 364 - enum a4xx_state_type { 365 - ST4_SHADER = 0, 366 - ST4_CONSTANTS = 1, 367 - ST4_UBO = 2, 368 - }; 369 - 370 - enum a4xx_state_src { 371 - SS4_DIRECT = 0, 372 - SS4_INDIRECT = 2, 373 - }; 374 - 375 - enum a6xx_state_block { 376 - SB6_VS_TEX = 0, 377 - SB6_HS_TEX = 1, 378 - SB6_DS_TEX = 2, 379 - SB6_GS_TEX = 3, 380 - SB6_FS_TEX = 4, 381 - SB6_CS_TEX = 5, 382 - SB6_VS_SHADER = 8, 383 - SB6_HS_SHADER = 9, 384 - SB6_DS_SHADER = 10, 385 - SB6_GS_SHADER = 11, 386 - SB6_FS_SHADER = 12, 387 - SB6_CS_SHADER = 13, 388 - SB6_IBO = 14, 389 - SB6_CS_IBO = 15, 390 - }; 391 - 392 - enum a6xx_state_type { 393 - ST6_SHADER = 0, 394 - ST6_CONSTANTS = 1, 395 - ST6_UBO = 2, 396 - ST6_IBO = 3, 397 - }; 398 - 399 - enum a6xx_state_src { 400 - SS6_DIRECT = 0, 401 - SS6_BINDLESS = 1, 402 - SS6_INDIRECT = 2, 403 - SS6_UBO = 3, 404 - }; 405 - 406 - enum a4xx_index_size { 407 - INDEX4_SIZE_8_BIT = 0, 408 - INDEX4_SIZE_16_BIT = 1, 409 - INDEX4_SIZE_32_BIT = 2, 410 - }; 411 - 412 - enum a6xx_patch_type { 413 - TESS_QUADS = 0, 414 - TESS_TRIANGLES = 1, 415 - TESS_ISOLINES = 2, 416 - }; 417 - 418 - enum a6xx_draw_indirect_opcode { 419 - INDIRECT_OP_NORMAL = 2, 420 - INDIRECT_OP_INDEXED = 4, 421 - INDIRECT_OP_INDIRECT_COUNT = 6, 422 - INDIRECT_OP_INDIRECT_COUNT_INDEXED = 7, 423 - }; 424 - 425 - enum cp_draw_pred_src { 426 - PRED_SRC_MEM = 5, 427 - }; 428 - 429 - enum cp_draw_pred_test { 430 - NE_0_PASS = 0, 431 - EQ_0_PASS = 1, 432 - }; 433 - 434 - enum cp_cond_function { 435 - WRITE_ALWAYS = 0, 436 - WRITE_LT = 1, 437 - WRITE_LE = 2, 438 - WRITE_EQ = 3, 439 - WRITE_NE = 4, 440 - WRITE_GE = 5, 441 - WRITE_GT = 6, 442 - }; 443 - 444 - enum poll_memory_type { 445 - POLL_REGISTER = 0, 446 - POLL_MEMORY = 1, 447 - POLL_SCRATCH = 2, 448 - POLL_ON_CHIP = 3, 449 - }; 450 - 451 - enum render_mode_cmd { 452 - BYPASS = 1, 453 - BINNING = 2, 454 - GMEM = 3, 455 - BLIT2D = 5, 456 - BLIT2DSCALE = 7, 457 - END2D = 8, 458 - }; 459 - 460 - enum event_write_src { 461 - EV_WRITE_USER_32B = 0, 462 - EV_WRITE_USER_64B = 1, 463 - EV_WRITE_TIMESTAMP_SUM = 2, 464 - EV_WRITE_ALWAYSON = 3, 465 - EV_WRITE_REGS_CONTENT = 4, 466 - }; 467 - 468 - enum event_write_dst { 469 - EV_DST_RAM = 0, 470 - EV_DST_ONCHIP = 1, 471 - }; 472 - 473 - enum cp_blit_cmd { 474 - BLIT_OP_FILL = 0, 475 - BLIT_OP_COPY = 1, 476 - BLIT_OP_SCALE = 3, 477 - }; 478 - 479 - enum a6xx_marker { 480 - RM6_BYPASS = 1, 481 - RM6_BINNING = 2, 482 - RM6_GMEM = 4, 483 - RM6_ENDVIS = 5, 484 - RM6_RESOLVE = 6, 485 - RM6_YIELD = 7, 486 - RM6_COMPUTE = 8, 487 - RM6_BLIT2DSCALE = 12, 488 - RM6_IB1LIST_START = 13, 489 - RM6_IB1LIST_END = 14, 490 - RM6_IFPC_ENABLE = 256, 491 - RM6_IFPC_DISABLE = 257, 492 - }; 493 - 494 - enum pseudo_reg { 495 - SMMU_INFO = 0, 496 - NON_SECURE_SAVE_ADDR = 1, 497 - SECURE_SAVE_ADDR = 2, 498 - NON_PRIV_SAVE_ADDR = 3, 499 - COUNTER = 4, 500 - DRAW_STRM_ADDRESS = 8, 501 - DRAW_STRM_SIZE_ADDRESS = 9, 502 - PRIM_STRM_ADDRESS = 10, 503 - UNK_STRM_ADDRESS = 11, 504 - UNK_STRM_SIZE_ADDRESS = 12, 505 - BINDLESS_BASE_0_ADDR = 16, 506 - BINDLESS_BASE_1_ADDR = 17, 507 - BINDLESS_BASE_2_ADDR = 18, 508 - BINDLESS_BASE_3_ADDR = 19, 509 - BINDLESS_BASE_4_ADDR = 20, 510 - BINDLESS_BASE_5_ADDR = 21, 511 - BINDLESS_BASE_6_ADDR = 22, 512 - }; 513 - 514 - enum source_type { 515 - SOURCE_REG = 0, 516 - SOURCE_SCRATCH_MEM = 1, 517 - }; 518 - 519 - enum compare_mode { 520 - PRED_TEST = 1, 521 - REG_COMPARE = 2, 522 - RENDER_MODE = 3, 523 - REG_COMPARE_IMM = 4, 524 - THREAD_MODE = 5, 525 - }; 526 - 527 - enum ctxswitch_ib { 528 - RESTORE_IB = 0, 529 - YIELD_RESTORE_IB = 1, 530 - SAVE_IB = 2, 531 - RB_SAVE_IB = 3, 532 - }; 533 - 534 - enum reg_tracker { 535 - TRACK_CNTL_REG = 1, 536 - TRACK_RENDER_CNTL = 2, 537 - UNK_EVENT_WRITE = 4, 538 - TRACK_LRZ = 8, 539 - }; 540 - 541 - enum ts_wait_value_src { 542 - TS_WAIT_GE_32B = 0, 543 - TS_WAIT_GE_64B = 1, 544 - TS_WAIT_GE_TIMESTAMP_SUM = 2, 545 - }; 546 - 547 - enum ts_wait_type { 548 - TS_WAIT_RAM = 0, 549 - TS_WAIT_ONCHIP = 1, 550 - }; 551 - 552 - enum pipe_count_op { 553 - PIPE_CLEAR_BV_BR = 1, 554 - PIPE_SET_BR_OFFSET = 2, 555 - PIPE_BR_WAIT_FOR_BV = 3, 556 - PIPE_BV_WAIT_FOR_BR = 4, 557 - }; 558 - 559 - enum timestamp_op { 560 - MODIFY_TIMESTAMP_CLEAR = 0, 561 - MODIFY_TIMESTAMP_ADD_GLOBAL = 1, 562 - MODIFY_TIMESTAMP_ADD_LOCAL = 2, 563 - }; 564 - 565 - enum cp_thread { 566 - CP_SET_THREAD_BR = 1, 567 - CP_SET_THREAD_BV = 2, 568 - CP_SET_THREAD_BOTH = 3, 569 - }; 570 - 571 - #define REG_CP_LOAD_STATE_0 0x00000000 572 - #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff 573 - #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0 574 - static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val) 575 - { 576 - return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK; 577 - } 578 - #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000 579 - #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16 580 - static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val) 581 - { 582 - return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK; 583 - } 584 - #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000 585 - #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19 586 - static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val) 587 - { 588 - return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK; 589 - } 590 - #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000 591 - #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22 592 - static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val) 593 - { 594 - return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK; 595 - } 596 - 597 - #define REG_CP_LOAD_STATE_1 0x00000001 598 - #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003 599 - #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0 600 - static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) 601 - { 602 - return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK; 603 - } 604 - #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc 605 - #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 606 - static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) 607 - { 608 - assert(!(val & 0x3)); 609 - return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; 610 - } 611 - 612 - #define REG_CP_LOAD_STATE4_0 0x00000000 613 - #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff 614 - #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0 615 - static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val) 616 - { 617 - return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK; 618 - } 619 - #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000 620 - #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16 621 - static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val) 622 - { 623 - return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK; 624 - } 625 - #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000 626 - #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18 627 - static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val) 628 - { 629 - return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK; 630 - } 631 - #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000 632 - #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22 633 - static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val) 634 - { 635 - return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK; 636 - } 637 - 638 - #define REG_CP_LOAD_STATE4_1 0x00000001 639 - #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003 640 - #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0 641 - static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) 642 - { 643 - return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK; 644 - } 645 - #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc 646 - #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 647 - static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) 648 - { 649 - assert(!(val & 0x3)); 650 - return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; 651 - } 652 - 653 - #define REG_CP_LOAD_STATE4_2 0x00000002 654 - #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 655 - #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0 656 - static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val) 657 - { 658 - return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK; 659 - } 660 - 661 - #define REG_CP_LOAD_STATE6_0 0x00000000 662 - #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff 663 - #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0 664 - static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val) 665 - { 666 - return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK; 667 - } 668 - #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x0000c000 669 - #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14 670 - static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val) 671 - { 672 - return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK; 673 - } 674 - #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000 675 - #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16 676 - static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val) 677 - { 678 - return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK; 679 - } 680 - #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000 681 - #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18 682 - static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val) 683 - { 684 - return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK; 685 - } 686 - #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000 687 - #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22 688 - static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) 689 - { 690 - return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK; 691 - } 692 - 693 - #define REG_CP_LOAD_STATE6_1 0x00000001 694 - #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc 695 - #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 696 - static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) 697 - { 698 - assert(!(val & 0x3)); 699 - return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; 700 - } 701 - 702 - #define REG_CP_LOAD_STATE6_2 0x00000002 703 - #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff 704 - #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0 705 - static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val) 706 - { 707 - return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK; 708 - } 709 - 710 - #define REG_CP_LOAD_STATE6_EXT_SRC_ADDR 0x00000001 711 - 712 - #define REG_CP_DRAW_INDX_0 0x00000000 713 - #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff 714 - #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0 715 - static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val) 716 - { 717 - return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK; 718 - } 719 - 720 - #define REG_CP_DRAW_INDX_1 0x00000001 721 - #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f 722 - #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0 723 - static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val) 724 - { 725 - return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK; 726 - } 727 - #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0 728 - #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6 729 - static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val) 730 - { 731 - return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK; 732 - } 733 - #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600 734 - #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9 735 - static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val) 736 - { 737 - return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK; 738 - } 739 - #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800 740 - #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11 741 - static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val) 742 - { 743 - return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK; 744 - } 745 - #define CP_DRAW_INDX_1_NOT_EOP 0x00001000 746 - #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000 747 - #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 748 - #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000 749 - #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24 750 - static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val) 751 - { 752 - return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK; 753 - } 754 - 755 - #define REG_CP_DRAW_INDX_2 0x00000002 756 - #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff 757 - #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0 758 - static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val) 759 - { 760 - return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK; 761 - } 762 - 763 - #define REG_CP_DRAW_INDX_3 0x00000003 764 - #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff 765 - #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0 766 - static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val) 767 - { 768 - return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK; 769 - } 770 - 771 - #define REG_CP_DRAW_INDX_4 0x00000004 772 - #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff 773 - #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0 774 - static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val) 775 - { 776 - return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK; 777 - } 778 - 779 - #define REG_CP_DRAW_INDX_2_0 0x00000000 780 - #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff 781 - #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0 782 - static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val) 783 - { 784 - return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK; 785 - } 786 - 787 - #define REG_CP_DRAW_INDX_2_1 0x00000001 788 - #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f 789 - #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0 790 - static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val) 791 - { 792 - return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK; 793 - } 794 - #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0 795 - #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6 796 - static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val) 797 - { 798 - return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK; 799 - } 800 - #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600 801 - #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9 802 - static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val) 803 - { 804 - return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK; 805 - } 806 - #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800 807 - #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11 808 - static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val) 809 - { 810 - return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK; 811 - } 812 - #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000 813 - #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000 814 - #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000 815 - #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000 816 - #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24 817 - static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val) 818 - { 819 - return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK; 820 - } 821 - 822 - #define REG_CP_DRAW_INDX_2_2 0x00000002 823 - #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff 824 - #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0 825 - static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val) 826 - { 827 - return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK; 828 - } 829 - 830 - #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000 831 - #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f 832 - #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0 833 - static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val) 834 - { 835 - return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK; 836 - } 837 - #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0 838 - #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6 839 - static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val) 840 - { 841 - return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK; 842 - } 843 - #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300 844 - #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8 845 - static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val) 846 - { 847 - return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK; 848 - } 849 - #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00 850 - #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10 851 - static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val) 852 - { 853 - return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK; 854 - } 855 - #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK 0x00003000 856 - #define CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT 12 857 - static inline uint32_t CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(enum a6xx_patch_type val) 858 - { 859 - return ((val) << CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PATCH_TYPE__MASK; 860 - } 861 - #define CP_DRAW_INDX_OFFSET_0_GS_ENABLE 0x00010000 862 - #define CP_DRAW_INDX_OFFSET_0_TESS_ENABLE 0x00020000 863 - 864 - #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001 865 - #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff 866 - #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0 867 - static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val) 868 - { 869 - return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK; 870 - } 871 - 872 - #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002 873 - #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff 874 - #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0 875 - static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val) 876 - { 877 - return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK; 878 - } 879 - 880 - #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003 881 - #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK 0xffffffff 882 - #define CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT 0 883 - static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) 884 - { 885 - return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK; 886 - } 887 - 888 - #define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004 889 - #define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff 890 - #define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 891 - static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) 892 - { 893 - return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; 894 - } 895 - 896 - #define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005 897 - #define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff 898 - #define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 899 - static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) 900 - { 901 - return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; 902 - } 903 - 904 - #define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 905 - 906 - #define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006 907 - #define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff 908 - #define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 909 - static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) 910 - { 911 - return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; 912 - } 913 - 914 - #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 915 - #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff 916 - #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 917 - static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val) 918 - { 919 - return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; 920 - } 921 - 922 - #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 923 - #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff 924 - #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0 925 - static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val) 926 - { 927 - return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK; 928 - } 929 - 930 - #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000 931 - #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 932 - #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0 933 - static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 934 - { 935 - return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK; 936 - } 937 - #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 938 - #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6 939 - static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 940 - { 941 - return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK; 942 - } 943 - #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300 944 - #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8 945 - static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 946 - { 947 - return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK; 948 - } 949 - #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 950 - #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10 951 - static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 952 - { 953 - return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK; 954 - } 955 - #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 956 - #define A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT 12 957 - static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) 958 - { 959 - return ((val) << A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE__MASK; 960 - } 961 - #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000 962 - #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 963 - 964 - #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 965 - #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff 966 - #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 967 - static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) 968 - { 969 - return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; 970 - } 971 - 972 - #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001 973 - #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff 974 - #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 975 - static inline uint32_t A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO(uint32_t val) 976 - { 977 - return ((val) << A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK; 978 - } 979 - 980 - #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002 981 - #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff 982 - #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0 983 - static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val) 984 - { 985 - return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK; 986 - } 987 - 988 - #define REG_A5XX_CP_DRAW_INDIRECT_INDIRECT 0x00000001 989 - 990 - #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000 991 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f 992 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0 993 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val) 994 - { 995 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK; 996 - } 997 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0 998 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6 999 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val) 1000 - { 1001 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK; 1002 - } 1003 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300 1004 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8 1005 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val) 1006 - { 1007 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK; 1008 - } 1009 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00 1010 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10 1011 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val) 1012 - { 1013 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK; 1014 - } 1015 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK 0x00003000 1016 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT 12 1017 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type val) 1018 - { 1019 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE__MASK; 1020 - } 1021 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000 1022 - #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 1023 - 1024 - #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 1025 - #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff 1026 - #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 1027 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val) 1028 - { 1029 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK; 1030 - } 1031 - 1032 - #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 1033 - #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff 1034 - #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0 1035 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val) 1036 - { 1037 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK; 1038 - } 1039 - 1040 - #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 1041 - #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff 1042 - #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0 1043 - static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) 1044 - { 1045 - return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; 1046 - } 1047 - 1048 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 1049 - #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff 1050 - #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 1051 - static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val) 1052 - { 1053 - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK; 1054 - } 1055 - 1056 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002 1057 - #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff 1058 - #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0 1059 - static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val) 1060 - { 1061 - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK; 1062 - } 1063 - 1064 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDX_BASE 0x00000001 1065 - 1066 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003 1067 - #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff 1068 - #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0 1069 - static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val) 1070 - { 1071 - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK; 1072 - } 1073 - 1074 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004 1075 - #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff 1076 - #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0 1077 - static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val) 1078 - { 1079 - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK; 1080 - } 1081 - 1082 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005 1083 - #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff 1084 - #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0 1085 - static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val) 1086 - { 1087 - return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK; 1088 - } 1089 - 1090 - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_INDIRECT 0x00000004 1091 - 1092 - #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_0 0x00000000 1093 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK 0x0000003f 1094 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT 0 1095 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE(enum pc_di_primtype val) 1096 - { 1097 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PRIM_TYPE__MASK; 1098 - } 1099 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK 0x000000c0 1100 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT 6 1101 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT(enum pc_di_src_sel val) 1102 - { 1103 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_SOURCE_SELECT__MASK; 1104 - } 1105 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK 0x00000300 1106 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT 8 1107 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL(enum pc_di_vis_cull_mode val) 1108 - { 1109 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_VIS_CULL__MASK; 1110 - } 1111 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK 0x00000c00 1112 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT 10 1113 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE(enum a4xx_index_size val) 1114 - { 1115 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_INDEX_SIZE__MASK; 1116 - } 1117 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK 0x00003000 1118 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT 12 1119 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE(enum a6xx_patch_type val) 1120 - { 1121 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_0_PATCH_TYPE__MASK; 1122 - } 1123 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_GS_ENABLE 0x00010000 1124 - #define A6XX_CP_DRAW_INDIRECT_MULTI_0_TESS_ENABLE 0x00020000 1125 - 1126 - #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_1 0x00000001 1127 - #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK 0x0000000f 1128 - #define A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT 0 1129 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(enum a6xx_draw_indirect_opcode val) 1130 - { 1131 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE__MASK; 1132 - } 1133 - #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK 0x003fff00 1134 - #define A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT 8 1135 - static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) 1136 - { 1137 - return ((val) << A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__SHIFT) & A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF__MASK; 1138 - } 1139 - 1140 - #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002 1141 - 1142 - #define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 1143 - 1144 - #define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 1145 - 1146 - #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 1147 - 1148 - #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 1149 - 1150 - #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 1151 - 1152 - #define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008 1153 - 1154 - #define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 1155 - 1156 - #define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005 1157 - 1158 - #define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007 1159 - 1160 - #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 1161 - 1162 - #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 1163 - 1164 - #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 1165 - 1166 - #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008 1167 - 1168 - #define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a 1169 - 1170 - #define REG_CP_DRAW_AUTO_0 0x00000000 1171 - #define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f 1172 - #define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0 1173 - static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val) 1174 - { 1175 - return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK; 1176 - } 1177 - #define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0 1178 - #define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6 1179 - static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val) 1180 - { 1181 - return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK; 1182 - } 1183 - #define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300 1184 - #define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8 1185 - static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val) 1186 - { 1187 - return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK; 1188 - } 1189 - #define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00 1190 - #define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10 1191 - static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val) 1192 - { 1193 - return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK; 1194 - } 1195 - #define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000 1196 - #define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12 1197 - static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val) 1198 - { 1199 - return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK; 1200 - } 1201 - #define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000 1202 - #define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000 1203 - 1204 - #define REG_CP_DRAW_AUTO_1 0x00000001 1205 - #define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff 1206 - #define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0 1207 - static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val) 1208 - { 1209 - return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK; 1210 - } 1211 - 1212 - #define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002 1213 - 1214 - #define REG_CP_DRAW_AUTO_4 0x00000004 1215 - #define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff 1216 - #define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0 1217 - static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val) 1218 - { 1219 - return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK; 1220 - } 1221 - 1222 - #define REG_CP_DRAW_AUTO_5 0x00000005 1223 - #define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff 1224 - #define CP_DRAW_AUTO_5_STRIDE__SHIFT 0 1225 - static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val) 1226 - { 1227 - return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK; 1228 - } 1229 - 1230 - #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000 1231 - #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001 1232 - 1233 - #define REG_CP_DRAW_PRED_ENABLE_LOCAL_0 0x00000000 1234 - #define CP_DRAW_PRED_ENABLE_LOCAL_0_ENABLE 0x00000001 1235 - 1236 - #define REG_CP_DRAW_PRED_SET_0 0x00000000 1237 - #define CP_DRAW_PRED_SET_0_SRC__MASK 0x000000f0 1238 - #define CP_DRAW_PRED_SET_0_SRC__SHIFT 4 1239 - static inline uint32_t CP_DRAW_PRED_SET_0_SRC(enum cp_draw_pred_src val) 1240 - { 1241 - return ((val) << CP_DRAW_PRED_SET_0_SRC__SHIFT) & CP_DRAW_PRED_SET_0_SRC__MASK; 1242 - } 1243 - #define CP_DRAW_PRED_SET_0_TEST__MASK 0x00000100 1244 - #define CP_DRAW_PRED_SET_0_TEST__SHIFT 8 1245 - static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) 1246 - { 1247 - return ((val) << CP_DRAW_PRED_SET_0_TEST__SHIFT) & CP_DRAW_PRED_SET_0_TEST__MASK; 1248 - } 1249 - 1250 - #define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001 1251 - 1252 - #define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*(i0)) 1253 - 1254 - static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 1255 - #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff 1256 - #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0 1257 - static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val) 1258 - { 1259 - return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK; 1260 - } 1261 - #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000 1262 - #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000 1263 - #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000 1264 - #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000 1265 - #define CP_SET_DRAW_STATE__0_BINNING 0x00100000 1266 - #define CP_SET_DRAW_STATE__0_GMEM 0x00200000 1267 - #define CP_SET_DRAW_STATE__0_SYSMEM 0x00400000 1268 - #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000 1269 - #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24 1270 - static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val) 1271 - { 1272 - return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK; 1273 - } 1274 - 1275 - static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 1276 - #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff 1277 - #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0 1278 - static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val) 1279 - { 1280 - return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK; 1281 - } 1282 - 1283 - static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 1284 - #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff 1285 - #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0 1286 - static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val) 1287 - { 1288 - return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK; 1289 - } 1290 - 1291 - #define REG_CP_SET_BIN_0 0x00000000 1292 - 1293 - #define REG_CP_SET_BIN_1 0x00000001 1294 - #define CP_SET_BIN_1_X1__MASK 0x0000ffff 1295 - #define CP_SET_BIN_1_X1__SHIFT 0 1296 - static inline uint32_t CP_SET_BIN_1_X1(uint32_t val) 1297 - { 1298 - return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK; 1299 - } 1300 - #define CP_SET_BIN_1_Y1__MASK 0xffff0000 1301 - #define CP_SET_BIN_1_Y1__SHIFT 16 1302 - static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val) 1303 - { 1304 - return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK; 1305 - } 1306 - 1307 - #define REG_CP_SET_BIN_2 0x00000002 1308 - #define CP_SET_BIN_2_X2__MASK 0x0000ffff 1309 - #define CP_SET_BIN_2_X2__SHIFT 0 1310 - static inline uint32_t CP_SET_BIN_2_X2(uint32_t val) 1311 - { 1312 - return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK; 1313 - } 1314 - #define CP_SET_BIN_2_Y2__MASK 0xffff0000 1315 - #define CP_SET_BIN_2_Y2__SHIFT 16 1316 - static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val) 1317 - { 1318 - return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK; 1319 - } 1320 - 1321 - #define REG_CP_SET_BIN_DATA_0 0x00000000 1322 - #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff 1323 - #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0 1324 - static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val) 1325 - { 1326 - return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK; 1327 - } 1328 - 1329 - #define REG_CP_SET_BIN_DATA_1 0x00000001 1330 - #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff 1331 - #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0 1332 - static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val) 1333 - { 1334 - return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK; 1335 - } 1336 - 1337 - #define REG_CP_SET_BIN_DATA5_0 0x00000000 1338 - #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000 1339 - #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16 1340 - static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val) 1341 - { 1342 - return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK; 1343 - } 1344 - #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000 1345 - #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22 1346 - static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val) 1347 - { 1348 - return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK; 1349 - } 1350 - 1351 - #define REG_CP_SET_BIN_DATA5_1 0x00000001 1352 - #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff 1353 - #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0 1354 - static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val) 1355 - { 1356 - return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK; 1357 - } 1358 - 1359 - #define REG_CP_SET_BIN_DATA5_2 0x00000002 1360 - #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff 1361 - #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0 1362 - static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val) 1363 - { 1364 - return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK; 1365 - } 1366 - 1367 - #define REG_CP_SET_BIN_DATA5_3 0x00000003 1368 - #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff 1369 - #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0 1370 - static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val) 1371 - { 1372 - return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK; 1373 - } 1374 - 1375 - #define REG_CP_SET_BIN_DATA5_4 0x00000004 1376 - #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff 1377 - #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0 1378 - static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val) 1379 - { 1380 - return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK; 1381 - } 1382 - 1383 - #define REG_CP_SET_BIN_DATA5_5 0x00000005 1384 - #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK 0xffffffff 1385 - #define CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT 0 1386 - static inline uint32_t CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO(uint32_t val) 1387 - { 1388 - return ((val) << CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_PRIM_STRM_LO__MASK; 1389 - } 1390 - 1391 - #define REG_CP_SET_BIN_DATA5_6 0x00000006 1392 - #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK 0xffffffff 1393 - #define CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT 0 1394 - static inline uint32_t CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI(uint32_t val) 1395 - { 1396 - return ((val) << CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__SHIFT) & CP_SET_BIN_DATA5_6_BIN_PRIM_STRM_HI__MASK; 1397 - } 1398 - 1399 - #define REG_CP_SET_BIN_DATA5_7 0x00000007 1400 - 1401 - #define REG_CP_SET_BIN_DATA5_9 0x00000009 1402 - 1403 - #define REG_CP_SET_BIN_DATA5_OFFSET_0 0x00000000 1404 - #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK 0x003f0000 1405 - #define CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT 16 1406 - static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE(uint32_t val) 1407 - { 1408 - return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_SIZE__MASK; 1409 - } 1410 - #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK 0x07c00000 1411 - #define CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT 22 1412 - static inline uint32_t CP_SET_BIN_DATA5_OFFSET_0_VSC_N(uint32_t val) 1413 - { 1414 - return ((val) << CP_SET_BIN_DATA5_OFFSET_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_OFFSET_0_VSC_N__MASK; 1415 - } 1416 - 1417 - #define REG_CP_SET_BIN_DATA5_OFFSET_1 0x00000001 1418 - #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK 0xffffffff 1419 - #define CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT 0 1420 - static inline uint32_t CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET(uint32_t val) 1421 - { 1422 - return ((val) << CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_1_BIN_DATA_OFFSET__MASK; 1423 - } 1424 - 1425 - #define REG_CP_SET_BIN_DATA5_OFFSET_2 0x00000002 1426 - #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK 0xffffffff 1427 - #define CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT 0 1428 - static inline uint32_t CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET(uint32_t val) 1429 - { 1430 - return ((val) << CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_2_BIN_SIZE_OFFSET__MASK; 1431 - } 1432 - 1433 - #define REG_CP_SET_BIN_DATA5_OFFSET_3 0x00000003 1434 - #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK 0xffffffff 1435 - #define CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT 0 1436 - static inline uint32_t CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET(uint32_t val) 1437 - { 1438 - return ((val) << CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__SHIFT) & CP_SET_BIN_DATA5_OFFSET_3_BIN_DATA2_OFFSET__MASK; 1439 - } 1440 - 1441 - #define REG_CP_REG_RMW_0 0x00000000 1442 - #define CP_REG_RMW_0_DST_REG__MASK 0x0003ffff 1443 - #define CP_REG_RMW_0_DST_REG__SHIFT 0 1444 - static inline uint32_t CP_REG_RMW_0_DST_REG(uint32_t val) 1445 - { 1446 - return ((val) << CP_REG_RMW_0_DST_REG__SHIFT) & CP_REG_RMW_0_DST_REG__MASK; 1447 - } 1448 - #define CP_REG_RMW_0_ROTATE__MASK 0x1f000000 1449 - #define CP_REG_RMW_0_ROTATE__SHIFT 24 1450 - static inline uint32_t CP_REG_RMW_0_ROTATE(uint32_t val) 1451 - { 1452 - return ((val) << CP_REG_RMW_0_ROTATE__SHIFT) & CP_REG_RMW_0_ROTATE__MASK; 1453 - } 1454 - #define CP_REG_RMW_0_SRC1_ADD 0x20000000 1455 - #define CP_REG_RMW_0_SRC1_IS_REG 0x40000000 1456 - #define CP_REG_RMW_0_SRC0_IS_REG 0x80000000 1457 - 1458 - #define REG_CP_REG_RMW_1 0x00000001 1459 - #define CP_REG_RMW_1_SRC0__MASK 0xffffffff 1460 - #define CP_REG_RMW_1_SRC0__SHIFT 0 1461 - static inline uint32_t CP_REG_RMW_1_SRC0(uint32_t val) 1462 - { 1463 - return ((val) << CP_REG_RMW_1_SRC0__SHIFT) & CP_REG_RMW_1_SRC0__MASK; 1464 - } 1465 - 1466 - #define REG_CP_REG_RMW_2 0x00000002 1467 - #define CP_REG_RMW_2_SRC1__MASK 0xffffffff 1468 - #define CP_REG_RMW_2_SRC1__SHIFT 0 1469 - static inline uint32_t CP_REG_RMW_2_SRC1(uint32_t val) 1470 - { 1471 - return ((val) << CP_REG_RMW_2_SRC1__SHIFT) & CP_REG_RMW_2_SRC1__MASK; 1472 - } 1473 - 1474 - #define REG_CP_REG_TO_MEM_0 0x00000000 1475 - #define CP_REG_TO_MEM_0_REG__MASK 0x0003ffff 1476 - #define CP_REG_TO_MEM_0_REG__SHIFT 0 1477 - static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val) 1478 - { 1479 - return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK; 1480 - } 1481 - #define CP_REG_TO_MEM_0_CNT__MASK 0x3ffc0000 1482 - #define CP_REG_TO_MEM_0_CNT__SHIFT 18 1483 - static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val) 1484 - { 1485 - return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK; 1486 - } 1487 - #define CP_REG_TO_MEM_0_64B 0x40000000 1488 - #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000 1489 - 1490 - #define REG_CP_REG_TO_MEM_1 0x00000001 1491 - #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff 1492 - #define CP_REG_TO_MEM_1_DEST__SHIFT 0 1493 - static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val) 1494 - { 1495 - return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK; 1496 - } 1497 - 1498 - #define REG_CP_REG_TO_MEM_2 0x00000002 1499 - #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff 1500 - #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0 1501 - static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val) 1502 - { 1503 - return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK; 1504 - } 1505 - 1506 - #define REG_CP_REG_TO_MEM_OFFSET_REG_0 0x00000000 1507 - #define CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK 0x0003ffff 1508 - #define CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT 0 1509 - static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_REG(uint32_t val) 1510 - { 1511 - return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_REG__MASK; 1512 - } 1513 - #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK 0x3ffc0000 1514 - #define CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT 18 1515 - static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_0_CNT(uint32_t val) 1516 - { 1517 - return ((val) << CP_REG_TO_MEM_OFFSET_REG_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_0_CNT__MASK; 1518 - } 1519 - #define CP_REG_TO_MEM_OFFSET_REG_0_64B 0x40000000 1520 - #define CP_REG_TO_MEM_OFFSET_REG_0_ACCUMULATE 0x80000000 1521 - 1522 - #define REG_CP_REG_TO_MEM_OFFSET_REG_1 0x00000001 1523 - #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK 0xffffffff 1524 - #define CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT 0 1525 - static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_1_DEST(uint32_t val) 1526 - { 1527 - return ((val) << CP_REG_TO_MEM_OFFSET_REG_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_1_DEST__MASK; 1528 - } 1529 - 1530 - #define REG_CP_REG_TO_MEM_OFFSET_REG_2 0x00000002 1531 - #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK 0xffffffff 1532 - #define CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT 0 1533 - static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI(uint32_t val) 1534 - { 1535 - return ((val) << CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_2_DEST_HI__MASK; 1536 - } 1537 - 1538 - #define REG_CP_REG_TO_MEM_OFFSET_REG_3 0x00000003 1539 - #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK 0x0003ffff 1540 - #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT 0 1541 - static inline uint32_t CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0(uint32_t val) 1542 - { 1543 - return ((val) << CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__SHIFT) & CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0__MASK; 1544 - } 1545 - #define CP_REG_TO_MEM_OFFSET_REG_3_OFFSET0_SCRATCH 0x00080000 1546 - 1547 - #define REG_CP_REG_TO_MEM_OFFSET_MEM_0 0x00000000 1548 - #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK 0x0003ffff 1549 - #define CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT 0 1550 - static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_REG(uint32_t val) 1551 - { 1552 - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_REG__MASK; 1553 - } 1554 - #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK 0x3ffc0000 1555 - #define CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT 18 1556 - static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_0_CNT(uint32_t val) 1557 - { 1558 - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_0_CNT__MASK; 1559 - } 1560 - #define CP_REG_TO_MEM_OFFSET_MEM_0_64B 0x40000000 1561 - #define CP_REG_TO_MEM_OFFSET_MEM_0_ACCUMULATE 0x80000000 1562 - 1563 - #define REG_CP_REG_TO_MEM_OFFSET_MEM_1 0x00000001 1564 - #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK 0xffffffff 1565 - #define CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT 0 1566 - static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_1_DEST(uint32_t val) 1567 - { 1568 - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_1_DEST__MASK; 1569 - } 1570 - 1571 - #define REG_CP_REG_TO_MEM_OFFSET_MEM_2 0x00000002 1572 - #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK 0xffffffff 1573 - #define CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT 0 1574 - static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI(uint32_t val) 1575 - { 1576 - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_2_DEST_HI__MASK; 1577 - } 1578 - 1579 - #define REG_CP_REG_TO_MEM_OFFSET_MEM_3 0x00000003 1580 - #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK 0xffffffff 1581 - #define CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT 0 1582 - static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO(uint32_t val) 1583 - { 1584 - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_3_OFFSET_LO__MASK; 1585 - } 1586 - 1587 - #define REG_CP_REG_TO_MEM_OFFSET_MEM_4 0x00000004 1588 - #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK 0xffffffff 1589 - #define CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT 0 1590 - static inline uint32_t CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI(uint32_t val) 1591 - { 1592 - return ((val) << CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__SHIFT) & CP_REG_TO_MEM_OFFSET_MEM_4_OFFSET_HI__MASK; 1593 - } 1594 - 1595 - #define REG_CP_MEM_TO_REG_0 0x00000000 1596 - #define CP_MEM_TO_REG_0_REG__MASK 0x0003ffff 1597 - #define CP_MEM_TO_REG_0_REG__SHIFT 0 1598 - static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val) 1599 - { 1600 - return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK; 1601 - } 1602 - #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000 1603 - #define CP_MEM_TO_REG_0_CNT__SHIFT 19 1604 - static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val) 1605 - { 1606 - return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK; 1607 - } 1608 - #define CP_MEM_TO_REG_0_SHIFT_BY_2 0x40000000 1609 - #define CP_MEM_TO_REG_0_UNK31 0x80000000 1610 - 1611 - #define REG_CP_MEM_TO_REG_1 0x00000001 1612 - #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff 1613 - #define CP_MEM_TO_REG_1_SRC__SHIFT 0 1614 - static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val) 1615 - { 1616 - return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK; 1617 - } 1618 - 1619 - #define REG_CP_MEM_TO_REG_2 0x00000002 1620 - #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff 1621 - #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0 1622 - static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val) 1623 - { 1624 - return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK; 1625 - } 1626 - 1627 - #define REG_CP_MEM_TO_MEM_0 0x00000000 1628 - #define CP_MEM_TO_MEM_0_NEG_A 0x00000001 1629 - #define CP_MEM_TO_MEM_0_NEG_B 0x00000002 1630 - #define CP_MEM_TO_MEM_0_NEG_C 0x00000004 1631 - #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000 1632 - #define CP_MEM_TO_MEM_0_WAIT_FOR_MEM_WRITES 0x40000000 1633 - #define CP_MEM_TO_MEM_0_UNK31 0x80000000 1634 - 1635 - #define REG_CP_MEMCPY_0 0x00000000 1636 - #define CP_MEMCPY_0_DWORDS__MASK 0xffffffff 1637 - #define CP_MEMCPY_0_DWORDS__SHIFT 0 1638 - static inline uint32_t CP_MEMCPY_0_DWORDS(uint32_t val) 1639 - { 1640 - return ((val) << CP_MEMCPY_0_DWORDS__SHIFT) & CP_MEMCPY_0_DWORDS__MASK; 1641 - } 1642 - 1643 - #define REG_CP_MEMCPY_1 0x00000001 1644 - #define CP_MEMCPY_1_SRC_LO__MASK 0xffffffff 1645 - #define CP_MEMCPY_1_SRC_LO__SHIFT 0 1646 - static inline uint32_t CP_MEMCPY_1_SRC_LO(uint32_t val) 1647 - { 1648 - return ((val) << CP_MEMCPY_1_SRC_LO__SHIFT) & CP_MEMCPY_1_SRC_LO__MASK; 1649 - } 1650 - 1651 - #define REG_CP_MEMCPY_2 0x00000002 1652 - #define CP_MEMCPY_2_SRC_HI__MASK 0xffffffff 1653 - #define CP_MEMCPY_2_SRC_HI__SHIFT 0 1654 - static inline uint32_t CP_MEMCPY_2_SRC_HI(uint32_t val) 1655 - { 1656 - return ((val) << CP_MEMCPY_2_SRC_HI__SHIFT) & CP_MEMCPY_2_SRC_HI__MASK; 1657 - } 1658 - 1659 - #define REG_CP_MEMCPY_3 0x00000003 1660 - #define CP_MEMCPY_3_DST_LO__MASK 0xffffffff 1661 - #define CP_MEMCPY_3_DST_LO__SHIFT 0 1662 - static inline uint32_t CP_MEMCPY_3_DST_LO(uint32_t val) 1663 - { 1664 - return ((val) << CP_MEMCPY_3_DST_LO__SHIFT) & CP_MEMCPY_3_DST_LO__MASK; 1665 - } 1666 - 1667 - #define REG_CP_MEMCPY_4 0x00000004 1668 - #define CP_MEMCPY_4_DST_HI__MASK 0xffffffff 1669 - #define CP_MEMCPY_4_DST_HI__SHIFT 0 1670 - static inline uint32_t CP_MEMCPY_4_DST_HI(uint32_t val) 1671 - { 1672 - return ((val) << CP_MEMCPY_4_DST_HI__SHIFT) & CP_MEMCPY_4_DST_HI__MASK; 1673 - } 1674 - 1675 - #define REG_CP_REG_TO_SCRATCH_0 0x00000000 1676 - #define CP_REG_TO_SCRATCH_0_REG__MASK 0x0003ffff 1677 - #define CP_REG_TO_SCRATCH_0_REG__SHIFT 0 1678 - static inline uint32_t CP_REG_TO_SCRATCH_0_REG(uint32_t val) 1679 - { 1680 - return ((val) << CP_REG_TO_SCRATCH_0_REG__SHIFT) & CP_REG_TO_SCRATCH_0_REG__MASK; 1681 - } 1682 - #define CP_REG_TO_SCRATCH_0_SCRATCH__MASK 0x00700000 1683 - #define CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT 20 1684 - static inline uint32_t CP_REG_TO_SCRATCH_0_SCRATCH(uint32_t val) 1685 - { 1686 - return ((val) << CP_REG_TO_SCRATCH_0_SCRATCH__SHIFT) & CP_REG_TO_SCRATCH_0_SCRATCH__MASK; 1687 - } 1688 - #define CP_REG_TO_SCRATCH_0_CNT__MASK 0x07000000 1689 - #define CP_REG_TO_SCRATCH_0_CNT__SHIFT 24 1690 - static inline uint32_t CP_REG_TO_SCRATCH_0_CNT(uint32_t val) 1691 - { 1692 - return ((val) << CP_REG_TO_SCRATCH_0_CNT__SHIFT) & CP_REG_TO_SCRATCH_0_CNT__MASK; 1693 - } 1694 - 1695 - #define REG_CP_SCRATCH_TO_REG_0 0x00000000 1696 - #define CP_SCRATCH_TO_REG_0_REG__MASK 0x0003ffff 1697 - #define CP_SCRATCH_TO_REG_0_REG__SHIFT 0 1698 - static inline uint32_t CP_SCRATCH_TO_REG_0_REG(uint32_t val) 1699 - { 1700 - return ((val) << CP_SCRATCH_TO_REG_0_REG__SHIFT) & CP_SCRATCH_TO_REG_0_REG__MASK; 1701 - } 1702 - #define CP_SCRATCH_TO_REG_0_UNK18 0x00040000 1703 - #define CP_SCRATCH_TO_REG_0_SCRATCH__MASK 0x00700000 1704 - #define CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT 20 1705 - static inline uint32_t CP_SCRATCH_TO_REG_0_SCRATCH(uint32_t val) 1706 - { 1707 - return ((val) << CP_SCRATCH_TO_REG_0_SCRATCH__SHIFT) & CP_SCRATCH_TO_REG_0_SCRATCH__MASK; 1708 - } 1709 - #define CP_SCRATCH_TO_REG_0_CNT__MASK 0x07000000 1710 - #define CP_SCRATCH_TO_REG_0_CNT__SHIFT 24 1711 - static inline uint32_t CP_SCRATCH_TO_REG_0_CNT(uint32_t val) 1712 - { 1713 - return ((val) << CP_SCRATCH_TO_REG_0_CNT__SHIFT) & CP_SCRATCH_TO_REG_0_CNT__MASK; 1714 - } 1715 - 1716 - #define REG_CP_SCRATCH_WRITE_0 0x00000000 1717 - #define CP_SCRATCH_WRITE_0_SCRATCH__MASK 0x00700000 1718 - #define CP_SCRATCH_WRITE_0_SCRATCH__SHIFT 20 1719 - static inline uint32_t CP_SCRATCH_WRITE_0_SCRATCH(uint32_t val) 1720 - { 1721 - return ((val) << CP_SCRATCH_WRITE_0_SCRATCH__SHIFT) & CP_SCRATCH_WRITE_0_SCRATCH__MASK; 1722 - } 1723 - 1724 - #define REG_CP_MEM_WRITE_0 0x00000000 1725 - #define CP_MEM_WRITE_0_ADDR_LO__MASK 0xffffffff 1726 - #define CP_MEM_WRITE_0_ADDR_LO__SHIFT 0 1727 - static inline uint32_t CP_MEM_WRITE_0_ADDR_LO(uint32_t val) 1728 - { 1729 - return ((val) << CP_MEM_WRITE_0_ADDR_LO__SHIFT) & CP_MEM_WRITE_0_ADDR_LO__MASK; 1730 - } 1731 - 1732 - #define REG_CP_MEM_WRITE_1 0x00000001 1733 - #define CP_MEM_WRITE_1_ADDR_HI__MASK 0xffffffff 1734 - #define CP_MEM_WRITE_1_ADDR_HI__SHIFT 0 1735 - static inline uint32_t CP_MEM_WRITE_1_ADDR_HI(uint32_t val) 1736 - { 1737 - return ((val) << CP_MEM_WRITE_1_ADDR_HI__SHIFT) & CP_MEM_WRITE_1_ADDR_HI__MASK; 1738 - } 1739 - 1740 - #define REG_CP_COND_WRITE_0 0x00000000 1741 - #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007 1742 - #define CP_COND_WRITE_0_FUNCTION__SHIFT 0 1743 - static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val) 1744 - { 1745 - return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK; 1746 - } 1747 - #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010 1748 - #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100 1749 - 1750 - #define REG_CP_COND_WRITE_1 0x00000001 1751 - #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff 1752 - #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0 1753 - static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val) 1754 - { 1755 - return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK; 1756 - } 1757 - 1758 - #define REG_CP_COND_WRITE_2 0x00000002 1759 - #define CP_COND_WRITE_2_REF__MASK 0xffffffff 1760 - #define CP_COND_WRITE_2_REF__SHIFT 0 1761 - static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val) 1762 - { 1763 - return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK; 1764 - } 1765 - 1766 - #define REG_CP_COND_WRITE_3 0x00000003 1767 - #define CP_COND_WRITE_3_MASK__MASK 0xffffffff 1768 - #define CP_COND_WRITE_3_MASK__SHIFT 0 1769 - static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val) 1770 - { 1771 - return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK; 1772 - } 1773 - 1774 - #define REG_CP_COND_WRITE_4 0x00000004 1775 - #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff 1776 - #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0 1777 - static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val) 1778 - { 1779 - return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK; 1780 - } 1781 - 1782 - #define REG_CP_COND_WRITE_5 0x00000005 1783 - #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff 1784 - #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0 1785 - static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val) 1786 - { 1787 - return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK; 1788 - } 1789 - 1790 - #define REG_CP_COND_WRITE5_0 0x00000000 1791 - #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007 1792 - #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0 1793 - static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) 1794 - { 1795 - return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; 1796 - } 1797 - #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008 1798 - #define CP_COND_WRITE5_0_POLL__MASK 0x00000030 1799 - #define CP_COND_WRITE5_0_POLL__SHIFT 4 1800 - static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val) 1801 - { 1802 - return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK; 1803 - } 1804 - #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 1805 - 1806 - #define REG_CP_COND_WRITE5_1 0x00000001 1807 - #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff 1808 - #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0 1809 - static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val) 1810 - { 1811 - return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK; 1812 - } 1813 - 1814 - #define REG_CP_COND_WRITE5_2 0x00000002 1815 - #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff 1816 - #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0 1817 - static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val) 1818 - { 1819 - return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK; 1820 - } 1821 - 1822 - #define REG_CP_COND_WRITE5_3 0x00000003 1823 - #define CP_COND_WRITE5_3_REF__MASK 0xffffffff 1824 - #define CP_COND_WRITE5_3_REF__SHIFT 0 1825 - static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val) 1826 - { 1827 - return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK; 1828 - } 1829 - 1830 - #define REG_CP_COND_WRITE5_4 0x00000004 1831 - #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff 1832 - #define CP_COND_WRITE5_4_MASK__SHIFT 0 1833 - static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val) 1834 - { 1835 - return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK; 1836 - } 1837 - 1838 - #define REG_CP_COND_WRITE5_5 0x00000005 1839 - #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff 1840 - #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0 1841 - static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val) 1842 - { 1843 - return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK; 1844 - } 1845 - 1846 - #define REG_CP_COND_WRITE5_6 0x00000006 1847 - #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff 1848 - #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0 1849 - static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val) 1850 - { 1851 - return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK; 1852 - } 1853 - 1854 - #define REG_CP_COND_WRITE5_7 0x00000007 1855 - #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff 1856 - #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0 1857 - static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val) 1858 - { 1859 - return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK; 1860 - } 1861 - 1862 - #define REG_CP_WAIT_MEM_GTE_0 0x00000000 1863 - #define CP_WAIT_MEM_GTE_0_RESERVED__MASK 0xffffffff 1864 - #define CP_WAIT_MEM_GTE_0_RESERVED__SHIFT 0 1865 - static inline uint32_t CP_WAIT_MEM_GTE_0_RESERVED(uint32_t val) 1866 - { 1867 - return ((val) << CP_WAIT_MEM_GTE_0_RESERVED__SHIFT) & CP_WAIT_MEM_GTE_0_RESERVED__MASK; 1868 - } 1869 - 1870 - #define REG_CP_WAIT_MEM_GTE_1 0x00000001 1871 - #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK 0xffffffff 1872 - #define CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT 0 1873 - static inline uint32_t CP_WAIT_MEM_GTE_1_POLL_ADDR_LO(uint32_t val) 1874 - { 1875 - return ((val) << CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_MEM_GTE_1_POLL_ADDR_LO__MASK; 1876 - } 1877 - 1878 - #define REG_CP_WAIT_MEM_GTE_2 0x00000002 1879 - #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK 0xffffffff 1880 - #define CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT 0 1881 - static inline uint32_t CP_WAIT_MEM_GTE_2_POLL_ADDR_HI(uint32_t val) 1882 - { 1883 - return ((val) << CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_MEM_GTE_2_POLL_ADDR_HI__MASK; 1884 - } 1885 - 1886 - #define REG_CP_WAIT_MEM_GTE_3 0x00000003 1887 - #define CP_WAIT_MEM_GTE_3_REF__MASK 0xffffffff 1888 - #define CP_WAIT_MEM_GTE_3_REF__SHIFT 0 1889 - static inline uint32_t CP_WAIT_MEM_GTE_3_REF(uint32_t val) 1890 - { 1891 - return ((val) << CP_WAIT_MEM_GTE_3_REF__SHIFT) & CP_WAIT_MEM_GTE_3_REF__MASK; 1892 - } 1893 - 1894 - #define REG_CP_WAIT_REG_MEM_0 0x00000000 1895 - #define CP_WAIT_REG_MEM_0_FUNCTION__MASK 0x00000007 1896 - #define CP_WAIT_REG_MEM_0_FUNCTION__SHIFT 0 1897 - static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) 1898 - { 1899 - return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK; 1900 - } 1901 - #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008 1902 - #define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030 1903 - #define CP_WAIT_REG_MEM_0_POLL__SHIFT 4 1904 - static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val) 1905 - { 1906 - return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK; 1907 - } 1908 - #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100 1909 - 1910 - #define REG_CP_WAIT_REG_MEM_1 0x00000001 1911 - #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK 0xffffffff 1912 - #define CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT 0 1913 - static inline uint32_t CP_WAIT_REG_MEM_1_POLL_ADDR_LO(uint32_t val) 1914 - { 1915 - return ((val) << CP_WAIT_REG_MEM_1_POLL_ADDR_LO__SHIFT) & CP_WAIT_REG_MEM_1_POLL_ADDR_LO__MASK; 1916 - } 1917 - 1918 - #define REG_CP_WAIT_REG_MEM_2 0x00000002 1919 - #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK 0xffffffff 1920 - #define CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT 0 1921 - static inline uint32_t CP_WAIT_REG_MEM_2_POLL_ADDR_HI(uint32_t val) 1922 - { 1923 - return ((val) << CP_WAIT_REG_MEM_2_POLL_ADDR_HI__SHIFT) & CP_WAIT_REG_MEM_2_POLL_ADDR_HI__MASK; 1924 - } 1925 - 1926 - #define REG_CP_WAIT_REG_MEM_3 0x00000003 1927 - #define CP_WAIT_REG_MEM_3_REF__MASK 0xffffffff 1928 - #define CP_WAIT_REG_MEM_3_REF__SHIFT 0 1929 - static inline uint32_t CP_WAIT_REG_MEM_3_REF(uint32_t val) 1930 - { 1931 - return ((val) << CP_WAIT_REG_MEM_3_REF__SHIFT) & CP_WAIT_REG_MEM_3_REF__MASK; 1932 - } 1933 - 1934 - #define REG_CP_WAIT_REG_MEM_4 0x00000004 1935 - #define CP_WAIT_REG_MEM_4_MASK__MASK 0xffffffff 1936 - #define CP_WAIT_REG_MEM_4_MASK__SHIFT 0 1937 - static inline uint32_t CP_WAIT_REG_MEM_4_MASK(uint32_t val) 1938 - { 1939 - return ((val) << CP_WAIT_REG_MEM_4_MASK__SHIFT) & CP_WAIT_REG_MEM_4_MASK__MASK; 1940 - } 1941 - 1942 - #define REG_CP_WAIT_REG_MEM_5 0x00000005 1943 - #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK 0xffffffff 1944 - #define CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT 0 1945 - static inline uint32_t CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(uint32_t val) 1946 - { 1947 - return ((val) << CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__SHIFT) & CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES__MASK; 1948 - } 1949 - 1950 - #define REG_CP_WAIT_TWO_REGS_0 0x00000000 1951 - #define CP_WAIT_TWO_REGS_0_REG0__MASK 0x0003ffff 1952 - #define CP_WAIT_TWO_REGS_0_REG0__SHIFT 0 1953 - static inline uint32_t CP_WAIT_TWO_REGS_0_REG0(uint32_t val) 1954 - { 1955 - return ((val) << CP_WAIT_TWO_REGS_0_REG0__SHIFT) & CP_WAIT_TWO_REGS_0_REG0__MASK; 1956 - } 1957 - 1958 - #define REG_CP_WAIT_TWO_REGS_1 0x00000001 1959 - #define CP_WAIT_TWO_REGS_1_REG1__MASK 0x0003ffff 1960 - #define CP_WAIT_TWO_REGS_1_REG1__SHIFT 0 1961 - static inline uint32_t CP_WAIT_TWO_REGS_1_REG1(uint32_t val) 1962 - { 1963 - return ((val) << CP_WAIT_TWO_REGS_1_REG1__SHIFT) & CP_WAIT_TWO_REGS_1_REG1__MASK; 1964 - } 1965 - 1966 - #define REG_CP_WAIT_TWO_REGS_2 0x00000002 1967 - #define CP_WAIT_TWO_REGS_2_REF__MASK 0xffffffff 1968 - #define CP_WAIT_TWO_REGS_2_REF__SHIFT 0 1969 - static inline uint32_t CP_WAIT_TWO_REGS_2_REF(uint32_t val) 1970 - { 1971 - return ((val) << CP_WAIT_TWO_REGS_2_REF__SHIFT) & CP_WAIT_TWO_REGS_2_REF__MASK; 1972 - } 1973 - 1974 - #define REG_CP_DISPATCH_COMPUTE_0 0x00000000 1975 - 1976 - #define REG_CP_DISPATCH_COMPUTE_1 0x00000001 1977 - #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff 1978 - #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0 1979 - static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val) 1980 - { 1981 - return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK; 1982 - } 1983 - 1984 - #define REG_CP_DISPATCH_COMPUTE_2 0x00000002 1985 - #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff 1986 - #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0 1987 - static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val) 1988 - { 1989 - return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK; 1990 - } 1991 - 1992 - #define REG_CP_DISPATCH_COMPUTE_3 0x00000003 1993 - #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff 1994 - #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0 1995 - static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val) 1996 - { 1997 - return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK; 1998 - } 1999 - 2000 - #define REG_CP_SET_RENDER_MODE_0 0x00000000 2001 - #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff 2002 - #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0 2003 - static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val) 2004 - { 2005 - return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK; 2006 - } 2007 - 2008 - #define REG_CP_SET_RENDER_MODE_1 0x00000001 2009 - #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff 2010 - #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0 2011 - static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val) 2012 - { 2013 - return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK; 2014 - } 2015 - 2016 - #define REG_CP_SET_RENDER_MODE_2 0x00000002 2017 - #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff 2018 - #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0 2019 - static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val) 2020 - { 2021 - return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK; 2022 - } 2023 - 2024 - #define REG_CP_SET_RENDER_MODE_3 0x00000003 2025 - #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008 2026 - #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010 2027 - 2028 - #define REG_CP_SET_RENDER_MODE_4 0x00000004 2029 - 2030 - #define REG_CP_SET_RENDER_MODE_5 0x00000005 2031 - #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff 2032 - #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0 2033 - static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val) 2034 - { 2035 - return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK; 2036 - } 2037 - 2038 - #define REG_CP_SET_RENDER_MODE_6 0x00000006 2039 - #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff 2040 - #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0 2041 - static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val) 2042 - { 2043 - return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK; 2044 - } 2045 - 2046 - #define REG_CP_SET_RENDER_MODE_7 0x00000007 2047 - #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff 2048 - #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0 2049 - static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val) 2050 - { 2051 - return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK; 2052 - } 2053 - 2054 - #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000 2055 - #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff 2056 - #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0 2057 - static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val) 2058 - { 2059 - return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK; 2060 - } 2061 - 2062 - #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001 2063 - #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff 2064 - #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0 2065 - static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) 2066 - { 2067 - return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK; 2068 - } 2069 - 2070 - #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 2071 - 2072 - #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 2073 - 2074 - #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 2075 - #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff 2076 - #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0 2077 - static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val) 2078 - { 2079 - return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK; 2080 - } 2081 - 2082 - #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 2083 - #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff 2084 - #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0 2085 - static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val) 2086 - { 2087 - return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK; 2088 - } 2089 - 2090 - #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006 2091 - #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff 2092 - #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0 2093 - static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val) 2094 - { 2095 - return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK; 2096 - } 2097 - 2098 - #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007 2099 - 2100 - #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000 2101 - 2102 - #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001 2103 - #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff 2104 - #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0 2105 - static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val) 2106 - { 2107 - return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK; 2108 - } 2109 - 2110 - #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002 2111 - #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff 2112 - #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0 2113 - static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val) 2114 - { 2115 - return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK; 2116 - } 2117 - 2118 - #define REG_CP_EVENT_WRITE_0 0x00000000 2119 - #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff 2120 - #define CP_EVENT_WRITE_0_EVENT__SHIFT 0 2121 - static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val) 2122 - { 2123 - return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK; 2124 - } 2125 - #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000 2126 - #define CP_EVENT_WRITE_0_IRQ 0x80000000 2127 - 2128 - #define REG_CP_EVENT_WRITE_1 0x00000001 2129 - #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff 2130 - #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0 2131 - static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val) 2132 - { 2133 - return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK; 2134 - } 2135 - 2136 - #define REG_CP_EVENT_WRITE_2 0x00000002 2137 - #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff 2138 - #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0 2139 - static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) 2140 - { 2141 - return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK; 2142 - } 2143 - 2144 - #define REG_CP_EVENT_WRITE_3 0x00000003 2145 - 2146 - #define REG_CP_EVENT_WRITE7_0 0x00000000 2147 - #define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff 2148 - #define CP_EVENT_WRITE7_0_EVENT__SHIFT 0 2149 - static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val) 2150 - { 2151 - return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK; 2152 - } 2153 - #define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000 2154 - #define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000 2155 - #define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF 0x00004000 2156 - #define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000 2157 - #define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000 2158 - #define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000 2159 - #define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000 2160 - #define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000 2161 - #define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20 2162 - static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val) 2163 - { 2164 - return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK; 2165 - } 2166 - #define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000 2167 - #define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24 2168 - static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val) 2169 - { 2170 - return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK; 2171 - } 2172 - #define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000 2173 - 2174 - #define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001 2175 - #define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff 2176 - #define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0 2177 - static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val) 2178 - { 2179 - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK; 2180 - } 2181 - 2182 - #define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002 2183 - #define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff 2184 - #define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0 2185 - static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val) 2186 - { 2187 - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK; 2188 - } 2189 - 2190 - #define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003 2191 - #define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff 2192 - #define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 2193 - static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) 2194 - { 2195 - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; 2196 - } 2197 - 2198 - #define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004 2199 - #define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff 2200 - #define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 2201 - static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) 2202 - { 2203 - return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; 2204 - } 2205 - 2206 - #define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001 2207 - #define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff 2208 - #define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0 2209 - static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val) 2210 - { 2211 - return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK; 2212 - } 2213 - 2214 - #define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003 2215 - #define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff 2216 - #define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 2217 - static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) 2218 - { 2219 - return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; 2220 - } 2221 - 2222 - #define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004 2223 - #define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff 2224 - #define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 2225 - static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) 2226 - { 2227 - return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; 2228 - } 2229 - 2230 - #define REG_CP_BLIT_0 0x00000000 2231 - #define CP_BLIT_0_OP__MASK 0x0000000f 2232 - #define CP_BLIT_0_OP__SHIFT 0 2233 - static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val) 2234 - { 2235 - return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK; 2236 - } 2237 - 2238 - #define REG_CP_BLIT_1 0x00000001 2239 - #define CP_BLIT_1_SRC_X1__MASK 0x00003fff 2240 - #define CP_BLIT_1_SRC_X1__SHIFT 0 2241 - static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val) 2242 - { 2243 - return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK; 2244 - } 2245 - #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000 2246 - #define CP_BLIT_1_SRC_Y1__SHIFT 16 2247 - static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val) 2248 - { 2249 - return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK; 2250 - } 2251 - 2252 - #define REG_CP_BLIT_2 0x00000002 2253 - #define CP_BLIT_2_SRC_X2__MASK 0x00003fff 2254 - #define CP_BLIT_2_SRC_X2__SHIFT 0 2255 - static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val) 2256 - { 2257 - return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK; 2258 - } 2259 - #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000 2260 - #define CP_BLIT_2_SRC_Y2__SHIFT 16 2261 - static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val) 2262 - { 2263 - return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK; 2264 - } 2265 - 2266 - #define REG_CP_BLIT_3 0x00000003 2267 - #define CP_BLIT_3_DST_X1__MASK 0x00003fff 2268 - #define CP_BLIT_3_DST_X1__SHIFT 0 2269 - static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val) 2270 - { 2271 - return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK; 2272 - } 2273 - #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000 2274 - #define CP_BLIT_3_DST_Y1__SHIFT 16 2275 - static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val) 2276 - { 2277 - return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK; 2278 - } 2279 - 2280 - #define REG_CP_BLIT_4 0x00000004 2281 - #define CP_BLIT_4_DST_X2__MASK 0x00003fff 2282 - #define CP_BLIT_4_DST_X2__SHIFT 0 2283 - static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val) 2284 - { 2285 - return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK; 2286 - } 2287 - #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000 2288 - #define CP_BLIT_4_DST_Y2__SHIFT 16 2289 - static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val) 2290 - { 2291 - return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK; 2292 - } 2293 - 2294 - #define REG_CP_EXEC_CS_0 0x00000000 2295 - 2296 - #define REG_CP_EXEC_CS_1 0x00000001 2297 - #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff 2298 - #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0 2299 - static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val) 2300 - { 2301 - return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK; 2302 - } 2303 - 2304 - #define REG_CP_EXEC_CS_2 0x00000002 2305 - #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff 2306 - #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0 2307 - static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val) 2308 - { 2309 - return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK; 2310 - } 2311 - 2312 - #define REG_CP_EXEC_CS_3 0x00000003 2313 - #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff 2314 - #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0 2315 - static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) 2316 - { 2317 - return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK; 2318 - } 2319 - 2320 - #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 2321 - 2322 - #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 2323 - #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff 2324 - #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 2325 - static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val) 2326 - { 2327 - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK; 2328 - } 2329 - 2330 - #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002 2331 - #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc 2332 - #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2 2333 - static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val) 2334 - { 2335 - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK; 2336 - } 2337 - #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000 2338 - #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12 2339 - static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val) 2340 - { 2341 - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK; 2342 - } 2343 - #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000 2344 - #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22 2345 - static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) 2346 - { 2347 - return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; 2348 - } 2349 - 2350 - #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 2351 - #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff 2352 - #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 2353 - static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val) 2354 - { 2355 - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK; 2356 - } 2357 - 2358 - #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002 2359 - #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff 2360 - #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0 2361 - static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val) 2362 - { 2363 - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK; 2364 - } 2365 - 2366 - #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003 2367 - #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc 2368 - #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2 2369 - static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val) 2370 - { 2371 - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK; 2372 - } 2373 - #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000 2374 - #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12 2375 - static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val) 2376 - { 2377 - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK; 2378 - } 2379 - #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000 2380 - #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22 2381 - static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val) 2382 - { 2383 - return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK; 2384 - } 2385 - 2386 - #define REG_A6XX_CP_SET_MARKER_0 0x00000000 2387 - #define A6XX_CP_SET_MARKER_0_MODE__MASK 0x000001ff 2388 - #define A6XX_CP_SET_MARKER_0_MODE__SHIFT 0 2389 - static inline uint32_t A6XX_CP_SET_MARKER_0_MODE(enum a6xx_marker val) 2390 - { 2391 - return ((val) << A6XX_CP_SET_MARKER_0_MODE__SHIFT) & A6XX_CP_SET_MARKER_0_MODE__MASK; 2392 - } 2393 - #define A6XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f 2394 - #define A6XX_CP_SET_MARKER_0_MARKER__SHIFT 0 2395 - static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val) 2396 - { 2397 - return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK; 2398 - } 2399 - 2400 - #define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*(i0)) 2401 - 2402 - static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } 2403 - #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff 2404 - #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 2405 - static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) 2406 - { 2407 - return ((val) << A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK; 2408 - } 2409 - 2410 - static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; } 2411 - #define A6XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff 2412 - #define A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0 2413 - static inline uint32_t A6XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val) 2414 - { 2415 - return ((val) << A6XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A6XX_CP_SET_PSEUDO_REG__1_LO__MASK; 2416 - } 2417 - 2418 - static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; } 2419 - #define A6XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff 2420 - #define A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0 2421 - static inline uint32_t A6XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val) 2422 - { 2423 - return ((val) << A6XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A6XX_CP_SET_PSEUDO_REG__2_HI__MASK; 2424 - } 2425 - 2426 - #define REG_A6XX_CP_REG_TEST_0 0x00000000 2427 - #define A6XX_CP_REG_TEST_0_REG__MASK 0x0003ffff 2428 - #define A6XX_CP_REG_TEST_0_REG__SHIFT 0 2429 - static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val) 2430 - { 2431 - return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK; 2432 - } 2433 - #define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff 2434 - #define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0 2435 - static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val) 2436 - { 2437 - return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK; 2438 - } 2439 - #define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000 2440 - #define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18 2441 - static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val) 2442 - { 2443 - return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK; 2444 - } 2445 - #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 2446 - #define A6XX_CP_REG_TEST_0_BIT__SHIFT 20 2447 - static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val) 2448 - { 2449 - return ((val) << A6XX_CP_REG_TEST_0_BIT__SHIFT) & A6XX_CP_REG_TEST_0_BIT__MASK; 2450 - } 2451 - #define A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME 0x02000000 2452 - #define A6XX_CP_REG_TEST_0_PRED_BIT__MASK 0x7c000000 2453 - #define A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT 26 2454 - static inline uint32_t A6XX_CP_REG_TEST_0_PRED_BIT(uint32_t val) 2455 - { 2456 - return ((val) << A6XX_CP_REG_TEST_0_PRED_BIT__SHIFT) & A6XX_CP_REG_TEST_0_PRED_BIT__MASK; 2457 - } 2458 - #define A6XX_CP_REG_TEST_0_PRED_UPDATE 0x80000000 2459 - 2460 - #define REG_A6XX_CP_REG_TEST_PRED_MASK 0x00000001 2461 - 2462 - #define REG_A6XX_CP_REG_TEST_PRED_VAL 0x00000002 2463 - 2464 - #define REG_CP_COND_REG_EXEC_0 0x00000000 2465 - #define CP_COND_REG_EXEC_0_REG0__MASK 0x0003ffff 2466 - #define CP_COND_REG_EXEC_0_REG0__SHIFT 0 2467 - static inline uint32_t CP_COND_REG_EXEC_0_REG0(uint32_t val) 2468 - { 2469 - return ((val) << CP_COND_REG_EXEC_0_REG0__SHIFT) & CP_COND_REG_EXEC_0_REG0__MASK; 2470 - } 2471 - #define CP_COND_REG_EXEC_0_PRED_BIT__MASK 0x007c0000 2472 - #define CP_COND_REG_EXEC_0_PRED_BIT__SHIFT 18 2473 - static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val) 2474 - { 2475 - return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK; 2476 - } 2477 - #define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000 2478 - #define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000 2479 - #define CP_COND_REG_EXEC_0_BINNING 0x02000000 2480 - #define CP_COND_REG_EXEC_0_GMEM 0x04000000 2481 - #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000 2482 - #define CP_COND_REG_EXEC_0_BV 0x02000000 2483 - #define CP_COND_REG_EXEC_0_BR 0x04000000 2484 - #define CP_COND_REG_EXEC_0_LPAC 0x08000000 2485 - #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000 2486 - #define CP_COND_REG_EXEC_0_MODE__SHIFT 28 2487 - static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) 2488 - { 2489 - return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK; 2490 - } 2491 - 2492 - #define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001 2493 - #define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff 2494 - #define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 2495 - static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) 2496 - { 2497 - return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK; 2498 - } 2499 - 2500 - #define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001 2501 - #define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff 2502 - #define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0 2503 - static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val) 2504 - { 2505 - return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK; 2506 - } 2507 - #define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000 2508 - 2509 - #define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001 2510 - #define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff 2511 - #define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 2512 - static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) 2513 - { 2514 - return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; 2515 - } 2516 - 2517 - #define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001 2518 - #define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff 2519 - #define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0 2520 - static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val) 2521 - { 2522 - return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK; 2523 - } 2524 - 2525 - #define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001 2526 - #define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff 2527 - #define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 2528 - static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) 2529 - { 2530 - return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; 2531 - } 2532 - 2533 - #define REG_CP_COND_REG_EXEC_2 0x00000002 2534 - #define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff 2535 - #define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0 2536 - static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val) 2537 - { 2538 - return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK; 2539 - } 2540 - 2541 - #define REG_CP_COND_EXEC_0 0x00000000 2542 - #define CP_COND_EXEC_0_ADDR0_LO__MASK 0xffffffff 2543 - #define CP_COND_EXEC_0_ADDR0_LO__SHIFT 0 2544 - static inline uint32_t CP_COND_EXEC_0_ADDR0_LO(uint32_t val) 2545 - { 2546 - return ((val) << CP_COND_EXEC_0_ADDR0_LO__SHIFT) & CP_COND_EXEC_0_ADDR0_LO__MASK; 2547 - } 2548 - 2549 - #define REG_CP_COND_EXEC_1 0x00000001 2550 - #define CP_COND_EXEC_1_ADDR0_HI__MASK 0xffffffff 2551 - #define CP_COND_EXEC_1_ADDR0_HI__SHIFT 0 2552 - static inline uint32_t CP_COND_EXEC_1_ADDR0_HI(uint32_t val) 2553 - { 2554 - return ((val) << CP_COND_EXEC_1_ADDR0_HI__SHIFT) & CP_COND_EXEC_1_ADDR0_HI__MASK; 2555 - } 2556 - 2557 - #define REG_CP_COND_EXEC_2 0x00000002 2558 - #define CP_COND_EXEC_2_ADDR1_LO__MASK 0xffffffff 2559 - #define CP_COND_EXEC_2_ADDR1_LO__SHIFT 0 2560 - static inline uint32_t CP_COND_EXEC_2_ADDR1_LO(uint32_t val) 2561 - { 2562 - return ((val) << CP_COND_EXEC_2_ADDR1_LO__SHIFT) & CP_COND_EXEC_2_ADDR1_LO__MASK; 2563 - } 2564 - 2565 - #define REG_CP_COND_EXEC_3 0x00000003 2566 - #define CP_COND_EXEC_3_ADDR1_HI__MASK 0xffffffff 2567 - #define CP_COND_EXEC_3_ADDR1_HI__SHIFT 0 2568 - static inline uint32_t CP_COND_EXEC_3_ADDR1_HI(uint32_t val) 2569 - { 2570 - return ((val) << CP_COND_EXEC_3_ADDR1_HI__SHIFT) & CP_COND_EXEC_3_ADDR1_HI__MASK; 2571 - } 2572 - 2573 - #define REG_CP_COND_EXEC_4 0x00000004 2574 - #define CP_COND_EXEC_4_REF__MASK 0xffffffff 2575 - #define CP_COND_EXEC_4_REF__SHIFT 0 2576 - static inline uint32_t CP_COND_EXEC_4_REF(uint32_t val) 2577 - { 2578 - return ((val) << CP_COND_EXEC_4_REF__SHIFT) & CP_COND_EXEC_4_REF__MASK; 2579 - } 2580 - 2581 - #define REG_CP_COND_EXEC_5 0x00000005 2582 - #define CP_COND_EXEC_5_DWORDS__MASK 0xffffffff 2583 - #define CP_COND_EXEC_5_DWORDS__SHIFT 0 2584 - static inline uint32_t CP_COND_EXEC_5_DWORDS(uint32_t val) 2585 - { 2586 - return ((val) << CP_COND_EXEC_5_DWORDS__SHIFT) & CP_COND_EXEC_5_DWORDS__MASK; 2587 - } 2588 - 2589 - #define REG_CP_SET_CTXSWITCH_IB_0 0x00000000 2590 - #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK 0xffffffff 2591 - #define CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT 0 2592 - static inline uint32_t CP_SET_CTXSWITCH_IB_0_ADDR_LO(uint32_t val) 2593 - { 2594 - return ((val) << CP_SET_CTXSWITCH_IB_0_ADDR_LO__SHIFT) & CP_SET_CTXSWITCH_IB_0_ADDR_LO__MASK; 2595 - } 2596 - 2597 - #define REG_CP_SET_CTXSWITCH_IB_1 0x00000001 2598 - #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK 0xffffffff 2599 - #define CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT 0 2600 - static inline uint32_t CP_SET_CTXSWITCH_IB_1_ADDR_HI(uint32_t val) 2601 - { 2602 - return ((val) << CP_SET_CTXSWITCH_IB_1_ADDR_HI__SHIFT) & CP_SET_CTXSWITCH_IB_1_ADDR_HI__MASK; 2603 - } 2604 - 2605 - #define REG_CP_SET_CTXSWITCH_IB_2 0x00000002 2606 - #define CP_SET_CTXSWITCH_IB_2_DWORDS__MASK 0x000fffff 2607 - #define CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT 0 2608 - static inline uint32_t CP_SET_CTXSWITCH_IB_2_DWORDS(uint32_t val) 2609 - { 2610 - return ((val) << CP_SET_CTXSWITCH_IB_2_DWORDS__SHIFT) & CP_SET_CTXSWITCH_IB_2_DWORDS__MASK; 2611 - } 2612 - #define CP_SET_CTXSWITCH_IB_2_TYPE__MASK 0x00300000 2613 - #define CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT 20 2614 - static inline uint32_t CP_SET_CTXSWITCH_IB_2_TYPE(enum ctxswitch_ib val) 2615 - { 2616 - return ((val) << CP_SET_CTXSWITCH_IB_2_TYPE__SHIFT) & CP_SET_CTXSWITCH_IB_2_TYPE__MASK; 2617 - } 2618 - 2619 - #define REG_CP_REG_WRITE_0 0x00000000 2620 - #define CP_REG_WRITE_0_TRACKER__MASK 0x0000000f 2621 - #define CP_REG_WRITE_0_TRACKER__SHIFT 0 2622 - static inline uint32_t CP_REG_WRITE_0_TRACKER(enum reg_tracker val) 2623 - { 2624 - return ((val) << CP_REG_WRITE_0_TRACKER__SHIFT) & CP_REG_WRITE_0_TRACKER__MASK; 2625 - } 2626 - 2627 - #define REG_CP_REG_WRITE_1 0x00000001 2628 - 2629 - #define REG_CP_REG_WRITE_2 0x00000002 2630 - 2631 - #define REG_CP_SMMU_TABLE_UPDATE_0 0x00000000 2632 - #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK 0xffffffff 2633 - #define CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT 0 2634 - static inline uint32_t CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(uint32_t val) 2635 - { 2636 - return ((val) << CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__SHIFT) & CP_SMMU_TABLE_UPDATE_0_TTBR0_LO__MASK; 2637 - } 2638 - 2639 - #define REG_CP_SMMU_TABLE_UPDATE_1 0x00000001 2640 - #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK 0x0000ffff 2641 - #define CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT 0 2642 - static inline uint32_t CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(uint32_t val) 2643 - { 2644 - return ((val) << CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__SHIFT) & CP_SMMU_TABLE_UPDATE_1_TTBR0_HI__MASK; 2645 - } 2646 - #define CP_SMMU_TABLE_UPDATE_1_ASID__MASK 0xffff0000 2647 - #define CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT 16 2648 - static inline uint32_t CP_SMMU_TABLE_UPDATE_1_ASID(uint32_t val) 2649 - { 2650 - return ((val) << CP_SMMU_TABLE_UPDATE_1_ASID__SHIFT) & CP_SMMU_TABLE_UPDATE_1_ASID__MASK; 2651 - } 2652 - 2653 - #define REG_CP_SMMU_TABLE_UPDATE_2 0x00000002 2654 - #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK 0xffffffff 2655 - #define CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT 0 2656 - static inline uint32_t CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(uint32_t val) 2657 - { 2658 - return ((val) << CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__SHIFT) & CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR__MASK; 2659 - } 2660 - 2661 - #define REG_CP_SMMU_TABLE_UPDATE_3 0x00000003 2662 - #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK 0xffffffff 2663 - #define CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT 0 2664 - static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) 2665 - { 2666 - return ((val) << CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__SHIFT) & CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK__MASK; 2667 - } 2668 - 2669 - #define REG_CP_START_BIN_BIN_COUNT 0x00000000 2670 - 2671 - #define REG_CP_START_BIN_PREFIX_ADDR 0x00000001 2672 - 2673 - #define REG_CP_START_BIN_PREFIX_DWORDS 0x00000003 2674 - 2675 - #define REG_CP_START_BIN_BODY_DWORDS 0x00000004 2676 - 2677 - #define REG_CP_WAIT_TIMESTAMP_0 0x00000000 2678 - #define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003 2679 - #define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0 2680 - static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val) 2681 - { 2682 - return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK; 2683 - } 2684 - #define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010 2685 - #define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4 2686 - static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val) 2687 - { 2688 - return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK; 2689 - } 2690 - 2691 - #define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001 2692 - 2693 - #define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001 2694 - 2695 - #define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003 2696 - 2697 - #define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004 2698 - 2699 - #define REG_CP_BV_BR_COUNT_OPS_0 0x00000000 2700 - #define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f 2701 - #define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0 2702 - static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val) 2703 - { 2704 - return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK; 2705 - } 2706 - 2707 - #define REG_CP_BV_BR_COUNT_OPS_1 0x00000001 2708 - #define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff 2709 - #define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0 2710 - static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val) 2711 - { 2712 - return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK; 2713 - } 2714 - 2715 - #define REG_CP_MODIFY_TIMESTAMP_0 0x00000000 2716 - #define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff 2717 - #define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0 2718 - static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val) 2719 - { 2720 - return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK; 2721 - } 2722 - #define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000 2723 - #define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28 2724 - static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val) 2725 - { 2726 - return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK; 2727 - } 2728 - 2729 - #define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000 2730 - #define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f 2731 - #define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0 2732 - static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val) 2733 - { 2734 - return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK; 2735 - } 2736 - 2737 - #define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001 2738 - #define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f 2739 - #define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0 2740 - static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val) 2741 - { 2742 - return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK; 2743 - } 2744 - 2745 - #define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002 2746 - #define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff 2747 - #define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0 2748 - static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val) 2749 - { 2750 - return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK; 2751 - } 2752 - 2753 - #define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003 2754 - #define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff 2755 - #define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0 2756 - static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val) 2757 - { 2758 - return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK; 2759 - } 2760 - 2761 - #define REG_CP_THREAD_CONTROL_0 0x00000000 2762 - #define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003 2763 - #define CP_THREAD_CONTROL_0_THREAD__SHIFT 0 2764 - static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val) 2765 - { 2766 - return ((val) << CP_THREAD_CONTROL_0_THREAD__SHIFT) & CP_THREAD_CONTROL_0_THREAD__MASK; 2767 - } 2768 - #define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000 2769 - #define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000 2770 - 2771 - #define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000 2772 - 2773 - #define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002 2774 - #define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff 2775 - #define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0 2776 - static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val) 2777 - { 2778 - return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK; 2779 - } 2780 - #define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000 2781 - #define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20 2782 - static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val) 2783 - { 2784 - return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK; 2785 - } 2786 - 2787 - #define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003 2788 - #define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff 2789 - #define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0 2790 - static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val) 2791 - { 2792 - return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK; 2793 - } 2794 - 2795 - #define REG_CP_RESET_CONTEXT_STATE_0 0x00000000 2796 - #define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001 2797 - #define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002 2798 - #define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004 2799 - 2800 - #ifdef __cplusplus 2801 - #endif 2802 - 2803 - #endif /* ADRENO_PM4_XML */

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