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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
powercap: intel_rapl: Move MSR primitives to MSR driver
MSR-specific RAPL primitives differ from those used by TPMI and MMIO
interfaces. Keeping them in the common driver requires
interface-specific handling logic and makes the common layer
unnecessarily complex.
Move the MSR primitive definitions and associated bitmasks into the
MSR interface driver. This change includes:
1. Move MSR-specific bitmask definitions to RAPL MSR driver.
2. Add MSR-local struct rapl_primitive_info instance and assign it to
priv->rpi during MSR probe.
3. Remove the primitive assignment logic from rapl_config() in the
common driver.
No functional changes are intended.
Co-developed-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Link: https://patch.msgid.link/20260331211950.3329932-7-sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
authored by
Kuppuswamy Sathyanarayanan
and committed by
Rafael J. Wysocki
b0ee5110
d7a718ff
+99
-105
-105
drivers/powercap/intel_rapl_common.c
-105
drivers/powercap/intel_rapl_common.c
···
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#include <asm/intel-family.h>
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#include <asm/msr.h>
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-
/* bitmasks for RAPL MSRs, used by primitive access functions */
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#define ENERGY_STATUS_MASK GENMASK(31, 0)
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-
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#define POWER_LIMIT1_MASK GENMASK(14, 0)
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#define POWER_LIMIT1_ENABLE BIT(15)
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#define POWER_LIMIT1_CLAMP BIT(16)
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-
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#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
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#define POWER_LIMIT2_ENABLE BIT_ULL(47)
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#define POWER_LIMIT2_CLAMP BIT_ULL(48)
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#define POWER_HIGH_LOCK BIT_ULL(63)
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#define POWER_LOW_LOCK BIT(31)
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-
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#define POWER_LIMIT4_MASK GENMASK(12, 0)
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-
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#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
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#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
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#define POWER_UNIT_OFFSET 0x00
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#define POWER_UNIT_MASK GENMASK(3, 0)
···
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#define TIME_UNIT_OFFSET 0x10
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#define TIME_UNIT_MASK GENMASK(19, 16)
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-
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#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
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#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
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#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
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#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
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49
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#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
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#define PP_POLICY_MASK GENMASK(4, 0)
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-
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/*
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* SPR has different layout for Psys Domain PowerLimit registers.
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* There are 17 bits of PL1 and PL2 instead of 15 bits.
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* The Enable bits and TimeWindow bits are also shifted as a result.
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*/
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#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
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#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
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#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
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#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
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/* Non HW constants */
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#define RAPL_PRIMITIVE_DUMMY BIT(2)
···
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return div64_u64(value, scale);
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}
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/* RAPL primitives for MSR and MMIO I/F */
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static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
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/* name, mask, shift, msr index, unit divisor */
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[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
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RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
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[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
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RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
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[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
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POWER_INFO_THERMAL_SPEC_MASK, 0,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
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POWER_INFO_MAX_TIME_WIN_MASK, 48,
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RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
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[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
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PERF_STATUS_THROTTLE_TIME_MASK, 0,
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RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
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[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
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RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
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[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
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32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
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17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
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0),
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[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
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49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
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0),
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[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
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19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
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51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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};
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static struct rapl_primitive_info *get_rpi(struct rapl_package *rp, int prim)
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{
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struct rapl_primitive_info *rpi = rp->priv->rpi;
···
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static int rapl_config(struct rapl_package *rp)
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{
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switch (rp->priv->type) {
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/* MMIO I/F shares the same register layout as MSR registers */
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case RAPL_IF_MSR:
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rp->priv->rpi = rpi_msr;
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break;
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default:
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return -EINVAL;
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}
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/* defaults_msr can be NULL on unsupported platforms */
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if (!rp->priv->defaults || !rp->priv->rpi)
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return -ENODEV;
+99
drivers/powercap/intel_rapl_msr.c
+99
drivers/powercap/intel_rapl_msr.c
···
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#define TIME_UNIT_OFFSET 0x10
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#define TIME_UNIT_MASK GENMASK(19, 16)
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/* bitmasks for RAPL MSRs, used by primitive access functions */
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#define ENERGY_STATUS_MASK GENMASK(31, 0)
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#define POWER_LIMIT1_MASK GENMASK(14, 0)
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#define POWER_LIMIT1_ENABLE BIT(15)
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#define POWER_LIMIT1_CLAMP BIT(16)
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+
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#define POWER_LIMIT2_MASK GENMASK_ULL(46, 32)
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#define POWER_LIMIT2_ENABLE BIT_ULL(47)
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#define POWER_LIMIT2_CLAMP BIT_ULL(48)
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#define POWER_HIGH_LOCK BIT_ULL(63)
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#define POWER_LOW_LOCK BIT(31)
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+
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#define POWER_LIMIT4_MASK GENMASK(12, 0)
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#define TIME_WINDOW1_MASK GENMASK_ULL(23, 17)
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#define TIME_WINDOW2_MASK GENMASK_ULL(55, 49)
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#define POWER_INFO_MAX_MASK GENMASK_ULL(46, 32)
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#define POWER_INFO_MIN_MASK GENMASK_ULL(30, 16)
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#define POWER_INFO_MAX_TIME_WIN_MASK GENMASK_ULL(53, 48)
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#define POWER_INFO_THERMAL_SPEC_MASK GENMASK(14, 0)
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#define PERF_STATUS_THROTTLE_TIME_MASK GENMASK(31, 0)
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#define PP_POLICY_MASK GENMASK(4, 0)
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+
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/*
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* SPR has different layout for Psys Domain PowerLimit registers.
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* There are 17 bits of PL1 and PL2 instead of 15 bits.
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* The Enable bits and TimeWindow bits are also shifted as a result.
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*/
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#define PSYS_POWER_LIMIT1_MASK GENMASK_ULL(16, 0)
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#define PSYS_POWER_LIMIT1_ENABLE BIT(17)
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#define PSYS_POWER_LIMIT2_MASK GENMASK_ULL(48, 32)
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#define PSYS_POWER_LIMIT2_ENABLE BIT_ULL(49)
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#define PSYS_TIME_WINDOW1_MASK GENMASK_ULL(25, 19)
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#define PSYS_TIME_WINDOW2_MASK GENMASK_ULL(57, 51)
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/* Sideband MBI registers */
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#define IOSF_CPU_POWER_BUDGET_CTL_BYT 0x02
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#define IOSF_CPU_POWER_BUDGET_CTL_TNG 0xDF
···
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return value ? value * rd->time_unit : rd->time_unit;
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}
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/* RAPL primitives for MSR I/F */
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static struct rapl_primitive_info rpi_msr[NR_RAPL_PRIMITIVES] = {
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/* name, mask, shift, msr index, unit divisor */
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[POWER_LIMIT1] = PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT2] = PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[POWER_LIMIT4] = PRIMITIVE_INFO_INIT(POWER_LIMIT4, POWER_LIMIT4_MASK, 0,
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RAPL_DOMAIN_REG_PL4, POWER_UNIT, 0),
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[ENERGY_COUNTER] = PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
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RAPL_DOMAIN_REG_STATUS, ENERGY_UNIT, 0),
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[FW_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_LOW_LOCK, 31,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[FW_HIGH_LOCK] = PRIMITIVE_INFO_INIT(FW_LOCK, POWER_HIGH_LOCK, 63,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL1_ENABLE] = PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL1_CLAMP] = PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_ENABLE] = PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[PL2_CLAMP] = PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
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RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT, 0),
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[TIME_WINDOW1] = PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[TIME_WINDOW2] = PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
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RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[THERMAL_SPEC_POWER] = PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER,
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POWER_INFO_THERMAL_SPEC_MASK, 0,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MAX_POWER] = PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MIN_POWER] = PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
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RAPL_DOMAIN_REG_INFO, POWER_UNIT, 0),
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[MAX_TIME_WINDOW] = PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW,
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POWER_INFO_MAX_TIME_WIN_MASK, 48,
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RAPL_DOMAIN_REG_INFO, TIME_UNIT, 0),
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[THROTTLED_TIME] = PRIMITIVE_INFO_INIT(THROTTLED_TIME,
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PERF_STATUS_THROTTLE_TIME_MASK, 0,
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RAPL_DOMAIN_REG_PERF, TIME_UNIT, 0),
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[PRIORITY_LEVEL] = PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
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RAPL_DOMAIN_REG_POLICY, ARBITRARY_UNIT, 0),
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[PSYS_POWER_LIMIT1] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT1, PSYS_POWER_LIMIT1_MASK, 0,
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RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[PSYS_POWER_LIMIT2] = PRIMITIVE_INFO_INIT(PSYS_POWER_LIMIT2, PSYS_POWER_LIMIT2_MASK,
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32, RAPL_DOMAIN_REG_LIMIT, POWER_UNIT, 0),
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[PSYS_PL1_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL1_ENABLE, PSYS_POWER_LIMIT1_ENABLE,
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17, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
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0),
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[PSYS_PL2_ENABLE] = PRIMITIVE_INFO_INIT(PSYS_PL2_ENABLE, PSYS_POWER_LIMIT2_ENABLE,
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49, RAPL_DOMAIN_REG_LIMIT, ARBITRARY_UNIT,
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0),
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[PSYS_TIME_WINDOW1] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW1, PSYS_TIME_WINDOW1_MASK,
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19, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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[PSYS_TIME_WINDOW2] = PRIMITIVE_INFO_INIT(PSYS_TIME_WINDOW2, PSYS_TIME_WINDOW2_MASK,
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51, RAPL_DOMAIN_REG_LIMIT, TIME_UNIT, 0),
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};
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+
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static const struct rapl_defaults rapl_defaults_core = {
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.floor_freq_reg_addr = 0,
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.check_unit = rapl_default_check_unit,
···
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rapl_msr_priv->read_raw = rapl_msr_read_raw;
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rapl_msr_priv->write_raw = rapl_msr_write_raw;
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rapl_msr_priv->defaults = (const struct rapl_defaults *)pdev->dev.platform_data;
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rapl_msr_priv->rpi = rpi_msr;
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if (id) {
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rapl_msr_priv->limits[RAPL_DOMAIN_PACKAGE] |= BIT(POWER_LIMIT4);