+2 -6

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 914 914 amdgpu_wreg64_t pcie_wreg64; 915 915 amdgpu_rreg64_ext_t pcie_rreg64_ext; 916 916 amdgpu_wreg64_ext_t pcie_wreg64_ext; 917 917 - /* protects concurrent gc_cac register access */ 918 918 - spinlock_t gc_cac_idx_lock; 919 919 - amdgpu_rreg_t gc_cac_rreg; 920 920 - amdgpu_wreg_t gc_cac_wreg; 921 917 /* protects concurrent se_cac register access */ 922 918 spinlock_t se_cac_idx_lock; 923 919 amdgpu_rreg_t se_cac_rreg; ··· 1332 1336 #define WREG32_UVD_CTX(reg, v) amdgpu_reg_uvd_ctx_wr32(adev, (reg), (v)) 1333 1337 #define RREG32_DIDT(reg) amdgpu_reg_didt_rd32(adev, (reg)) 1334 1338 #define WREG32_DIDT(reg, v) amdgpu_reg_didt_wr32(adev, (reg), (v)) 1335 1335 - #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg)) 1336 1336 - #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v)) 1339 1339 + #define RREG32_GC_CAC(reg) amdgpu_reg_gc_cac_rd32(adev, (reg)) 1340 1340 + #define WREG32_GC_CAC(reg, v) amdgpu_reg_gc_cac_wr32(adev, (reg), (v)) 1337 1341 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg)) 1338 1342 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v)) 1339 1343 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))

-3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

reviewed

··· 3842 3842 adev->pcie_wreg64 = &amdgpu_invalid_wreg64; 3843 3843 adev->pcie_rreg64_ext = &amdgpu_invalid_rreg64_ext; 3844 3844 adev->pcie_wreg64_ext = &amdgpu_invalid_wreg64_ext; 3845 3845 - adev->gc_cac_rreg = &amdgpu_invalid_rreg; 3846 3846 - adev->gc_cac_wreg = &amdgpu_invalid_wreg; 3847 3845 adev->audio_endpt_rreg = &amdgpu_block_invalid_rreg; 3848 3846 adev->audio_endpt_wreg = &amdgpu_block_invalid_wreg; 3849 3847 ··· 3889 3891 3890 3892 spin_lock_init(&adev->mmio_idx_lock); 3891 3893 spin_lock_init(&adev->pcie_idx_lock); 3892 3892 - spin_lock_init(&adev->gc_cac_idx_lock); 3893 3894 spin_lock_init(&adev->se_cac_idx_lock); 3894 3895 spin_lock_init(&adev->audio_endpt_idx_lock); 3895 3896 spin_lock_init(&adev->mm_stats.lock);

+24

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c

reviewed

··· 46 46 spin_lock_init(&adev->reg.didt.lock); 47 47 adev->reg.didt.rreg = NULL; 48 48 adev->reg.didt.wreg = NULL; 49 49 + 50 50 + spin_lock_init(&adev->reg.gc_cac.lock); 51 51 + adev->reg.gc_cac.rreg = NULL; 52 52 + adev->reg.gc_cac.wreg = NULL; 49 53 } 50 54 51 55 uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg) ··· 107 103 return; 108 104 } 109 105 adev->reg.didt.wreg(adev, reg, v); 106 106 + } 107 107 + 108 108 + uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg) 109 109 + { 110 110 + if (!adev->reg.gc_cac.rreg) { 111 111 + dev_err_once(adev->dev, "GC_CAC register read not supported\n"); 112 112 + return 0; 113 113 + } 114 114 + return adev->reg.gc_cac.rreg(adev, reg); 115 115 + } 116 116 + 117 117 + void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 118 118 + uint32_t v) 119 119 + { 120 120 + if (!adev->reg.gc_cac.wreg) { 121 121 + dev_err_once(adev->dev, 122 122 + "GC_CAC register write not supported\n"); 123 123 + return; 124 124 + } 125 125 + adev->reg.gc_cac.wreg(adev, reg, v); 110 126 } 111 127 112 128 /*

+4

drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h

reviewed

··· 42 42 struct amdgpu_reg_ind smc; 43 43 struct amdgpu_reg_ind uvd_ctx; 44 44 struct amdgpu_reg_ind didt; 45 45 + struct amdgpu_reg_ind gc_cac; 45 46 }; 46 47 47 48 void amdgpu_reg_access_init(struct amdgpu_device *adev); ··· 52 51 void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 53 52 uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg); 54 53 void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v); 54 54 + uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg); 55 55 + void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg, 56 56 + uint32_t v); 55 57 56 58 typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t); 57 59 typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);

+6 -6

drivers/gpu/drm/amd/amdgpu/soc15.c

reviewed

··· 298 298 unsigned long flags; 299 299 u32 r; 300 300 301 301 - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 301 301 + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 302 302 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 303 303 r = RREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA); 304 304 - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 304 304 + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 305 305 return r; 306 306 } 307 307 ··· 309 309 { 310 310 unsigned long flags; 311 311 312 312 - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 312 312 + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 313 313 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, (reg)); 314 314 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA, (v)); 315 315 - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 315 315 + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 316 316 } 317 317 318 318 static u32 soc15_se_cac_rreg(struct amdgpu_device *adev, u32 reg) ··· 973 973 adev->reg.uvd_ctx.wreg = &soc15_uvd_ctx_wreg; 974 974 adev->reg.didt.rreg = &soc15_didt_rreg; 975 975 adev->reg.didt.wreg = &soc15_didt_wreg; 976 976 - adev->gc_cac_rreg = &soc15_gc_cac_rreg; 977 977 - adev->gc_cac_wreg = &soc15_gc_cac_wreg; 976 976 + adev->reg.gc_cac.rreg = &soc15_gc_cac_rreg; 977 977 + adev->reg.gc_cac.wreg = &soc15_gc_cac_wreg; 978 978 adev->se_cac_rreg = &soc15_se_cac_rreg; 979 979 adev->se_cac_wreg = &soc15_se_cac_wreg; 980 980

+6 -6

drivers/gpu/drm/amd/amdgpu/vi.c

reviewed

··· 416 416 unsigned long flags; 417 417 u32 r; 418 418 419 419 - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 419 419 + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 420 420 WREG32(mmGC_CAC_IND_INDEX, (reg)); 421 421 r = RREG32(mmGC_CAC_IND_DATA); 422 422 - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 422 422 + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 423 423 return r; 424 424 } 425 425 ··· 427 427 { 428 428 unsigned long flags; 429 429 430 430 - spin_lock_irqsave(&adev->gc_cac_idx_lock, flags); 430 430 + spin_lock_irqsave(&adev->reg.gc_cac.lock, flags); 431 431 WREG32(mmGC_CAC_IND_INDEX, (reg)); 432 432 WREG32(mmGC_CAC_IND_DATA, (v)); 433 433 - spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags); 433 433 + spin_unlock_irqrestore(&adev->reg.gc_cac.lock, flags); 434 434 } 435 435 436 436 ··· 1466 1466 adev->reg.uvd_ctx.wreg = &vi_uvd_ctx_wreg; 1467 1467 adev->reg.didt.rreg = &vi_didt_rreg; 1468 1468 adev->reg.didt.wreg = &vi_didt_wreg; 1469 1469 - adev->gc_cac_rreg = &vi_gc_cac_rreg; 1470 1470 - adev->gc_cac_wreg = &vi_gc_cac_wreg; 1469 1469 + adev->reg.gc_cac.rreg = &vi_gc_cac_rreg; 1470 1470 + adev->reg.gc_cac.wreg = &vi_gc_cac_wreg; 1471 1471 1472 1472 adev->asic_funcs = &vi_asic_funcs; 1473 1473