tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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pinctrl: ocelot: Extend support for lan9645xf family

Extend pinctrl-ocelot driver to support the lan9645xf chip family.

Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Reviewed-by: Daniel Machon <daniel.machon@microchip.com>
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>

authored by

Jens Emil Schulz Østergaard and committed by
Linus Walleij b20d212f 96bfeba8

+177
+177
drivers/pinctrl/pinctrl-ocelot.c
··· 97 97 FUNC_FC_SHRD20, 98 98 FUNC_FUSA, 99 99 FUNC_GPIO, 100 + FUNC_I2C, 101 + FUNC_I2C_Sa, 100 102 FUNC_IB_TRG_a, 101 103 FUNC_IB_TRG_b, 102 104 FUNC_IB_TRG_c, ··· 114 112 FUNC_IRQ1, 115 113 FUNC_IRQ1_IN, 116 114 FUNC_IRQ1_OUT, 115 + FUNC_IRQ2, 117 116 FUNC_IRQ3, 118 117 FUNC_IRQ4, 119 118 FUNC_EXT_IRQ, 119 + FUNC_MACLED, 120 120 FUNC_MIIM, 121 121 FUNC_MIIM_a, 122 122 FUNC_MIIM_b, ··· 130 126 FUNC_OB_TRG_a, 131 127 FUNC_OB_TRG_b, 132 128 FUNC_PHY_LED, 129 + FUNC_PHY_DBG, 133 130 FUNC_PCI_WAKE, 134 131 FUNC_MD, 135 132 FUNC_PCIE_PERST, ··· 161 156 FUNC_SG0, 162 157 FUNC_SG1, 163 158 FUNC_SG2, 159 + FUNC_SPI, 164 160 FUNC_SGPIO_a, 165 161 FUNC_SGPIO_b, 166 162 FUNC_SI, 167 163 FUNC_SI2, 164 + FUNC_SI_Sa, 168 165 FUNC_SYNCE, 169 166 FUNC_TACHO, 170 167 FUNC_TACHO_a, ··· 195 188 FUNC_EMMC_SD, 196 189 FUNC_REF_CLK, 197 190 FUNC_RCVRD_CLK, 191 + FUNC_RGMII, 198 192 FUNC_MAX 199 193 }; 200 194 ··· 245 237 [FUNC_FC_SHRD20] = "fc_shrd20", 246 238 [FUNC_FUSA] = "fusa", 247 239 [FUNC_GPIO] = "gpio", 240 + [FUNC_I2C] = "i2c", 241 + [FUNC_I2C_Sa] = "i2c_slave_a", 248 242 [FUNC_IB_TRG_a] = "ib_trig_a", 249 243 [FUNC_IB_TRG_b] = "ib_trig_b", 250 244 [FUNC_IB_TRG_c] = "ib_trig_c", ··· 262 252 [FUNC_IRQ1] = "irq1", 263 253 [FUNC_IRQ1_IN] = "irq1_in", 264 254 [FUNC_IRQ1_OUT] = "irq1_out", 255 + [FUNC_IRQ2] = "irq2", 265 256 [FUNC_IRQ3] = "irq3", 266 257 [FUNC_IRQ4] = "irq4", 267 258 [FUNC_EXT_IRQ] = "ext_irq", 259 + [FUNC_MACLED] = "mac_led", 268 260 [FUNC_MIIM] = "miim", 269 261 [FUNC_MIIM_a] = "miim_a", 270 262 [FUNC_MIIM_b] = "miim_b", ··· 275 263 [FUNC_MIIM_Sb] = "miim_slave_b", 276 264 [FUNC_MIIM_IRQ] = "miim_irq", 277 265 [FUNC_PHY_LED] = "phy_led", 266 + [FUNC_PHY_DBG] = "phy_dbg", 278 267 [FUNC_PCI_WAKE] = "pci_wake", 279 268 [FUNC_PCIE_PERST] = "pcie_perst", 280 269 [FUNC_MD] = "md", ··· 313 300 [FUNC_SGPIO_b] = "sgpio_b", 314 301 [FUNC_SI] = "si", 315 302 [FUNC_SI2] = "si2", 303 + [FUNC_SI_Sa] = "si_slave_a", 304 + [FUNC_SPI] = "spi", 316 305 [FUNC_SYNCE] = "synce", 317 306 [FUNC_TACHO] = "tacho", 318 307 [FUNC_TACHO_a] = "tacho_a", ··· 343 328 [FUNC_EMMC_SD] = "emmc_sd", 344 329 [FUNC_REF_CLK] = "ref_clk", 345 330 [FUNC_RCVRD_CLK] = "rcvrd_clk", 331 + [FUNC_RGMII] = "rgmii", 346 332 }; 347 333 348 334 struct ocelot_pmx_func { ··· 1339 1323 LAN969X_PIN(66), 1340 1324 }; 1341 1325 1326 + #define LAN9645X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \ 1327 + static struct ocelot_pin_caps lan9645x_pin_##p = { \ 1328 + .pin = p, \ 1329 + .functions = { \ 1330 + FUNC_##f0, FUNC_##f1, FUNC_##f2, \ 1331 + FUNC_##f3 \ 1332 + }, \ 1333 + .a_functions = { \ 1334 + FUNC_##f4, FUNC_##f5, FUNC_##f6, \ 1335 + FUNC_##f7 \ 1336 + }, \ 1337 + } 1338 + 1339 + /* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */ 1340 + LAN9645X_P(0, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG); 1341 + LAN9645X_P(1, GPIO, SPI, SI_Sa, I2C_Sa, MIIM_Sa, UART, MIIM, PHY_DBG); 1342 + LAN9645X_P(2, GPIO, SPI, SI_Sa, I2C, NONE, NONE, NONE, PHY_DBG); 1343 + LAN9645X_P(3, GPIO, SPI, SI_Sa, I2C, MIIM_Sa, NONE, NONE, PHY_DBG); 1344 + LAN9645X_P(4, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG); 1345 + LAN9645X_P(5, GPIO, RGMII, TWI_SCL_M, I2C, NONE, NONE, SI_Sa, PHY_DBG); 1346 + LAN9645X_P(6, GPIO, RGMII, TWI_SCL_M, NONE, NONE, NONE, SI_Sa, PHY_DBG); 1347 + LAN9645X_P(7, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, SI_Sa, PHY_DBG); 1348 + LAN9645X_P(8, GPIO, RGMII, TWI_SCL_M, SFP, SGPIO_a, MIIM, NONE, PHY_DBG); 1349 + LAN9645X_P(9, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ1, UART, PHY_DBG); 1350 + LAN9645X_P(10, GPIO, RGMII, TWI_SCL_M, RECO_CLK, SGPIO_a, IRQ2, UART, PHY_DBG); 1351 + LAN9645X_P(11, GPIO, RGMII, TWI_SCL_M, MIIM, NONE, IRQ3, NONE, PHY_DBG); 1352 + LAN9645X_P(12, GPIO, RGMII, TWI_SCL_M, MIIM, PTP0, NONE, NONE, PHY_DBG); 1353 + LAN9645X_P(13, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP1, MACLED, NONE, PHY_DBG); 1354 + LAN9645X_P(14, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP2, MACLED, NONE, PHY_DBG); 1355 + LAN9645X_P(15, GPIO, RGMII, TWI_SCL_M, CLKMON, PTP3, NONE, NONE, PHY_DBG); 1356 + LAN9645X_P(16, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1357 + LAN9645X_P(17, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1358 + LAN9645X_P(18, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1359 + LAN9645X_P(19, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1360 + LAN9645X_P(20, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1361 + LAN9645X_P(21, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1362 + LAN9645X_P(22, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1363 + LAN9645X_P(23, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1364 + LAN9645X_P(24, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1365 + LAN9645X_P(25, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1366 + LAN9645X_P(26, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1367 + LAN9645X_P(27, GPIO, RGMII, NONE, NONE, NONE, NONE, NONE, PHY_DBG); 1368 + LAN9645X_P(28, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R); 1369 + LAN9645X_P(29, GPIO, RECO_CLK, MIIM, NONE, NONE, NONE, NONE, R); 1370 + LAN9645X_P(30, GPIO, PTP0, I2C, UART, NONE, NONE, NONE, R); 1371 + LAN9645X_P(31, GPIO, PTP1, TWI_SCL_M, UART, NONE, NONE, NONE, R); 1372 + LAN9645X_P(32, GPIO, PTP2, TWI_SCL_M, NONE, NONE, NONE, NONE, R); 1373 + LAN9645X_P(33, GPIO, PTP3, IRQ0, NONE, NONE, NONE, NONE, R); 1374 + LAN9645X_P(34, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, NONE, NONE, R); 1375 + LAN9645X_P(35, GPIO, RECO_CLK, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1376 + LAN9645X_P(36, GPIO, PTP0, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1377 + LAN9645X_P(37, GPIO, PTP1, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1378 + LAN9645X_P(38, GPIO, NONE, PHY_LED, PHY_LED, NONE, MACLED, NONE, R); 1379 + LAN9645X_P(39, GPIO, UART, PHY_LED, NONE, NONE, MACLED, NONE, R); 1380 + LAN9645X_P(40, GPIO, SPI, PHY_LED, SGPIO_a, NONE, MACLED, NONE, R); 1381 + LAN9645X_P(41, GPIO, SPI, PHY_LED, SGPIO_a, IRQ1, MACLED, NONE, R); 1382 + LAN9645X_P(42, GPIO, SPI, PHY_LED, SGPIO_a, IRQ2, MACLED, SFP, R); 1383 + LAN9645X_P(43, GPIO, SPI, PHY_LED, SGPIO_a, IRQ3, MACLED, SFP, R); 1384 + LAN9645X_P(44, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R); 1385 + LAN9645X_P(45, GPIO, MIIM, I2C, NONE, NONE, NONE, NONE, R); 1386 + LAN9645X_P(46, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R); 1387 + LAN9645X_P(47, GPIO, NONE, PHY_LED, NONE, NONE, NONE, NONE, R); 1388 + LAN9645X_P(48, GPIO, MIIM_Sa, PHY_LED, NONE, NONE, NONE, NONE, R); 1389 + LAN9645X_P(49, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R); 1390 + LAN9645X_P(50, GPIO, MIIM_Sa, PHY_LED, I2C_Sa, NONE, NONE, NONE, R); 1391 + 1392 + #define LAN9645X_PIN(n) { \ 1393 + .number = n, \ 1394 + .name = "GPIO_"#n, \ 1395 + .drv_data = &lan9645x_pin_##n \ 1396 + } 1397 + 1398 + static const struct pinctrl_pin_desc lan9645x_pins[] = { 1399 + LAN9645X_PIN(0), 1400 + LAN9645X_PIN(1), 1401 + LAN9645X_PIN(2), 1402 + LAN9645X_PIN(3), 1403 + LAN9645X_PIN(4), 1404 + LAN9645X_PIN(5), 1405 + LAN9645X_PIN(6), 1406 + LAN9645X_PIN(7), 1407 + LAN9645X_PIN(8), 1408 + LAN9645X_PIN(9), 1409 + LAN9645X_PIN(10), 1410 + LAN9645X_PIN(11), 1411 + LAN9645X_PIN(12), 1412 + LAN9645X_PIN(13), 1413 + LAN9645X_PIN(14), 1414 + LAN9645X_PIN(15), 1415 + LAN9645X_PIN(16), 1416 + LAN9645X_PIN(17), 1417 + LAN9645X_PIN(18), 1418 + LAN9645X_PIN(19), 1419 + LAN9645X_PIN(20), 1420 + LAN9645X_PIN(21), 1421 + LAN9645X_PIN(22), 1422 + LAN9645X_PIN(23), 1423 + LAN9645X_PIN(24), 1424 + LAN9645X_PIN(25), 1425 + LAN9645X_PIN(26), 1426 + LAN9645X_PIN(27), 1427 + LAN9645X_PIN(28), 1428 + LAN9645X_PIN(29), 1429 + LAN9645X_PIN(30), 1430 + LAN9645X_PIN(31), 1431 + LAN9645X_PIN(32), 1432 + LAN9645X_PIN(33), 1433 + LAN9645X_PIN(34), 1434 + LAN9645X_PIN(35), 1435 + LAN9645X_PIN(36), 1436 + LAN9645X_PIN(37), 1437 + LAN9645X_PIN(38), 1438 + LAN9645X_PIN(39), 1439 + LAN9645X_PIN(40), 1440 + LAN9645X_PIN(41), 1441 + LAN9645X_PIN(42), 1442 + LAN9645X_PIN(43), 1443 + LAN9645X_PIN(44), 1444 + LAN9645X_PIN(45), 1445 + LAN9645X_PIN(46), 1446 + LAN9645X_PIN(47), 1447 + LAN9645X_PIN(48), 1448 + LAN9645X_PIN(49), 1449 + LAN9645X_PIN(50), 1450 + }; 1451 + 1342 1452 static int ocelot_get_functions_count(struct pinctrl_dev *pctldev) 1343 1453 { 1344 1454 return ARRAY_SIZE(ocelot_function_names); ··· 1613 1471 return 0; 1614 1472 } 1615 1473 1474 + static int lan9645x_gpio_request_enable(struct pinctrl_dev *pctldev, 1475 + struct pinctrl_gpio_range *range, 1476 + unsigned int offset) 1477 + { 1478 + return 0; 1479 + } 1480 + 1616 1481 static const struct pinmux_ops ocelot_pmx_ops = { 1617 1482 .get_functions_count = ocelot_get_functions_count, 1618 1483 .get_function_name = ocelot_get_function_name, ··· 1636 1487 .set_mux = lan966x_pinmux_set_mux, 1637 1488 .gpio_set_direction = ocelot_gpio_set_direction, 1638 1489 .gpio_request_enable = lan966x_gpio_request_enable, 1490 + }; 1491 + 1492 + static const struct pinmux_ops lan9645x_pmx_ops = { 1493 + .get_functions_count = ocelot_get_functions_count, 1494 + .get_function_name = ocelot_get_function_name, 1495 + .get_function_groups = ocelot_get_function_groups, 1496 + .set_mux = lan966x_pinmux_set_mux, 1497 + .gpio_set_direction = ocelot_gpio_set_direction, 1498 + .gpio_request_enable = lan9645x_gpio_request_enable, 1639 1499 }; 1640 1500 1641 1501 static int ocelot_pctl_get_groups_count(struct pinctrl_dev *pctldev) ··· 2044 1886 }, 2045 1887 }; 2046 1888 1889 + static struct ocelot_match_data lan9645xf_desc = { 1890 + .desc = { 1891 + .name = "lan9645xf-pinctrl", 1892 + .pins = lan9645x_pins, 1893 + .npins = ARRAY_SIZE(lan9645x_pins), 1894 + .pctlops = &ocelot_pctl_ops, 1895 + .pmxops = &lan9645x_pmx_ops, 1896 + .confops = &ocelot_confops, 1897 + .owner = THIS_MODULE, 1898 + }, 1899 + .pincfg_data = { 1900 + .pd_bit = BIT(3), 1901 + .pu_bit = BIT(2), 1902 + .drive_bits = GENMASK(1, 0), 1903 + }, 1904 + .n_alt_modes = 7, 1905 + }; 1906 + 2047 1907 static int ocelot_create_group_func_map(struct device *dev, 2048 1908 struct ocelot_pinctrl *info) 2049 1909 { ··· 2396 2220 { .compatible = "microchip,sparx5-pinctrl", .data = &sparx5_desc }, 2397 2221 { .compatible = "microchip,lan966x-pinctrl", .data = &lan966x_desc }, 2398 2222 { .compatible = "microchip,lan9691-pinctrl", .data = &lan969x_desc }, 2223 + { .compatible = "microchip,lan96455f-pinctrl", .data = &lan9645xf_desc }, 2399 2224 {}, 2400 2225 }; 2401 2226 MODULE_DEVICE_TABLE(of, ocelot_pinctrl_of_match);