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drm/amdgpu: GFX12.1 scratch memory limit up to 57-bit

The scratch aperture or gmc private aperture in flat memory contains
57 bits of data on gfx v12.1.0 compared to the 32 bits from previous.

Add new helper kfd_init_apertures_v12 for gfx version >= v12.1.0 which
supports 57-bit VA space.

v2:
- update pdd->scratch_limit (Yu, Lang)
- update fixes tag (Felix Kuehling)
- add helper kfd_init_apertures_v12

Fixes: db1882b3ff0c ("drm/amdkfd: Update LDS, Scratch base for 57bit address")
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Lang Yu <lang.yu@amd.com>
Acked-by: Felix Kuehling <felix.kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Philip Yang and committed by
Alex Deucher b2d13a41 89b814a3

+34 -13
+1 -1
drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
··· 1405 1405 /* 1406 1406 * Configure apertures: 1407 1407 * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) 1408 - * Scratch: 0x10000000'00000000 - 0x10000001'00000000 (4GB) 1408 + * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) 1409 1409 */ 1410 1410 sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1411 1411 (adev->gmc.private_aperture_start >> 58));
+8 -2
drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
··· 654 654 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; 655 655 adev->gmc.shared_aperture_end = 656 656 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; 657 + 657 658 adev->gmc.private_aperture_start = 0x1000000000000000ULL; 658 - adev->gmc.private_aperture_end = 659 - adev->gmc.private_aperture_start + (4ULL << 30) - 1; 659 + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) 660 + adev->gmc.private_aperture_end = 661 + adev->gmc.private_aperture_start + (1ULL << 57) - 1; 662 + else 663 + adev->gmc.private_aperture_end = 664 + adev->gmc.private_aperture_start + (4ULL << 30) - 1; 665 + 660 666 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF; 661 667 662 668 return 0;
+25 -10
drivers/gpu/drm/amd/amdkfd/kfd_flat_memory.c
··· 342 342 343 343 static void kfd_init_apertures_v9(struct kfd_process_device *pdd, uint8_t id) 344 344 { 345 - if (KFD_GC_VERSION(pdd->dev) >= IP_VERSION(12, 1, 0)) 346 - pdd->lds_base = pdd->dev->adev->gmc.shared_aperture_start; 347 - else 348 - pdd->lds_base = MAKE_LDS_APP_BASE_V9(); 345 + pdd->lds_base = MAKE_LDS_APP_BASE_V9(); 349 346 pdd->lds_limit = MAKE_LDS_APP_LIMIT(pdd->lds_base); 350 347 351 348 pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM; 352 349 pdd->gpuvm_limit = 353 350 pdd->dev->kfd->shared_resources.gpuvm_size - 1; 354 351 355 - if (KFD_GC_VERSION(pdd->dev) >= IP_VERSION(12, 1, 0)) 356 - pdd->scratch_base = pdd->dev->adev->gmc.private_aperture_start; 357 - else 358 - pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9(); 352 + pdd->scratch_base = MAKE_SCRATCH_APP_BASE_V9(); 359 353 pdd->scratch_limit = MAKE_SCRATCH_APP_LIMIT(pdd->scratch_base); 354 + 355 + /* 356 + * Place TBA/TMA on opposite side of VM hole to prevent 357 + * stray faults from triggering SVM on these pages. 358 + */ 359 + pdd->qpd.cwsr_base = AMDGPU_VA_RESERVED_TRAP_START(pdd->dev->adev); 360 + } 361 + 362 + static void kfd_init_apertures_v12(struct kfd_process_device *pdd, uint8_t id) 363 + { 364 + pdd->lds_base = pdd->dev->adev->gmc.shared_aperture_start; 365 + pdd->lds_limit = pdd->dev->adev->gmc.shared_aperture_end; 366 + 367 + pdd->gpuvm_base = AMDGPU_VA_RESERVED_BOTTOM; 368 + pdd->gpuvm_limit = 369 + pdd->dev->kfd->shared_resources.gpuvm_size - 1; 370 + 371 + pdd->scratch_base = pdd->dev->adev->gmc.private_aperture_start; 372 + pdd->scratch_limit = pdd->dev->adev->gmc.private_aperture_end; 360 373 361 374 /* 362 375 * Place TBA/TMA on opposite side of VM hole to prevent ··· 425 412 kfd_init_apertures_vi(pdd, id); 426 413 break; 427 414 default: 428 - if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) 415 + if (KFD_GC_VERSION(dev) >= IP_VERSION(12, 1, 0)) { 416 + kfd_init_apertures_v12(pdd, id); 417 + } else if (KFD_GC_VERSION(dev) >= IP_VERSION(9, 0, 1)) { 429 418 kfd_init_apertures_v9(pdd, id); 430 - else { 419 + } else { 431 420 WARN(1, "Unexpected ASIC family %u", 432 421 dev->adev->asic_type); 433 422 return -EINVAL;