tjh.dev / kernel
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drm/amdgpu: Move pcie lock to register block

Move pcie register access lock to register access block.

Signed-off-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Lijo Lazar and committed by
Alex Deucher b2d55124 4a6ab037

+56 -57
-2
drivers/gpu/drm/amd/amdgpu/amdgpu.h
··· 902 902 struct amdgpu_mmio_remap rmmio_remap; 903 903 /* Indirect register access blocks */ 904 904 struct amdgpu_reg_access reg; 905 - /* protects concurrent PCIE register access */ 906 - spinlock_t pcie_idx_lock; 907 905 struct amdgpu_doorbell doorbell; 908 906 909 907 /* clock/pll info */
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
··· 3732 3732 return r; 3733 3733 3734 3734 spin_lock_init(&adev->mmio_idx_lock); 3735 - spin_lock_init(&adev->pcie_idx_lock); 3736 3735 spin_lock_init(&adev->mm_stats.lock); 3737 3736 spin_lock_init(&adev->virt.rlcg_reg_lock); 3738 3737 spin_lock_init(&adev->wb.lock);
+21 -20
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c
··· 59 59 adev->reg.audio_endpt.rreg = NULL; 60 60 adev->reg.audio_endpt.wreg = NULL; 61 61 62 + spin_lock_init(&adev->reg.pcie.lock); 62 63 adev->reg.pcie.rreg = NULL; 63 64 adev->reg.pcie.wreg = NULL; 64 65 adev->reg.pcie.rreg_ext = NULL; ··· 527 526 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); 528 527 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); 529 528 530 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 529 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 531 530 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 532 531 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 533 532 534 533 writel(reg_addr, pcie_index_offset); 535 534 readl(pcie_index_offset); 536 535 r = readl(pcie_data_offset); 537 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 536 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 538 537 539 538 return r; 540 539 } ··· 566 565 pcie_index_hi = 0; 567 566 } 568 567 569 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 568 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 570 569 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 571 570 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 572 571 if (pcie_index_hi != 0) ··· 587 586 readl(pcie_index_hi_offset); 588 587 } 589 588 590 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 589 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 591 590 592 591 return r; 593 592 } ··· 610 609 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); 611 610 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); 612 611 613 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 612 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 614 613 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 615 614 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 616 615 ··· 622 621 writel(reg_addr + 4, pcie_index_offset); 623 622 readl(pcie_index_offset); 624 623 r |= ((u64)readl(pcie_data_offset) << 32); 625 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 624 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 626 625 627 626 return r; 628 627 } ··· 642 641 pcie_index_hi = 643 642 adev->nbio.funcs->get_pcie_index_hi_offset(adev); 644 643 645 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 644 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 646 645 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 647 646 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 648 647 if (pcie_index_hi != 0) ··· 672 671 readl(pcie_index_hi_offset); 673 672 } 674 673 675 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 674 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 676 675 677 676 return r; 678 677 } ··· 695 694 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); 696 695 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); 697 696 698 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 697 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 699 698 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 700 699 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 701 700 ··· 703 702 readl(pcie_index_offset); 704 703 writel(reg_data, pcie_data_offset); 705 704 readl(pcie_data_offset); 706 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 705 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 707 706 } 708 707 709 708 void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, ··· 722 721 else 723 722 pcie_index_hi = 0; 724 723 725 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 724 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 726 725 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 727 726 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 728 727 if (pcie_index_hi != 0) ··· 744 743 readl(pcie_index_hi_offset); 745 744 } 746 745 747 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 746 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 748 747 } 749 748 750 749 /** ··· 765 764 pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); 766 765 pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); 767 766 768 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 767 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 769 768 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 770 769 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 771 770 ··· 779 778 readl(pcie_index_offset); 780 779 writel((u32)(reg_data >> 32), pcie_data_offset); 781 780 readl(pcie_data_offset); 782 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 781 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 783 782 } 784 783 785 784 void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, ··· 797 796 pcie_index_hi = 798 797 adev->nbio.funcs->get_pcie_index_hi_offset(adev); 799 798 800 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 799 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 801 800 pcie_index_offset = (void __iomem *)adev->rmmio + pcie_index * 4; 802 801 pcie_data_offset = (void __iomem *)adev->rmmio + pcie_data * 4; 803 802 if (pcie_index_hi != 0) ··· 829 828 readl(pcie_index_hi_offset); 830 829 } 831 830 832 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 831 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 833 832 } 834 833 835 834 u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg) ··· 840 839 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 841 840 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 842 841 843 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 842 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 844 843 WREG32(address, reg * 4); 845 844 (void)RREG32(address); 846 845 r = RREG32(data); 847 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 846 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 848 847 return r; 849 848 } 850 849 ··· 855 854 address = adev->nbio.funcs->get_pcie_port_index_offset(adev); 856 855 data = adev->nbio.funcs->get_pcie_port_data_offset(adev); 857 856 858 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 857 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 859 858 WREG32(address, reg * 4); 860 859 (void)RREG32(address); 861 860 WREG32(data, v); 862 861 (void)RREG32(data); 863 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 862 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 864 863 } 865 864 866 865 uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.h
··· 56 56 }; 57 57 58 58 struct amdgpu_reg_pcie_ind { 59 + spinlock_t lock; 59 60 amdgpu_rreg_t rreg; 60 61 amdgpu_wreg_t wreg; 61 62 amdgpu_rreg_ext_t rreg_ext;
+4 -4
drivers/gpu/drm/amd/amdgpu/cik.c
··· 154 154 unsigned long flags; 155 155 u32 r; 156 156 157 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 157 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 158 158 WREG32(mmPCIE_INDEX, reg); 159 159 (void)RREG32(mmPCIE_INDEX); 160 160 r = RREG32(mmPCIE_DATA); 161 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 161 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 162 162 return r; 163 163 } 164 164 ··· 166 166 { 167 167 unsigned long flags; 168 168 169 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 169 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 170 170 WREG32(mmPCIE_INDEX, reg); 171 171 (void)RREG32(mmPCIE_INDEX); 172 172 WREG32(mmPCIE_DATA, v); 173 173 (void)RREG32(mmPCIE_DATA); 174 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 174 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 175 175 } 176 176 177 177 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
+10 -10
drivers/gpu/drm/amd/amdgpu/df_v3_6.c
··· 51 51 address = adev->nbio.funcs->get_pcie_index_offset(adev); 52 52 data = adev->nbio.funcs->get_pcie_data_offset(adev); 53 53 54 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 54 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 55 55 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); 56 56 WREG32(data, ficaa_val); 57 57 ··· 61 61 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); 62 62 ficadh_val = RREG32(data); 63 63 64 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 64 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 65 65 66 66 return (((ficadh_val & 0xFFFFFFFFFFFFFFFF) << 32) | ficadl_val); 67 67 } ··· 74 74 address = adev->nbio.funcs->get_pcie_index_offset(adev); 75 75 data = adev->nbio.funcs->get_pcie_data_offset(adev); 76 76 77 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 77 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 78 78 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessAddress3); 79 79 WREG32(data, ficaa_val); 80 80 ··· 84 84 WREG32(address, smnDF_PIE_AON_FabricIndirectConfigAccessDataHi3); 85 85 WREG32(data, ficadh_val); 86 86 87 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 87 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 88 88 } 89 89 90 90 /* ··· 102 102 address = adev->nbio.funcs->get_pcie_index_offset(adev); 103 103 data = adev->nbio.funcs->get_pcie_data_offset(adev); 104 104 105 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 105 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 106 106 WREG32(address, lo_addr); 107 107 *lo_val = RREG32(data); 108 108 WREG32(address, hi_addr); 109 109 *hi_val = RREG32(data); 110 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 110 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 111 111 } 112 112 113 113 /* ··· 124 124 address = adev->nbio.funcs->get_pcie_index_offset(adev); 125 125 data = adev->nbio.funcs->get_pcie_data_offset(adev); 126 126 127 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 127 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 128 128 WREG32(address, lo_addr); 129 129 WREG32(data, lo_val); 130 130 WREG32(address, hi_addr); 131 131 WREG32(data, hi_val); 132 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 132 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 133 133 } 134 134 135 135 /* same as perfmon_wreg but return status on write value check */ ··· 143 143 address = adev->nbio.funcs->get_pcie_index_offset(adev); 144 144 data = adev->nbio.funcs->get_pcie_data_offset(adev); 145 145 146 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 146 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 147 147 WREG32(address, lo_addr); 148 148 WREG32(data, lo_val); 149 149 WREG32(address, hi_addr); ··· 153 153 lo_val_rb = RREG32(data); 154 154 WREG32(address, hi_addr); 155 155 hi_val_rb = RREG32(data); 156 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 156 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 157 157 158 158 if (!(lo_val == lo_val_rb && hi_val == hi_val_rb)) 159 159 return -EBUSY;
+16 -16
drivers/gpu/drm/amd/amdgpu/si.c
··· 1027 1027 unsigned long flags; 1028 1028 u32 r; 1029 1029 1030 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1030 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1031 1031 WREG32(AMDGPU_PCIE_INDEX, reg); 1032 1032 (void)RREG32(AMDGPU_PCIE_INDEX); 1033 1033 r = RREG32(AMDGPU_PCIE_DATA); 1034 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1034 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1035 1035 return r; 1036 1036 } 1037 1037 ··· 1039 1039 { 1040 1040 unsigned long flags; 1041 1041 1042 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1042 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1043 1043 WREG32(AMDGPU_PCIE_INDEX, reg); 1044 1044 (void)RREG32(AMDGPU_PCIE_INDEX); 1045 1045 WREG32(AMDGPU_PCIE_DATA, v); 1046 1046 (void)RREG32(AMDGPU_PCIE_DATA); 1047 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1047 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1048 1048 } 1049 1049 1050 1050 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg) ··· 1052 1052 unsigned long flags; 1053 1053 u32 r; 1054 1054 1055 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1055 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1056 1056 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1057 1057 (void)RREG32(PCIE_PORT_INDEX); 1058 1058 r = RREG32(PCIE_PORT_DATA); 1059 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1059 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1060 1060 return r; 1061 1061 } 1062 1062 ··· 1064 1064 { 1065 1065 unsigned long flags; 1066 1066 1067 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 1067 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 1068 1068 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff)); 1069 1069 (void)RREG32(PCIE_PORT_INDEX); 1070 1070 WREG32(PCIE_PORT_DATA, (v)); 1071 1071 (void)RREG32(PCIE_PORT_DATA); 1072 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 1072 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 1073 1073 } 1074 1074 1075 1075 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg) ··· 2380 2380 unsigned long flags; 2381 2381 u32 r; 2382 2382 2383 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2383 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2384 2384 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2385 2385 r = RREG32(EVERGREEN_PIF_PHY0_DATA); 2386 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2386 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2387 2387 return r; 2388 2388 } 2389 2389 ··· 2391 2391 { 2392 2392 unsigned long flags; 2393 2393 2394 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2394 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2395 2395 WREG32(EVERGREEN_PIF_PHY0_INDEX, ((reg) & 0xffff)); 2396 2396 WREG32(EVERGREEN_PIF_PHY0_DATA, (v)); 2397 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2397 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2398 2398 } 2399 2399 2400 2400 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg) ··· 2402 2402 unsigned long flags; 2403 2403 u32 r; 2404 2404 2405 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2405 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2406 2406 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2407 2407 r = RREG32(EVERGREEN_PIF_PHY1_DATA); 2408 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2408 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2409 2409 return r; 2410 2410 } 2411 2411 ··· 2413 2413 { 2414 2414 unsigned long flags; 2415 2415 2416 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 2416 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 2417 2417 WREG32(EVERGREEN_PIF_PHY1_INDEX, ((reg) & 0xffff)); 2418 2418 WREG32(EVERGREEN_PIF_PHY1_DATA, (v)); 2419 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 2419 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 2420 2420 } 2421 2421 static void si_program_aspm(struct amdgpu_device *adev) 2422 2422 {
+4 -4
drivers/gpu/drm/amd/amdgpu/vi.c
··· 299 299 unsigned long flags; 300 300 u32 r; 301 301 302 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 302 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 303 303 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 304 304 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 305 305 r = RREG32_NO_KIQ(mmPCIE_DATA); 306 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 306 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 307 307 return r; 308 308 } 309 309 ··· 311 311 { 312 312 unsigned long flags; 313 313 314 - spin_lock_irqsave(&adev->pcie_idx_lock, flags); 314 + spin_lock_irqsave(&adev->reg.pcie.lock, flags); 315 315 WREG32_NO_KIQ(mmPCIE_INDEX, reg); 316 316 (void)RREG32_NO_KIQ(mmPCIE_INDEX); 317 317 WREG32_NO_KIQ(mmPCIE_DATA, v); 318 318 (void)RREG32_NO_KIQ(mmPCIE_DATA); 319 - spin_unlock_irqrestore(&adev->pcie_idx_lock, flags); 319 + spin_unlock_irqrestore(&adev->reg.pcie.lock, flags); 320 320 } 321 321 322 322 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)