drm/amd/pp: Use atombios api directly in powerplay (v2)

+76 -69

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.c

··· 23 23 #include "pp_debug.h" 24 24 #include <linux/module.h> 25 25 #include <linux/slab.h> 26 - 26 + #include "atom.h" 27 27 #include "ppatomctrl.h" 28 28 #include "atombios.h" 29 29 #include "cgs_common.h" ··· 128 128 return 0; 129 129 } 130 130 131 - 132 131 int atomctrl_initialize_mc_reg_table( 133 132 struct pp_hwmgr *hwmgr, 134 133 uint8_t module_index, ··· 140 141 u16 size; 141 142 142 143 vram_info = (ATOM_VRAM_INFO_HEADER_V2_1 *) 143 - cgs_atom_get_data_table(hwmgr->device, 144 + smu_atom_get_data_table(hwmgr->adev, 144 145 GetIndexIntoMasterTable(DATA, VRAM_Info), &size, &frev, &crev); 145 146 146 147 if (module_index >= vram_info->ucNumOfVRAMModule) { ··· 173 174 uint32_t engine_clock, 174 175 uint32_t memory_clock) 175 176 { 177 + struct amdgpu_device *adev = hwmgr->adev; 178 + 176 179 SET_ENGINE_CLOCK_PS_ALLOCATION engine_clock_parameters; 177 180 178 181 /* They are both in 10KHz Units. */ ··· 185 184 /* in 10 khz units.*/ 186 185 engine_clock_parameters.sReserved.ulClock = 187 186 cpu_to_le32(memory_clock & SET_CLOCK_FREQ_MASK); 188 - return cgs_atom_exec_cmd_table(hwmgr->device, 187 + 188 + return amdgpu_atom_execute_table(adev->mode_info.atom_context, 189 189 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings), 190 - &engine_clock_parameters); 190 + (uint32_t *)&engine_clock_parameters); 191 191 } 192 192 193 193 /** ··· 205 203 union voltage_object_info *voltage_info; 206 204 207 205 voltage_info = (union voltage_object_info *) 208 - cgs_atom_get_data_table(device, index, 206 + smu_atom_get_data_table(device, index, 209 207 &size, &frev, &crev); 210 208 211 209 if (voltage_info != NULL) ··· 249 247 pp_atomctrl_memory_clock_param *mpll_param, 250 248 bool strobe_mode) 251 249 { 250 + struct amdgpu_device *adev = hwmgr->adev; 252 251 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 mpll_parameters; 253 252 int result; 254 253 255 254 mpll_parameters.ulClock = cpu_to_le32(clock_value); 256 255 mpll_parameters.ucInputFlag = (uint8_t)((strobe_mode) ? 1 : 0); 257 256 258 - result = cgs_atom_exec_cmd_table 259 - (hwmgr->device, 257 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 260 258 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam), 261 - &mpll_parameters); 259 + (uint32_t *)&mpll_parameters); 262 260 263 261 if (0 == result) { 264 262 mpll_param->mpll_fb_divider.clk_frac = ··· 297 295 int atomctrl_get_memory_pll_dividers_vi(struct pp_hwmgr *hwmgr, 298 296 uint32_t clock_value, pp_atomctrl_memory_clock_param *mpll_param) 299 297 { 298 + struct amdgpu_device *adev = hwmgr->adev; 300 299 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2 mpll_parameters; 301 300 int result; 302 301 303 302 mpll_parameters.ulClock.ulClock = cpu_to_le32(clock_value); 304 303 305 - result = cgs_atom_exec_cmd_table(hwmgr->device, 304 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 306 305 GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam), 307 - &mpll_parameters); 306 + (uint32_t *)&mpll_parameters); 308 307 309 308 if (!result) 310 309 mpll_param->mpll_post_divider = ··· 318 315 uint32_t clock_value, 319 316 pp_atomctrl_clock_dividers_kong *dividers) 320 317 { 318 + struct amdgpu_device *adev = hwmgr->adev; 321 319 COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 pll_parameters; 322 320 int result; 323 321 324 322 pll_parameters.ulClock = cpu_to_le32(clock_value); 325 323 326 - result = cgs_atom_exec_cmd_table 327 - (hwmgr->device, 324 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 328 325 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), 329 - &pll_parameters); 326 + (uint32_t *)&pll_parameters); 330 327 331 328 if (0 == result) { 332 329 dividers->pll_post_divider = pll_parameters.ucPostDiv; ··· 341 338 uint32_t clock_value, 342 339 pp_atomctrl_clock_dividers_vi *dividers) 343 340 { 341 + struct amdgpu_device *adev = hwmgr->adev; 344 342 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters; 345 343 int result; 346 344 347 345 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value); 348 346 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; 349 347 350 - result = cgs_atom_exec_cmd_table 351 - (hwmgr->device, 348 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 352 349 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), 353 - &pll_patameters); 350 + (uint32_t *)&pll_patameters); 354 351 355 352 if (0 == result) { 356 353 dividers->pll_post_divider = ··· 378 375 uint32_t clock_value, 379 376 pp_atomctrl_clock_dividers_ai *dividers) 380 377 { 378 + struct amdgpu_device *adev = hwmgr->adev; 381 379 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7 pll_patameters; 382 380 int result; 383 381 384 382 pll_patameters.ulClock.ulClock = cpu_to_le32(clock_value); 385 383 pll_patameters.ulClock.ucPostDiv = COMPUTE_GPUCLK_INPUT_FLAG_SCLK; 386 384 387 - result = cgs_atom_exec_cmd_table 388 - (hwmgr->device, 385 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 389 386 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), 390 - &pll_patameters); 387 + (uint32_t *)&pll_patameters); 391 388 392 389 if (0 == result) { 393 390 dividers->usSclk_fcw_frac = le16_to_cpu(pll_patameters.usSclk_fcw_frac); ··· 410 407 uint32_t clock_value, 411 408 pp_atomctrl_clock_dividers_vi *dividers) 412 409 { 410 + struct amdgpu_device *adev = hwmgr->adev; 413 411 COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 pll_patameters; 414 412 int result; 415 413 ··· 418 414 pll_patameters.ulClock.ucPostDiv = 419 415 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK; 420 416 421 - result = cgs_atom_exec_cmd_table 422 - (hwmgr->device, 417 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 423 418 GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL), 424 - &pll_patameters); 419 + (uint32_t *)&pll_patameters); 425 420 426 421 if (0 == result) { 427 422 dividers->pll_post_divider = ··· 455 452 uint32_t clock; 456 453 457 454 fw_info = (ATOM_FIRMWARE_INFO *) 458 - cgs_atom_get_data_table(hwmgr->device, 455 + smu_atom_get_data_table(hwmgr->adev, 459 456 GetIndexIntoMasterTable(DATA, FirmwareInfo), 460 457 &size, &frev, &crev); 461 458 ··· 479 476 uint8_t voltage_mode) 480 477 { 481 478 ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info = 482 - (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device); 479 + (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev); 483 480 bool ret; 484 481 485 482 PP_ASSERT_WITH_CODE((NULL != voltage_info), ··· 498 495 pp_atomctrl_voltage_table *voltage_table) 499 496 { 500 497 ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info = 501 - (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device); 498 + (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev); 502 499 const ATOM_VOLTAGE_OBJECT_V3 *voltage_object; 503 500 unsigned int i; 504 501 ··· 575 572 void *table_address; 576 573 577 574 table_address = (ATOM_GPIO_PIN_LUT *) 578 - cgs_atom_get_data_table(device, 575 + smu_atom_get_data_table(device, 579 576 GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT), 580 577 &size, &frev, &crev); 581 578 ··· 595 592 { 596 593 bool bRet = false; 597 594 ATOM_GPIO_PIN_LUT *gpio_lookup_table = 598 - get_gpio_lookup_table(hwmgr->device); 595 + get_gpio_lookup_table(hwmgr->adev); 599 596 600 597 PP_ASSERT_WITH_CODE((NULL != gpio_lookup_table), 601 598 "Could not find GPIO lookup Table in BIOS.", return false); ··· 616 613 bool debug) 617 614 { 618 615 ATOM_ASIC_PROFILING_INFO_V3_4 *getASICProfilingInfo; 619 - 616 + struct amdgpu_device *adev = hwmgr->adev; 620 617 EFUSE_LINEAR_FUNC_PARAM sRO_fuse; 621 618 EFUSE_LINEAR_FUNC_PARAM sCACm_fuse; 622 619 EFUSE_LINEAR_FUNC_PARAM sCACb_fuse; ··· 643 640 int result; 644 641 645 642 getASICProfilingInfo = (ATOM_ASIC_PROFILING_INFO_V3_4 *) 646 - cgs_atom_get_data_table(hwmgr->device, 643 + smu_atom_get_data_table(hwmgr->adev, 647 644 GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo), 648 645 NULL, NULL, NULL); 649 646 ··· 709 706 710 707 sOutput_FuseValues.sEfuse = sInput_FuseValues; 711 708 712 - result = cgs_atom_exec_cmd_table(hwmgr->device, 709 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 713 710 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 714 - &sOutput_FuseValues); 711 + (uint32_t *)&sOutput_FuseValues); 715 712 716 713 if (result) 717 714 return result; ··· 730 727 731 728 sOutput_FuseValues.sEfuse = sInput_FuseValues; 732 729 733 - result = cgs_atom_exec_cmd_table(hwmgr->device, 730 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 734 731 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 735 - &sOutput_FuseValues); 732 + (uint32_t *)&sOutput_FuseValues); 736 733 737 734 if (result) 738 735 return result; ··· 750 747 sInput_FuseValues.ucBitLength = sCACb_fuse.ucEfuseLength; 751 748 sOutput_FuseValues.sEfuse = sInput_FuseValues; 752 749 753 - result = cgs_atom_exec_cmd_table(hwmgr->device, 750 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 754 751 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 755 - &sOutput_FuseValues); 752 + (uint32_t *)&sOutput_FuseValues); 756 753 757 754 if (result) 758 755 return result; ··· 771 768 772 769 sOutput_FuseValues.sEfuse = sInput_FuseValues; 773 770 774 - result = cgs_atom_exec_cmd_table(hwmgr->device, 771 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 775 772 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 776 - &sOutput_FuseValues); 773 + (uint32_t *)&sOutput_FuseValues); 777 774 778 775 if (result) 779 776 return result; ··· 793 790 794 791 sOutput_FuseValues.sEfuse = sInput_FuseValues; 795 792 796 - result = cgs_atom_exec_cmd_table(hwmgr->device, 793 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 797 794 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 798 - &sOutput_FuseValues); 795 + (uint32_t *)&sOutput_FuseValues); 799 796 if (result) 800 797 return result; 801 798 ··· 814 811 sInput_FuseValues.ucBitLength = sKv_b_fuse.ucEfuseLength; 815 812 sOutput_FuseValues.sEfuse = sInput_FuseValues; 816 813 817 - result = cgs_atom_exec_cmd_table(hwmgr->device, 814 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 818 815 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 819 - &sOutput_FuseValues); 816 + (uint32_t *)&sOutput_FuseValues); 820 817 821 818 if (result) 822 819 return result; ··· 845 842 846 843 sOutput_FuseValues.sEfuse = sInput_FuseValues; 847 844 848 - result = cgs_atom_exec_cmd_table(hwmgr->device, 845 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 849 846 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 850 - &sOutput_FuseValues); 847 + (uint32_t *)&sOutput_FuseValues); 851 848 852 849 if (result) 853 850 return result; ··· 1056 1053 uint32_t sclk, uint16_t virtual_voltage_Id, 1057 1054 uint16_t *voltage) 1058 1055 { 1059 - int result; 1056 + struct amdgpu_device *adev = hwmgr->adev; 1060 1057 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space; 1058 + int result; 1061 1059 1062 1060 get_voltage_info_param_space.ucVoltageType = 1063 1061 voltage_type; ··· 1069 1065 get_voltage_info_param_space.ulSCLKFreq = 1070 1066 cpu_to_le32(sclk); 1071 1067 1072 - result = cgs_atom_exec_cmd_table(hwmgr->device, 1068 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 1073 1069 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), 1074 - &get_voltage_info_param_space); 1070 + (uint32_t *)&get_voltage_info_param_space); 1075 1071 1076 1072 if (0 != result) 1077 1073 return result; ··· 1092 1088 uint16_t virtual_voltage_id, 1093 1089 uint16_t *voltage) 1094 1090 { 1091 + struct amdgpu_device *adev = hwmgr->adev; 1092 + GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space; 1095 1093 int result; 1096 1094 int entry_id; 1097 - GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 get_voltage_info_param_space; 1098 1095 1099 1096 /* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */ 1100 1097 for (entry_id = 0; entry_id < hwmgr->dyn_state.vddc_dependency_on_sclk->count; entry_id++) { ··· 1116 1111 get_voltage_info_param_space.ulSCLKFreq = 1117 1112 cpu_to_le32(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[entry_id].clk); 1118 1113 1119 - result = cgs_atom_exec_cmd_table(hwmgr->device, 1114 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 1120 1115 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), 1121 - &get_voltage_info_param_space); 1116 + (uint32_t *)&get_voltage_info_param_space); 1122 1117 1123 1118 if (0 != result) 1124 1119 return result; ··· 1140 1135 u16 size; 1141 1136 1142 1137 fw_info = (ATOM_COMMON_TABLE_HEADER *) 1143 - cgs_atom_get_data_table(hwmgr->device, 1138 + smu_atom_get_data_table(hwmgr->adev, 1144 1139 GetIndexIntoMasterTable(DATA, FirmwareInfo), 1145 1140 &size, &frev, &crev); 1146 1141 ··· 1172 1167 u16 size; 1173 1168 1174 1169 table = (ATOM_ASIC_INTERNAL_SS_INFO *) 1175 - cgs_atom_get_data_table(device, 1170 + smu_atom_get_data_table(device, 1176 1171 GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info), 1177 1172 &size, &frev, &crev); 1178 1173 ··· 1193 1188 1194 1189 memset(ssEntry, 0x00, sizeof(pp_atomctrl_internal_ss_info)); 1195 1190 1196 - table = asic_internal_ss_get_ss_table(hwmgr->device); 1191 + table = asic_internal_ss_get_ss_table(hwmgr->adev); 1197 1192 1198 1193 if (NULL == table) 1199 1194 return -1; ··· 1265 1260 ASIC_INTERNAL_ENGINE_SS, engine_clock, ssInfo); 1266 1261 } 1267 1262 1268 - int atomctrl_read_efuse(void *device, uint16_t start_index, 1263 + int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, 1269 1264 uint16_t end_index, uint32_t mask, uint32_t *efuse) 1270 1265 { 1266 + struct amdgpu_device *adev = hwmgr->adev; 1271 1267 int result; 1272 1268 READ_EFUSE_VALUE_PARAMETER efuse_param; 1273 1269 ··· 1278 1272 efuse_param.sEfuse.ucBitLength = (uint8_t) 1279 1273 ((end_index - start_index) + 1); 1280 1274 1281 - result = cgs_atom_exec_cmd_table(device, 1275 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 1282 1276 GetIndexIntoMasterTable(COMMAND, ReadEfuseValue), 1283 - &efuse_param); 1277 + (uint32_t *)&efuse_param); 1284 1278 if (!result) 1285 1279 *efuse = le32_to_cpu(efuse_param.ulEfuseValue) & mask; 1286 1280 ··· 1290 1284 int atomctrl_set_ac_timing_ai(struct pp_hwmgr *hwmgr, uint32_t memory_clock, 1291 1285 uint8_t level) 1292 1286 { 1287 + struct amdgpu_device *adev = hwmgr->adev; 1293 1288 DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1 memory_clock_parameters; 1294 1289 int result; 1295 1290 ··· 1300 1293 ADJUST_MC_SETTING_PARAM; 1301 1294 memory_clock_parameters.asDPMMCReg.ucMclkDPMState = level; 1302 1295 1303 - result = cgs_atom_exec_cmd_table 1304 - (hwmgr->device, 1296 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 1305 1297 GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings), 1306 - &memory_clock_parameters); 1298 + (uint32_t *)&memory_clock_parameters); 1307 1299 1308 1300 return result; 1309 1301 } ··· 1310 1304 int atomctrl_get_voltage_evv_on_sclk_ai(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 1311 1305 uint32_t sclk, uint16_t virtual_voltage_Id, uint32_t *voltage) 1312 1306 { 1313 - 1307 + struct amdgpu_device *adev = hwmgr->adev; 1314 1308 int result; 1315 1309 GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3 get_voltage_info_param_space; 1316 1310 ··· 1319 1313 get_voltage_info_param_space.usVoltageLevel = cpu_to_le16(virtual_voltage_Id); 1320 1314 get_voltage_info_param_space.ulSCLKFreq = cpu_to_le32(sclk); 1321 1315 1322 - result = cgs_atom_exec_cmd_table(hwmgr->device, 1316 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 1323 1317 GetIndexIntoMasterTable(COMMAND, GetVoltageInfo), 1324 - &get_voltage_info_param_space); 1318 + (uint32_t *)&get_voltage_info_param_space); 1325 1319 1326 1320 if (0 != result) 1327 1321 return result; ··· 1340 1334 u16 size; 1341 1335 1342 1336 ATOM_SMU_INFO_V2_1 *psmu_info = 1343 - (ATOM_SMU_INFO_V2_1 *)cgs_atom_get_data_table(hwmgr->device, 1337 + (ATOM_SMU_INFO_V2_1 *)smu_atom_get_data_table(hwmgr->adev, 1344 1338 GetIndexIntoMasterTable(DATA, SMU_Info), 1345 1339 &size, &frev, &crev); 1346 1340 ··· 1368 1362 return -EINVAL; 1369 1363 1370 1364 profile = (ATOM_ASIC_PROFILING_INFO_V3_6 *) 1371 - cgs_atom_get_data_table(hwmgr->device, 1365 + smu_atom_get_data_table(hwmgr->adev, 1372 1366 GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo), 1373 1367 NULL, NULL, NULL); 1374 1368 if (!profile) ··· 1408 1402 uint16_t *load_line) 1409 1403 { 1410 1404 ATOM_VOLTAGE_OBJECT_INFO_V3_1 *voltage_info = 1411 - (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->device); 1405 + (ATOM_VOLTAGE_OBJECT_INFO_V3_1 *)get_voltage_info_table(hwmgr->adev); 1412 1406 1413 1407 const ATOM_VOLTAGE_OBJECT_V3 *voltage_object; 1414 1408 ··· 1427 1421 1428 1422 int atomctrl_get_leakage_id_from_efuse(struct pp_hwmgr *hwmgr, uint16_t *virtual_voltage_id) 1429 1423 { 1430 - int result; 1424 + struct amdgpu_device *adev = hwmgr->adev; 1431 1425 SET_VOLTAGE_PS_ALLOCATION allocation; 1432 1426 SET_VOLTAGE_PARAMETERS_V1_3 *voltage_parameters = 1433 1427 (SET_VOLTAGE_PARAMETERS_V1_3 *)&allocation.sASICSetVoltage; 1428 + int result; 1434 1429 1435 1430 voltage_parameters->ucVoltageMode = ATOM_GET_LEAKAGE_ID; 1436 1431 1437 - result = cgs_atom_exec_cmd_table(hwmgr->device, 1432 + result = amdgpu_atom_execute_table(adev->mode_info.atom_context, 1438 1433 GetIndexIntoMasterTable(COMMAND, SetVoltage), 1439 - voltage_parameters); 1434 + (uint32_t *)voltage_parameters); 1440 1435 1441 1436 *virtual_voltage_id = voltage_parameters->usVoltageLevel; 1442 1437 ··· 1460 1453 ix = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo); 1461 1454 1462 1455 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *) 1463 - cgs_atom_get_data_table(hwmgr->device, 1456 + smu_atom_get_data_table(hwmgr->adev, 1464 1457 ix, 1465 1458 NULL, NULL, NULL); 1466 1459 if (!profile)

+1 -1

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomctrl.h

··· 298 298 extern int atomctrl_get_engine_pll_dividers_kong(struct pp_hwmgr *hwmgr, 299 299 uint32_t clock_value, 300 300 pp_atomctrl_clock_dividers_kong *dividers); 301 - extern int atomctrl_read_efuse(void *device, uint16_t start_index, 301 + extern int atomctrl_read_efuse(struct pp_hwmgr *hwmgr, uint16_t start_index, 302 302 uint16_t end_index, uint32_t mask, uint32_t *efuse); 303 303 extern int atomctrl_calculate_voltage_evv_on_sclk(struct pp_hwmgr *hwmgr, uint8_t voltage_type, 304 304 uint32_t sclk, uint16_t virtual_voltage_Id, uint16_t *voltage, uint16_t dpm_level, bool debug);

+45 -43

drivers/gpu/drm/amd/powerplay/hwmgr/ppatomfwctrl.c

··· 23 23 24 24 #include "ppatomfwctrl.h" 25 25 #include "atomfirmware.h" 26 + #include "atom.h" 26 27 #include "pp_debug.h" 27 - 28 28 29 29 static const union atom_voltage_object_v4 *pp_atomfwctrl_lookup_voltage_type_v4( 30 30 const struct atom_voltage_objects_info_v4_1 *voltage_object_info_table, ··· 38 38 39 39 while (offset < size) { 40 40 const union atom_voltage_object_v4 *voltage_object = 41 - (const union atom_voltage_object_v4 *)(start + offset); 41 + (const union atom_voltage_object_v4 *)(start + offset); 42 42 43 - if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type && 44 - voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode) 45 - return voltage_object; 43 + if (voltage_type == voltage_object->gpio_voltage_obj.header.voltage_type && 44 + voltage_mode == voltage_object->gpio_voltage_obj.header.voltage_mode) 45 + return voltage_object; 46 46 47 - offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size); 47 + offset += le16_to_cpu(voltage_object->gpio_voltage_obj.header.object_size); 48 48 49 - } 49 + } 50 50 51 - return NULL; 51 + return NULL; 52 52 } 53 53 54 54 static struct atom_voltage_objects_info_v4_1 *pp_atomfwctrl_get_voltage_info_table( 55 55 struct pp_hwmgr *hwmgr) 56 56 { 57 - const void *table_address; 58 - uint16_t idx; 57 + const void *table_address; 58 + uint16_t idx; 59 59 60 - idx = GetIndexIntoMasterDataTable(voltageobject_info); 61 - table_address = cgs_atom_get_data_table(hwmgr->device, 62 - idx, NULL, NULL, NULL); 60 + idx = GetIndexIntoMasterDataTable(voltageobject_info); 61 + table_address = smu_atom_get_data_table(hwmgr->adev, 62 + idx, NULL, NULL, NULL); 63 63 64 - PP_ASSERT_WITH_CODE( 65 - table_address, 66 - "Error retrieving BIOS Table Address!", 67 - return NULL); 64 + PP_ASSERT_WITH_CODE(table_address, 65 + "Error retrieving BIOS Table Address!", 66 + return NULL); 68 67 69 - return (struct atom_voltage_objects_info_v4_1 *)table_address; 68 + return (struct atom_voltage_objects_info_v4_1 *)table_address; 70 69 } 71 70 72 71 /** ··· 166 167 uint16_t idx; 167 168 168 169 idx = GetIndexIntoMasterDataTable(gpio_pin_lut); 169 - table_address = cgs_atom_get_data_table(hwmgr->device, 170 + table_address = smu_atom_get_data_table(hwmgr->adev, 170 171 idx, NULL, NULL, NULL); 171 172 PP_ASSERT_WITH_CODE(table_address, 172 173 "Error retrieving BIOS Table Address!", ··· 247 248 uint32_t clock_type, uint32_t clock_value, 248 249 struct pp_atomfwctrl_clock_dividers_soc15 *dividers) 249 250 { 251 + struct amdgpu_device *adev = hwmgr->adev; 250 252 struct compute_gpu_clock_input_parameter_v1_8 pll_parameters; 251 253 struct compute_gpu_clock_output_parameter_v1_8 *pll_output; 252 - int result; 253 254 uint32_t idx; 254 255 255 256 pll_parameters.gpuclock_10khz = (uint32_t)clock_value; 256 257 pll_parameters.gpu_clock_type = clock_type; 257 258 258 259 idx = GetIndexIntoMasterCmdTable(computegpuclockparam); 259 - result = cgs_atom_exec_cmd_table(hwmgr->device, idx, &pll_parameters); 260 260 261 - if (!result) { 262 - pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *) 263 - &pll_parameters; 264 - dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); 265 - dividers->ulDid = le32_to_cpu(pll_output->dfs_did); 266 - dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); 267 - dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); 268 - dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); 269 - dividers->ucPll_ss_enable = pll_output->pll_ss_enable; 270 - } 271 - return result; 261 + if (amdgpu_atom_execute_table( 262 + adev->mode_info.atom_context, idx, (uint32_t *)&pll_parameters)) 263 + return -EINVAL; 264 + 265 + pll_output = (struct compute_gpu_clock_output_parameter_v1_8 *) 266 + &pll_parameters; 267 + dividers->ulClock = le32_to_cpu(pll_output->gpuclock_10khz); 268 + dividers->ulDid = le32_to_cpu(pll_output->dfs_did); 269 + dividers->ulPll_fb_mult = le32_to_cpu(pll_output->pll_fb_mult); 270 + dividers->ulPll_ss_fbsmult = le32_to_cpu(pll_output->pll_ss_fbsmult); 271 + dividers->usPll_ss_slew_frac = le16_to_cpu(pll_output->pll_ss_slew_frac); 272 + dividers->ucPll_ss_enable = pll_output->pll_ss_enable; 273 + 274 + return 0; 272 275 } 273 276 274 277 int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr, ··· 284 283 285 284 idx = GetIndexIntoMasterDataTable(asic_profiling_info); 286 285 profile = (struct atom_asic_profiling_info_v4_1 *) 287 - cgs_atom_get_data_table(hwmgr->device, 286 + smu_atom_get_data_table(hwmgr->adev, 288 287 idx, NULL, NULL, NULL); 289 288 290 289 if (!profile) ··· 468 467 469 468 idx = GetIndexIntoMasterDataTable(smu_info); 470 469 info = (struct atom_smu_info_v3_1 *) 471 - cgs_atom_get_data_table(hwmgr->device, 470 + smu_atom_get_data_table(hwmgr->adev, 472 471 idx, NULL, NULL, NULL); 473 472 474 473 if (!info) { ··· 490 489 491 490 int pp_atomfwctrl__get_clk_information_by_clkid(struct pp_hwmgr *hwmgr, BIOS_CLKID id, uint32_t *frequency) 492 491 { 492 + struct amdgpu_device *adev = hwmgr->adev; 493 493 struct atom_get_smu_clock_info_parameters_v3_1 parameters; 494 494 struct atom_get_smu_clock_info_output_parameters_v3_1 *output; 495 495 uint32_t ix; ··· 499 497 parameters.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ; 500 498 501 499 ix = GetIndexIntoMasterCmdTable(getsmuclockinfo); 502 - if (!cgs_atom_exec_cmd_table(hwmgr->device, ix, &parameters)) { 503 - output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters; 504 - *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000; 505 - } else { 506 - pr_info("Error execute_table getsmuclockinfo!"); 507 - return -1; 508 - } 500 + 501 + if (amdgpu_atom_execute_table( 502 + adev->mode_info.atom_context, ix, (uint32_t *)&parameters)) 503 + return -EINVAL; 504 + 505 + output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&parameters; 506 + *frequency = output->atom_smu_outputclkfreq.smu_clock_freq_hz / 10000; 509 507 510 508 return 0; 511 509 } ··· 519 517 520 518 ix = GetIndexIntoMasterDataTable(firmwareinfo); 521 519 info = (struct atom_firmware_info_v3_1 *) 522 - cgs_atom_get_data_table(hwmgr->device, 520 + smu_atom_get_data_table(hwmgr->adev, 523 521 ix, NULL, NULL, NULL); 524 522 525 523 if (!info) { ··· 555 553 556 554 ix = GetIndexIntoMasterDataTable(smc_dpm_info); 557 555 info = (struct atom_smc_dpm_info_v4_1 *) 558 - cgs_atom_get_data_table(hwmgr->device, 556 + smu_atom_get_data_table(hwmgr->adev, 559 557 ix, NULL, NULL, NULL); 560 558 if (!info) { 561 559 pr_info("Error retrieving BIOS Table Address!");

+1 -1

drivers/gpu/drm/amd/powerplay/hwmgr/process_pptables_v1_0.c

··· 141 141 142 142 if (!table_address) { 143 143 table_address = (ATOM_Tonga_POWERPLAYTABLE *) 144 - cgs_atom_get_data_table(hwmgr->device, 144 + smu_atom_get_data_table(hwmgr->adev, 145 145 index, &size, &frev, &crev); 146 146 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/ 147 147 hwmgr->soft_pp_table_size = size;

+2 -2

drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c

··· 837 837 hwmgr->soft_pp_table = &soft_dummy_pp_table[0]; 838 838 hwmgr->soft_pp_table_size = sizeof(soft_dummy_pp_table); 839 839 } else { 840 - table_addr = cgs_atom_get_data_table(hwmgr->device, 840 + table_addr = smu_atom_get_data_table(hwmgr->adev, 841 841 GetIndexIntoMasterTable(DATA, PowerPlayInfo), 842 842 &size, &frev, &crev); 843 843 hwmgr->soft_pp_table = table_addr; ··· 1058 1058 return 0; 1059 1059 1060 1060 /* We assume here that fw_info is unchanged if this call fails.*/ 1061 - fw_info = cgs_atom_get_data_table(hwmgr->device, 1061 + fw_info = smu_atom_get_data_table(hwmgr->adev, 1062 1062 GetIndexIntoMasterTable(DATA, FirmwareInfo), 1063 1063 &size, &frev, &crev); 1064 1064

+1 -2

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

··· 2957 2957 /* First retrieve the Boot clocks and VDDC from the firmware info table. 2958 2958 * We assume here that fw_info is unchanged if this call fails. 2959 2959 */ 2960 - fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)cgs_atom_get_data_table( 2961 - hwmgr->device, index, 2960 + fw_info = (ATOM_FIRMWARE_INFO_V2_2 *)smu_atom_get_data_table(hwmgr->adev, index, 2962 2961 &size, &frev, &crev); 2963 2962 if (!fw_info) 2964 2963 /* During a test, there is no firmware info table. */

+1 -2

drivers/gpu/drm/amd/powerplay/hwmgr/smu8_hwmgr.c

··· 314 314 uint8_t frev, crev; 315 315 uint16_t size; 316 316 317 - info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *) cgs_atom_get_data_table( 318 - hwmgr->device, 317 + info = (ATOM_INTEGRATED_SYSTEM_INFO_V1_9 *)smu_atom_get_data_table(hwmgr->adev, 319 318 GetIndexIntoMasterTable(DATA, IntegratedSystemInfo), 320 319 &size, &frev, &crev); 321 320

+16

drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.c

··· 24 24 #include "pp_debug.h" 25 25 #include "ppatomctrl.h" 26 26 #include "ppsmc.h" 27 + #include "atom.h" 27 28 28 29 uint8_t convert_to_vid(uint16_t vddc) 29 30 { ··· 608 607 source); 609 608 610 609 return 0; 610 + } 611 + 612 + void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, 613 + uint8_t *frev, uint8_t *crev) 614 + { 615 + struct amdgpu_device *adev = dev; 616 + uint16_t data_start; 617 + 618 + if (amdgpu_atom_parse_data_header( 619 + adev->mode_info.atom_context, table, size, 620 + frev, crev, &data_start)) 621 + return (uint8_t *)adev->mode_info.atom_context->bios + 622 + data_start; 623 + 624 + return NULL; 611 625 }

+3

drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h

··· 82 82 83 83 int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr); 84 84 85 + void *smu_atom_get_data_table(void *dev, uint32_t table, uint16_t *size, 86 + uint8_t *frev, uint8_t *crev); 87 + 85 88 #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT 86 89 #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK 87 90

+1 -1

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_processpptables.c

··· 52 52 53 53 if (!table_address) { 54 54 table_address = (ATOM_Vega10_POWERPLAYTABLE *) 55 - cgs_atom_get_data_table(hwmgr->device, index, 55 + smu_atom_get_data_table(hwmgr->adev, index, 56 56 &size, &frev, &crev); 57 57 58 58 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/

+1 -1

drivers/gpu/drm/amd/powerplay/hwmgr/vega12_processpptables.c

··· 51 51 52 52 if (!table_address) { 53 53 table_address = (ATOM_Vega12_POWERPLAYTABLE *) 54 - cgs_atom_get_data_table(hwmgr->device, index, 54 + smu_atom_get_data_table(hwmgr->adev, index, 55 55 &size, &frev, &crev); 56 56 57 57 hwmgr->soft_pp_table = table_address; /*Cache the result in RAM.*/

+1 -1

drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c

··· 337 337 if (!hwmgr->not_vf) 338 338 return false; 339 339 340 - if (!atomctrl_read_efuse(hwmgr->device, AVFS_EN_LSB, AVFS_EN_MSB, 340 + if (!atomctrl_read_efuse(hwmgr, AVFS_EN_LSB, AVFS_EN_MSB, 341 341 mask, &efuse)) { 342 342 if (efuse) 343 343 return true;

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