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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
clk: qcom: camcc-sc8180x: Refactor to use qcom_cc_driver_data
Use a qcom_cc_driver_data struct instead of a long custom probe
callback to align with modern qcom/gcc-*.c style.
No functional change intended.
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-12-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Val Packett
and committed by
Bjorn Andersson
b39ae8c2
acf7a91d
+32
-35
+32
-35
drivers/clk/qcom/camcc-sc8180x.c
+32
-35
drivers/clk/qcom/camcc-sc8180x.c
···
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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-
#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sc8180x-camcc.h>
···
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static struct clk_alpha_pll cam_cc_pll0 = {
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.offset = 0x0,
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+
.config = &cam_cc_pll0_config,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
···
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static struct clk_alpha_pll cam_cc_pll1 = {
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.offset = 0x1000,
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+
.config = &cam_cc_pll1_config,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
···
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static struct clk_alpha_pll cam_cc_pll2 = {
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.offset = 0x2000,
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.config = &cam_cc_pll2_config,
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.vco_table = regera_vco,
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.num_vco = ARRAY_SIZE(regera_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_REGERA],
···
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static struct clk_alpha_pll cam_cc_pll3 = {
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.offset = 0x3000,
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.config = &cam_cc_pll3_config,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
···
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static struct clk_alpha_pll cam_cc_pll4 = {
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.offset = 0x4000,
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.config = &cam_cc_pll4_config,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
···
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static struct clk_alpha_pll cam_cc_pll5 = {
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.offset = 0x4078,
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.config = &cam_cc_pll5_config,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
···
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static struct clk_alpha_pll cam_cc_pll6 = {
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.offset = 0x40f0,
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.config = &cam_cc_pll6_config,
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.vco_table = trion_vco,
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.num_vco = ARRAY_SIZE(trion_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
···
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[CAM_CC_MCLK7_BCR] = { 0x50e0 },
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};
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+
static struct clk_alpha_pll *cam_cc_sc8180x_plls[] = {
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&cam_cc_pll0,
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&cam_cc_pll1,
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&cam_cc_pll2,
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&cam_cc_pll3,
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&cam_cc_pll4,
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&cam_cc_pll5,
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&cam_cc_pll6,
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+
};
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+
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+
static u32 cam_cc_sc8180x_critical_cbcrs[] = {
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0xc1e4, /* CAM_CC_GDSC_CLK */
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0xc200, /* CAM_CC_SLEEP_CLK */
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+
};
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+
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static const struct regmap_config cam_cc_sc8180x_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xf0d4,
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.fast_io = true,
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+
};
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+
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+
static struct qcom_cc_driver_data cam_cc_sc8180x_driver_data = {
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+
.alpha_plls = cam_cc_sc8180x_plls,
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+
.num_alpha_plls = ARRAY_SIZE(cam_cc_sc8180x_plls),
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+
.clk_cbcrs = cam_cc_sc8180x_critical_cbcrs,
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+
.num_clk_cbcrs = ARRAY_SIZE(cam_cc_sc8180x_critical_cbcrs),
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};
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static const struct qcom_cc_desc cam_cc_sc8180x_desc = {
···
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.num_resets = ARRAY_SIZE(cam_cc_sc8180x_resets),
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.gdscs = cam_cc_sc8180x_gdscs,
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.num_gdscs = ARRAY_SIZE(cam_cc_sc8180x_gdscs),
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.use_rpm = true,
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.driver_data = &cam_cc_sc8180x_driver_data,
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};
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static const struct of_device_id cam_cc_sc8180x_match_table[] = {
···
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static int cam_cc_sc8180x_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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ret = devm_pm_runtime_enable(&pdev->dev);
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if (ret)
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return ret;
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ret = pm_runtime_resume_and_get(&pdev->dev);
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if (ret)
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return ret;
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regmap = qcom_cc_map(pdev, &cam_cc_sc8180x_desc);
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if (IS_ERR(regmap)) {
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pm_runtime_put(&pdev->dev);
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return PTR_ERR(regmap);
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}
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clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
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clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
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clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
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clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
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clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
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clk_trion_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
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clk_trion_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
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-
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/* Keep some clocks always enabled */
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qcom_branch_set_clk_en(regmap, 0xc1e4); /* CAM_CC_GDSC_CLK */
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qcom_branch_set_clk_en(regmap, 0xc200); /* CAM_CC_SLEEP_CLK */
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ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sc8180x_desc, regmap);
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pm_runtime_put(&pdev->dev);
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return ret;
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return qcom_cc_probe(pdev, &cam_cc_sc8180x_desc);
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}
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static struct platform_driver cam_cc_sc8180x_driver = {