Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/{i915, xe}/pcode: move display pcode calls to parent interface
Call the parent driver pcode functions through the parent interface
function pointers instead of expecting both to have functions of the
same name.
In i915, add the interface to existing intel_pcode.[ch], while in xe
move them to new display/xe_display_pcode.[ch] and build it only for
CONFIG_DRM_XE_DISPLAY=y.
Do not add separate write and write_timeout calls in the
interface. Instead, handle the default 1 ms timeout in the
intel_parent.c glue layer.
This drops the last intel_pcode.h includes from display, and allows us
to remove the corresponding xe compat header.
v2: initialize .pcode in i915
Reviewed-by: Michał Grzelak <michal.grzelak@intel.com>
Link: https://patch.msgid.link/20260126112925.2452171-1-jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+161
-125
+4
-4
drivers/gpu/drm/i915/display/hsw_ips.c
+4
-4
drivers/gpu/drm/i915/display/hsw_ips.c
···
14
14
#include "intel_display_regs.h"
15
15
#include "intel_display_rpm.h"
16
16
#include "intel_display_types.h"
17
-
#include "intel_pcode.h"
17
+
#include "intel_parent.h"
18
18
19
19
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
20
20
{
···
39
39
40
40
if (display->platform.broadwell) {
41
41
drm_WARN_ON(display->drm,
42
-
intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL,
43
-
val | IPS_PCODE_CONTROL));
42
+
intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL,
43
+
val | IPS_PCODE_CONTROL));
44
44
/*
45
45
* Quoting Art Runyan: "its not safe to expect any particular
46
46
* value in IPS_CTL bit 31 after enabling IPS through the
···
72
72
73
73
if (display->platform.broadwell) {
74
74
drm_WARN_ON(display->drm,
75
-
intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0));
75
+
intel_parent_pcode_write(display, DISPLAY_IPS_CONTROL, 0));
76
76
/*
77
77
* Wait for PCODE to finish disabling IPS. The BSpec specified
78
78
* 42ms timeout value leads to occasional timeouts so use 100ms
+11
-11
drivers/gpu/drm/i915/display/intel_bw.c
+11
-11
drivers/gpu/drm/i915/display/intel_bw.c
···
15
15
#include "intel_display_utils.h"
16
16
#include "intel_dram.h"
17
17
#include "intel_mchbar_regs.h"
18
-
#include "intel_pcode.h"
18
+
#include "intel_parent.h"
19
19
#include "intel_uncore.h"
20
20
#include "skl_watermark.h"
21
21
···
114
114
u16 dclk;
115
115
int ret;
116
116
117
-
ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
118
-
ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
119
-
&val, &val2);
117
+
ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
118
+
ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
119
+
&val, &val2);
120
120
if (ret)
121
121
return ret;
122
122
···
141
141
int ret;
142
142
int i;
143
143
144
-
ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
145
-
ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
144
+
ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
145
+
ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
146
146
if (ret)
147
147
return ret;
148
148
···
189
189
return 0;
190
190
191
191
/* bspec says to keep retrying for at least 1 ms */
192
-
ret = intel_pcode_request(display->drm, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
193
-
points_mask,
194
-
ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
195
-
ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
196
-
1);
192
+
ret = intel_parent_pcode_request(display, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
193
+
points_mask,
194
+
ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
195
+
ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
196
+
1);
197
197
198
198
if (ret < 0) {
199
199
drm_err(display->drm,
+27
-27
drivers/gpu/drm/i915/display/intel_cdclk.c
+27
-27
drivers/gpu/drm/i915/display/intel_cdclk.c
···
42
42
#include "intel_display_wa.h"
43
43
#include "intel_dram.h"
44
44
#include "intel_mchbar_regs.h"
45
+
#include "intel_parent.h"
45
46
#include "intel_pci_config.h"
46
-
#include "intel_pcode.h"
47
47
#include "intel_plane.h"
48
48
#include "intel_psr.h"
49
49
#include "intel_step.h"
···
888
888
"trying to change cdclk frequency with cdclk not enabled\n"))
889
889
return;
890
890
891
-
ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
891
+
ret = intel_parent_pcode_write(display, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
892
892
if (ret) {
893
893
drm_err(display->drm,
894
894
"failed to inform pcode about cdclk change\n");
···
918
918
if (ret)
919
919
drm_err(display->drm, "Switching back to LCPLL failed\n");
920
920
921
-
intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ,
922
-
cdclk_config->voltage_level);
921
+
intel_parent_pcode_write(display, HSW_PCODE_DE_WRITE_FREQ_REQ,
922
+
cdclk_config->voltage_level);
923
923
924
924
intel_de_write(display, CDCLK_FREQ,
925
925
DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
···
1175
1175
drm_WARN_ON_ONCE(display->drm,
1176
1176
display->platform.skylake && vco == 8640000);
1177
1177
1178
-
ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
1179
-
SKL_CDCLK_PREPARE_FOR_CHANGE,
1180
-
SKL_CDCLK_READY_FOR_CHANGE,
1181
-
SKL_CDCLK_READY_FOR_CHANGE, 3);
1178
+
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
1179
+
SKL_CDCLK_PREPARE_FOR_CHANGE,
1180
+
SKL_CDCLK_READY_FOR_CHANGE,
1181
+
SKL_CDCLK_READY_FOR_CHANGE, 3);
1182
1182
if (ret) {
1183
1183
drm_err(display->drm,
1184
1184
"Failed to inform PCU about cdclk change (%d)\n", ret);
···
1221
1221
intel_de_posting_read(display, CDCLK_CTL);
1222
1222
1223
1223
/* inform PCU of the change */
1224
-
intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
1225
-
cdclk_config->voltage_level);
1224
+
intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
1225
+
cdclk_config->voltage_level);
1226
1226
1227
1227
intel_update_cdclk(display);
1228
1228
}
···
2247
2247
if (DISPLAY_VER(display) >= 14 || display->platform.dg2)
2248
2248
; /* NOOP */
2249
2249
else if (DISPLAY_VER(display) >= 11)
2250
-
ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
2251
-
SKL_CDCLK_PREPARE_FOR_CHANGE,
2252
-
SKL_CDCLK_READY_FOR_CHANGE,
2253
-
SKL_CDCLK_READY_FOR_CHANGE, 3);
2250
+
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
2251
+
SKL_CDCLK_PREPARE_FOR_CHANGE,
2252
+
SKL_CDCLK_READY_FOR_CHANGE,
2253
+
SKL_CDCLK_READY_FOR_CHANGE, 3);
2254
2254
else
2255
2255
/*
2256
2256
* BSpec requires us to wait up to 150usec, but that leads to
2257
2257
* timeouts; the 2ms used here is based on experiment.
2258
2258
*/
2259
-
ret = intel_pcode_write_timeout(display->drm,
2260
-
HSW_PCODE_DE_WRITE_FREQ_REQ,
2261
-
0x80000000, 2);
2259
+
ret = intel_parent_pcode_write_timeout(display,
2260
+
HSW_PCODE_DE_WRITE_FREQ_REQ,
2261
+
0x80000000, 2);
2262
2262
2263
2263
if (ret) {
2264
2264
drm_err(display->drm,
···
2287
2287
* Display versions 14 and beyond
2288
2288
*/;
2289
2289
else if (DISPLAY_VER(display) >= 11 && !display->platform.dg2)
2290
-
ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL,
2291
-
cdclk_config->voltage_level);
2290
+
ret = intel_parent_pcode_write(display, SKL_PCODE_CDCLK_CONTROL,
2291
+
cdclk_config->voltage_level);
2292
2292
if (DISPLAY_VER(display) < 11) {
2293
2293
/*
2294
2294
* The timeout isn't specified, the 2ms used here is based on
···
2296
2296
* FIXME: Waiting for the request completion could be delayed
2297
2297
* until the next PCODE request based on BSpec.
2298
2298
*/
2299
-
ret = intel_pcode_write_timeout(display->drm,
2300
-
HSW_PCODE_DE_WRITE_FREQ_REQ,
2301
-
cdclk_config->voltage_level, 2);
2299
+
ret = intel_parent_pcode_write_timeout(display,
2300
+
HSW_PCODE_DE_WRITE_FREQ_REQ,
2301
+
cdclk_config->voltage_level, 2);
2302
2302
}
2303
2303
if (ret) {
2304
2304
drm_err(display->drm,
···
2598
2598
if (pipe_count_update_valid)
2599
2599
update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2600
2600
2601
-
ret = intel_pcode_request(display->drm, SKL_PCODE_CDCLK_CONTROL,
2602
-
SKL_CDCLK_PREPARE_FOR_CHANGE |
2603
-
update_mask,
2604
-
SKL_CDCLK_READY_FOR_CHANGE,
2605
-
SKL_CDCLK_READY_FOR_CHANGE, 3);
2601
+
ret = intel_parent_pcode_request(display, SKL_PCODE_CDCLK_CONTROL,
2602
+
SKL_CDCLK_PREPARE_FOR_CHANGE |
2603
+
update_mask,
2604
+
SKL_CDCLK_READY_FOR_CHANGE,
2605
+
SKL_CDCLK_READY_FOR_CHANGE, 3);
2606
2606
if (ret)
2607
2607
drm_err(display->drm,
2608
2608
"Failed to inform PCU about display config (err %d)\n",
+1
-2
drivers/gpu/drm/i915/display/intel_display_power.c
+1
-2
drivers/gpu/drm/i915/display/intel_display_power.c
···
26
26
#include "intel_mchbar_regs.h"
27
27
#include "intel_parent.h"
28
28
#include "intel_pch_refclk.h"
29
-
#include "intel_pcode.h"
30
29
#include "intel_pmdemand.h"
31
30
#include "intel_pps_regs.h"
32
31
#include "intel_snps_phy.h"
···
1259
1260
static void hsw_write_dcomp(struct intel_display *display, u32 val)
1260
1261
{
1261
1262
if (display->platform.haswell) {
1262
-
if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val))
1263
+
if (intel_parent_pcode_write(display, GEN6_PCODE_WRITE_D_COMP, val))
1263
1264
drm_dbg_kms(display->drm, "Failed to write to D_COMP\n");
1264
1265
} else {
1265
1266
intel_de_write(display, D_COMP_BDW, val);
+2
-3
drivers/gpu/drm/i915/display/intel_display_power_well.c
+2
-3
drivers/gpu/drm/i915/display/intel_display_power_well.c
···
27
27
#include "intel_dpll.h"
28
28
#include "intel_hotplug.h"
29
29
#include "intel_parent.h"
30
-
#include "intel_pcode.h"
31
30
#include "intel_pps.h"
32
31
#include "intel_psr.h"
33
32
#include "intel_tc.h"
···
517
518
int ret, tries = 0;
518
519
519
520
while (1) {
520
-
ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0);
521
+
ret = intel_parent_pcode_write(display, ICL_PCODE_EXIT_TCCOLD, 0);
521
522
if (ret != -EAGAIN || ++tries == 3)
522
523
break;
523
524
msleep(1);
···
1790
1791
* Spec states that we should timeout the request after 200us
1791
1792
* but the function below will timeout after 500us
1792
1793
*/
1793
-
ret = intel_pcode_read(display->drm, TGL_PCODE_TCCOLD, &low_val, &high_val);
1794
+
ret = intel_parent_pcode_read(display, TGL_PCODE_TCCOLD, &low_val, &high_val);
1794
1795
if (ret == 0) {
1795
1796
if (block &&
1796
1797
(low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
+3
-3
drivers/gpu/drm/i915/display/intel_dram.c
+3
-3
drivers/gpu/drm/i915/display/intel_dram.c
···
13
13
#include "intel_display_utils.h"
14
14
#include "intel_dram.h"
15
15
#include "intel_mchbar_regs.h"
16
-
#include "intel_pcode.h"
16
+
#include "intel_parent.h"
17
17
#include "intel_uncore.h"
18
18
#include "vlv_iosf_sb.h"
19
19
···
692
692
u32 val = 0;
693
693
int ret;
694
694
695
-
ret = intel_pcode_read(display->drm, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
696
-
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
695
+
ret = intel_parent_pcode_read(display, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
696
+
ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
697
697
if (ret)
698
698
return ret;
699
699
+1
-2
drivers/gpu/drm/i915/display/intel_hdcp.c
+1
-2
drivers/gpu/drm/i915/display/intel_hdcp.c
···
33
33
#include "intel_hdcp_regs.h"
34
34
#include "intel_hdcp_shim.h"
35
35
#include "intel_parent.h"
36
-
#include "intel_pcode.h"
37
36
#include "intel_step.h"
38
37
39
38
#define USE_HDCP_GSC(__display) (DISPLAY_VER(__display) >= 14)
···
397
398
* Mailbox interface.
398
399
*/
399
400
if (DISPLAY_VER(display) == 9 && !display->platform.broxton) {
400
-
ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1);
401
+
ret = intel_parent_pcode_write(display, SKL_PCODE_LOAD_HDCP_KEYS, 1);
401
402
if (ret) {
402
403
drm_err(display->drm,
403
404
"Failed to initiate HDCP key load (%d)\n",
+22
drivers/gpu/drm/i915/display/intel_parent.c
+22
drivers/gpu/drm/i915/display/intel_parent.c
···
92
92
display->parent->pc8->unblock(display->drm);
93
93
}
94
94
95
+
/* pcode */
96
+
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1)
97
+
{
98
+
return display->parent->pcode->read(display->drm, mbox, val, val1);
99
+
}
100
+
101
+
int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms)
102
+
{
103
+
return display->parent->pcode->write(display->drm, mbox, val, timeout_ms);
104
+
}
105
+
106
+
int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val)
107
+
{
108
+
return intel_parent_pcode_write_timeout(display, mbox, val, 1);
109
+
}
110
+
111
+
int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
112
+
u32 reply_mask, u32 reply, int timeout_base_ms)
113
+
{
114
+
return display->parent->pcode->request(display->drm, mbox, request, reply_mask, reply, timeout_base_ms);
115
+
}
116
+
95
117
/* rps */
96
118
bool intel_parent_rps_available(struct intel_display *display)
97
119
{
+7
drivers/gpu/drm/i915/display/intel_parent.h
+7
drivers/gpu/drm/i915/display/intel_parent.h
···
36
36
void intel_parent_pc8_block(struct intel_display *display);
37
37
void intel_parent_pc8_unblock(struct intel_display *display);
38
38
39
+
/* pcode */
40
+
int intel_parent_pcode_read(struct intel_display *display, u32 mbox, u32 *val, u32 *val1);
41
+
int intel_parent_pcode_write_timeout(struct intel_display *display, u32 mbox, u32 val, int timeout_ms);
42
+
int intel_parent_pcode_write(struct intel_display *display, u32 mbox, u32 val);
43
+
int intel_parent_pcode_request(struct intel_display *display, u32 mbox, u32 request,
44
+
u32 reply_mask, u32 reply, int timeout_base_ms);
45
+
39
46
/* rps */
40
47
bool intel_parent_rps_available(struct intel_display *display);
41
48
void intel_parent_rps_boost_if_not_started(struct intel_display *display, struct dma_fence *fence);
+10
-11
drivers/gpu/drm/i915/display/skl_watermark.c
+10
-11
drivers/gpu/drm/i915/display/skl_watermark.c
···
26
26
#include "intel_fb.h"
27
27
#include "intel_fixed.h"
28
28
#include "intel_flipq.h"
29
-
#include "intel_pcode.h"
29
+
#include "intel_parent.h"
30
30
#include "intel_plane.h"
31
31
#include "intel_vblank.h"
32
32
#include "intel_wm.h"
···
115
115
u32 val = 0;
116
116
int ret;
117
117
118
-
ret = intel_pcode_read(display->drm,
119
-
GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
120
-
&val, NULL);
118
+
ret = intel_parent_pcode_read(display, GEN12_PCODE_READ_SAGV_BLOCK_TIME_US,
119
+
&val, NULL);
121
120
if (ret) {
122
121
drm_dbg_kms(display->drm, "Couldn't read SAGV block time!\n");
123
122
return 0;
···
183
184
return;
184
185
185
186
drm_dbg_kms(display->drm, "Enabling SAGV\n");
186
-
ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL,
187
-
GEN9_SAGV_ENABLE);
187
+
ret = intel_parent_pcode_write(display, GEN9_PCODE_SAGV_CONTROL,
188
+
GEN9_SAGV_ENABLE);
188
189
189
190
/* We don't need to wait for SAGV when enabling */
190
191
···
216
217
217
218
drm_dbg_kms(display->drm, "Disabling SAGV\n");
218
219
/* bspec says to keep retrying for at least 1 ms */
219
-
ret = intel_pcode_request(display->drm, GEN9_PCODE_SAGV_CONTROL,
220
-
GEN9_SAGV_DISABLE,
221
-
GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1);
220
+
ret = intel_parent_pcode_request(display, GEN9_PCODE_SAGV_CONTROL,
221
+
GEN9_SAGV_DISABLE,
222
+
GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, 1);
222
223
/*
223
224
* Some skl systems, pre-release machines in particular,
224
225
* don't actually have SAGV.
···
3282
3283
3283
3284
/* read the first set of memory latencies[0:3] */
3284
3285
val = 0; /* data0 to be programmed to 0 for first set */
3285
-
ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
3286
+
ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
3286
3287
if (ret) {
3287
3288
drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
3288
3289
return;
···
3295
3296
3296
3297
/* read the second set of memory latencies[4:7] */
3297
3298
val = 1; /* data0 to be programmed to 1 for second set */
3298
-
ret = intel_pcode_read(display->drm, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
3299
+
ret = intel_parent_pcode_read(display, GEN9_PCODE_READ_MEM_LATENCY, &val, NULL);
3299
3300
if (ret) {
3300
3301
drm_err(display->drm, "SKL Mailbox read error = %d\n", ret);
3301
3302
return;
+1
drivers/gpu/drm/i915/i915_driver.c
+1
drivers/gpu/drm/i915/i915_driver.c
···
771
771
.irq = &i915_display_irq_interface,
772
772
.panic = &i915_display_panic_interface,
773
773
.pc8 = &i915_display_pc8_interface,
774
+
.pcode = &i915_display_pcode_interface,
774
775
.rpm = &i915_display_rpm_interface,
775
776
.rps = &i915_display_rps_interface,
776
777
.stolen = &i915_display_stolen_interface,
+11
-5
drivers/gpu/drm/i915/intel_pcode.c
+11
-5
drivers/gpu/drm/i915/intel_pcode.c
···
4
4
*/
5
5
6
6
#include <drm/drm_print.h>
7
+
#include <drm/intel/display_parent_interface.h>
7
8
8
9
#include "i915_drv.h"
9
10
#include "i915_reg.h"
···
277
276
return err;
278
277
}
279
278
280
-
/* Helpers with drm device */
281
-
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
279
+
static int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
282
280
{
283
281
struct drm_i915_private *i915 = to_i915(drm);
284
282
285
283
return snb_pcode_read(&i915->uncore, mbox, val, val1);
286
284
}
287
285
288
-
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
286
+
static int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
289
287
{
290
288
struct drm_i915_private *i915 = to_i915(drm);
291
289
292
290
return snb_pcode_write_timeout(&i915->uncore, mbox, val, timeout_ms);
293
291
}
294
292
295
-
int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
296
-
u32 reply_mask, u32 reply, int timeout_base_ms)
293
+
static int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
294
+
u32 reply_mask, u32 reply, int timeout_base_ms)
297
295
{
298
296
struct drm_i915_private *i915 = to_i915(drm);
299
297
300
298
return skl_pcode_request(&i915->uncore, mbox, request, reply_mask, reply,
301
299
timeout_base_ms);
302
300
}
301
+
302
+
const struct intel_display_pcode_interface i915_display_pcode_interface = {
303
+
.read = intel_pcode_read,
304
+
.write = intel_pcode_write_timeout,
305
+
.request = intel_pcode_request,
306
+
};
+1
-8
drivers/gpu/drm/i915/intel_pcode.h
+1
-8
drivers/gpu/drm/i915/intel_pcode.h
···
27
27
int snb_pcode_read_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 *val);
28
28
int snb_pcode_write_p(struct intel_uncore *uncore, u32 mbcmd, u32 p1, u32 p2, u32 val);
29
29
30
-
/* Helpers with drm device */
31
-
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
32
-
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
33
-
#define intel_pcode_write(drm, mbox, val) \
34
-
intel_pcode_write_timeout((drm), (mbox), (val), 1)
35
-
36
-
int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
37
-
u32 reply_mask, u32 reply, int timeout_base_ms);
30
+
extern const struct intel_display_pcode_interface i915_display_pcode_interface;
38
31
39
32
#endif /* _INTEL_PCODE_H */
+1
drivers/gpu/drm/xe/Makefile
+1
drivers/gpu/drm/xe/Makefile
-11
drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
-11
drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h
+2
drivers/gpu/drm/xe/display/xe_display.c
+2
drivers/gpu/drm/xe/display/xe_display.c
···
35
35
#include "intel_hotplug.h"
36
36
#include "intel_opregion.h"
37
37
#include "skl_watermark.h"
38
+
#include "xe_display_pcode.h"
38
39
#include "xe_display_rpm.h"
39
40
#include "xe_dsb_buffer.h"
40
41
#include "xe_hdcp_gsc.h"
···
545
544
.initial_plane = &xe_display_initial_plane_interface,
546
545
.irq = &xe_display_irq_interface,
547
546
.panic = &xe_display_panic_interface,
547
+
.pcode = &xe_display_pcode_interface,
548
548
.rpm = &xe_display_rpm_interface,
549
549
.stolen = &xe_display_stolen_interface,
550
550
};
+38
drivers/gpu/drm/xe/display/xe_display_pcode.c
+38
drivers/gpu/drm/xe/display/xe_display_pcode.c
···
1
+
// SPDX-License-Identifier: MIT
2
+
/* Copyright © 2026 Intel Corporation */
3
+
4
+
#include <drm/intel/display_parent_interface.h>
5
+
6
+
#include "xe_device.h"
7
+
#include "xe_pcode.h"
8
+
9
+
static int xe_display_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
10
+
{
11
+
struct xe_device *xe = to_xe_device(drm);
12
+
struct xe_tile *tile = xe_device_get_root_tile(xe);
13
+
14
+
return xe_pcode_read(tile, mbox, val, val1);
15
+
}
16
+
17
+
static int xe_display_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
18
+
{
19
+
struct xe_device *xe = to_xe_device(drm);
20
+
struct xe_tile *tile = xe_device_get_root_tile(xe);
21
+
22
+
return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);
23
+
}
24
+
25
+
static int xe_display_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
26
+
u32 reply_mask, u32 reply, int timeout_base_ms)
27
+
{
28
+
struct xe_device *xe = to_xe_device(drm);
29
+
struct xe_tile *tile = xe_device_get_root_tile(xe);
30
+
31
+
return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);
32
+
}
33
+
34
+
const struct intel_display_pcode_interface xe_display_pcode_interface = {
35
+
.read = xe_display_pcode_read,
36
+
.write = xe_display_pcode_write_timeout,
37
+
.request = xe_display_pcode_request,
38
+
};
+9
drivers/gpu/drm/xe/display/xe_display_pcode.h
+9
drivers/gpu/drm/xe/display/xe_display_pcode.h
-30
drivers/gpu/drm/xe/xe_pcode.c
-30
drivers/gpu/drm/xe/xe_pcode.c
···
348
348
return xe_pcode_ready(xe, false);
349
349
}
350
350
ALLOW_ERROR_INJECTION(xe_pcode_probe_early, ERRNO); /* See xe_pci_probe */
351
-
352
-
/* Helpers with drm device. These should only be called by the display side */
353
-
#if IS_ENABLED(CONFIG_DRM_XE_DISPLAY)
354
-
355
-
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1)
356
-
{
357
-
struct xe_device *xe = to_xe_device(drm);
358
-
struct xe_tile *tile = xe_device_get_root_tile(xe);
359
-
360
-
return xe_pcode_read(tile, mbox, val, val1);
361
-
}
362
-
363
-
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms)
364
-
{
365
-
struct xe_device *xe = to_xe_device(drm);
366
-
struct xe_tile *tile = xe_device_get_root_tile(xe);
367
-
368
-
return xe_pcode_write_timeout(tile, mbox, val, timeout_ms);
369
-
}
370
-
371
-
int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
372
-
u32 reply_mask, u32 reply, int timeout_base_ms)
373
-
{
374
-
struct xe_device *xe = to_xe_device(drm);
375
-
struct xe_tile *tile = xe_device_get_root_tile(xe);
376
-
377
-
return xe_pcode_request(tile, mbox, request, reply_mask, reply, timeout_base_ms);
378
-
}
379
-
380
-
#endif
-8
drivers/gpu/drm/xe/xe_pcode.h
-8
drivers/gpu/drm/xe/xe_pcode.h
···
34
34
| FIELD_PREP(PCODE_MB_PARAM1, param1)\
35
35
| FIELD_PREP(PCODE_MB_PARAM2, param2))
36
36
37
-
/* Helpers with drm device */
38
-
int intel_pcode_read(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
39
-
int intel_pcode_write_timeout(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
40
-
#define intel_pcode_write(drm, mbox, val) \
41
-
intel_pcode_write_timeout((drm), (mbox), (val), 1)
42
-
int intel_pcode_request(struct drm_device *drm, u32 mbox, u32 request,
43
-
u32 reply_mask, u32 reply, int timeout_base_ms);
44
-
45
37
#endif
+10
include/drm/intel/display_parent_interface.h
+10
include/drm/intel/display_parent_interface.h
···
66
66
void (*unblock)(struct drm_device *drm);
67
67
};
68
68
69
+
struct intel_display_pcode_interface {
70
+
int (*read)(struct drm_device *drm, u32 mbox, u32 *val, u32 *val1);
71
+
int (*write)(struct drm_device *drm, u32 mbox, u32 val, int timeout_ms);
72
+
int (*request)(struct drm_device *drm, u32 mbox, u32 request,
73
+
u32 reply_mask, u32 reply, int timeout_base_ms);
74
+
};
75
+
69
76
struct intel_display_rpm_interface {
70
77
struct ref_tracker *(*get)(const struct drm_device *drm);
71
78
struct ref_tracker *(*get_raw)(const struct drm_device *drm);
···
141
134
142
135
/** @pc8: PC8 interface. Optional. */
143
136
const struct intel_display_pc8_interface *pc8;
137
+
138
+
/** @pcode: Pcode interface */
139
+
const struct intel_display_pcode_interface *pcode;
144
140
145
141
/** @rpm: Runtime PM functions */
146
142
const struct intel_display_rpm_interface *rpm;