Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dp: move phy_configure_opts to dp_ctrl
There is little point in sharing phy configuration structure between
several modules. Move it to dp_ctrl, which becomes the only submodule
re-configuring the PHY.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576124/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-9-098d5f581dd3@linaro.org
+27
-38
-19
drivers/gpu/drm/msm/dp/dp_catalog.c
-19
drivers/gpu/drm/msm/dp/dp_catalog.c
···
765
765
dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0);
766
766
}
767
767
768
-
int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog,
769
-
u8 v_level, u8 p_level)
770
-
{
771
-
struct dp_catalog_private *catalog = container_of(dp_catalog,
772
-
struct dp_catalog_private, dp_catalog);
773
-
struct dp_io *dp_io = catalog->io;
774
-
struct phy *phy = dp_io->phy;
775
-
struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
776
-
777
-
/* TODO: Update for all lanes instead of just first one */
778
-
opts_dp->voltage[0] = v_level;
779
-
opts_dp->pre[0] = p_level;
780
-
opts_dp->set_voltages = 1;
781
-
phy_configure(phy, &dp_io->phy_opts);
782
-
opts_dp->set_voltages = 0;
783
-
784
-
return 0;
785
-
}
786
-
787
768
void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog,
788
769
u32 pattern)
789
770
{
-2
drivers/gpu/drm/msm/dp/dp_catalog.h
-2
drivers/gpu/drm/msm/dp/dp_catalog.h
···
111
111
u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog);
112
112
u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog);
113
113
void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog);
114
-
int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level,
115
-
u8 p_level);
116
114
int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog);
117
115
u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog);
118
116
void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog,
+27
-14
drivers/gpu/drm/msm/dp/dp_ctrl.c
+27
-14
drivers/gpu/drm/msm/dp/dp_ctrl.c
···
87
87
88
88
struct clk *pixel_clk;
89
89
90
+
union phy_configure_opts phy_opts;
91
+
90
92
struct completion idle_comp;
91
93
struct completion psr_op_comp;
92
94
struct completion video_comp;
···
1014
1012
return ret;
1015
1013
}
1016
1014
1015
+
static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl,
1016
+
u8 v_level, u8 p_level)
1017
+
{
1018
+
union phy_configure_opts *phy_opts = &ctrl->phy_opts;
1019
+
1020
+
/* TODO: Update for all lanes instead of just first one */
1021
+
phy_opts->dp.voltage[0] = v_level;
1022
+
phy_opts->dp.pre[0] = p_level;
1023
+
phy_opts->dp.set_voltages = 1;
1024
+
phy_configure(ctrl->parser->io.phy, phy_opts);
1025
+
phy_opts->dp.set_voltages = 0;
1026
+
1027
+
return 0;
1028
+
}
1029
+
1017
1030
static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl)
1018
1031
{
1019
1032
struct dp_link *link = ctrl->link;
···
1041
1024
drm_dbg_dp(ctrl->drm_dev,
1042
1025
"voltage level: %d emphasis level: %d\n",
1043
1026
voltage_swing_level, pre_emphasis_level);
1044
-
ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1027
+
ret = dp_ctrl_set_vx_px(ctrl,
1045
1028
voltage_swing_level, pre_emphasis_level);
1046
1029
1047
1030
if (ret)
···
1437
1420
static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl)
1438
1421
{
1439
1422
int ret = 0;
1440
-
struct dp_io *dp_io = &ctrl->parser->io;
1441
-
struct phy *phy = dp_io->phy;
1442
-
struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1423
+
struct phy *phy = ctrl->parser->io.phy;
1443
1424
const u8 *dpcd = ctrl->panel->dpcd;
1444
1425
1445
-
opts_dp->lanes = ctrl->link->link_params.num_lanes;
1446
-
opts_dp->link_rate = ctrl->link->link_params.rate / 100;
1447
-
opts_dp->ssc = drm_dp_max_downspread(dpcd);
1426
+
ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
1427
+
ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100;
1428
+
ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd);
1448
1429
1449
-
phy_configure(phy, &dp_io->phy_opts);
1430
+
phy_configure(phy, &ctrl->phy_opts);
1450
1431
phy_power_on(phy);
1451
1432
1452
1433
dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000);
···
1582
1567
1583
1568
static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl)
1584
1569
{
1570
+
struct phy *phy = ctrl->parser->io.phy;
1585
1571
int ret = 0;
1586
-
struct dp_io *dp_io = &ctrl->parser->io;
1587
-
struct phy *phy = dp_io->phy;
1588
-
struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp;
1589
1572
1590
1573
dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false);
1591
-
opts_dp->lanes = ctrl->link->link_params.num_lanes;
1592
-
phy_configure(phy, &dp_io->phy_opts);
1574
+
ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes;
1575
+
phy_configure(phy, &ctrl->phy_opts);
1593
1576
/*
1594
1577
* Disable and re-enable the mainlink clock since the
1595
1578
* link clock might have been adjusted as part of the
···
1667
1654
1668
1655
drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested);
1669
1656
1670
-
if (dp_catalog_ctrl_update_vx_px(ctrl->catalog,
1657
+
if (dp_ctrl_set_vx_px(ctrl,
1671
1658
ctrl->link->phy_params.v_level,
1672
1659
ctrl->link->phy_params.p_level)) {
1673
1660
DRM_ERROR("Failed to set v/p levels\n");
-3
drivers/gpu/drm/msm/dp/dp_parser.h
-3
drivers/gpu/drm/msm/dp/dp_parser.h
···
7
7
#define _DP_PARSER_H_
8
8
9
9
#include <linux/platform_device.h>
10
-
#include <linux/phy/phy.h>
11
-
#include <linux/phy/phy-dp.h>
12
10
13
11
#include "msm_drv.h"
14
12
···
35
37
struct dp_io {
36
38
struct dss_io_data dp_controller;
37
39
struct phy *phy;
38
-
union phy_configure_opts phy_opts;
39
40
};
40
41
41
42
/**