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clk: qcom: gcc-msm8996: drop unsupported clock sources

In preparation of updating the msm8996 gcc driver, drop all unsupported
GPLL sources (gpll1/gpll1_early_div, gpll2/gpll2_early and gpll3).
Downstream kernel also does not provide support for these GPLL sources,
so it is safe to drop them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211228045415.20543-14-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson b554a687 ed96df3d

+6 -49
+6 -49
drivers/clk/qcom/gcc-msm8996.c
··· 27 27 enum { 28 28 P_XO, 29 29 P_GPLL0, 30 - P_GPLL2, 31 - P_GPLL3, 32 - P_GPLL1, 33 - P_GPLL2_EARLY, 34 30 P_GPLL0_EARLY_DIV, 35 31 P_SLEEP_CLK, 36 32 P_GPLL4, 37 33 P_AUD_REF_CLK, 38 - P_GPLL1_EARLY_DIV 39 34 }; 40 35 41 36 static const struct parent_map gcc_sleep_clk_map[] = { ··· 122 127 "xo", 123 128 "gpll0", 124 129 "gpll4", 125 - "gpll0_early_div" 126 - }; 127 - 128 - static const struct parent_map gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map[] = { 129 - { P_XO, 0 }, 130 - { P_GPLL0, 1 }, 131 - { P_GPLL1_EARLY_DIV, 3 }, 132 - { P_GPLL1, 4 }, 133 - { P_GPLL4, 5 }, 134 - { P_GPLL0_EARLY_DIV, 6 } 135 - }; 136 - 137 - static const char * const gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div[] = { 138 - "xo", 139 - "gpll0", 140 - "gpll1_early_div", 141 - "gpll1", 142 - "gpll4", 143 - "gpll0_early_div" 144 - }; 145 - 146 - static const struct parent_map gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map[] = { 147 - { P_XO, 0 }, 148 - { P_GPLL0, 1 }, 149 - { P_GPLL2, 2 }, 150 - { P_GPLL3, 3 }, 151 - { P_GPLL1, 4 }, 152 - { P_GPLL2_EARLY, 5 }, 153 - { P_GPLL0_EARLY_DIV, 6 } 154 - }; 155 - 156 - static const char * const gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div[] = { 157 - "xo", 158 - "gpll0", 159 - "gpll2", 160 - "gpll3", 161 - "gpll1", 162 - "gpll2_early", 163 130 "gpll0_early_div" 164 131 }; 165 132 ··· 242 285 static struct clk_rcg2 system_noc_clk_src = { 243 286 .cmd_rcgr = 0x0401c, 244 287 .hid_width = 5, 245 - .parent_map = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div_map, 288 + .parent_map = gcc_xo_gpll0_gpll0_early_div_map, 246 289 .freq_tbl = ftbl_system_noc_clk_src, 247 290 .clkr.hw.init = &(struct clk_init_data){ 248 291 .name = "system_noc_clk_src", 249 - .parent_names = gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div, 250 - .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll2_early_gpll0_early_div), 292 + .parent_names = gcc_xo_gpll0_gpll0_early_div, 293 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div), 251 294 .ops = &clk_rcg2_ops, 252 295 }, 253 296 }; ··· 1214 1257 static struct clk_rcg2 qspi_ser_clk_src = { 1215 1258 .cmd_rcgr = 0x8b00c, 1216 1259 .hid_width = 5, 1217 - .parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map, 1260 + .parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map, 1218 1261 .freq_tbl = ftbl_qspi_ser_clk_src, 1219 1262 .clkr.hw.init = &(struct clk_init_data){ 1220 1263 .name = "qspi_ser_clk_src", 1221 - .parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div, 1222 - .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div), 1264 + .parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div, 1265 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_early_div), 1223 1266 .ops = &clk_rcg2_ops, 1224 1267 }, 1225 1268 };