Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/msm/dpu: Implement CTL_PIPE_ACTIVE for v12.0 DPU
v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for
selective activation of pipes, which replaces earlier
dpu_hw_ctl_setup_blendstage() code path for newer devices.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/659630/
Link: https://lore.kernel.org/r/20250618-b4-sm8750-display-v7-11-a591c609743d@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
authored by
Krzysztof Kozlowski
and committed by
Dmitry Baryshkov
b567e928
8984f97c
+47
-2
+9
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+9
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
···
453
453
u32 lm_idx;
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bool bg_alpha_enable = false;
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DECLARE_BITMAP(active_fetch, SSPP_MAX);
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+
DECLARE_BITMAP(active_pipes, SSPP_MAX);
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memset(active_fetch, 0, sizeof(active_fetch));
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+
memset(active_pipes, 0, sizeof(active_pipes));
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drm_atomic_crtc_for_each_plane(plane, crtc) {
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state = plane->state;
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if (!state)
···
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bg_alpha_enable = true;
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set_bit(pstate->pipe.sspp->idx, active_fetch);
475
+
set_bit(pstate->pipe.sspp->idx, active_pipes);
477
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_dpu_crtc_blend_setup_pipe(crtc, plane,
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mixer, cstate->num_mixers,
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pstate->stage,
···
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if (pstate->r_pipe.sspp) {
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set_bit(pstate->r_pipe.sspp->idx, active_fetch);
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+
set_bit(pstate->r_pipe.sspp->idx, active_pipes);
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_dpu_crtc_blend_setup_pipe(crtc, plane,
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mixer, cstate->num_mixers,
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pstate->stage,
···
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if (ctl->ops.set_active_fetch_pipes)
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ctl->ops.set_active_fetch_pipes(ctl, active_fetch);
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+
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+
if (ctl->ops.set_active_pipes)
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+
ctl->ops.set_active_pipes(ctl, active_pipes);
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_dpu_crtc_program_lm_output_roi(crtc);
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}
···
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mixer[i].lm_ctl);
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if (mixer[i].lm_ctl->ops.set_active_fetch_pipes)
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mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL);
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+
if (mixer[i].lm_ctl->ops.set_active_pipes)
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mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL);
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}
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541
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/* initialize stage cfg */
+3
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+3
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+27
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+27
-2
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
···
42
42
#define CTL_INTF_FLUSH 0x110
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#define CTL_CDM_FLUSH 0x114
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#define CTL_PERIPH_FLUSH 0x128
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+
#define CTL_PIPE_ACTIVE 0x12c
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#define CTL_INTF_MASTER 0x134
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#define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4))
47
48
···
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if (ctx->ops.set_active_fetch_pipes)
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ctx->ops.set_active_fetch_pipes(ctx, NULL);
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+
if (ctx->ops.set_active_pipes)
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ctx->ops.set_active_pipes(ctx, NULL);
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+
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if (cfg->intf) {
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intf_active = DPU_REG_READ(c, CTL_INTF_ACTIVE);
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intf_active &= ~BIT(cfg->intf - INTF_0);
···
739
735
}
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736
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DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val);
738
+
}
739
+
740
+
static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_ctl *ctx,
741
+
unsigned long *active_pipes)
742
+
{
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int i;
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+
u32 val = 0;
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+
746
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if (active_pipes) {
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for (i = 0; i < SSPP_MAX; i++) {
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if (test_bit(i, active_pipes) &&
749
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fetch_tbl[i] != CTL_INVALID_BIT)
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val |= BIT(fetch_tbl[i]);
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}
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}
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+
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DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val);
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}
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/**
···
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c->ops.trigger_pending = dpu_hw_ctl_trigger_pending;
822
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c->ops.reset = dpu_hw_ctl_reset_control;
823
802
c->ops.wait_reset_status = dpu_hw_ctl_wait_reset_status;
824
-
c->ops.clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
825
-
c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
803
+
if (mdss_ver->core_major_ver < 12) {
804
+
c->ops.clear_all_blendstages = dpu_hw_ctl_clear_all_blendstages;
805
+
c->ops.setup_blendstage = dpu_hw_ctl_setup_blendstage;
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+
} else {
807
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c->ops.set_active_pipes = dpu_hw_ctl_set_active_pipes;
808
+
}
826
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c->ops.update_pending_flush_sspp = dpu_hw_ctl_update_pending_flush_sspp;
827
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c->ops.update_pending_flush_mixer = dpu_hw_ctl_update_pending_flush_mixer;
828
811
if (mdss_ver->core_major_ver >= 7)
+8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+8
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
···
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void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx,
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unsigned long *fetch_active);
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+
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/**
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* Set active pipes attached to this CTL
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* @ctx: ctl path ctx pointer
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* @active_pipes: bitmap of enum dpu_sspp
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*/
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void (*set_active_pipes)(struct dpu_hw_ctl *ctx,
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unsigned long *active_pipes);
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};
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/**