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drm/msm/registers: Sync GPU registers from mesa

In particular, to pull in a SP_READ_SEL_LOCATION bitfield size fix to
fix a7xx GPU snapshot.

Sync from mesa commit 15ee3873aa4d ("freedreno/registers: Update GMU
register xml").

Cc: Karmjit Mahil <karmjit.mahil@igalia.com>
Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/673558/

Rob Clark b5bad77e 60e9f776

+512 -479
+4 -4
drivers/gpu/drm/msm/adreno/a6xx_gpu.c
··· 264 264 * Needed for preemption 265 265 */ 266 266 OUT_PKT7(ring, CP_MEM_WRITE, 5); 267 - OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr))); 268 - OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr))); 267 + OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_LO(lower_32_bits(memptr))); 268 + OUT_RING(ring, A5XX_CP_MEM_WRITE_ADDR_HI(upper_32_bits(memptr))); 269 269 OUT_RING(ring, lower_32_bits(ttbr)); 270 270 OUT_RING(ring, upper_32_bits(ttbr)); 271 271 OUT_RING(ring, ctx->seqno); ··· 295 295 */ 296 296 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6); 297 297 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ)); 298 - OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 298 + OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_LO( 299 299 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS)); 300 - OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0)); 300 + OUT_RING(ring, CP_WAIT_REG_MEM_POLL_ADDR_HI(0)); 301 301 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1)); 302 302 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1)); 303 303 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));
+2 -2
drivers/gpu/drm/msm/adreno/a6xx_preempt.c
··· 111 111 112 112 postamble[count++] = PKT7(CP_WAIT_REG_MEM, 6); 113 113 postamble[count++] = CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ); 114 - postamble[count++] = CP_WAIT_REG_MEM_1_POLL_ADDR_LO( 114 + postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_LO( 115 115 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS); 116 - postamble[count++] = CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0); 116 + postamble[count++] = CP_WAIT_REG_MEM_POLL_ADDR_HI(0); 117 117 postamble[count++] = CP_WAIT_REG_MEM_3_REF(0x1); 118 118 postamble[count++] = CP_WAIT_REG_MEM_4_MASK(0x1); 119 119 postamble[count++] = CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0);
+410 -300
drivers/gpu/drm/msm/registers/adreno/a6xx.xml
··· 814 814 <bitfield name="Y" low="16" high="29" type="uint"/> 815 815 </bitset> 816 816 817 - <reg32 offset="0x8000" name="GRAS_CL_CNTL" usage="rp_blit"> 817 + <bitset name="a6xx_gras_cl_cntl" inline="yes"> 818 818 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/> 819 819 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/> 820 820 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/> ··· 826 826 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/> 827 827 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/> 828 828 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/> 829 - </reg32> 829 + </bitset> 830 + 831 + <reg32 offset="0x8000" name="GRAS_CL_CNTL" type="a6xx_gras_cl_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 830 832 831 833 <bitset name="a6xx_gras_xs_clip_cull_distance" inline="yes"> 832 834 <bitfield name="CLIP_MASK" low="0" high="7"/> 833 835 <bitfield name="CULL_MASK" low="8" high="15"/> 834 836 </bitset> 835 - <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 836 - <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 837 - <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit"/> 838 - <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit"/> 837 + <reg32 offset="0x8001" name="GRAS_CL_VS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 838 + <reg32 offset="0x8002" name="GRAS_CL_DS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 839 + <reg32 offset="0x8003" name="GRAS_CL_GS_CLIP_CULL_DISTANCE" type="a6xx_gras_xs_clip_cull_distance" usage="rp_blit" variants="A6XX-A7XX" /> 840 + <reg32 offset="0x8004" name="GRAS_CL_ARRAY_SIZE" low="0" high="10" type="uint" usage="rp_blit" variants="A6XX-A7XX" /> 839 841 840 - <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" usage="rp_blit"> 842 + <bitset name="a6xx_gras_cl_interp_cntl" inline="yes"> 841 843 <!-- see also RB_INTERP_CNTL --> 842 844 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/> 843 845 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/> ··· 850 848 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/> 851 849 <bitfield name="UNK10" pos="10" type="boolean" variants="A7XX-"/> 852 850 <bitfield name="UNK11" pos="11" type="boolean" variants="A7XX-"/> 853 - </reg32> 854 - <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" usage="rp_blit"> 851 + </bitset> 852 + 853 + <reg32 offset="0x8005" name="GRAS_CL_INTERP_CNTL" type="a6xx_gras_cl_interp_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 854 + 855 + <bitset name="a6xx_gras_cl_guardband_clip_adj" inline="true"> 855 856 <bitfield name="HORZ" low="0" high="8" type="uint"/> 856 857 <bitfield name="VERT" low="10" high="18" type="uint"/> 857 - </reg32> 858 + </bitset> 859 + 860 + <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ" type="a6xx_gras_cl_guardband_clip_adj" variants="A6XX-A7XX" usage="rp_blit"/> 858 861 859 862 <!-- Something connected to depth-stencil attachment size --> 860 863 <reg32 offset="0x8007" name="GRAS_UNKNOWN_8007" variants="A7XX-" usage="rp_blit"/> 861 864 862 - <reg32 offset="0x8008" name="GRAS_UNKNOWN_8008" variants="A7XX-" usage="cmd"/> 865 + <!-- the scale/offset is per view, with up to 6 views --> 866 + <bitset name="a6xx_gras_bin_foveat" inline="yes"> 867 + <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 868 + <enum name="a7xx_bin_scale"> 869 + <value value="0" name="NOSCALE"/> 870 + <value value="1" name="SCALE2X"/> 871 + <value value="2" name="SCALE4X"/> 872 + </enum> 873 + <bitfield name="XSCALE_0" low="8" high="9" type="a7xx_bin_scale"/> 874 + <bitfield name="YSCALE_0" low="10" high="11" type="a7xx_bin_scale"/> 875 + <bitfield name="XSCALE_1" low="12" high="13" type="a7xx_bin_scale"/> 876 + <bitfield name="YSCALE_1" low="14" high="15" type="a7xx_bin_scale"/> 877 + <bitfield name="XSCALE_2" low="16" high="17" type="a7xx_bin_scale"/> 878 + <bitfield name="YSCALE_2" low="18" high="19" type="a7xx_bin_scale"/> 879 + <bitfield name="XSCALE_3" low="20" high="21" type="a7xx_bin_scale"/> 880 + <bitfield name="YSCALE_3" low="22" high="23" type="a7xx_bin_scale"/> 881 + <bitfield name="XSCALE_4" low="24" high="25" type="a7xx_bin_scale"/> 882 + <bitfield name="YSCALE_4" low="26" high="27" type="a7xx_bin_scale"/> 883 + <bitfield name="XSCALE_5" low="28" high="29" type="a7xx_bin_scale"/> 884 + <bitfield name="YSCALE_5" low="30" high="31" type="a7xx_bin_scale"/> 885 + </bitset> 863 886 864 - <reg32 offset="0x8009" name="GRAS_UNKNOWN_8009" variants="A7XX-" usage="cmd"/> 865 - <reg32 offset="0x800a" name="GRAS_UNKNOWN_800A" variants="A7XX-" usage="cmd"/> 866 - <reg32 offset="0x800b" name="GRAS_UNKNOWN_800B" variants="A7XX-" usage="cmd"/> 867 - <reg32 offset="0x800c" name="GRAS_UNKNOWN_800C" variants="A7XX-" usage="cmd"/> 887 + <reg32 offset="0x8008" name="GRAS_BIN_FOVEAT" type="a6xx_gras_bin_foveat" variants="A7XX" usage="cmd"/> 888 + 889 + <reg32 offset="0x8009" name="GRAS_BIN_FOVEAT_OFFSET_0" variants="A7XX-" usage="cmd"> 890 + <bitfield name="XOFFSET_0" low="0" high="9" shr="2" type="uint"/> 891 + <bitfield name="XOFFSET_1" low="10" high="19" shr="2" type="uint"/> 892 + <bitfield name="XOFFSET_2" low="20" high="29" shr="2" type="uint"/> 893 + </reg32> 894 + <reg32 offset="0x800a" name="GRAS_BIN_FOVEAT_OFFSET_1" variants="A7XX-" usage="cmd"> 895 + <bitfield name="XOFFSET_3" low="0" high="9" shr="2" type="uint"/> 896 + <bitfield name="XOFFSET_4" low="10" high="19" shr="2" type="uint"/> 897 + <bitfield name="XOFFSET_5" low="20" high="29" shr="2" type="uint"/> 898 + </reg32> 899 + <reg32 offset="0x800b" name="GRAS_BIN_FOVEAT_OFFSET_2" variants="A7XX-" usage="cmd"> 900 + <bitfield name="YOFFSET_0" low="0" high="9" shr="2" type="uint"/> 901 + <bitfield name="YOFFSET_1" low="10" high="19" shr="2" type="uint"/> 902 + <bitfield name="YOFFSET_2" low="20" high="29" shr="2" type="uint"/> 903 + </reg32> 904 + <reg32 offset="0x800c" name="GRAS_BIN_FOVEAT_OFFSET_3" variants="A7XX-" usage="cmd"> 905 + <bitfield name="YOFFSET_3" low="0" high="9" shr="2" type="uint"/> 906 + <bitfield name="YOFFSET_4" low="10" high="19" shr="2" type="uint"/> 907 + <bitfield name="YOFFSET_5" low="20" high="29" shr="2" type="uint"/> 908 + </reg32> 868 909 869 910 <!-- <reg32 offset="0x80f0" name="GRAS_UNKNOWN_80F0" type="a6xx_reg_xy"/> --> 870 911 871 912 <!-- 0x8006-0x800f invalid --> 872 - <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" usage="rp_blit"> 913 + <array offset="0x8010" name="GRAS_CL_VIEWPORT" stride="6" length="16" variants="A6XX-A7XX" usage="rp_blit"> 873 914 <reg32 offset="0" name="XOFFSET" type="float"/> 874 915 <reg32 offset="1" name="XSCALE" type="float"/> 875 916 <reg32 offset="2" name="YOFFSET" type="float"/> ··· 920 875 <reg32 offset="4" name="ZOFFSET" type="float"/> 921 876 <reg32 offset="5" name="ZSCALE" type="float"/> 922 877 </array> 923 - <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" usage="rp_blit"> 878 + 879 + <array offset="0x8070" name="GRAS_CL_VIEWPORT_ZCLAMP" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 924 880 <reg32 offset="0" name="MIN" type="float"/> 925 881 <reg32 offset="1" name="MAX" type="float"/> 926 882 </array> 927 883 928 - <reg32 offset="0x8090" name="GRAS_SU_CNTL" usage="rp_blit"> 884 + <bitset name="a6xx_gras_su_cntl" varset="chip"> 929 885 <bitfield name="CULL_FRONT" pos="0" type="boolean"/> 930 886 <bitfield name="CULL_BACK" pos="1" type="boolean"/> 931 887 <bitfield name="FRONT_CW" pos="2" type="boolean"/> ··· 936 890 <bitfield name="LINE_MODE" pos="13" type="a5xx_line_mode"/> 937 891 <bitfield name="UNK15" low="15" high="16"/> 938 892 <!-- 939 - On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 940 - the ability to add the view index to either the RT array 941 - index or the viewport index, and it seems that 942 - MULTIVIEW_ENABLE doesn't do anything, instead we need to 943 - set at least one of RENDERTARGETINDEXINCR or 944 - VIEWPORTINDEXINCR to enable multiview. The blob still 945 - sets MULTIVIEW_ENABLE regardless. 946 - TODO: what about gen2 (a640)? 893 + On gen1 only MULTIVIEW_ENABLE exists. On gen3 we have 894 + the ability to add the view index to either the RT array 895 + index or the viewport index, and it seems that 896 + MULTIVIEW_ENABLE doesn't do anything, instead we need to 897 + set at least one of RENDERTARGETINDEXINCR or 898 + VIEWPORTINDEXINCR to enable multiview. The blob still 899 + sets MULTIVIEW_ENABLE regardless. 900 + TODO: what about gen2 (a640)? 947 901 --> 948 902 <bitfield name="MULTIVIEW_ENABLE" pos="17" type="boolean"/> 949 - <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean"/> 950 - <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean"/> 951 - <bitfield name="UNK20" low="20" high="22"/> 952 - </reg32> 953 - <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" usage="rp_blit"> 903 + <bitfield name="RENDERTARGETINDEXINCR" pos="18" type="boolean" variants="A6XX-A7XX"/> 904 + <bitfield name="VIEWPORTINDEXINCR" pos="19" type="boolean" variants="A6XX-A7XX"/> 905 + <bitfield name="UNK20" low="20" high="22" variants="A6XX-A7XX"/> 906 + </bitset> 907 + <reg32 offset="0x8090" name="GRAS_SU_CNTL" type="a6xx_gras_su_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 908 + 909 + <bitset name="a6xx_gras_su_point_minmax" inline="yes"> 954 910 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/> 955 911 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/> 956 - </reg32> 957 - <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" usage="rp_blit"/> 912 + </bitset> 913 + 914 + <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX" type="a6xx_gras_su_point_minmax" variants="A6XX-A7XX" usage="rp_blit"/> 915 + <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4" variants="A6XX-A7XX" usage="rp_blit"/> 916 + 917 + <bitset name="a6xx_gras_su_depth_cntl" inline="yes"> 918 + <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 919 + </bitset> 920 + 921 + <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" variants="A6XX-A7XX" type="a6xx_gras_su_depth_cntl" usage="rp_blit"/> 922 + 923 + <bitset name="a6xx_gras_su_stencil_cntl" inline="yes"> 924 + <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 925 + </bitset> 926 + 927 + <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" type="a6xx_gras_su_stencil_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 928 + 929 + <bitset name="a6xx_gras_su_render_cntl" inline="yes"> 930 + <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 931 + </bitset> 932 + 933 + <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" type="a6xx_gras_su_render_cntl" variants="A7XX" usage="rp_blit"/> 934 + 958 935 <!-- 0x8093 invalid --> 959 - <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" usage="rp_blit"> 936 + <bitset name="a6xx_depth_plane_cntl" inline="yes"> 960 937 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 961 - </reg32> 962 - <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" usage="rp_blit"/> 963 - <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" usage="rp_blit"/> 964 - <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" usage="rp_blit"/> 965 - <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 966 - <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" usage="rp_blit"> 938 + </bitset> 939 + 940 + <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 941 + <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 942 + <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 943 + <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float" variants="A6XX-A7XX" usage="rp_blit"/> 944 + <bitset name="a6xx_depth_buffer_info" inline="yes"> 967 945 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 968 946 <bitfield name="UNK3" pos="3"/> 969 - </reg32> 947 + </bitset> 970 948 971 - <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" usage="cmd"> 949 + <!-- duplicates RB_DEPTH_BUFFER_INFO: --> 950 + <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO" type="a6xx_depth_buffer_info" variants="A6XX-A7XX" usage="rp_blit"/> 951 + 952 + <bitset name="a6xx_gras_su_conservative_ras_cntl" inline="yes"> 972 953 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 973 954 <enum name="a6xx_shift_amount"> 974 955 <value value="0" name="NO_SHIFT"/> ··· 1005 932 <bitfield name="SHIFTAMOUNT" low="1" high="2" type="a6xx_shift_amount"/> 1006 933 <bitfield name="INNERCONSERVATIVERASEN" pos="3" type="boolean"/> 1007 934 <bitfield name="UNK4" low="4" high="5"/> 1008 - </reg32> 935 + </bitset> 936 + 937 + <reg32 offset="0x8099" name="GRAS_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_gras_su_conservative_ras_cntl" variants="A6XX-A7XX" usage="cmd"/> 938 + 1009 939 <reg32 offset="0x809a" name="GRAS_SU_PATH_RENDERING_CNTL"> 1010 940 <bitfield name="UNK0" pos="0" type="boolean"/> 1011 941 <bitfield name="LINELENGTHEN" pos="1" type="boolean"/> ··· 1018 942 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/> 1019 943 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/> 1020 944 </bitset> 1021 - <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 1022 - <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 1023 - <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" usage="rp_blit"/> 1024 - <!-- 0x809e/0x809f invalid --> 945 + <reg32 offset="0x809b" name="GRAS_SU_VS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 946 + <reg32 offset="0x809c" name="GRAS_SU_GS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 947 + <reg32 offset="0x809d" name="GRAS_SU_DS_SIV_CNTL" type="a6xx_gras_us_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 948 + 949 + <bitset name="a6xx_rast_cntl" inline="yes"> 950 + <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 951 + </bitset> 1025 952 1026 953 <enum name="a6xx_sequenced_thread_dist"> 1027 954 <value value="0x0" name="DIST_SCREEN_COORD"/> ··· 1072 993 <value value="0x3" name="RB_BT"/> 1073 994 </enum> 1074 995 1075 - <reg32 offset="0x80a0" name="GRAS_SC_CNTL" usage="rp_blit"> 996 + <bitset name="a6xx_gras_sc_cntl" inline="yes"> 1076 997 <bitfield name="CCUSINGLECACHELINESIZE" low="0" high="2"/> 1077 998 <bitfield name="SINGLE_PRIM_MODE" low="3" high="4" type="a6xx_single_prim_mode"/> 1078 999 <bitfield name="RASTER_MODE" pos="5" type="a6xx_raster_mode"/> ··· 1082 1003 <bitfield name="UNK9" pos="9" type="boolean"/> 1083 1004 <bitfield name="ROTATION" low="10" high="11" type="uint"/> 1084 1005 <bitfield name="EARLYVIZOUTEN" pos="12" type="boolean"/> 1085 - </reg32> 1006 + </bitset> 1007 + 1008 + <reg32 offset="0x80a0" name="GRAS_SC_CNTL" type="a6xx_gras_sc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1086 1009 1087 1010 <enum name="a6xx_render_mode"> 1088 1011 <value value="0x0" name="RENDERING_PASS"/> ··· 1105 1024 <value value="0x4" name="LRZ_FEEDBACK_LATE_Z"/> 1106 1025 </enum> 1107 1026 1108 - <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" usage="rp_blit"> 1027 + <bitset name="a6xx_bin_cntl" inline="yes"> 1109 1028 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1110 1029 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1111 1030 <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> ··· 1118 1037 In sysmem mode GRAS_LRZ_CNTL.LRZ_WRITE is not considered. 1119 1038 </doc> 1120 1039 <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1121 - <bitfield name="UNK27" pos="27"/> 1122 - </reg32> 1040 + <bitfield name="FORCE_LRZ_DIS" pos="27" type="boolean"/> 1041 + </bitset> 1123 1042 1124 - <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" usage="rp_blit"> 1043 + <reg32 offset="0x80a1" name="GRAS_SC_BIN_CNTL" type="a6xx_bin_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1044 + 1045 + <bitset name="a6xx_gras_sc_ras_msaa_cntl" inline="yes"> 1125 1046 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1126 1047 <bitfield name="UNK2" pos="2"/> 1127 1048 <bitfield name="UNK3" pos="3"/> 1128 - </reg32> 1129 - <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" usage="rp_blit"> 1049 + </bitset> 1050 + 1051 + <reg32 offset="0x80a2" name="GRAS_SC_RAS_MSAA_CNTL" type="a6xx_gras_sc_ras_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1052 + 1053 + <bitset name="a6xx_gras_sc_dest_msaa_cntl" inline="yes"> 1130 1054 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/> 1131 1055 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/> 1132 - </reg32> 1056 + </bitset> 1057 + 1058 + <reg32 offset="0x80a3" name="GRAS_SC_DEST_MSAA_CNTL" type="a6xx_gras_sc_dest_msaa_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1133 1059 1134 1060 <bitset name="a6xx_msaa_sample_pos_cntl" inline="yes"> 1135 1061 <bitfield name="UNK0" pos="0"/> ··· 1154 1066 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/> 1155 1067 </bitset> 1156 1068 1157 - <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 1158 - <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1159 - <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 1069 + <reg32 offset="0x80a4" name="GRAS_SC_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1070 + <reg32 offset="0x80a5" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1071 + <reg32 offset="0x80a6" name="GRAS_SC_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" variants="A6XX-A7XX" usage="rp_blit"/> 1160 1072 1161 - <reg32 offset="0x80a7" name="GRAS_UNKNOWN_80A7" variants="A7XX-" usage="cmd"/> 1073 + <reg32 offset="0x80a7" name="GRAS_ROTATION_CNTL" variants="A7XX" usage="cmd"/> 1162 1074 1163 - <!-- 0x80a7-0x80ae invalid --> 1164 - <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0" usage="cmd"/> 1075 + <bitset name="a6xx_screen_scissor_cntl" inline="yes"> 1076 + <bitfield name="SCISSOR_DISABLE" pos="0" type="boolean"/> 1077 + </bitset> 1078 + 1079 + <reg32 offset="0x80af" name="GRAS_SC_SCREEN_SCISSOR_CNTL" type="a6xx_screen_scissor_cntl" variants="A6XX-A7XX" pos="0" usage="cmd"/> 1165 1080 1166 1081 <bitset name="a6xx_scissor_xy" inline="yes"> 1167 1082 <bitfield name="X" low="0" high="15" type="uint"/> 1168 1083 <bitfield name="Y" low="16" high="31" type="uint"/> 1169 1084 </bitset> 1170 - <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" usage="rp_blit"> 1171 - <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1172 - <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1173 - </array> 1174 - <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" usage="rp_blit"> 1085 + 1086 + <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1175 1087 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1176 1088 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1177 1089 </array> 1178 1090 1179 - <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1180 - <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1091 + <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16" variants="A6XX-A7XX" usage="rp_blit"> 1092 + <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/> 1093 + <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/> 1094 + </array> 1095 + 1096 + <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1097 + <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1181 1098 1182 1099 <enum name="a6xx_fsr_combiner"> 1183 1100 <value value="0" name="FSR_COMBINER_OP_KEEP"/> ··· 1192 1099 <value value="4" name="FSR_COMBINER_OP_MUL"/> 1193 1100 </enum> 1194 1101 1195 - <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" variants="A7XX-" usage="rp_blit"> 1102 + <bitset name="a6xx_gras_vrs_config"> 1196 1103 <bitfield name="PIPELINE_FSR_ENABLE" pos="0" type="boolean"/> 1197 1104 <bitfield name="FRAG_SIZE_X" low="1" high="2" type="uint"/> 1198 1105 <bitfield name="FRAG_SIZE_Y" low="3" high="4" type="uint"/> ··· 1200 1107 <bitfield name="COMBINER_OP_2" low="8" high="10" type="a6xx_fsr_combiner"/> 1201 1108 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="13" type="boolean"/> 1202 1109 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="20" type="boolean"/> 1203 - </reg32> 1204 - <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1110 + </bitset> 1111 + 1112 + <reg32 offset="0x80f4" name="GRAS_VRS_CONFIG" type="a6xx_gras_vrs_config" variants="A7XX" usage="rp_blit"/> 1113 + 1114 + <bitset name="a6xx_gras_quality_buffer_info" inline="yes"> 1205 1115 <bitfield name="LAYERED" pos="0" type="boolean"/> 1206 1116 <bitfield name="TILE_MODE" low="1" high="2" type="a6xx_tile_mode"/> 1207 - </reg32> 1208 - <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" variants="A7XX-" usage="rp_blit"> 1117 + </bitset> 1118 + 1119 + <reg32 offset="0x80f5" name="GRAS_QUALITY_BUFFER_INFO" type="a6xx_gras_quality_buffer_info" variants="A7XX" usage="rp_blit"/> 1120 + 1121 + <bitset name="a6xx_gras_quality_buffer_dimension" inline="yes"> 1209 1122 <bitfield name="WIDTH" low="0" high="15" type="uint"/> 1210 1123 <bitfield name="HEIGHT" low="16" high="31" type="uint"/> 1211 - </reg32> 1212 - <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX-" type="waddress" usage="rp_blit"/> 1213 - <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" variants="A7XX-" usage="rp_blit"> 1124 + </bitset> 1125 + 1126 + <reg32 offset="0x80f6" name="GRAS_QUALITY_BUFFER_DIMENSION" type="a6xx_gras_quality_buffer_dimension" variants="A7XX" usage="rp_blit"/> 1127 + 1128 + <reg64 offset="0x80f8" name="GRAS_QUALITY_BUFFER_BASE" variants="A7XX" type="waddress" usage="rp_blit"/> 1129 + 1130 + <bitset name="a6xx_gras_quality_buffer_pitch" inline="yes"> 1214 1131 <bitfield name="PITCH" shr="6" low="0" high="7" type="uint"/> 1215 1132 <bitfield name="ARRAY_PITCH" shr="6" low="10" high="28" type="uint"/> 1216 - </reg32> 1133 + </bitset> 1134 + 1135 + <reg32 offset="0x80fa" name="GRAS_QUALITY_BUFFER_PITCH" type="a6xx_gras_quality_buffer_pitch" variants="A7XX" usage="rp_blit"/> 1217 1136 1218 1137 <enum name="a6xx_lrz_dir_status"> 1219 1138 <value value="0x1" name="LRZ_DIR_LE"/> ··· 1233 1128 <value value="0x3" name="LRZ_DIR_INVALID"/> 1234 1129 </enum> 1235 1130 1236 - <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" usage="rp_blit"> 1131 + <bitset name="a6xx_gras_lrz_cntl" inline="yes"> 1237 1132 <bitfield name="ENABLE" pos="0" type="boolean"/> 1238 1133 <doc>LRZ write also disabled for blend/etc.</doc> 1239 1134 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/> ··· 1260 1155 </doc> 1261 1156 <bitfield name="DISABLE_ON_WRONG_DIR" pos="9" type="boolean" variants="A6XX"/> 1262 1157 <bitfield name="Z_FUNC" low="11" high="13" type="adreno_compare_func" variants="A7XX-"/> 1263 - </reg32> 1158 + </bitset> 1159 + 1160 + <reg32 offset="0x8100" name="GRAS_LRZ_CNTL" type="a6xx_gras_lrz_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1264 1161 1265 1162 <enum name="a6xx_fragcoord_sample_mode"> 1266 1163 <value value="0" name="FRAGCOORD_CENTER"/> 1267 1164 <value value="3" name="FRAGCOORD_SAMPLE"/> 1268 1165 </enum> 1269 1166 1270 - <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" low="0" high="2" usage="rp_blit"> 1167 + <bitset name="a6xx_gras_lrz_ps_input_cntl" inline="yes"> 1271 1168 <bitfield name="SAMPLEID" pos="0" type="boolean"/> 1272 1169 <bitfield name="FRAGCOORDSAMPLEMODE" low="1" high="2" type="a6xx_fragcoord_sample_mode"/> 1273 - </reg32> 1170 + </bitset> 1274 1171 1275 - <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" usage="rp_blit"> 1172 + <reg32 offset="0x8101" name="GRAS_LRZ_PS_INPUT_CNTL" type="a6xx_gras_lrz_ps_input_cntl" usage="rp_blit" variants="A6XX-A7XX"/> 1173 + 1174 + <bitset name="a6xx_gras_lrz_mrt_buffer_info_0" inline="yes"> 1276 1175 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/> 1277 - </reg32> 1278 - <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit"/> 1279 - <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" usage="rp_blit"> 1176 + </bitset> 1177 + 1178 + <reg32 offset="0x8102" name="GRAS_LRZ_MRT_BUFFER_INFO_0" type="a6xx_gras_lrz_mrt_buffer_info_0" usage="rp_blit" variants="A6XX-A7XX"/> 1179 + 1180 + <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress" usage="rp_blit" variants="A6XX-A7XX"/> 1181 + 1182 + <bitset name="a6xx_gras_lrz_buffer_pitch" inline="yes"> 1280 1183 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/> 1281 1184 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="8" type="uint"/> 1282 - </reg32> 1185 + </bitset> 1186 + 1187 + <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH" type="a6xx_gras_lrz_buffer_pitch" usage="rp_blit" variants="A6XX-A7XX"/> 1283 1188 1284 1189 <!-- 1285 1190 The LRZ "fast clear" buffer is initialized to zero's by blob, and ··· 1322 1207 not. 1323 1208 --> 1324 1209 <reg64 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress" usage="rp_blit"/> 1325 - <!-- 0x8108 invalid --> 1326 1210 <reg32 offset="0x8109" name="GRAS_LRZ_PS_SAMPLEFREQ_CNTL" usage="rp_blit"> 1327 1211 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/> 1328 1212 </reg32> ··· 1346 1232 1347 1233 <!-- 0x810c-0x810f invalid --> 1348 1234 1349 - <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1" usage="cmd"/> 1235 + <reg32 offset="0x8110" name="GRAS_MODE_CNTL" low="0" high="1" variants="A6XX-A7XX" usage="cmd"/> 1350 1236 1351 1237 <!-- A bit tentative but it's a color and it is followed by LRZ_CLEAR --> 1352 - <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX-"/> 1238 + <reg32 offset="0x8111" name="GRAS_LRZ_DEPTH_CLEAR" type="float" variants="A7XX"/> 1353 1239 1354 - <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1240 + <bitset name="a6xx_gras_lrz_depth_buffer_info" inline="yes"> 1355 1241 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1356 1242 <bitfield name="UNK3" pos="3"/> 1357 - </reg32> 1243 + </bitset> 1358 1244 1359 - <!-- Always written together and always equal 09510840 00000a62 --> 1360 - <reg32 offset="0x8120" name="GRAS_UNKNOWN_8120" variants="A7XX-" usage="cmd"/> 1361 - <reg32 offset="0x8121" name="GRAS_UNKNOWN_8121" variants="A7XX-" usage="cmd"/> 1245 + <reg32 offset="0x8113" name="GRAS_LRZ_DEPTH_BUFFER_INFO" type="a6xx_gras_lrz_depth_buffer_info" variants="A7XX" usage="rp_blit"/> 1246 + 1247 + <doc>LUT used to convert quality buffer values to HW shading rate values. An array of 4-bit values.</doc> 1248 + <array offset="0x8120" name="GRAS_LRZ_QUALITY_LOOKUP_TABLE" variants="A7XX-" stride="1" length="2"/> 1362 1249 1363 1250 <!-- 0x8112-0x83ff invalid --> 1364 1251 ··· 1384 1269 <bitfield name="D24S8" pos="19" type="boolean"/> 1385 1270 <!-- some sort of channel mask, disabled channels are set to zero ? --> 1386 1271 <bitfield name="MASK" low="20" high="23"/> 1387 - <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/> 1272 + <bitfield name="IFMT" low="24" high="26" type="a6xx_2d_ifmt"/> 1273 + <bitfield name="UNK27" pos="27" type="boolean"/> 1274 + <bitfield name="UNK28" pos="28" type="boolean"/> 1388 1275 <bitfield name="RASTER_MODE" pos="29" type="a6xx_raster_mode"/> 1389 - <bitfield name="UNK30" pos="30" type="boolean" variants="A7XX-"/> 1276 + <bitfield name="COPY" pos="30" type="boolean" variants="A7XX-"/> 1390 1277 </bitset> 1391 1278 1392 - <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" usage="rp_blit"/> 1279 + <reg32 offset="0x8400" name="GRAS_A2D_BLT_CNTL" type="a6xx_a2d_bit_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1393 1280 <!-- note: the low 8 bits for src coords are valid, probably fixed point 1394 1281 it would be a bit weird though, since we subtract 1 from BR coords 1395 1282 apparently signed, gallium driver uses negative coords and it works? 1396 1283 --> 1397 - <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" usage="rp_blit"/> 1398 - <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" usage="rp_blit"/> 1399 - <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" usage="rp_blit"/> 1400 - <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" usage="rp_blit"/> 1401 - <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1402 - <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1284 + <reg32 offset="0x8401" name="GRAS_A2D_SRC_XMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1285 + <reg32 offset="0x8402" name="GRAS_A2D_SRC_XMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1286 + <reg32 offset="0x8403" name="GRAS_A2D_SRC_YMIN" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1287 + <reg32 offset="0x8404" name="GRAS_A2D_SRC_YMAX" low="8" high="24" type="int" variants="A6XX-A7XX" usage="rp_blit"/> 1288 + <reg32 offset="0x8405" name="GRAS_A2D_DEST_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1289 + <reg32 offset="0x8406" name="GRAS_A2D_DEST_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1403 1290 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/> 1404 1291 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/> 1405 1292 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/> 1406 - <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" usage="rp_blit"/> 1407 - <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" usage="rp_blit"/> 1408 - <!-- 0x840c-0x85ff invalid --> 1293 + <reg32 offset="0x840a" name="GRAS_A2D_SCISSOR_TL" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1294 + <reg32 offset="0x840b" name="GRAS_A2D_SCISSOR_BR" type="a6xx_reg_xy" variants="A6XX-A7XX" usage="rp_blit"/> 1409 1295 1410 1296 <!-- always 0x880 ? (and 0 in a640/a650 traces?) --> 1411 1297 <reg32 offset="0x8600" name="GRAS_DBG_ECO_CNTL" usage="cmd"> ··· 1424 1308 --> 1425 1309 1426 1310 <!-- same as GRAS_BIN_CONTROL, but without bit 27: --> 1427 - <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX" usage="rp_blit"> 1428 - <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1429 - <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1430 - <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1431 - <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1432 - <bitfield name="BUFFERS_LOCATION" low="22" high="23" type="a6xx_buffers_location"/> 1433 - <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1434 - </reg32> 1435 - 1436 - <reg32 offset="0x8800" name="RB_CNTL" variants="A7XX-" usage="rp_blit"> 1437 - <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1438 - <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1439 - <bitfield name="RENDER_MODE" low="18" high="20" type="a6xx_render_mode"/> 1440 - <bitfield name="FORCE_LRZ_WRITE_DIS" pos="21" type="boolean"/> 1441 - <bitfield name="LRZ_FEEDBACK_ZMODE_MASK" low="24" high="26" type="a6xx_lrz_feedback_mask"/> 1442 - </reg32> 1311 + <reg32 offset="0x8800" name="RB_CNTL" variants="A6XX-A7XX" type="a6xx_bin_cntl" usage="rp_blit"/> 1443 1312 1444 1313 <reg32 offset="0x8801" name="RB_RENDER_CNTL" variants="A6XX" usage="rp_blit"> 1445 1314 <bitfield name="CCUSINGLECACHELINESIZE" low="3" high="5"/> ··· 1447 1346 <bitfield name="RASTER_DIRECTION" low="9" high="10" type="a6xx_raster_direction"/> 1448 1347 <bitfield name="CONSERVATIVERASEN" pos="11" type="boolean"/> 1449 1348 <bitfield name="INNERCONSERVATIVERASEN" pos="12" type="boolean"/> 1450 - </reg32> 1451 - <reg32 offset="0x8116" name="GRAS_SU_RENDER_CNTL" variants="A7XX-" usage="rp_blit"> 1452 - <bitfield name="FS_DISABLE" pos="7" type="boolean"/> 1453 1349 </reg32> 1454 1350 1455 1351 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL" usage="rp_blit"> ··· 1614 1516 <bitfield name="SAMPLE_MASK" low="16" high="31"/> 1615 1517 </reg32> 1616 1518 <!-- 0x8866-0x886f invalid --> 1617 - <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" usage="rp_blit"> 1618 - <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/> 1619 - </reg32> 1519 + <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL" type="a6xx_depth_plane_cntl" usage="rp_blit"/> 1620 1520 1621 1521 <reg32 offset="0x8871" name="RB_DEPTH_CNTL" usage="rp_blit"> 1622 1522 <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> ··· 1628 1532 <bitfield name="Z_READ_ENABLE" pos="6" type="boolean"/> 1629 1533 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/> 1630 1534 </reg32> 1631 - <reg32 offset="0x8114" name="GRAS_SU_DEPTH_CNTL" usage="rp_blit"> 1632 - <bitfield name="Z_TEST_ENABLE" pos="0" type="boolean"/> 1633 - </reg32> 1535 + 1634 1536 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: --> 1635 - <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1636 - <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> 1637 - <bitfield name="UNK3" low="3" high="4"/> 1638 - </reg32> 1537 + <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A6XX" type="a6xx_depth_buffer_info" usage="rp_blit"/> 1639 1538 <!-- first 4 bits duplicates GRAS_SU_DEPTH_BUFFER_INFO --> 1640 1539 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO" variants="A7XX-" usage="rp_blit"> 1641 1540 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/> ··· 1666 1575 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/> 1667 1576 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/> 1668 1577 </reg32> 1669 - <reg32 offset="0x8115" name="GRAS_SU_STENCIL_CNTL" usage="rp_blit"> 1670 - <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/> 1671 - </reg32> 1578 + 1672 1579 <reg32 offset="0x8881" name="RB_STENCIL_BUFFER_INFO" variants="A6XX" usage="rp_blit"> 1673 1580 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/> 1674 1581 <bitfield name="UNK1" pos="1" type="boolean"/> ··· 1705 1616 <reg32 offset="0x8899" name="RB_UNKNOWN_8899" variants="A7XX-" usage="cmd"/> 1706 1617 <!-- 0x8899-0x88bf invalid --> 1707 1618 <!-- clamps depth value for depth test/write --> 1708 - <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit"/> 1709 - <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit"/> 1619 + <reg32 offset="0x88c0" name="RB_VIEWPORT_ZCLAMP_MIN" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 1620 + <reg32 offset="0x88c1" name="RB_VIEWPORT_ZCLAMP_MAX" type="float" usage="rp_blit" variants="A6XX-A7XX"/> 1621 + 1710 1622 <!-- 0x88c2-0x88cf invalid--> 1711 1623 <reg32 offset="0x88d0" name="RB_RESOLVE_CNTL_0" usage="rp_blit"> 1712 1624 <bitfield name="UNK0" low="0" high="12"/> ··· 1716 1626 <reg32 offset="0x88d1" name="RB_RESOLVE_CNTL_1" type="a6xx_reg_xy" usage="rp_blit"/> 1717 1627 <reg32 offset="0x88d2" name="RB_RESOLVE_CNTL_2" type="a6xx_reg_xy" usage="rp_blit"/> 1718 1628 <!-- weird to duplicate other regs from same block?? --> 1719 - <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" usage="rp_blit"> 1629 + <reg32 offset="0x88d3" name="RB_RESOLVE_CNTL_3" variants="A6XX-A7XX" usage="rp_blit"> 1720 1630 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/> 1721 1631 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/> 1722 1632 </reg32> ··· 1740 1650 <!-- array-pitch is size of layer --> 1741 1651 <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint" usage="rp_blit"/> 1742 1652 <reg64 offset="0x88dc" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1743 - <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" usage="rp_blit"> 1653 + 1654 + <bitset name="a6xx_flag_buffer_pitch" inline="yes"> 1744 1655 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1745 - <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1746 - </reg32> 1656 + <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 1657 + </bitset> 1658 + 1659 + <reg32 offset="0x88de" name="RB_RESOLVE_SYSTEM_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="rp_blit"/> 1747 1660 1748 1661 <reg32 offset="0x88df" name="RB_RESOLVE_CLEAR_COLOR_DW0" usage="rp_blit"/> 1749 1662 <reg32 offset="0x88e0" name="RB_RESOLVE_CLEAR_COLOR_DW1" usage="rp_blit"/> ··· 1819 1726 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11" usage="cmd"/> 1820 1727 <!-- could be for separate stencil? (or may not be a flag buffer at all) --> 1821 1728 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/> 1822 - <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH"> 1823 - <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1824 - <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/> 1825 - </reg32> 1729 + <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch"/> 1826 1730 1827 1731 <reg32 offset="0x88f4" name="RB_VRS_CONFIG" usage="rp_blit"> 1828 1732 <bitfield name="UNK2" pos="2" type="boolean"/> ··· 1827 1737 <bitfield name="ATTACHMENT_FSR_ENABLE" pos="5" type="boolean"/> 1828 1738 <bitfield name="PRIMITIVE_FSR_ENABLE" pos="18" type="boolean"/> 1829 1739 </reg32> 1830 - <!-- Connected to VK_EXT_fragment_density_map? --> 1831 - <reg32 offset="0x88f5" name="RB_UNKNOWN_88F5" variants="A7XX-"/> 1740 + <reg32 offset="0x88f5" name="RB_BIN_FOVEAT" variants="A7XX-" usage="cmd"> 1741 + <bitfield name="BINSCALEEN" pos="6" type="boolean"/> 1742 + </reg32> 1832 1743 <!-- 0x88f6-0x88ff invalid --> 1833 1744 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1834 1745 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH" usage="rp_blit"> ··· 1838 1747 <bitfield name="UNK8" low="8" high="10"/> 1839 1748 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/> 1840 1749 </reg32> 1750 + 1841 1751 <array offset="0x8903" name="RB_COLOR_FLAG_BUFFER" stride="3" length="8" usage="rp_blit"> 1842 1752 <reg64 offset="0" name="ADDR" type="waddress" align="64"/> 1843 - <reg32 offset="2" name="PITCH"> 1844 - <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/> 1845 - <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/> 1846 - </reg32> 1753 + <reg32 offset="2" name="PITCH" type="a6xx_flag_buffer_pitch"/> 1847 1754 </array> 1848 1755 <!-- 0x891b-0x8926 invalid --> 1849 1756 <doc> ··· 1904 1815 <reg64 offset="0x8c1e" name="RB_A2D_DEST_BUFFER_BASE_2" type="waddress" align="64" usage="rp_blit"/> 1905 1816 1906 1817 <reg64 offset="0x8c20" name="RB_A2D_DEST_FLAG_BUFFER_BASE" type="waddress" align="64" usage="rp_blit"/> 1907 - <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> 1818 + <reg32 offset="0x8c22" name="RB_A2D_DEST_FLAG_BUFFER_PITCH" type="a6xx_flag_buffer_pitch" usage="rp_blit"/> 1908 1819 <!-- this is a guess but seems likely (for NV12 with UBWC): --> 1909 1820 <reg64 offset="0x8c23" name="RB_A2D_DEST_FLAG_BUFFER_BASE_1" type="waddress" align="64" usage="rp_blit"/> 1910 1821 <reg32 offset="0x8c25" name="RB_A2D_DEST_FLAG_BUFFER_PITCH_1" low="0" high="7" shr="6" type="uint" usage="rp_blit"/> ··· 2010 1921 <bitfield name="CLIP_DIST_03_LOC" low="8" high="15" type="uint"/> 2011 1922 <bitfield name="CLIP_DIST_47_LOC" low="16" high="23" type="uint"/> 2012 1923 </bitset> 2013 - <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2014 - <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2015 - <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1924 + <reg32 offset="0x9101" name="VPC_VS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1925 + <reg32 offset="0x9102" name="VPC_GS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1926 + <reg32 offset="0x9103" name="VPC_DS_CLIP_CULL_CNTL" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2016 1927 2017 - <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2018 - <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 2019 - <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" usage="rp_blit"/> 1928 + <reg32 offset="0x9311" name="VPC_VS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1929 + <reg32 offset="0x9312" name="VPC_GS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1930 + <reg32 offset="0x9313" name="VPC_DS_CLIP_CULL_CNTL_V2" type="a6xx_vpc_xs_clip_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2020 1931 2021 1932 <bitset name="a6xx_vpc_xs_siv_cntl" inline="yes"> 2022 1933 <bitfield name="LAYERLOC" low="0" high="7" type="uint"/> ··· 2024 1935 <bitfield name="SHADINGRATELOC" low="16" high="23" type="uint" variants="A7XX-"/> 2025 1936 </bitset> 2026 1937 2027 - <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2028 - <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2029 - <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1938 + <reg32 offset="0x9104" name="VPC_VS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1939 + <reg32 offset="0x9105" name="VPC_GS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1940 + <reg32 offset="0x9106" name="VPC_DS_SIV_CNTL" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2030 1941 2031 - <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2032 - <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 2033 - <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" usage="rp_blit"/> 1942 + 1943 + <reg32 offset="0x9314" name="VPC_VS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1944 + <reg32 offset="0x9315" name="VPC_GS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1945 + <reg32 offset="0x9316" name="VPC_DS_SIV_CNTL_V2" type="a6xx_vpc_xs_siv_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 1946 + 1947 + <bitset name="a6xx_vpc_rast_stream_cntl" inline="yes"> 1948 + <!-- which stream to send to GRAS --> 1949 + <bitfield name="STREAM" low="0" high="1" type="uint"/> 1950 + <!-- discard primitives before rasterization --> 1951 + <bitfield name="DISCARD" pos="2" type="boolean"/> 1952 + </bitset> 1953 + 1954 + <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A6XX" usage="rp_blit"/> 1955 + <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 1956 + <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" type="a6xx_vpc_rast_stream_cntl" variants="A7XX" usage="rp_blit"/> 2034 1957 2035 1958 <reg32 offset="0x9107" name="VPC_UNKNOWN_9107" variants="A6XX" usage="rp_blit"> 2036 1959 <!-- this mirrors VPC_RAST_STREAM_CNTL::DISCARD, although it seems it's unused --> 2037 1960 <bitfield name="RASTER_DISCARD" pos="0" type="boolean"/> 2038 1961 <bitfield name="UNK2" pos="2" type="boolean"/> 2039 1962 </reg32> 2040 - <reg32 offset="0x9108" name="VPC_RAST_CNTL" usage="rp_blit"> 2041 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2042 - </reg32> 2043 1963 1964 + <reg32 offset="0x9108" name="VPC_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2044 1965 <bitset name="a6xx_pc_cntl" inline="yes"> 2045 1966 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/> 2046 1967 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/> ··· 2090 1991 <bitfield name="VIEWS" low="2" high="6" type="uint"/> 2091 1992 </bitset> 2092 1993 2093 - <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX-" usage="rp_blit"/> 2094 - <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX-" usage="rp_blit"/> 2095 - <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX-" usage="rp_blit"/> 2096 - <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX-" usage="rp_blit"/> 1994 + <reg32 offset="0x9109" name="VPC_PC_CNTL" type="a6xx_pc_cntl" variants="A7XX" usage="rp_blit"/> 1995 + <reg32 offset="0x910a" name="VPC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A7XX" usage="rp_blit"/> 1996 + <reg32 offset="0x910b" name="VPC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A7XX" usage="rp_blit"/> 1997 + <reg32 offset="0x910c" name="VPC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A7XX" usage="rp_blit"/> 2097 1998 2098 1999 <enum name="a6xx_varying_interp_mode"> 2099 2000 <value value="0" name="INTERP_SMOOTH"/> ··· 2110 2011 </enum> 2111 2012 2112 2013 <!-- 0x9109-0x91ff invalid --> 2113 - <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" usage="rp_blit"> 2014 + <array offset="0x9200" name="VPC_VARYING_INTERP_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="rp_blit"> 2114 2015 <doc>Packed array of a6xx_varying_interp_mode</doc> 2115 2016 <reg32 offset="0x0" name="MODE"/> 2116 2017 </array> 2117 - <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE_0" stride="1" length="8" usage="rp_blit"> 2018 + <array offset="0x9208" name="VPC_VARYING_REPLACE_MODE" stride="1" length="8" variants="A6XX-A7XX" usage="rp_blit"> 2118 2019 <doc>Packed array of a6xx_varying_ps_repl_mode</doc> 2119 2020 <reg32 offset="0x0" name="MODE"/> 2120 2021 </array> ··· 2123 2024 <reg32 offset="0x9210" name="VPC_UNKNOWN_9210" low="0" high="31" variants="A6XX" usage="cmd"/> 2124 2025 <reg32 offset="0x9211" name="VPC_UNKNOWN_9211" low="0" high="31" variants="A6XX" usage="cmd"/> 2125 2026 2126 - <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL_0" stride="1" length="4" usage="rp_blit"> 2027 + <array offset="0x9212" name="VPC_VARYING_LM_TRANSFER_CNTL" stride="1" length="4" variants="A6XX-A7XX" usage="rp_blit"> 2127 2028 <!-- one bit per varying component: --> 2128 2029 <reg32 offset="0" name="DISABLE"/> 2129 2030 </array> 2130 2031 2131 - <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" usage="rp_blit"> 2032 + <bitset name="a6xx_vpc_so_mapping_wptr" inline="yes"> 2132 2033 <!-- 2133 2034 Choose which DWORD to write to. There is an array of 2134 2035 (4 * 64) DWORD's, dumped in the devcoredump at ··· 2155 2056 <bitfield name="ADDR" low="0" high="7" type="hex"/> 2156 2057 <!-- clear all A_EN and B_EN bits for all DWORD's --> 2157 2058 <bitfield name="RESET" pos="16" type="boolean"/> 2158 - </reg32> 2159 - <!-- special register, write multiple times to load SO program (not readable) --> 2160 - <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" usage="rp_blit"> 2059 + </bitset> 2060 + 2061 + <reg32 offset="0x9216" name="VPC_SO_MAPPING_WPTR" type="a6xx_vpc_so_mapping_wptr" variants="A6XX-A7XX" usage="rp_blit"/> 2062 + 2063 + <bitset name="a6xx_vpc_so_mapping_port" inline="yes"> 2161 2064 <bitfield name="A_BUF" low="0" high="1" type="uint"/> 2162 2065 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/> 2163 2066 <bitfield name="A_EN" pos="11" type="boolean"/> 2164 2067 <bitfield name="B_BUF" low="12" high="13" type="uint"/> 2165 2068 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/> 2166 2069 <bitfield name="B_EN" pos="23" type="boolean"/> 2167 - </reg32> 2070 + </bitset> 2168 2071 2169 - <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" usage="cmd"/> 2072 + <!-- special register, write multiple times to load SO program (not readable) --> 2073 + <reg32 offset="0x9217" name="VPC_SO_MAPPING_PORT" type="a6xx_vpc_so_mapping_port" variants="A6XX-A7XX" usage="rp_blit"/> 2170 2074 2171 - <array offset="0x921a" name="VPC_SO" stride="7" length="4" usage="cmd"> 2075 + <reg64 offset="0x9218" name="VPC_SO_QUERY_BASE" type="waddress" align="32" variants="A6XX-A7XX" usage="cmd"/> 2076 + 2077 + <array offset="0x921a" name="VPC_SO" stride="7" length="4" variants="A6XX-A7XX" usage="cmd"> 2172 2078 <reg64 offset="0" name="BUFFER_BASE" type="waddress" align="32"/> 2173 2079 <reg32 offset="2" name="BUFFER_SIZE" low="2" high="31" shr="2"/> 2174 2080 <reg32 offset="3" name="BUFFER_STRIDE" low="0" high="9" shr="2"/> ··· 2181 2077 <reg64 offset="5" name="FLUSH_BASE" type="waddress" align="32"/> 2182 2078 </array> 2183 2079 2184 - <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" usage="cmd"> 2080 + <bitset name="a6xx_vpc_replace_mode_cntl" inline="yes"> 2185 2081 <bitfield name="INVERT" pos="0" type="boolean"/> 2186 - </reg32> 2187 - <!-- 0x9237-0x92ff invalid --> 2188 - <!-- always 0x0 ? --> 2189 - <reg32 offset="0x9300" name="VPC_UNKNOWN_9300" low="0" high="2" usage="cmd"/> 2082 + </bitset> 2083 + 2084 + <reg32 offset="0x9236" name="VPC_REPLACE_MODE_CNTL" type="a6xx_vpc_replace_mode_cntl" variants="A6XX-A7XX" usage="cmd"/> 2085 + 2086 + <reg32 offset="0x9300" name="VPC_ROTATION_CNTL" low="0" high="2" variants="A6XX-A7XX" usage="cmd"/> 2190 2087 2191 2088 <bitset name="a6xx_vpc_xs_cntl" inline="yes"> 2192 2089 <doc> ··· 2206 2101 </doc> 2207 2102 </bitfield> 2208 2103 </bitset> 2209 - <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2210 - <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2211 - <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" usage="rp_blit"/> 2212 2104 2213 - <reg32 offset="0x9304" name="VPC_PS_CNTL" usage="rp_blit"> 2105 + <reg32 offset="0x9301" name="VPC_VS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2106 + <reg32 offset="0x9302" name="VPC_GS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2107 + <reg32 offset="0x9303" name="VPC_DS_CNTL" type="a6xx_vpc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2108 + 2109 + <bitset name="a6xx_vpc_ps_cntl" inline="yes"> 2214 2110 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/> 2215 2111 <!-- for fixed-function (i.e. no GS) gl_PrimitiveID in FS --> 2216 2112 <bitfield name="PRIMIDLOC" low="8" high="15" type="uint"/> ··· 2228 2122 ViewID through the VS. 2229 2123 </doc> 2230 2124 </bitfield> 2231 - </reg32> 2125 + </bitset> 2232 2126 2233 - <reg32 offset="0x9305" name="VPC_SO_CNTL" usage="rp_blit"> 2127 + <reg32 offset="0x9304" name="VPC_PS_CNTL" type="a6xx_vpc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2128 + 2129 + <bitset name="a6xx_vpc_so_cntl" inline="yes"> 2234 2130 <!-- 2235 2131 It's offset by 1, and 0 means "disabled" 2236 2132 --> ··· 2241 2133 <bitfield name="BUF2_STREAM" low="6" high="8" type="uint"/> 2242 2134 <bitfield name="BUF3_STREAM" low="9" high="11" type="uint"/> 2243 2135 <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2244 - </reg32> 2245 - <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" usage="rp_blit"> 2136 + </bitset> 2137 + 2138 + <reg32 offset="0x9305" name="VPC_SO_CNTL" type="a6xx_vpc_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2139 + 2140 + <bitset name="a6xx_so_override" inline="yes"> 2246 2141 <bitfield name="DISABLE" pos="0" type="boolean"/> 2247 - </reg32> 2248 - <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" variants="A6XX-" usage="rp_blit"> <!-- A702 + A7xx --> 2249 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2250 - </reg32> 2251 - <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2252 - <bitfield name="SIZE_GMEM" low="0" high="31"/> 2253 - </reg32> 2254 - <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX-" usage="rp_blit"> 2255 - <bitfield name="BASE_GMEM" low="0" high="31"/> 2256 - </reg32> 2257 - <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX-" usage="rp_blit"> 2258 - <bitfield name="SIZE_GMEM" low="0" high="31"/> 2259 - </reg32> 2142 + </bitset> 2143 + 2144 + <reg32 offset="0x9306" name="VPC_SO_OVERRIDE" type="a6xx_so_override" variants="A6XX-A7XX" usage="rp_blit"/> 2145 + 2146 + <reg32 offset="0x9807" name="PC_DGEN_SO_OVERRIDE" type="a6xx_so_override" variants="A7XX" usage="rp_blit"/> 2147 + 2148 + <reg32 offset="0x9307" name="VPC_PS_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2149 + 2150 + <reg32 offset="0x9308" name="VPC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/> 2151 + <reg32 offset="0x9309" name="VPC_ATTR_BUF_GMEM_BASE" variants="A7XX" type="uint" usage="rp_blit"/> 2152 + 2153 + <reg32 offset="0x9b09" name="PC_ATTR_BUF_GMEM_SIZE" variants="A7XX" type="uint" usage="rp_blit"/> 2154 + 2155 + <reg32 offset="0x930a" name="VPC_UNKNOWN_930A" variants="A7XX"/> 2156 + 2157 + <reg32 offset="0x960a" name="VPC_FLATSHADE_MODE_CNTL" variants="A7XX"/> 2260 2158 2261 2159 <!-- 0x9307-0x95ff invalid --> 2262 2160 ··· 2277 2163 <!-- TODO: regs from 0x9624-0x963a --> 2278 2164 <!-- 0x963b-0x97ff invalid --> 2279 2165 2280 - <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" usage="rp_blit"/> 2166 + <reg32 offset="0x9800" name="PC_HS_PARAM_0" low="0" high="5" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 2281 2167 2282 - <!-- always 0x0 ? --> 2283 - <reg32 offset="0x9801" name="PC_HS_PARAM_1" usage="rp_blit"> 2168 + <bitset name="a6xx_pc_hs_param_1" inline="yes"> 2284 2169 <bitfield name="SIZE" low="0" high="10" type="uint"/> 2285 2170 <bitfield name="UNK13" pos="13"/> 2286 - </reg32> 2171 + </bitset> 2287 2172 2288 - <reg32 offset="0x9802" name="PC_DS_PARAM" usage="rp_blit"> 2173 + <reg32 offset="0x9801" name="PC_HS_PARAM_1" type="a6xx_pc_hs_param_1" variants="A6XX-A7XX" usage="rp_blit"/> 2174 + 2175 + <bitset name="a6xx_pc_ds_param" inline="yes"> 2289 2176 <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/> 2290 2177 <bitfield name="OUTPUT" low="2" high="3" type="a6xx_tess_output"/> 2291 - </reg32> 2178 + </bitset> 2292 2179 2293 - <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" usage="rp_blit"/> 2294 - <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" usage="rp_blit"/> 2180 + <reg32 offset="0x9802" name="PC_DS_PARAM" type="a6xx_pc_ds_param" variants="A6XX-A7XX" usage="rp_blit"/> 2181 + 2182 + <reg32 offset="0x9803" name="PC_RESTART_INDEX" low="0" high="31" type="uint" variants="A6XX-A7XX" usage="rp_blit"/> 2183 + 2184 + <reg32 offset="0x9804" name="PC_MODE_CNTL" low="0" high="7" variants="A6XX-A7XX" usage="rp_blit"/> 2295 2185 2296 2186 <reg32 offset="0x9805" name="PC_POWER_CNTL" low="0" high="2" usage="rp_blit"/> 2297 2187 2298 - <reg32 offset="0x9806" name="PC_PS_CNTL" usage="rp_blit"> 2188 + <bitset name="a6xx_pc_ps_cntl" inline="yes"> 2299 2189 <bitfield name="PRIMITIVEIDEN" pos="0" type="boolean"/> 2300 - </reg32> 2190 + </bitset> 2191 + 2192 + <reg32 offset="0x9806" name="PC_PS_CNTL" type="a6xx_pc_ps_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2193 + 2194 + <bitset name="a6xx_pc_dgen_so_cntl" inline="yes"> 2195 + <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2196 + </bitset> 2301 2197 2302 2198 <!-- New in a6xx gen3+ --> 2303 - <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" usage="rp_blit"> 2304 - <bitfield name="STREAM_ENABLE" low="15" high="18" type="hex"/> 2305 - </reg32> 2199 + <reg32 offset="0x9808" name="PC_DGEN_SO_CNTL" type="a6xx_pc_dgen_so_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2306 2200 2307 - <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL"> 2201 + <bitset name="a6xx_pc_dgen_su_conservative_ras_cntl" inline="yes"> 2308 2202 <bitfield name="CONSERVATIVERASEN" pos="0" type="boolean"/> 2309 - </reg32> 2310 - <!-- 0x980b-0x983f invalid --> 2203 + </bitset> 2204 + 2205 + <reg32 offset="0x980a" name="PC_DGEN_SU_CONSERVATIVE_RAS_CNTL" type="a6xx_pc_dgen_su_conservative_ras_cntl" variants="A6XX-A7XX"/> 2311 2206 2312 2207 <!-- 0x9840 - 0x9842 are not readable --> 2313 - <reg32 offset="0x9840" name="PC_DRAW_INITIATOR"> 2208 + <bitset name="a6xx_draw_initiator" inline="yes"> 2314 2209 <bitfield name="STATE_ID" low="0" high="7"/> 2315 - </reg32> 2210 + </bitset> 2316 2211 2317 - <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR"> 2318 - <bitfield name="STATE_ID" low="0" high="7"/> 2319 - </reg32> 2212 + <reg32 offset="0x9840" name="PC_DRAW_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 2213 + <reg32 offset="0x9841" name="PC_KERNEL_INITIATOR" type="a6xx_draw_initiator" variants="A6XX-A7XX"/> 2320 2214 2321 - <reg32 offset="0x9842" name="PC_EVENT_INITIATOR"> 2215 + <bitset name="a6xx_event_initiator" inline="yes"> 2322 2216 <!-- I think only the low bit is actually used? --> 2323 2217 <bitfield name="STATE_ID" low="16" high="23"/> 2324 2218 <bitfield name="EVENT" low="0" high="6" type="vgt_event_type"/> 2325 - </reg32> 2219 + </bitset> 2220 + 2221 + <reg32 offset="0x9842" name="PC_EVENT_INITIATOR" type="a6xx_event_initiator" variants="A6XX-A7XX"/> 2326 2222 2327 2223 <!-- 2328 2224 0x9880 written in a lot of places by SQE, same value gets written ··· 2343 2219 2344 2220 <!-- 0x9843-0x997f invalid --> 2345 2221 2346 - <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" variants="A6XX" usage="rp_blit"> 2347 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2348 - </reg32> 2349 - <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" variants="A7XX-" usage="rp_blit"> 2350 - <bitfield name="MODE" low="0" high="1" type="a6xx_polygon_mode"/> 2351 - </reg32> 2352 - 2353 - <reg32 offset="0x9980" name="VPC_RAST_STREAM_CNTL" variants="A6XX" usage="rp_blit"> 2354 - <!-- which stream to send to GRAS --> 2355 - <bitfield name="STREAM" low="0" high="1" type="uint"/> 2356 - <!-- discard primitives before rasterization --> 2357 - <bitfield name="DISCARD" pos="2" type="boolean"/> 2358 - </reg32> 2359 - <!-- VPC_RAST_STREAM_CNTL --> 2360 - <reg32 offset="0x9107" name="VPC_RAST_STREAM_CNTL" variants="A7XX-" usage="rp_blit"> 2361 - <!-- which stream to send to GRAS --> 2362 - <bitfield name="STREAM" low="0" high="1" type="uint"/> 2363 - <!-- discard primitives before rasterization --> 2364 - <bitfield name="DISCARD" pos="2" type="boolean"/> 2365 - </reg32> 2366 - <reg32 offset="0x9317" name="VPC_RAST_STREAM_CNTL_V2" variants="A7XX-" usage="rp_blit"> 2367 - <!-- which stream to send to GRAS --> 2368 - <bitfield name="STREAM" low="0" high="1" type="uint"/> 2369 - <!-- discard primitives before rasterization --> 2370 - <bitfield name="DISCARD" pos="2" type="boolean"/> 2371 - </reg32> 2222 + <reg32 offset="0x9981" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A6XX" usage="rp_blit"/> 2223 + <reg32 offset="0x9809" name="PC_DGEN_RAST_CNTL" type="a6xx_rast_cntl" variants="A7XX" usage="rp_blit"/> 2372 2224 2373 2225 <!-- Both are a750+. 2374 2226 Probably needed to correctly overlap execution of several draws. 2375 2227 --> 2376 - <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2228 + <reg32 offset="0x9885" name="PC_HS_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 2377 2229 <!-- Blob adds a bit more space {0x10, 0x20, 0x30, 0x40} bytes, but the meaning of 2378 2230 this additional space is not known. 2379 2231 --> 2380 - <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX-" usage="cmd"/> 2232 + <reg32 offset="0x9886" name="PC_TF_BUFFER_SIZE" variants="A7XX" usage="cmd"/> 2381 2233 2382 2234 <!-- 0x9982-0x9aff invalid --> 2383 2235 2384 - <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" usage="rp_blit"/> 2236 + <reg32 offset="0x9b00" name="PC_CNTL" type="a6xx_pc_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2385 2237 2386 2238 <bitset name="a6xx_pc_xs_cntl" inline="yes"> 2387 2239 <doc> ··· 2370 2270 <bitfield name="LAYER" pos="9" type="boolean"/> 2371 2271 <bitfield name="VIEW" pos="10" type="boolean"/> 2372 2272 <!-- note: PC_VS_CNTL doesn't have the PRIMITIVE_ID bit --> 2273 + <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2373 2274 <bitfield name="PRIMITIVE_ID" pos="11" type="boolean"/> 2374 2275 <bitfield name="CLIP_MASK" low="16" high="23" type="uint"/> 2375 2276 <bitfield name="SHADINGRATE" pos="24" type="boolean" variants="A7XX-"/> 2376 2277 </bitset> 2377 2278 2378 - <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2379 - <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2380 - <!-- since HS can't output anything, only PRIMITIVE_ID is valid --> 2381 - <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2382 - <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" usage="rp_blit"/> 2279 + <reg32 offset="0x9b01" name="PC_VS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2280 + <reg32 offset="0x9b02" name="PC_GS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2281 + <reg32 offset="0x9b03" name="PC_HS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2282 + <reg32 offset="0x9b04" name="PC_DS_CNTL" type="a6xx_pc_xs_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2383 2283 2384 - <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" usage="rp_blit"/> 2284 + <reg32 offset="0x9b05" name="PC_GS_PARAM_0" type="a6xx_gs_param_0" variants="A6XX-A7XX" usage="rp_blit"/> 2385 2285 2386 2286 <reg32 offset="0x9b06" name="PC_PRIMITIVE_CNTL_6" variants="A6XX" usage="rp_blit"> 2387 2287 <doc> ··· 2390 2290 <bitfield name="STRIDE_IN_VPC" low="0" high="10" type="uint"/> 2391 2291 </reg32> 2392 2292 2393 - <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" usage="rp_blit"/> 2293 + <reg32 offset="0x9b07" name="PC_STEREO_RENDERING_CNTL" type="a6xx_stereo_rendering_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 2394 2294 <!-- mask of enabled views, doesn't exist on A630 --> 2395 - <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" usage="rp_blit"/> 2295 + <reg32 offset="0x9b08" name="PC_STEREO_RENDERING_VIEWMASK" type="hex" low="0" high="15" variants="A6XX-A7XX" usage="rp_blit"/> 2396 2296 <!-- 0x9b09-0x9bff invalid --> 2397 2297 <reg32 offset="0x9c00" name="PC_2D_EVENT_CMD"> 2398 2298 <!-- special register (but note first 8 bits can be written/read) --> ··· 2403 2303 <!-- TODO: 0x9e00-0xa000 range incomplete --> 2404 2304 <reg32 offset="0x9e00" name="PC_DBG_ECO_CNTL"/> 2405 2305 <reg32 offset="0x9e01" name="PC_ADDR_MODE_CNTL" type="a5xx_address_mode"/> 2406 - <reg64 offset="0x9e04" name="PC_DMA_BASE"/> 2407 - <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint"/> 2408 - <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint"/> 2409 - <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 2410 - <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX-" type="waddress" align="32" usage="cmd"/> 2306 + <reg64 offset="0x9e04" name="PC_DMA_BASE" type="address" variants="A6XX-A7XX"/> 2307 + <reg32 offset="0x9e06" name="PC_DMA_OFFSET" type="uint" variants="A6XX-A7XX"/> 2308 + <reg32 offset="0x9e07" name="PC_DMA_SIZE" type="uint" variants="A6XX-A7XX"/> 2411 2309 2412 - <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx"> 2310 + <reg64 offset="0x9e08" name="PC_TESS_BASE" variants="A6XX" type="waddress" align="32" usage="cmd"/> 2311 + <reg64 offset="0x9810" name="PC_TESS_BASE" variants="A7XX" type="waddress" align="32" usage="cmd"/> 2312 + 2313 + <reg32 offset="0x9e0b" name="PC_DRAWCALL_CNTL" type="vgt_draw_initiator_a4xx" variants="A6XX-A7XX"> 2413 2314 <doc> 2414 2315 Possibly not really "initiating" the draw but the layout is similar 2415 2316 to VGT_DRAW_INITIATOR on older gens 2416 2317 </doc> 2417 2318 </reg32> 2418 - <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint"/> 2419 - <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint"/> 2319 + <reg32 offset="0x9e0c" name="PC_DRAWCALL_INSTANCE_NUM" type="uint" variants="A6XX-A7XX"/> 2320 + <reg32 offset="0x9e0d" name="PC_DRAWCALL_SIZE" type="uint" variants="A6XX-A7XX"/> 2420 2321 2421 2322 <!-- These match the contents of CP_SET_BIN_DATA (not written directly) --> 2422 - <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL"> 2323 + <bitset name="a6xx_pc_vis_stream_cntl" inline="yes"> 2423 2324 <bitfield name="UNK0" low="0" high="15"/> 2424 2325 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/> 2425 2326 <bitfield name="VSC_N" low="22" high="26" type="uint"/> 2426 - </reg32> 2427 - <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2428 - <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32"/> 2327 + </bitset> 2429 2328 2430 - <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE"> 2329 + <reg32 offset="0x9e11" name="PC_VIS_STREAM_CNTL" type="a6xx_pc_vis_stream_cntl" variants="A6XX-A7XX"/> 2330 + <reg64 offset="0x9e12" name="PC_PVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 2331 + <reg64 offset="0x9e14" name="PC_DVIS_STREAM_BIN_BASE" type="waddress" align="32" variants="A6XX-A7XX"/> 2332 + 2333 + <bitset name="a6xx_pc_drawcall_cntl_override" inline="yes"> 2431 2334 <doc>Written by CP_SET_VISIBILITY_OVERRIDE handler</doc> 2432 2335 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 2433 - </reg32> 2336 + </bitset> 2337 + 2338 + <reg32 offset="0x9e1c" name="PC_DRAWCALL_CNTL_OVERRIDE" type="a6xx_pc_drawcall_cntl_override" variants="A6XX-A7XX"/> 2434 2339 2435 2340 <reg32 offset="0x9e24" name="PC_UNKNOWN_9E24" variants="A7XX-" usage="cmd"/> 2436 2341 ··· 3041 2936 <reg32 offset="0xa9b3" name="SP_CS_PROGRAM_COUNTER_OFFSET" type="uint" usage="cmd"/> 3042 2937 <reg64 offset="0xa9b4" name="SP_CS_BASE" type="address" align="32" usage="cmd"/> 3043 2938 <reg32 offset="0xa9b6" name="SP_CS_PVT_MEM_PARAM" type="a6xx_sp_xs_pvt_mem_param" usage="cmd"/> 3044 - <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" align="32" usage="cmd"/> 2939 + <reg64 offset="0xa9b7" name="SP_CS_PVT_MEM_BASE" type="waddress" align="32" usage="cmd"/> 3045 2940 <reg32 offset="0xa9b9" name="SP_CS_PVT_MEM_SIZE" type="a6xx_sp_xs_pvt_mem_size" usage="cmd"/> 3046 2941 <reg32 offset="0xa9ba" name="SP_CS_TSIZE" low="0" high="7" type="uint" usage="cmd"/> 3047 2942 <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config" usage="cmd"/> ··· 3126 3021 UAV state for compute shader: 3127 3022 --> 3128 3023 <reg64 offset="0xa9f2" name="SP_CS_UAV_BASE" type="address" align="16" variants="A6XX"/> 3129 - <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX"/> 3024 + <reg64 offset="0xa9f8" name="SP_CS_UAV_BASE" type="address" align="16" variants="A7XX-"/> 3130 3025 <reg32 offset="0xaa00" name="SP_CS_USIZE" low="0" high="6" type="uint"/> 3131 3026 3132 3027 <!-- Correlated with avgs/uvgs usage in FS --> ··· 3209 3104 instructions VS/HS/DS/GS/FS. See SP_CS_UAV_BASE_* for compute shaders. 3210 3105 --> 3211 3106 <reg64 offset="0xab1a" name="SP_GFX_UAV_BASE" type="address" align="16" usage="cmd"/> 3212 - <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" usage="cmd"/> 3107 + <reg32 offset="0xab20" name="SP_GFX_USIZE" low="0" high="6" type="uint" variants="A6XX-A7XX" usage="cmd"/> 3213 3108 3214 - <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX-" usage="cmd"/> 3109 + <reg32 offset="0xab22" name="SP_UNKNOWN_AB22" variants="A7XX" usage="cmd"/> 3110 + 3111 + <enum name="a6xx_sp_a2d_output_ifmt_type"> 3112 + <value name="OUTPUT_IFMT_2D_FLOAT" value="0"/> 3113 + <value name="OUTPUT_IFMT_2D_SINT" value="1"/> 3114 + <value name="OUTPUT_IFMT_2D_UINT" value="2"/> 3115 + </enum> 3215 3116 3216 3117 <bitset name="a6xx_sp_a2d_output_info" inline="yes"> 3217 - <bitfield name="NORM" pos="0" type="boolean"/> 3218 - <bitfield name="SINT" pos="1" type="boolean"/> 3219 - <bitfield name="UINT" pos="2" type="boolean"/> 3118 + <bitfield name="HALF_PRECISION" pos="0" type="boolean"/> 3119 + <bitfield name="IFMT_TYPE" low="1" high="2" type="a6xx_sp_a2d_output_ifmt_type"/> 3220 3120 <!-- looks like HW only cares about the base type of this format, 3221 3121 which matches the ifmt? --> 3222 3122 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_format"/> ··· 3266 3156 <reg32 offset="0xae6b" name="SP_UNKNOWN_AE6B" variants="A7XX-" usage="cmd"/> 3267 3157 <reg32 offset="0xae6c" name="SP_HLSQ_DBG_ECO_CNTL" variants="A7XX-" usage="cmd"/> 3268 3158 <reg32 offset="0xae6d" name="SP_READ_SEL" variants="A7XX-"> 3269 - <bitfield name="LOCATION" low="18" high="19" type="a7xx_state_location"/> 3159 + <bitfield name="LOCATION" low="18" high="20" type="a7xx_state_location"/> 3270 3160 <bitfield name="PIPE" low="16" high="17" type="a7xx_pipe"/> 3271 3161 <bitfield name="STATETYPE" low="8" high="15" type="a7xx_statetype_id"/> 3272 3162 <bitfield name="USPTP" low="4" high="7"/> ··· 3302 3192 3303 3193 <!-- looks to work in the same way as a5xx: --> 3304 3194 <reg64 offset="0xb302" name="TPL1_GFX_BORDER_COLOR_BASE" type="address" align="128" usage="cmd"/> 3305 - <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" usage="rp_blit"/> 3195 + <reg32 offset="0xb304" name="TPL1_MSAA_SAMPLE_POS_CNTL" type="a6xx_msaa_sample_pos_cntl" variants="A6XX-A7XX" usage="rp_blit"/> 3306 3196 <reg32 offset="0xb305" name="TPL1_PROGRAMMABLE_MSAA_POS_0" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3307 3197 <reg32 offset="0xb306" name="TPL1_PROGRAMMABLE_MSAA_POS_1" type="a6xx_programmable_msaa_pos" usage="rp_blit"/> 3308 3198 <reg32 offset="0xb307" name="TPL1_WINDOW_OFFSET" type="a6xx_reg_xy" usage="rp_blit"/> ··· 3342 3232 </reg32> 3343 3233 3344 3234 <reg32 offset="0xb2c0" name="TPL1_A2D_SRC_TEXTURE_INFO" type="a6xx_a2d_src_texture_info" variants="A7XX-" usage="rp_blit"/> 3345 - <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX"> 3235 + <reg32 offset="0xb2c1" name="TPL1_A2D_SRC_TEXTURE_SIZE" variants="A7XX-"> 3346 3236 <bitfield name="WIDTH" low="0" high="14" type="uint"/> 3347 3237 <bitfield name="HEIGHT" low="15" high="29" type="uint"/> 3348 3238 </reg32> 3349 3239 <reg64 offset="0xb2c2" name="TPL1_A2D_SRC_TEXTURE_BASE" type="address" align="16" variants="A7XX-" usage="rp_blit"/> 3350 - <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX"> 3240 + <reg32 offset="0xb2c4" name="TPL1_A2D_SRC_TEXTURE_PITCH" variants="A7XX-"> 3351 3241 <!-- 3352 3242 Bits from 3..9 must be zero unless 'TPL1_A2D_BLT_CNTL::TYPE' 3353 3243 is A6XX_TEX_IMG_BUFFER, which allows for lower alignment. ··· 3380 3270 <reg32 offset="0xb2ce" name="SP_PS_UNKNOWN_B4CE" low="0" high="31" variants="A7XX"/> 3381 3271 <reg32 offset="0xb2cf" name="SP_PS_UNKNOWN_B4CF" low="0" high="30" variants="A7XX"/> 3382 3272 <reg32 offset="0xb2d0" name="SP_PS_UNKNOWN_B4D0" low="0" high="29" variants="A7XX"/> 3383 - <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX"/> 3273 + <reg32 offset="0xb2d1" name="TPL1_A2D_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-"/> 3384 3274 <reg32 offset="0xb2d2" name="TPL1_A2D_BLT_CNTL" variants="A7XX-" usage="rp_blit"> 3385 3275 <bitfield name="RAW_COPY" pos="0" type="boolean"/> 3386 3276 <bitfield name="START_OFFSET_TEXELS" low="16" high="21"/> 3387 3277 <bitfield name="TYPE" low="29" high="31" type="a6xx_tex_type"/> 3388 3278 </reg32> 3389 - <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX-" usage="rp_blit"/> 3279 + <reg32 offset="0xab21" name="SP_WINDOW_OFFSET" type="a6xx_reg_xy" variants="A7XX" usage="rp_blit"/> 3390 3280 3391 3281 <!-- always 0x100000 or 0x1000000? --> 3392 3282 <reg32 offset="0xb600" name="TPL1_DBG_ECO_CNTL" low="0" high="25" usage="cmd"/> ··· 3744 3634 <reg32 offset="0xbb10" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A6XX" usage="rp_blit"/> 3745 3635 <reg32 offset="0xab03" name="SP_PS_CONST_CONFIG" type="a6xx_xs_const_config" variants="A7XX-" usage="rp_blit"/> 3746 3636 3747 - <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX_0" stride="1" length="64" variants="A7XX-"/> 3637 + <array offset="0xab40" name="SP_SHARED_CONSTANT_GFX" stride="1" length="64" variants="A7XX"/> 3748 3638 3749 3639 <reg32 offset="0xbb11" name="HLSQ_SHARED_CONSTS" variants="A6XX" usage="cmd"> 3750 3640 <doc> ··· 3906 3796 <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/> 3907 3797 </domain> 3908 3798 3909 - <domain name="A7XX_CX_DBGC" width="32"> 3799 + <domain name="A7XX_CX_DBGC" width="32" varset="chip"> 3910 3800 <!-- Bitfields shifted, but otherwise the same: --> 3911 3801 <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A" variants="A7XX-"> 3912 3802 <bitfield high="7" low="0" name="PING_INDEX"/>
-40
drivers/gpu/drm/msm/registers/adreno/a6xx_descriptors.xml
··· 9 9 10 10 <domain name="A6XX_TEX_SAMP" width="32"> 11 11 <doc>Texture sampler dwords</doc> 12 - <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 13 - <value name="A6XX_TEX_NEAREST" value="0"/> 14 - <value name="A6XX_TEX_LINEAR" value="1"/> 15 - <value name="A6XX_TEX_ANISO" value="2"/> 16 - <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 17 - </enum> 18 - <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 19 - <value name="A6XX_TEX_REPEAT" value="0"/> 20 - <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 21 - <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 22 - <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 23 - <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 24 - </enum> 25 - <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 26 - <value name="A6XX_TEX_ANISO_1" value="0"/> 27 - <value name="A6XX_TEX_ANISO_2" value="1"/> 28 - <value name="A6XX_TEX_ANISO_4" value="2"/> 29 - <value name="A6XX_TEX_ANISO_8" value="3"/> 30 - <value name="A6XX_TEX_ANISO_16" value="4"/> 31 - </enum> 32 - <enum name="a6xx_reduction_mode"> 33 - <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 34 - <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 35 - <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 36 - </enum> 37 - <enum name="a6xx_fast_border_color"> 38 - <!-- R B G A --> 39 - <value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/> 40 - <value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/> 41 - <value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/> 42 - <value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/> 43 - </enum> 44 12 45 13 <reg32 offset="0" name="0"> 46 14 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/> ··· 47 79 48 80 <domain name="A6XX_TEX_CONST" width="32" varset="chip"> 49 81 <doc>Texture constant dwords</doc> 50 - <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 51 - <value name="A6XX_TEX_X" value="0"/> 52 - <value name="A6XX_TEX_Y" value="1"/> 53 - <value name="A6XX_TEX_Z" value="2"/> 54 - <value name="A6XX_TEX_W" value="3"/> 55 - <value name="A6XX_TEX_ZERO" value="4"/> 56 - <value name="A6XX_TEX_ONE" value="5"/> 57 - </enum> 58 82 <reg32 offset="0" name="0"> 59 83 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/> 60 84 <bitfield name="SRGB" pos="2" type="boolean"/>
+48 -2
drivers/gpu/drm/msm/registers/adreno/a6xx_enums.xml
··· 320 320 16b float: 3 321 321 --> 322 322 <enum name="a6xx_2d_ifmt"> 323 - <value value="0x10" name="R2D_UNORM8"/> 324 323 <value value="0x7" name="R2D_INT32"/> 325 324 <value value="0x6" name="R2D_INT16"/> 326 325 <value value="0x5" name="R2D_INT8"/> 327 326 <value value="0x4" name="R2D_FLOAT32"/> 328 327 <value value="0x3" name="R2D_FLOAT16"/> 328 + <value value="0x2" name="R2D_SNORM8"/> 329 329 <value value="0x1" name="R2D_UNORM8_SRGB"/> 330 - <value value="0x0" name="R2D_RAW"/> 330 + <value value="0x0" name="R2D_UNORM8"/> 331 331 </enum> 332 332 333 333 <enum name="a6xx_tex_type"> ··· 378 378 <value value="0x1" name="TESS_LINES"/> 379 379 <value value="0x2" name="TESS_CW_TRIS"/> 380 380 <value value="0x3" name="TESS_CCW_TRIS"/> 381 + </enum> 382 + 383 + <enum name="a6xx_tex_filter"> <!-- same as a4xx? --> 384 + <value name="A6XX_TEX_NEAREST" value="0"/> 385 + <value name="A6XX_TEX_LINEAR" value="1"/> 386 + <value name="A6XX_TEX_ANISO" value="2"/> 387 + <value name="A6XX_TEX_CUBIC" value="3"/> <!-- a650 only --> 388 + </enum> 389 + 390 + <enum name="a6xx_tex_clamp"> <!-- same as a4xx? --> 391 + <value name="A6XX_TEX_REPEAT" value="0"/> 392 + <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/> 393 + <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/> 394 + <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/> 395 + <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/> 396 + </enum> 397 + 398 + <enum name="a6xx_tex_aniso"> <!-- same as a4xx? --> 399 + <value name="A6XX_TEX_ANISO_1" value="0"/> 400 + <value name="A6XX_TEX_ANISO_2" value="1"/> 401 + <value name="A6XX_TEX_ANISO_4" value="2"/> 402 + <value name="A6XX_TEX_ANISO_8" value="3"/> 403 + <value name="A6XX_TEX_ANISO_16" value="4"/> 404 + </enum> 405 + 406 + <enum name="a6xx_reduction_mode"> 407 + <value name="A6XX_REDUCTION_MODE_AVERAGE" value="0"/> 408 + <value name="A6XX_REDUCTION_MODE_MIN" value="1"/> 409 + <value name="A6XX_REDUCTION_MODE_MAX" value="2"/> 410 + </enum> 411 + 412 + <enum name="a6xx_fast_border_color"> 413 + <!-- R B G A --> 414 + <value name="A6XX_BORDER_COLOR_0_0_0_0" value="0"/> 415 + <value name="A6XX_BORDER_COLOR_0_0_0_1" value="1"/> 416 + <value name="A6XX_BORDER_COLOR_1_1_1_0" value="2"/> 417 + <value name="A6XX_BORDER_COLOR_1_1_1_1" value="3"/> 418 + </enum> 419 + 420 + <enum name="a6xx_tex_swiz"> <!-- same as a4xx? --> 421 + <value name="A6XX_TEX_X" value="0"/> 422 + <value name="A6XX_TEX_Y" value="1"/> 423 + <value name="A6XX_TEX_Z" value="2"/> 424 + <value name="A6XX_TEX_W" value="3"/> 425 + <value name="A6XX_TEX_ZERO" value="4"/> 426 + <value name="A6XX_TEX_ONE" value="5"/> 381 427 </enum> 382 428 383 429 </database>
+48 -131
drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml
··· 120 120 <value name="LRZ_FLUSH" value="38" variants="A5XX-"/> 121 121 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX-"/> 122 122 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX-A6XX"/> 123 - <value name="UNK_40" value="40" variants="A7XX"/> 123 + <value name="LRZ_CACHE_INVALIDATE" value="40" variants="A7XX"/> 124 124 <value name="LRZ_Q_CACHE_INVALIDATE" value="41" variants="A7XX"/> 125 125 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX-"/> 126 126 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX-"/> 127 - <value name="UNK_2C" value="44" variants="A5XX-"/> 128 - <value name="UNK_2D" value="45" variants="A5XX-"/> 127 + <value name="VSC_BINNING_START" value="44" variants="A5XX-"/> 128 + <value name="VSC_BINNING_END" value="45" variants="A5XX-"/> 129 129 130 130 <!-- a6xx events --> 131 131 <doc> ··· 523 523 <!-- 524 524 Seems to set the mode flags which control which CP_SET_DRAW_STATE 525 525 packets are executed, based on their ENABLE_MASK values 526 - 526 + 527 527 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE 528 528 packets w/ ENABLE_MASK & 0x6 to execute immediately 529 529 --> ··· 640 640 <value name="CP_BV_BR_COUNT_OPS" value="0x1b" variants="A7XX-"/> 641 641 <doc> Clears, adds to local, or adds to global timestamp </doc> 642 642 <value name="CP_MODIFY_TIMESTAMP" value="0x1c" variants="A7XX-"/> 643 - <!-- similar to CP_CONTEXT_REG_BUNCH, but discards first two dwords?? --> 644 - <value name="CP_CONTEXT_REG_BUNCH2" value="0x5d" variants="A7XX-"/> 643 + <value name="CP_NON_CONTEXT_REG_BUNCH" value="0x5d" variants="A7XX-"/> 645 644 <doc> 646 645 Write to a scratch memory that is read by CP_REG_TEST with 647 646 SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. ··· 917 918 </reg32> 918 919 919 920 <stripe varset="chip" variants="A5XX-"> 920 - <reg32 offset="4" name="4"> 921 - <bitfield name="INDX_BASE_LO" low="0" high="31"/> 922 - </reg32> 923 - <reg32 offset="5" name="5"> 924 - <bitfield name="INDX_BASE_HI" low="0" high="31"/> 925 - </reg32> 926 921 <reg64 offset="4" name="INDX_BASE" type="address"/> 927 922 <reg32 offset="6" name="6"> 928 923 <!-- max # of elements in index buffer --> ··· 1092 1099 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/> 1093 1100 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/> 1094 1101 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/> 1095 - <bitfield name="GROUP_ID" low="24" high="28" type="uint"/> 1102 + <!-- high bit is 28 until a750: --> 1103 + <bitfield name="GROUP_ID" low="24" high="29" type="uint"/> 1096 1104 </reg32> 1105 + <reg64 offset="1" name="ADDR" type="address"/> 1097 1106 <reg32 offset="1" name="1"> 1098 1107 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/> 1099 1108 </reg32> ··· 1161 1166 </reg32> 1162 1167 <stripe varset="a7xx_abs_mask_mode" variants="NO_ABS_MASK"> 1163 1168 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1164 - <reg32 offset="1" name="1"> 1165 - <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1166 - </reg32> 1167 - <reg32 offset="2" name="2"> 1168 - <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1169 - </reg32> 1169 + <reg64 offset="1" name="BIN_DATA_ADDR" type="address"/> 1170 1170 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1171 - <reg32 offset="3" name="3"> 1172 - <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1173 - </reg32> 1174 - <reg32 offset="4" name="4"> 1175 - <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1176 - </reg32> 1171 + <reg64 offset="3" name="BIN_SIZE_ADDR" type="address"/> 1177 1172 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1178 - <reg32 offset="5" name="5"> 1179 - <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1180 - </reg32> 1181 - <reg32 offset="6" name="6"> 1182 - <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1183 - </reg32> 1173 + <reg64 offset="5" name="BIN_PRIM_STRM" type="address"/> 1184 1174 <!-- 1185 1175 a7xx adds a few more addresses to the end of the pkt 1186 1176 --> ··· 1175 1195 <stripe varset="a7xx_abs_mask_mode" variants="ABS_MASK"> 1176 1196 <reg32 offset="1" name="ABS_MASK"/> 1177 1197 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS --> 1178 - <reg32 offset="2" name="2"> 1179 - <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/> 1180 - </reg32> 1181 - <reg32 offset="3" name="3"> 1182 - <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/> 1183 - </reg32> 1198 + <reg64 offset="2" name="BIN_DATA_ADDR" type="address"/> 1184 1199 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)--> 1185 - <reg32 offset="4" name="4"> 1186 - <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/> 1187 - </reg32> 1188 - <reg32 offset="5" name="5"> 1189 - <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/> 1190 - </reg32> 1200 + <reg64 offset="4" name="BIN_SIZE_ADDR" type="address"/> 1191 1201 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: --> 1192 - <reg32 offset="6" name="6"> 1193 - <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/> 1194 - </reg32> 1195 - <reg32 offset="7" name="7"> 1196 - <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/> 1197 - </reg32> 1202 + <reg64 offset="6" name="BIN_PRIM_STRM" type="address"/> 1198 1203 <!-- 1199 1204 a7xx adds a few more addresses to the end of the pkt 1200 1205 --> ··· 1265 1300 </reg32> 1266 1301 </domain> 1267 1302 1268 - <domain name="CP_REG_TO_MEM" width="32"> 1303 + <domain name="CP_REG_TO_MEM" width="32" prefix="chip"> 1269 1304 <reg32 offset="0" name="0"> 1270 1305 <bitfield name="REG" low="0" high="17" type="hex"/> 1271 1306 <!-- number of registers/dwords copied is max(CNT, 1). --> ··· 1273 1308 <bitfield name="64B" pos="30" type="boolean"/> 1274 1309 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1275 1310 </reg32> 1276 - <reg32 offset="1" name="1"> 1277 - <bitfield name="DEST" low="0" high="31"/> 1278 - </reg32> 1279 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1280 - <bitfield name="DEST_HI" low="0" high="31"/> 1281 - </reg32> 1311 + <stripe varset="chip" variants="A2XX-A4XX"> 1312 + <reg32 offset="1" name="DEST" type="address"/> 1313 + </stripe> 1314 + <stripe varset="chip" variants="A5XX-"> 1315 + <reg64 offset="1" name="DEST" type="address"/> 1316 + </stripe> 1282 1317 </domain> 1283 1318 1284 1319 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32"> ··· 1294 1329 <bitfield name="64B" pos="30" type="boolean"/> 1295 1330 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1296 1331 </reg32> 1297 - <reg32 offset="1" name="1"> 1298 - <bitfield name="DEST" low="0" high="31"/> 1299 - </reg32> 1300 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1301 - <bitfield name="DEST_HI" low="0" high="31"/> 1302 - </reg32> 1332 + <reg64 offset="1" name="DEST" type="waddress"/> 1303 1333 <reg32 offset="3" name="3"> 1304 1334 <bitfield name="OFFSET0" low="0" high="17" type="hex"/> 1305 1335 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/> ··· 1314 1354 <bitfield name="64B" pos="30" type="boolean"/> 1315 1355 <bitfield name="ACCUMULATE" pos="31" type="boolean"/> 1316 1356 </reg32> 1317 - <reg32 offset="1" name="1"> 1318 - <bitfield name="DEST" low="0" high="31"/> 1319 - </reg32> 1320 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1321 - <bitfield name="DEST_HI" low="0" high="31"/> 1322 - </reg32> 1323 - <reg32 offset="3" name="3"> 1324 - <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/> 1325 - </reg32> 1326 - <reg32 offset="4" name="4"> 1327 - <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/> 1328 - </reg32> 1357 + <reg64 offset="1" name="DEST" type="waddress"/> 1358 + <reg64 offset="3" name="OFFSET" type="waddress"/> 1329 1359 </domain> 1330 1360 1331 1361 <domain name="CP_MEM_TO_REG" width="32"> ··· 1328 1378 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 --> 1329 1379 <bitfield name="UNK31" pos="31" type="boolean"/> 1330 1380 </reg32> 1331 - <reg32 offset="1" name="1"> 1332 - <bitfield name="SRC" low="0" high="31"/> 1333 - </reg32> 1334 - <reg32 offset="2" name="2" varset="chip" variants="A5XX-"> 1335 - <bitfield name="SRC_HI" low="0" high="31"/> 1336 - </reg32> 1381 + <stripe varset="chip" variants="A2XX-A4XX"> 1382 + <reg32 offset="1" name="SRC" type="address"/> 1383 + </stripe> 1384 + <stripe varset="chip" variants="A5XX-"> 1385 + <reg64 offset="1" name="SRC" type="address"/> 1386 + </stripe> 1337 1387 </domain> 1338 1388 1339 1389 <domain name="CP_MEM_TO_MEM" width="32"> ··· 1353 1403 <!-- some other kind of wait --> 1354 1404 <bitfield name="UNK31" pos="31" type="boolean"/> 1355 1405 </reg32> 1406 + <reg64 offset="1" name="DST" type="waddress"/> 1407 + <reg64 offset="3" name="SRC_A" type="address"/> 1408 + <reg64 offset="5" name="SRC_B" type="address"/> 1409 + <reg64 offset="7" name="SRC_C" type="address"/> 1356 1410 <!-- 1357 1411 followed by sequence of addresses.. the first is the 1358 1412 destination and the rest are N src addresses which are ··· 1415 1461 </domain> 1416 1462 1417 1463 <domain name="CP_MEM_WRITE" width="32"> 1418 - <reg32 offset="0" name="0"> 1419 - <bitfield name="ADDR_LO" low="0" high="31"/> 1420 - </reg32> 1421 - <reg32 offset="1" name="1"> 1422 - <bitfield name="ADDR_HI" low="0" high="31"/> 1423 - </reg32> 1464 + <stripe varset="chip" variants="A2XX-A4XX"> 1465 + <reg32 offset="0" name="ADDR" type="address"/> 1466 + </stripe> 1467 + <stripe varset="chip" variants="A5XX-"> 1468 + <reg64 offset="0" name="ADDR" type="address"/> 1469 + </stripe> 1424 1470 <!-- followed by the DWORDs to write --> 1425 1471 </domain> 1426 1472 ··· 1472 1518 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1473 1519 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1474 1520 </reg32> 1475 - <reg32 offset="1" name="1"> 1476 - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1477 - </reg32> 1478 - <reg32 offset="2" name="2"> 1479 - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1480 - </reg32> 1521 + <reg64 offset="1" name="POLL_ADDR" type="address"/> 1481 1522 <reg32 offset="3" name="3"> 1482 1523 <bitfield name="REF" low="0" high="31"/> 1483 1524 </reg32> 1484 1525 <reg32 offset="4" name="4"> 1485 1526 <bitfield name="MASK" low="0" high="31"/> 1486 1527 </reg32> 1487 - <reg32 offset="5" name="5"> 1488 - <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/> 1489 - </reg32> 1490 - <reg32 offset="6" name="6"> 1491 - <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/> 1492 - </reg32> 1528 + <reg64 offset="5" name="WRITE_ADDR" type="waddress"/> 1493 1529 <reg32 offset="7" name="7"> 1494 1530 <bitfield name="WRITE_DATA" low="0" high="31"/> 1495 1531 </reg32> ··· 1494 1550 <!-- Reserved for flags, presumably? Unused in FW --> 1495 1551 <bitfield name="RESERVED" low="0" high="31" type="hex"/> 1496 1552 </reg32> 1497 - <reg32 offset="1" name="1"> 1498 - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1499 - </reg32> 1500 - <reg32 offset="2" name="2"> 1501 - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1502 - </reg32> 1553 + <reg64 offset="1" name="POLL_ADDR" type="address"/> 1503 1554 <reg32 offset="3" name="3"> 1504 1555 <bitfield name="REF" low="0" high="31"/> 1505 1556 </reg32> ··· 1512 1573 <bitfield name="POLL" low="4" high="5" type="poll_memory_type"/> 1513 1574 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/> 1514 1575 </reg32> 1515 - <reg32 offset="1" name="1"> 1516 - <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/> 1517 - </reg32> 1518 - <reg32 offset="2" name="2"> 1519 - <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/> 1520 - </reg32> 1576 + <reg64 offset="1" name="POLL_ADDR" type="address"/> 1521 1577 <reg32 offset="3" name="3"> 1522 1578 <bitfield name="REF" low="0" high="31"/> 1523 1579 </reg32> ··· 1646 1712 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for 1647 1713 context switch? 1648 1714 --> 1649 - <reg32 offset="1" name="1"> 1650 - <bitfield name="ADDR_0_LO" low="0" high="31"/> 1651 - </reg32> 1652 - <reg32 offset="2" name="2"> 1653 - <bitfield name="ADDR_0_HI" low="0" high="31"/> 1654 - </reg32> 1715 + <reg64 offset="1" name="ADDR" type="waddress"/> 1655 1716 <reg32 offset="3" name="3"> 1656 1717 <!-- ??? --> 1657 1718 </reg32> ··· 1761 1832 <reg32 offset="0" name="0"> 1762 1833 </reg32> 1763 1834 <stripe varset="chip" variants="A4XX"> 1764 - <reg32 offset="1" name="1"> 1765 - <bitfield name="ADDR" low="0" high="31"/> 1766 - </reg32> 1835 + <reg32 offset="1" name="ADDR" type="address"/> 1767 1836 <reg32 offset="2" name="2"> 1768 1837 <!-- localsize is value minus one: --> 1769 1838 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> ··· 1770 1843 </reg32> 1771 1844 </stripe> 1772 1845 <stripe varset="chip" variants="A5XX-"> 1773 - <reg32 offset="1" name="1"> 1774 - <bitfield name="ADDR_LO" low="0" high="31"/> 1775 - </reg32> 1776 - <reg32 offset="2" name="2"> 1777 - <bitfield name="ADDR_HI" low="0" high="31"/> 1778 - </reg32> 1846 + <reg64 offset="1" name="ADDR" type="address"/> 1779 1847 <reg32 offset="3" name="3"> 1780 1848 <!-- localsize is value minus one: --> 1781 1849 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/> ··· 2083 2161 </doc> 2084 2162 </value> 2085 2163 </enum> 2086 - <reg32 offset="0" name="0"> 2087 - <bitfield name="ADDR_LO" low="0" high="31"/> 2088 - </reg32> 2089 - <reg32 offset="1" name="1"> 2090 - <bitfield name="ADDR_HI" low="0" high="31"/> 2091 - </reg32> 2164 + <reg64 offset="0" name="ADDR" type="address"/> 2092 2165 <reg32 offset="2" name="2"> 2093 2166 <bitfield name="DWORDS" low="0" high="19" type="uint"/> 2094 2167 <bitfield name="TYPE" low="20" high="21" type="amble_type"/>