Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dmaengine: dw-edma: Add non-LL mode
AMD MDB IP supports Linked List (LL) mode as well as non-LL mode.
The current code does not have the mechanisms to enable the
DMA transactions using the non-LL mode. The following two cases
are added with this patch:
- For the AMD (Xilinx) only, when a valid physical base address of
the device side DDR is not configured, then the IP can still be
used in non-LL mode. For all the channels DMA transactions will
be using the non-LL mode only. This, the default non-LL mode,
is not applicable for Synopsys IP with the current code addition.
- If the default mode is LL-mode, for both AMD (Xilinx) and Synosys,
and if user wants to use non-LL mode then user can do so via
configuring the peripheral_config param of dma_slave_config.
Signed-off-by: Devendra K Verma <devendra.verma@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/20260318070403.1634706-3-devendra.verma@amd.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Devendra K Verma
and committed by
Vinod Koul
b7560798
14eb9a1d
+143
-15
+46
-1
drivers/dma/dw-edma/dw-edma-core.c
+46
-1
drivers/dma/dw-edma/dw-edma-core.c
···
223
223
struct dma_slave_config *config)
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{
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struct dw_edma_chan *chan = dchan2dw_edma_chan(dchan);
226
+
bool cfg_non_ll;
227
+
int non_ll = 0;
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+
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+
chan->non_ll = false;
230
+
if (chan->dw->chip->mf == EDMA_MF_HDMA_NATIVE) {
231
+
if (config->peripheral_config &&
232
+
config->peripheral_size != sizeof(int)) {
233
+
dev_err(dchan->device->dev,
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+
"config param peripheral size mismatch\n");
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+
return -EINVAL;
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+
}
237
+
238
+
/*
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+
* When there is no valid LLP base address available then the
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+
* default DMA ops will use the non-LL mode.
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+
*
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+
* Cases where LL mode is enabled and client wants to use the
243
+
* non-LL mode then also client can do so via providing the
244
+
* peripheral_config param.
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+
*/
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+
cfg_non_ll = chan->dw->chip->cfg_non_ll;
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+
if (config->peripheral_config) {
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+
non_ll = *(int *)config->peripheral_config;
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+
250
+
if (cfg_non_ll && !non_ll) {
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+
dev_err(dchan->device->dev, "invalid configuration\n");
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+
return -EINVAL;
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+
}
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+
}
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+
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+
if (cfg_non_ll || non_ll)
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+
chan->non_ll = true;
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+
} else if (config->peripheral_config) {
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+
dev_err(dchan->device->dev,
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"peripheral config param applicable only for HDMA\n");
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+
return -EINVAL;
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+
}
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memcpy(&chan->config, config, sizeof(*config));
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chan->configured = true;
···
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struct dw_edma_desc *desc;
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u64 src_addr, dst_addr;
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size_t fsz = 0;
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+
u32 bursts_max;
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u32 cnt = 0;
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int i;
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364
···
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return NULL;
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}
455
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+
/*
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+
* For non-LL mode, only a single burst can be handled
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+
* in a single chunk unlike LL mode where multiple bursts
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+
* can be configured in a single chunk.
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+
*/
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bursts_max = chan->non_ll ? 1 : chan->ll_max;
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+
456
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desc = dw_edma_alloc_desc(chan);
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if (unlikely(!desc))
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goto err_alloc;
···
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if (xfer->type == EDMA_XFER_SCATTER_GATHER && !sg)
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break;
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-
if (chunk->bursts_alloc == chan->ll_max) {
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+
if (chunk->bursts_alloc == bursts_max) {
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chunk = dw_edma_alloc_chunk(desc);
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if (unlikely(!chunk))
501
456
goto err_alloc;
+1
drivers/dma/dw-edma/dw-edma-core.h
+1
drivers/dma/dw-edma/dw-edma-core.h
+31
-13
drivers/dma/dw-edma/dw-edma-pcie.c
+31
-13
drivers/dma/dw-edma/dw-edma-pcie.c
···
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pdata->devmem_phys_off = off;
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}
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+
static u64 dw_edma_get_phys_addr(struct pci_dev *pdev,
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struct dw_edma_pcie_data *pdata,
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+
enum pci_barno bar)
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+
{
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+
if (pdev->vendor == PCI_VENDOR_ID_XILINX)
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return pdata->devmem_phys_off;
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return pci_bus_address(pdev, bar);
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+
}
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+
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static int dw_edma_pcie_probe(struct pci_dev *pdev,
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const struct pci_device_id *pid)
300
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{
···
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struct dw_edma_chip *chip;
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int err, nr_irqs;
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int i, mask;
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+
bool non_ll = false;
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struct dw_edma_pcie_data *vsec_data __free(kfree) =
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kmalloc_obj(*vsec_data);
···
339
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/*
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* There is no valid address found for the LL memory
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-
* space on the device side.
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+
* space on the device side. In the absence of LL base
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+
* address use the non-LL mode or simple mode supported by
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+
* the HDMA IP.
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*/
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if (vsec_data->devmem_phys_off == DW_PCIE_XILINX_MDB_INVALID_ADDR)
345
-
return -ENOMEM;
337
+
non_ll = true;
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/*
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* Configure the channel LL and data blocks if number of
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* channels enabled in VSEC capability are more than the
350
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* channels configured in xilinx_mdb_data.
351
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*/
352
-
dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,
353
-
DW_PCIE_XILINX_MDB_LL_OFF_GAP,
354
-
DW_PCIE_XILINX_MDB_LL_SIZE,
355
-
DW_PCIE_XILINX_MDB_DT_OFF_GAP,
356
-
DW_PCIE_XILINX_MDB_DT_SIZE);
344
+
if (!non_ll)
345
+
dw_edma_set_chan_region_offset(vsec_data, BAR_2, 0,
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+
DW_PCIE_XILINX_MDB_LL_OFF_GAP,
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+
DW_PCIE_XILINX_MDB_LL_SIZE,
348
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DW_PCIE_XILINX_MDB_DT_OFF_GAP,
349
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DW_PCIE_XILINX_MDB_DT_SIZE);
357
350
}
358
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/* Mapping PCI BAR regions */
···
404
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chip->mf = vsec_data->mf;
405
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chip->nr_irqs = nr_irqs;
406
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chip->ops = &dw_edma_pcie_plat_ops;
394
+
chip->cfg_non_ll = non_ll;
407
395
408
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chip->ll_wr_cnt = vsec_data->wr_ch_cnt;
409
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chip->ll_rd_cnt = vsec_data->rd_ch_cnt;
···
413
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if (!chip->reg_base)
414
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return -ENOMEM;
415
401
416
-
for (i = 0; i < chip->ll_wr_cnt; i++) {
402
+
for (i = 0; i < chip->ll_wr_cnt && !non_ll; i++) {
417
403
struct dw_edma_region *ll_region = &chip->ll_region_wr[i];
418
404
struct dw_edma_region *dt_region = &chip->dt_region_wr[i];
419
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struct dw_edma_block *ll_block = &vsec_data->ll_wr[i];
···
424
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return -ENOMEM;
425
411
426
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ll_region->vaddr.io += ll_block->off;
427
-
ll_region->paddr = pci_bus_address(pdev, ll_block->bar);
413
+
ll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,
414
+
ll_block->bar);
428
415
ll_region->paddr += ll_block->off;
429
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ll_region->sz = ll_block->sz;
430
417
···
434
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return -ENOMEM;
435
420
436
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dt_region->vaddr.io += dt_block->off;
437
-
dt_region->paddr = pci_bus_address(pdev, dt_block->bar);
422
+
dt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,
423
+
dt_block->bar);
438
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dt_region->paddr += dt_block->off;
439
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dt_region->sz = dt_block->sz;
440
426
}
441
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442
-
for (i = 0; i < chip->ll_rd_cnt; i++) {
428
+
for (i = 0; i < chip->ll_rd_cnt && !non_ll; i++) {
443
429
struct dw_edma_region *ll_region = &chip->ll_region_rd[i];
444
430
struct dw_edma_region *dt_region = &chip->dt_region_rd[i];
445
431
struct dw_edma_block *ll_block = &vsec_data->ll_rd[i];
···
451
435
return -ENOMEM;
452
436
453
437
ll_region->vaddr.io += ll_block->off;
454
-
ll_region->paddr = pci_bus_address(pdev, ll_block->bar);
438
+
ll_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,
439
+
ll_block->bar);
455
440
ll_region->paddr += ll_block->off;
456
441
ll_region->sz = ll_block->sz;
457
442
···
461
444
return -ENOMEM;
462
445
463
446
dt_region->vaddr.io += dt_block->off;
464
-
dt_region->paddr = pci_bus_address(pdev, dt_block->bar);
447
+
dt_region->paddr = dw_edma_get_phys_addr(pdev, vsec_data,
448
+
dt_block->bar);
465
449
dt_region->paddr += dt_block->off;
466
450
dt_region->sz = dt_block->sz;
467
451
}
+63
-1
drivers/dma/dw-edma/dw-hdma-v0-core.c
+63
-1
drivers/dma/dw-edma/dw-hdma-v0-core.c
···
225
225
readl(chunk->ll_region.vaddr.io);
226
226
}
227
227
228
-
static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
228
+
static void dw_hdma_v0_core_ll_start(struct dw_edma_chunk *chunk, bool first)
229
229
{
230
230
struct dw_edma_chan *chan = chunk->chan;
231
231
struct dw_edma *dw = chan->dw;
···
261
261
262
262
/* Doorbell */
263
263
SET_CH_32(dw, chan->dir, chan->id, doorbell, HDMA_V0_DOORBELL_START);
264
+
}
265
+
266
+
static void dw_hdma_v0_core_non_ll_start(struct dw_edma_chunk *chunk)
267
+
{
268
+
struct dw_edma_chan *chan = chunk->chan;
269
+
struct dw_edma *dw = chan->dw;
270
+
struct dw_edma_burst *child;
271
+
u32 val;
272
+
273
+
child = list_first_entry_or_null(&chunk->burst->list,
274
+
struct dw_edma_burst, list);
275
+
if (!child)
276
+
return;
277
+
278
+
SET_CH_32(dw, chan->dir, chan->id, ch_en, HDMA_V0_CH_EN);
279
+
280
+
/* Source address */
281
+
SET_CH_32(dw, chan->dir, chan->id, sar.lsb,
282
+
lower_32_bits(child->sar));
283
+
SET_CH_32(dw, chan->dir, chan->id, sar.msb,
284
+
upper_32_bits(child->sar));
285
+
286
+
/* Destination address */
287
+
SET_CH_32(dw, chan->dir, chan->id, dar.lsb,
288
+
lower_32_bits(child->dar));
289
+
SET_CH_32(dw, chan->dir, chan->id, dar.msb,
290
+
upper_32_bits(child->dar));
291
+
292
+
/* Transfer size */
293
+
SET_CH_32(dw, chan->dir, chan->id, transfer_size, child->sz);
294
+
295
+
/* Interrupt setup */
296
+
val = GET_CH_32(dw, chan->dir, chan->id, int_setup) |
297
+
HDMA_V0_STOP_INT_MASK |
298
+
HDMA_V0_ABORT_INT_MASK |
299
+
HDMA_V0_LOCAL_STOP_INT_EN |
300
+
HDMA_V0_LOCAL_ABORT_INT_EN;
301
+
302
+
if (!(dw->chip->flags & DW_EDMA_CHIP_LOCAL)) {
303
+
val |= HDMA_V0_REMOTE_STOP_INT_EN |
304
+
HDMA_V0_REMOTE_ABORT_INT_EN;
305
+
}
306
+
307
+
SET_CH_32(dw, chan->dir, chan->id, int_setup, val);
308
+
309
+
/* Channel control setup */
310
+
val = GET_CH_32(dw, chan->dir, chan->id, control1);
311
+
val &= ~HDMA_V0_LINKLIST_EN;
312
+
SET_CH_32(dw, chan->dir, chan->id, control1, val);
313
+
314
+
SET_CH_32(dw, chan->dir, chan->id, doorbell,
315
+
HDMA_V0_DOORBELL_START);
316
+
}
317
+
318
+
static void dw_hdma_v0_core_start(struct dw_edma_chunk *chunk, bool first)
319
+
{
320
+
struct dw_edma_chan *chan = chunk->chan;
321
+
322
+
if (chan->non_ll)
323
+
dw_hdma_v0_core_non_ll_start(chunk);
324
+
else
325
+
dw_hdma_v0_core_ll_start(chunk, first);
264
326
}
265
327
266
328
static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan)
+1
drivers/dma/dw-edma/dw-hdma-v0-regs.h
+1
drivers/dma/dw-edma/dw-hdma-v0-regs.h