tjh.dev / kernel
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clk: imx: pll14xx: Add 208 MHz and 416 MHz entries for PLL1416x

The PLL1416x is used to implement SYS_PLL3 on i.MX8MP and can be used
to drive CLKOUTn clock. Add 208 MHz and 416 MHz entries to the PLL so
they can be generated by the PLL and used to produce e.g. 13 MHz or
26 MHz on CLKOUTn output.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20241112013805.333798-1-marex@denx.de
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>

authored by

Marek Vasut and committed by
Abel Vesa b7f67545 a9b7c84d

+2
+2
drivers/clk/imx/clk-pll14xx.c
··· 56 56 PLL_1416X_RATE(700000000U, 350, 3, 2), 57 57 PLL_1416X_RATE(640000000U, 320, 3, 2), 58 58 PLL_1416X_RATE(600000000U, 300, 3, 2), 59 + PLL_1416X_RATE(416000000U, 208, 3, 2), 59 60 PLL_1416X_RATE(320000000U, 160, 3, 2), 61 + PLL_1416X_RATE(208000000U, 208, 3, 3), 60 62 }; 61 63 62 64 static const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] = {