Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: camcc-sm8450: Add SM8475 support
Add support to the SM8475 camera clock controller by extending the
SM8450 camera clock controller, which is almost identical but has some
minor differences.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-11-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Danila Tikhonov
and committed by
Bjorn Andersson
b815ccf5
f7f4afdd
+285
-11
+1
-1
drivers/clk/qcom/Kconfig
+1
-1
drivers/clk/qcom/Kconfig
···
857
857
depends on ARM64 || COMPILE_TEST
858
858
select SM_GCC_8450
859
859
help
860
-
Support for the camera clock controller on SM8450 devices.
860
+
Support for the camera clock controller on SM8450 or SM8475 devices.
861
861
Say Y if you want to support camera devices and camera functionality.
862
862
863
863
config SM_CAMCC_8550
+284
-10
drivers/clk/qcom/camcc-sm8450.c
+284
-10
drivers/clk/qcom/camcc-sm8450.c
···
54
54
{ 864000000, 1056000000, 0 },
55
55
};
56
56
57
+
static const struct pll_vco rivian_ole_vco[] = {
58
+
{ 864000000, 1075000000, 0 },
59
+
};
60
+
57
61
static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
58
62
59
63
static const struct alpha_pll_config cam_cc_pll0_config = {
···
68
64
.config_ctl_hi1_val = 0x32aa299c,
69
65
.user_ctl_val = 0x00008400,
70
66
.user_ctl_hi_val = 0x00000805,
67
+
};
68
+
69
+
static const struct alpha_pll_config sm8475_cam_cc_pll0_config = {
70
+
.l = 0x3e,
71
+
.alpha = 0x8000,
72
+
.config_ctl_val = 0x20485699,
73
+
.config_ctl_hi_val = 0x00182261,
74
+
.config_ctl_hi1_val = 0x82aa299c,
75
+
.test_ctl_val = 0x00000000,
76
+
.test_ctl_hi_val = 0x00000003,
77
+
.test_ctl_hi1_val = 0x00009000,
78
+
.test_ctl_hi2_val = 0x00000034,
79
+
.user_ctl_val = 0x00008400,
80
+
.user_ctl_hi_val = 0x00000005,
71
81
};
72
82
73
83
static struct clk_alpha_pll cam_cc_pll0 = {
···
102
84
static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
103
85
{ 0x1, 2 },
104
86
{ }
87
+
};
88
+
89
+
static struct clk_init_data sm8475_cam_cc_pll0_out_even_init = {
90
+
.name = "cam_cc_pll0_out_even",
91
+
.parent_hws = (const struct clk_hw*[]) {
92
+
&cam_cc_pll0.clkr.hw,
93
+
},
94
+
.num_parents = 1,
95
+
.flags = CLK_SET_RATE_PARENT,
96
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
105
97
};
106
98
107
99
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
···
135
107
static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
136
108
{ 0x2, 3 },
137
109
{ }
110
+
};
111
+
112
+
static struct clk_init_data sm8475_cam_cc_pll0_out_odd_init = {
113
+
.name = "cam_cc_pll0_out_odd",
114
+
.parent_hws = (const struct clk_hw*[]) {
115
+
&cam_cc_pll0.clkr.hw,
116
+
},
117
+
.num_parents = 1,
118
+
.flags = CLK_SET_RATE_PARENT,
119
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
138
120
};
139
121
140
122
static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
···
175
137
.user_ctl_hi_val = 0x00000805,
176
138
};
177
139
140
+
static const struct alpha_pll_config sm8475_cam_cc_pll1_config = {
141
+
.l = 0x25,
142
+
.alpha = 0xeaaa,
143
+
.config_ctl_val = 0x20485699,
144
+
.config_ctl_hi_val = 0x00182261,
145
+
.config_ctl_hi1_val = 0x82aa299c,
146
+
.test_ctl_val = 0x00000000,
147
+
.test_ctl_hi_val = 0x00000003,
148
+
.test_ctl_hi1_val = 0x00009000,
149
+
.test_ctl_hi2_val = 0x00000034,
150
+
.user_ctl_val = 0x00000400,
151
+
.user_ctl_hi_val = 0x00000005,
152
+
};
153
+
178
154
static struct clk_alpha_pll cam_cc_pll1 = {
179
155
.offset = 0x1000,
180
156
.vco_table = lucid_evo_vco,
···
207
155
static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
208
156
{ 0x1, 2 },
209
157
{ }
158
+
};
159
+
160
+
static struct clk_init_data sm8475_cam_cc_pll1_out_even_init = {
161
+
.name = "cam_cc_pll1_out_even",
162
+
.parent_hws = (const struct clk_hw*[]) {
163
+
&cam_cc_pll1.clkr.hw,
164
+
},
165
+
.num_parents = 1,
166
+
.flags = CLK_SET_RATE_PARENT,
167
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
210
168
};
211
169
212
170
static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
···
245
183
.config_ctl_hi1_val = 0x00000217,
246
184
};
247
185
186
+
static const struct alpha_pll_config sm8475_cam_cc_pll2_config = {
187
+
.l = 0x32,
188
+
.alpha = 0x0,
189
+
.config_ctl_val = 0x10000030,
190
+
.config_ctl_hi_val = 0x80890263,
191
+
.config_ctl_hi1_val = 0x00000217,
192
+
.user_ctl_val = 0x00000001,
193
+
.user_ctl_hi_val = 0x00000000,
194
+
};
195
+
248
196
static struct clk_alpha_pll cam_cc_pll2 = {
249
197
.offset = 0x2000,
250
198
.vco_table = rivian_evo_vco,
···
280
208
.user_ctl_hi_val = 0x00000805,
281
209
};
282
210
211
+
static const struct alpha_pll_config sm8475_cam_cc_pll3_config = {
212
+
.l = 0x2d,
213
+
.alpha = 0x0,
214
+
.config_ctl_val = 0x20485699,
215
+
.config_ctl_hi_val = 0x00182261,
216
+
.config_ctl_hi1_val = 0x82aa299c,
217
+
.test_ctl_val = 0x00000000,
218
+
.test_ctl_hi_val = 0x00000003,
219
+
.test_ctl_hi1_val = 0x00009000,
220
+
.test_ctl_hi2_val = 0x00000034,
221
+
.user_ctl_val = 0x00000400,
222
+
.user_ctl_hi_val = 0x00000005,
223
+
};
224
+
283
225
static struct clk_alpha_pll cam_cc_pll3 = {
284
226
.offset = 0x3000,
285
227
.vco_table = lucid_evo_vco,
···
312
226
static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
313
227
{ 0x1, 2 },
314
228
{ }
229
+
};
230
+
231
+
static struct clk_init_data sm8475_cam_cc_pll3_out_even_init = {
232
+
.name = "cam_cc_pll3_out_even",
233
+
.parent_hws = (const struct clk_hw*[]) {
234
+
&cam_cc_pll3.clkr.hw,
235
+
},
236
+
.num_parents = 1,
237
+
.flags = CLK_SET_RATE_PARENT,
238
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
315
239
};
316
240
317
241
static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
···
352
256
.user_ctl_hi_val = 0x00000805,
353
257
};
354
258
259
+
static const struct alpha_pll_config sm8475_cam_cc_pll4_config = {
260
+
.l = 0x2d,
261
+
.alpha = 0x0,
262
+
.config_ctl_val = 0x20485699,
263
+
.config_ctl_hi_val = 0x00182261,
264
+
.config_ctl_hi1_val = 0x82aa299c,
265
+
.test_ctl_val = 0x00000000,
266
+
.test_ctl_hi_val = 0x00000003,
267
+
.test_ctl_hi1_val = 0x00009000,
268
+
.test_ctl_hi2_val = 0x00000034,
269
+
.user_ctl_val = 0x00000400,
270
+
.user_ctl_hi_val = 0x00000005,
271
+
};
272
+
355
273
static struct clk_alpha_pll cam_cc_pll4 = {
356
274
.offset = 0x4000,
357
275
.vco_table = lucid_evo_vco,
···
384
274
static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
385
275
{ 0x1, 2 },
386
276
{ }
277
+
};
278
+
279
+
static struct clk_init_data sm8475_cam_cc_pll4_out_even_init = {
280
+
.name = "cam_cc_pll4_out_even",
281
+
.parent_hws = (const struct clk_hw*[]) {
282
+
&cam_cc_pll4.clkr.hw,
283
+
},
284
+
.num_parents = 1,
285
+
.flags = CLK_SET_RATE_PARENT,
286
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
387
287
};
388
288
389
289
static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
···
424
304
.user_ctl_hi_val = 0x00000805,
425
305
};
426
306
307
+
static const struct alpha_pll_config sm8475_cam_cc_pll5_config = {
308
+
.l = 0x2d,
309
+
.alpha = 0x0,
310
+
.config_ctl_val = 0x20485699,
311
+
.config_ctl_hi_val = 0x00182261,
312
+
.config_ctl_hi1_val = 0x82aa299c,
313
+
.test_ctl_val = 0x00000000,
314
+
.test_ctl_hi_val = 0x00000003,
315
+
.test_ctl_hi1_val = 0x00009000,
316
+
.test_ctl_hi2_val = 0x00000034,
317
+
.user_ctl_val = 0x00000400,
318
+
.user_ctl_hi_val = 0x00000005,
319
+
};
320
+
427
321
static struct clk_alpha_pll cam_cc_pll5 = {
428
322
.offset = 0x5000,
429
323
.vco_table = lucid_evo_vco,
···
456
322
static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
457
323
{ 0x1, 2 },
458
324
{ }
325
+
};
326
+
327
+
static struct clk_init_data sm8475_cam_cc_pll5_out_even_init = {
328
+
.name = "cam_cc_pll5_out_even",
329
+
.parent_hws = (const struct clk_hw*[]) {
330
+
&cam_cc_pll5.clkr.hw,
331
+
},
332
+
.num_parents = 1,
333
+
.flags = CLK_SET_RATE_PARENT,
334
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
459
335
};
460
336
461
337
static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
···
496
352
.user_ctl_hi_val = 0x00000805,
497
353
};
498
354
355
+
static const struct alpha_pll_config sm8475_cam_cc_pll6_config = {
356
+
.l = 0x2d,
357
+
.alpha = 0x0,
358
+
.config_ctl_val = 0x20485699,
359
+
.config_ctl_hi_val = 0x00182261,
360
+
.config_ctl_hi1_val = 0x82aa299c,
361
+
.test_ctl_val = 0x00000000,
362
+
.test_ctl_hi_val = 0x00000003,
363
+
.test_ctl_hi1_val = 0x00009000,
364
+
.test_ctl_hi2_val = 0x00000034,
365
+
.user_ctl_val = 0x00000400,
366
+
.user_ctl_hi_val = 0x00000005,
367
+
};
368
+
499
369
static struct clk_alpha_pll cam_cc_pll6 = {
500
370
.offset = 0x6000,
501
371
.vco_table = lucid_evo_vco,
···
528
370
static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
529
371
{ 0x1, 2 },
530
372
{ }
373
+
};
374
+
375
+
static struct clk_init_data sm8475_cam_cc_pll6_out_even_init = {
376
+
.name = "cam_cc_pll6_out_even",
377
+
.parent_hws = (const struct clk_hw*[]) {
378
+
&cam_cc_pll6.clkr.hw,
379
+
},
380
+
.num_parents = 1,
381
+
.flags = CLK_SET_RATE_PARENT,
382
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
531
383
};
532
384
533
385
static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
···
568
400
.user_ctl_hi_val = 0x00000805,
569
401
};
570
402
403
+
static const struct alpha_pll_config sm8475_cam_cc_pll7_config = {
404
+
.l = 0x2d,
405
+
.alpha = 0x0,
406
+
.config_ctl_val = 0x20485699,
407
+
.config_ctl_hi_val = 0x00182261,
408
+
.config_ctl_hi1_val = 0x82aa299c,
409
+
.test_ctl_val = 0x00000000,
410
+
.test_ctl_hi_val = 0x00000003,
411
+
.test_ctl_hi1_val = 0x00009000,
412
+
.test_ctl_hi2_val = 0x00000034,
413
+
.user_ctl_val = 0x00000400,
414
+
.user_ctl_hi_val = 0x00000005,
415
+
};
416
+
571
417
static struct clk_alpha_pll cam_cc_pll7 = {
572
418
.offset = 0x7000,
573
419
.vco_table = lucid_evo_vco,
···
600
418
static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
601
419
{ 0x1, 2 },
602
420
{ }
421
+
};
422
+
423
+
static struct clk_init_data sm8475_cam_cc_pll7_out_even_init = {
424
+
.name = "cam_cc_pll7_out_even",
425
+
.parent_hws = (const struct clk_hw*[]) {
426
+
&cam_cc_pll7.clkr.hw,
427
+
},
428
+
.num_parents = 1,
429
+
.flags = CLK_SET_RATE_PARENT,
430
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
603
431
};
604
432
605
433
static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
···
640
448
.user_ctl_hi_val = 0x00000805,
641
449
};
642
450
451
+
static const struct alpha_pll_config sm8475_cam_cc_pll8_config = {
452
+
.l = 0x32,
453
+
.alpha = 0x0,
454
+
.config_ctl_val = 0x20485699,
455
+
.config_ctl_hi_val = 0x00182261,
456
+
.config_ctl_hi1_val = 0x82aa299c,
457
+
.test_ctl_val = 0x00000000,
458
+
.test_ctl_hi_val = 0x00000003,
459
+
.test_ctl_hi1_val = 0x00009000,
460
+
.test_ctl_hi2_val = 0x00000034,
461
+
.user_ctl_val = 0x00000400,
462
+
.user_ctl_hi_val = 0x00000005,
463
+
};
464
+
643
465
static struct clk_alpha_pll cam_cc_pll8 = {
644
466
.offset = 0x8000,
645
467
.vco_table = lucid_evo_vco,
···
672
466
static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
673
467
{ 0x1, 2 },
674
468
{ }
469
+
};
470
+
471
+
static struct clk_init_data sm8475_cam_cc_pll8_out_even_init = {
472
+
.name = "cam_cc_pll8_out_even",
473
+
.parent_hws = (const struct clk_hw*[]) {
474
+
&cam_cc_pll8.clkr.hw,
475
+
},
476
+
.num_parents = 1,
477
+
.flags = CLK_SET_RATE_PARENT,
478
+
.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
675
479
};
676
480
677
481
static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
···
3033
2817
3034
2818
static const struct of_device_id cam_cc_sm8450_match_table[] = {
3035
2819
{ .compatible = "qcom,sm8450-camcc" },
2820
+
{ .compatible = "qcom,sm8475-camcc" },
3036
2821
{ }
3037
2822
};
3038
2823
MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
···
3046
2829
if (IS_ERR(regmap))
3047
2830
return PTR_ERR(regmap);
3048
2831
3049
-
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
3050
-
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
3051
-
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
3052
-
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
3053
-
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
3054
-
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
3055
-
clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
3056
-
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
3057
-
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
2832
+
if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) {
2833
+
/* Update CAMCC PLL0 */
2834
+
cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2835
+
cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2836
+
cam_cc_pll0_out_even.clkr.hw.init = &sm8475_cam_cc_pll0_out_even_init;
2837
+
cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2838
+
cam_cc_pll0_out_odd.clkr.hw.init = &sm8475_cam_cc_pll0_out_odd_init;
2839
+
2840
+
/* Update CAMCC PLL1 */
2841
+
cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2842
+
cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2843
+
cam_cc_pll1_out_even.clkr.hw.init = &sm8475_cam_cc_pll1_out_even_init;
2844
+
2845
+
/* Update CAMCC PLL2 */
2846
+
cam_cc_pll2.vco_table = rivian_ole_vco;
2847
+
2848
+
/* Update CAMCC PLL3 */
2849
+
cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2850
+
cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2851
+
cam_cc_pll3_out_even.clkr.hw.init = &sm8475_cam_cc_pll3_out_even_init;
2852
+
2853
+
/* Update CAMCC PLL4 */
2854
+
cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2855
+
cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2856
+
cam_cc_pll4_out_even.clkr.hw.init = &sm8475_cam_cc_pll4_out_even_init;
2857
+
2858
+
/* Update CAMCC PLL5 */
2859
+
cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2860
+
cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2861
+
cam_cc_pll5_out_even.clkr.hw.init = &sm8475_cam_cc_pll5_out_even_init;
2862
+
2863
+
/* Update CAMCC PLL6 */
2864
+
cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2865
+
cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2866
+
cam_cc_pll6_out_even.clkr.hw.init = &sm8475_cam_cc_pll6_out_even_init;
2867
+
2868
+
/* Update CAMCC PLL7 */
2869
+
cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2870
+
cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2871
+
cam_cc_pll7_out_even.clkr.hw.init = &sm8475_cam_cc_pll7_out_even_init;
2872
+
2873
+
/* Update CAMCC PLL8 */
2874
+
cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2875
+
cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
2876
+
cam_cc_pll8_out_even.clkr.hw.init = &sm8475_cam_cc_pll8_out_even_init;
2877
+
2878
+
clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_config);
2879
+
clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_config);
2880
+
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_config);
2881
+
clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_config);
2882
+
clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_config);
2883
+
clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_config);
2884
+
clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_config);
2885
+
clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_config);
2886
+
clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_config);
2887
+
} else {
2888
+
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
2889
+
clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
2890
+
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
2891
+
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
2892
+
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
2893
+
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
2894
+
clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config);
2895
+
clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config);
2896
+
clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config);
2897
+
}
3058
2898
3059
2899
return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap);
3060
2900
}
···
3126
2852
3127
2853
module_platform_driver(cam_cc_sm8450_driver);
3128
2854
3129
-
MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
2855
+
MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver");
3130
2856
MODULE_LICENSE("GPL");