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clk: qcom: videocc-sm8450: Add SM8475 support

Add support to the SM8475 video clock controller by extending the
SM8450 video clock controller, which is almost identical but has some
minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-9-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Danila Tikhonov and committed by
Bjorn Andersson
f7f4afdd 0b71e3b0

+46 -4
+1 -1
drivers/clk/qcom/Kconfig
··· 1285 1285 select QCOM_GDSC 1286 1286 help 1287 1287 Support for the video clock controller on Qualcomm Technologies, Inc. 1288 - SM8450 devices. 1288 + SM8450 or SM8475 devices. 1289 1289 Say Y if you want to support video devices and functionality such as 1290 1290 video encode/decode. 1291 1291 endif
+45 -3
drivers/clk/qcom/videocc-sm8450.c
··· 46 46 .user_ctl_hi_val = 0x00000805, 47 47 }; 48 48 49 + static const struct alpha_pll_config sm8475_video_cc_pll0_config = { 50 + /* .l includes CAL_L_VAL, L_VAL fields */ 51 + .l = 0x1e, 52 + .alpha = 0x0, 53 + .config_ctl_val = 0x20485699, 54 + .config_ctl_hi_val = 0x00182261, 55 + .config_ctl_hi1_val = 0x82aa299c, 56 + .test_ctl_val = 0x00000000, 57 + .test_ctl_hi_val = 0x00000003, 58 + .test_ctl_hi1_val = 0x00009000, 59 + .test_ctl_hi2_val = 0x00000034, 60 + .user_ctl_val = 0x00000000, 61 + .user_ctl_hi_val = 0x00000005, 62 + }; 63 + 49 64 static struct clk_alpha_pll video_cc_pll0 = { 50 65 .offset = 0x0, 51 66 .vco_table = lucid_evo_vco, ··· 87 72 .config_ctl_hi1_val = 0x32aa299c, 88 73 .user_ctl_val = 0x00000000, 89 74 .user_ctl_hi_val = 0x00000805, 75 + }; 76 + 77 + static const struct alpha_pll_config sm8475_video_cc_pll1_config = { 78 + /* .l includes CAL_L_VAL, L_VAL fields */ 79 + .l = 0x2b, 80 + .alpha = 0xc000, 81 + .config_ctl_val = 0x20485699, 82 + .config_ctl_hi_val = 0x00182261, 83 + .config_ctl_hi1_val = 0x82aa299c, 84 + .test_ctl_val = 0x00000000, 85 + .test_ctl_hi_val = 0x00000003, 86 + .test_ctl_hi1_val = 0x00009000, 87 + .test_ctl_hi2_val = 0x00000034, 88 + .user_ctl_val = 0x00000000, 89 + .user_ctl_hi_val = 0x00000005, 90 90 }; 91 91 92 92 static struct clk_alpha_pll video_cc_pll1 = { ··· 427 397 428 398 static const struct of_device_id video_cc_sm8450_match_table[] = { 429 399 { .compatible = "qcom,sm8450-videocc" }, 400 + { .compatible = "qcom,sm8475-videocc" }, 430 401 { } 431 402 }; 432 403 MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); ··· 451 420 return PTR_ERR(regmap); 452 421 } 453 422 454 - clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 455 - clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 423 + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { 424 + /* Update VideoCC PLL0 */ 425 + video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 426 + 427 + /* Update VideoCC PLL1 */ 428 + video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; 429 + 430 + clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll0_config); 431 + clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll1_config); 432 + } else { 433 + clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config); 434 + clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config); 435 + } 456 436 457 437 /* Keep some clocks always-on */ 458 438 qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ ··· 487 445 488 446 module_platform_driver(video_cc_sm8450_driver); 489 447 490 - MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver"); 448 + MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver"); 491 449 MODULE_LICENSE("GPL");