Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: videocc-sm8450: Add SM8475 support
Add support to the SM8475 video clock controller by extending the
SM8450 video clock controller, which is almost identical but has some
minor differences.
Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240818204348.197788-9-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Danila Tikhonov
and committed by
Bjorn Andersson
f7f4afdd
0b71e3b0
+46
-4
+1
-1
drivers/clk/qcom/Kconfig
+1
-1
drivers/clk/qcom/Kconfig
···
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select QCOM_GDSC
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help
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Support for the video clock controller on Qualcomm Technologies, Inc.
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-
SM8450 devices.
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SM8450 or SM8475 devices.
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Say Y if you want to support video devices and functionality such as
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video encode/decode.
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endif
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-3
drivers/clk/qcom/videocc-sm8450.c
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-3
drivers/clk/qcom/videocc-sm8450.c
···
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_video_cc_pll0_config = {
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/* .l includes CAL_L_VAL, L_VAL fields */
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.l = 0x1e,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000005,
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};
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+
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static struct clk_alpha_pll video_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_evo_vco,
···
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000805,
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};
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static const struct alpha_pll_config sm8475_video_cc_pll1_config = {
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/* .l includes CAL_L_VAL, L_VAL fields */
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.l = 0x2b,
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.alpha = 0xc000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x82aa299c,
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.test_ctl_val = 0x00000000,
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.test_ctl_hi_val = 0x00000003,
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.test_ctl_hi1_val = 0x00009000,
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.test_ctl_hi2_val = 0x00000034,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00000005,
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};
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static struct clk_alpha_pll video_cc_pll1 = {
···
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static const struct of_device_id video_cc_sm8450_match_table[] = {
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{ .compatible = "qcom,sm8450-videocc" },
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{ .compatible = "qcom,sm8475-videocc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);
···
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return PTR_ERR(regmap);
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}
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-
clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
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clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
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if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) {
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/* Update VideoCC PLL0 */
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video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
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+
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/* Update VideoCC PLL1 */
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video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
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clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll0_config);
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clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll1_config);
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} else {
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clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
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clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
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}
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/* Keep some clocks always-on */
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qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */
···
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module_platform_driver(video_cc_sm8450_driver);
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-
MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
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MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver");
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MODULE_LICENSE("GPL");