+15

arch/arm64/boot/dts/freescale/Makefile

reviewed

··· 114 114 dtb-$(CONFIG_ARCH_MXC) += imx8mm-evkb.dtb 115 115 dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-ctouch2.dtb 116 116 dtb-$(CONFIG_ARCH_MXC) += imx8mm-icore-mx8mm-edimm2.2.dtb 117 117 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-iot-gateway.dtb 117 118 dtb-$(CONFIG_ARCH_MXC) += imx8mm-innocomm-wb15-evk.dtb 118 119 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl.dtb 119 120 dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-bl-osm-s.dtb ··· 178 177 dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb 179 178 dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb 180 179 dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb 180 180 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mp-ras314.dtb 181 181 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb 182 182 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb 183 183 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb ··· 192 190 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb 193 191 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb 194 192 dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb 193 193 + 194 194 + imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo 195 195 + dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb 195 196 196 197 imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo 197 198 imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo ··· 236 231 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb 237 232 dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb 238 233 dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb 234 234 + dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb 239 235 dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb 240 236 dtb-$(CONFIG_ARCH_MXC) += imx93-phyboard-segin.dtb 241 237 dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb 242 238 dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb 243 239 dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb 240 240 + dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb 244 241 245 242 imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo 246 243 imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo ··· 269 262 dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb 270 263 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb 271 264 dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb 265 265 + 266 266 + imx8mm-phygate-tauri-l-rs232-rs232-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs232.dtbo 267 267 + imx8mm-phygate-tauri-l-rs232-cts-rts-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rts-cts.dtbo 268 268 + imx8mm-phygate-tauri-l-rs232-rs485-dtbs := imx8mm-phygate-tauri-l.dtb imx8mm-phygate-tauri-l-rs232-rs485.dtbo 269 269 + 270 270 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs232.dtb 271 271 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-cts-rts.dtb 272 272 + dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l-rs232-rs485.dtb 272 273 273 274 dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb 274 275 dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb

+39 -40

arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi

reviewed

··· 74 74 75 75 timer { 76 76 compatible = "arm,armv8-timer"; 77 77 - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 78 78 - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 79 79 - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 80 80 - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 77 77 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 78 78 + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 79 79 + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 80 80 + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 81 81 }; 82 82 83 83 pmu { 84 84 compatible = "arm,cortex-a53-pmu"; 85 85 - interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; 85 85 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 86 86 }; 87 87 88 88 gic: interrupt-controller@1400000 { ··· 93 93 <0x0 0x1402000 0 0x2000>, /* GICC */ 94 94 <0x0 0x1404000 0 0x2000>, /* GICH */ 95 95 <0x0 0x1406000 0 0x2000>; /* GICV */ 96 96 - interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; 96 96 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 97 97 }; 98 98 99 99 reboot { ··· 156 156 status = "disabled"; 157 157 }; 158 158 159 159 - esdhc0: esdhc@1560000 { 159 159 + esdhc0: mmc@1560000 { 160 160 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; 161 161 reg = <0x0 0x1560000 0x0 0x10000>; 162 162 - interrupts = <0 62 0x4>; 162 162 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 163 163 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 164 164 QORIQ_CLK_PLL_DIV(1)>; 165 165 voltage-ranges = <1800 1800 3300 3300>; ··· 175 175 big-endian; 176 176 }; 177 177 178 178 - esdhc1: esdhc@1580000 { 178 178 + esdhc1: mmc@1580000 { 179 179 compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; 180 180 reg = <0x0 0x1580000 0x0 0x10000>; 181 181 - interrupts = <0 65 0x4>; 181 181 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 182 182 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 183 183 QORIQ_CLK_PLL_DIV(1)>; 184 184 voltage-ranges = <1800 1800 3300 3300>; ··· 305 305 tmu: tmu@1f00000 { 306 306 compatible = "fsl,qoriq-tmu"; 307 307 reg = <0x0 0x1f00000 0x0 0x10000>; 308 308 - interrupts = <0 33 0x4>; 308 308 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 309 309 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; 310 310 fsl,tmu-calibration = 311 311 <0x00000000 0x00000025>, ··· 355 355 #address-cells = <1>; 356 356 #size-cells = <0>; 357 357 reg = <0x0 0x2180000 0x0 0x10000>; 358 358 - interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 358 358 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 359 359 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 360 360 QORIQ_CLK_PLL_DIV(4)>; 361 361 scl-gpios = <&gpio0 2 0>; ··· 367 367 #address-cells = <1>; 368 368 #size-cells = <0>; 369 369 reg = <0x0 0x2190000 0x0 0x10000>; 370 370 - interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 370 370 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 371 371 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 372 372 QORIQ_CLK_PLL_DIV(4)>; 373 373 scl-gpios = <&gpio0 13 0>; ··· 379 379 #address-cells = <1>; 380 380 #size-cells = <0>; 381 381 reg = <0x0 0x2100000 0x0 0x10000>; 382 382 - interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>; 382 382 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 383 383 clock-names = "dspi"; 384 384 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 385 385 QORIQ_CLK_PLL_DIV(1)>; ··· 391 391 duart0: serial@21c0500 { 392 392 compatible = "fsl,ns16550", "ns16550a"; 393 393 reg = <0x00 0x21c0500 0x0 0x100>; 394 394 - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 394 394 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 395 395 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 396 396 QORIQ_CLK_PLL_DIV(1)>; 397 397 status = "disabled"; ··· 400 400 duart1: serial@21c0600 { 401 401 compatible = "fsl,ns16550", "ns16550a"; 402 402 reg = <0x00 0x21c0600 0x0 0x100>; 403 403 - interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; 403 403 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 404 404 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 405 405 QORIQ_CLK_PLL_DIV(1)>; 406 406 status = "disabled"; 407 407 }; 408 408 409 409 gpio0: gpio@2300000 { 410 410 - compatible = "fsl,qoriq-gpio"; 410 410 + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 411 411 reg = <0x0 0x2300000 0x0 0x10000>; 412 412 - interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; 412 412 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 413 413 gpio-controller; 414 414 #gpio-cells = <2>; 415 415 interrupt-controller; ··· 417 417 }; 418 418 419 419 gpio1: gpio@2310000 { 420 420 - compatible = "fsl,qoriq-gpio"; 420 420 + compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio"; 421 421 reg = <0x0 0x2310000 0x0 0x10000>; 422 422 - interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 422 422 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 423 423 gpio-controller; 424 424 #gpio-cells = <2>; 425 425 interrupt-controller; ··· 430 430 compatible = "fsl,ls1012a-wdt", 431 431 "fsl,imx21-wdt"; 432 432 reg = <0x0 0x2ad0000 0x0 0x10000>; 433 433 - interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 433 433 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 434 434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(1)>; 435 435 big-endian; 436 436 }; ··· 439 439 #sound-dai-cells = <0>; 440 440 compatible = "fsl,vf610-sai"; 441 441 reg = <0x0 0x2b50000 0x0 0x10000>; 442 442 - interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; 442 442 + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 443 443 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 444 444 QORIQ_CLK_PLL_DIV(4)>, 445 445 <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 449 449 <&clockgen QORIQ_CLK_PLATFORM_PLL 450 450 QORIQ_CLK_PLL_DIV(4)>; 451 451 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 452 452 - dma-names = "tx", "rx"; 453 453 - dmas = <&edma0 1 47>, 454 454 - <&edma0 1 46>; 452 452 + dma-names = "rx", "tx"; 453 453 + dmas = <&edma0 1 46>, 454 454 + <&edma0 1 47>; 455 455 status = "disabled"; 456 456 }; 457 457 ··· 459 459 #sound-dai-cells = <0>; 460 460 compatible = "fsl,vf610-sai"; 461 461 reg = <0x0 0x2b60000 0x0 0x10000>; 462 462 - interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; 462 462 + interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 463 463 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 464 464 QORIQ_CLK_PLL_DIV(4)>, 465 465 <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 469 469 <&clockgen QORIQ_CLK_PLATFORM_PLL 470 470 QORIQ_CLK_PLL_DIV(4)>; 471 471 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 472 472 - dma-names = "tx", "rx"; 473 473 - dmas = <&edma0 1 45>, 474 474 - <&edma0 1 44>; 472 472 + dma-names = "rx", "tx"; 473 473 + dmas = <&edma0 1 44>, 474 474 + <&edma0 1 45>; 475 475 status = "disabled"; 476 476 }; 477 477 ··· 481 481 reg = <0x0 0x2c00000 0x0 0x10000>, 482 482 <0x0 0x2c10000 0x0 0x10000>, 483 483 <0x0 0x2c20000 0x0 0x10000>; 484 484 - interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, 485 485 - <0 103 IRQ_TYPE_LEVEL_HIGH>; 484 484 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 485 485 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 486 486 interrupt-names = "edma-tx", "edma-err"; 487 487 dma-channels = <32>; 488 488 big-endian; ··· 496 496 usb0: usb@2f00000 { 497 497 compatible = "snps,dwc3"; 498 498 reg = <0x0 0x2f00000 0x0 0x10000>; 499 499 - interrupts = <0 60 0x4>; 499 499 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 500 500 dr_mode = "host"; 501 501 snps,quirk-frame-length-adjustment = <0x20>; 502 502 snps,dis_rxdet_inp3_quirk; 503 503 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 504 504 - snps,host-vbus-glitches; 505 504 }; 506 505 507 506 sata: sata@3200000 { ··· 508 509 reg = <0x0 0x3200000 0x0 0x10000>, 509 510 <0x0 0x20140520 0x0 0x4>; 510 511 reg-names = "ahci", "sata-ecc"; 511 511 - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 512 512 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 512 513 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 513 514 QORIQ_CLK_PLL_DIV(1)>; 514 515 dma-coherent; ··· 518 519 usb1: usb@8600000 { 519 520 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; 520 521 reg = <0x0 0x8600000 0x0 0x1000>; 521 521 - interrupts = <0 139 0x4>; 522 522 + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 522 523 dr_mode = "host"; 523 524 phy_type = "ulpi"; 524 525 }; ··· 527 528 compatible = "fsl,ls1012a-msi"; 528 529 reg = <0x0 0x1572000 0x0 0x8>; 529 530 msi-controller; 530 530 - interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; 531 531 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 531 532 }; 532 533 533 534 pcie1: pcie@3400000 { ··· 535 536 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 536 537 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 537 538 reg-names = "regs", "config"; 538 538 - interrupts = <0 118 0x4>, /* controller interrupt */ 539 539 - <0 117 0x4>; /* PME interrupt */ 540 540 - interrupt-names = "aer", "pme"; 539 539 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 540 540 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 541 541 + interrupt-names = "pme", "aer"; 541 542 #address-cells = <3>; 542 543 #size-cells = <2>; 543 544 device_type = "pci"; ··· 562 563 #fsl,rcpm-wakeup-cells = <1>; 563 564 }; 564 565 565 565 - ftm_alarm0: timer@29d0000 { 566 566 + ftm_alarm0: rtc@29d0000 { 566 567 compatible = "fsl,ls1012a-ftm-alarm"; 567 568 reg = <0x0 0x29d0000 0x0 0x10000>; 568 569 fsl,rcpm-wakeup = <&rcpm 0x20000>;

+31

arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts

reviewed

··· 201 201 #address-cells = <1>; 202 202 #size-cells = <0>; 203 203 204 204 + i2c@0 { 205 205 + #address-cells = <1>; 206 206 + #size-cells = <0>; 207 207 + reg = <0x0>; 208 208 + 209 209 + /* Atmel AT24C512C-XHD­B: 64 KB EEPROM */ 210 210 + eeprom@50 { 211 211 + compatible = "atmel,24c512"; 212 212 + reg = <0x50>; 213 213 + #address-cells = <1>; 214 214 + #size-cells = <1>; 215 215 + }; 216 216 + 217 217 + /* AT24C04C 512-byte DDR4 SPD EEPROM */ 218 218 + /* Documentation says 0x51, but must be even and i2cdetect says 0x52 */ 219 219 + eeprom@52 { 220 220 + compatible = "atmel,24c04"; 221 221 + reg = <0x52>; 222 222 + #address-cells = <1>; 223 223 + #size-cells = <1>; 224 224 + }; 225 225 + 226 226 + /* Atmel AT24C02C-XHM­B: 256-byte EEPROM */ 227 227 + eeprom@57 { 228 228 + compatible = "atmel,24c02"; 229 229 + reg = <0x57>; 230 230 + #address-cells = <1>; 231 231 + #size-cells = <1>; 232 232 + }; 233 233 + }; 234 234 + 204 235 i2c@1 { 205 236 #address-cells = <1>; 206 237 #size-cells = <0>;

+28 -27

arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi

reviewed

··· 155 155 }; 156 156 157 157 thermal-zones { 158 158 - ddr-controller { 158 158 + ddr-thermal { 159 159 polling-delay-passive = <1000>; 160 160 polling-delay = <5000>; 161 161 thermal-sensors = <&tmu 0>; ··· 175 175 }; 176 176 }; 177 177 178 178 - core-cluster { 178 178 + core-cluster-thermal { 179 179 polling-delay-passive = <1000>; 180 180 polling-delay = <5000>; 181 181 thermal-sensors = <&tmu 1>; ··· 674 674 }; 675 675 676 676 pcie_ep1: pcie-ep@3400000 { 677 677 - compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 677 677 + compatible = "fsl,ls1028a-pcie-ep"; 678 678 reg = <0x00 0x03400000 0x0 0x00100000 679 679 0x80 0x00000000 0x8 0x00000000>; 680 680 reg-names = "regs", "addr_space"; ··· 713 713 }; 714 714 715 715 pcie_ep2: pcie-ep@3500000 { 716 716 - compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep"; 716 716 + compatible = "fsl,ls1028a-pcie-ep"; 717 717 reg = <0x00 0x03500000 0x0 0x00100000 718 718 0x88 0x00000000 0x8 0x00000000>; 719 719 reg-names = "regs", "addr_space"; ··· 828 828 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 829 829 interrupt-names = "qdma-error", "qdma-queue0", 830 830 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 831 831 + #dma-cells = <1>; 831 832 dma-channels = <8>; 832 833 block-number = <1>; 833 834 block-offset = <0x10000>; ··· 860 859 malidp0: display@f080000 { 861 860 compatible = "arm,mali-dp500"; 862 861 reg = <0x0 0xf080000 0x0 0x10000>; 863 863 - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, 864 864 - <0 223 IRQ_TYPE_LEVEL_HIGH>; 862 862 + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 863 863 + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 865 864 interrupt-names = "DE", "SE"; 866 865 clocks = <&dpclk>, 867 866 <&clockgen QORIQ_CLK_HWACCEL 2>, ··· 903 902 <&clockgen QORIQ_CLK_PLATFORM_PLL 904 903 QORIQ_CLK_PLL_DIV(2)>; 905 904 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 906 906 - dma-names = "tx", "rx"; 907 907 - dmas = <&edma0 1 4>, 908 908 - <&edma0 1 3>; 905 905 + dma-names = "rx", "tx"; 906 906 + dmas = <&edma0 1 3>, 907 907 + <&edma0 1 4>; 909 908 fsl,sai-asynchronous; 910 909 status = "disabled"; 911 910 }; ··· 924 923 <&clockgen QORIQ_CLK_PLATFORM_PLL 925 924 QORIQ_CLK_PLL_DIV(2)>; 926 925 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 927 927 - dma-names = "tx", "rx"; 928 928 - dmas = <&edma0 1 6>, 929 929 - <&edma0 1 5>; 926 926 + dma-names = "rx", "tx"; 927 927 + dmas = <&edma0 1 5>, 928 928 + <&edma0 1 6>; 930 929 fsl,sai-asynchronous; 931 930 status = "disabled"; 932 931 }; ··· 945 944 <&clockgen QORIQ_CLK_PLATFORM_PLL 946 945 QORIQ_CLK_PLL_DIV(2)>; 947 946 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 948 948 - dma-names = "tx", "rx"; 949 949 - dmas = <&edma0 1 8>, 950 950 - <&edma0 1 7>; 947 947 + dma-names = "rx", "tx"; 948 948 + dmas = <&edma0 1 7>, 949 949 + <&edma0 1 8>; 951 950 fsl,sai-asynchronous; 952 951 status = "disabled"; 953 952 }; ··· 966 965 <&clockgen QORIQ_CLK_PLATFORM_PLL 967 966 QORIQ_CLK_PLL_DIV(2)>; 968 967 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 969 969 - dma-names = "tx", "rx"; 970 970 - dmas = <&edma0 1 10>, 971 971 - <&edma0 1 9>; 968 968 + dma-names = "rx", "tx"; 969 969 + dmas = <&edma0 1 9>, 970 970 + <&edma0 1 10>; 972 971 fsl,sai-asynchronous; 973 972 status = "disabled"; 974 973 }; ··· 987 986 <&clockgen QORIQ_CLK_PLATFORM_PLL 988 987 QORIQ_CLK_PLL_DIV(2)>; 989 988 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 990 990 - dma-names = "tx", "rx"; 991 991 - dmas = <&edma0 1 12>, 992 992 - <&edma0 1 11>; 989 989 + dma-names = "rx", "tx"; 990 990 + dmas = <&edma0 1 11>, 991 991 + <&edma0 1 12>; 993 992 fsl,sai-asynchronous; 994 993 status = "disabled"; 995 994 }; ··· 1008 1007 <&clockgen QORIQ_CLK_PLATFORM_PLL 1009 1008 QORIQ_CLK_PLL_DIV(2)>; 1010 1009 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1011 1011 - dma-names = "tx", "rx"; 1012 1012 - dmas = <&edma0 1 14>, 1013 1013 - <&edma0 1 13>; 1010 1010 + dma-names = "rx", "tx"; 1011 1011 + dmas = <&edma0 1 13>, 1012 1012 + <&edma0 1 14>; 1014 1013 fsl,sai-asynchronous; 1015 1014 status = "disabled"; 1016 1015 }; ··· 1025 1024 tmu: tmu@1f80000 { 1026 1025 compatible = "fsl,qoriq-tmu"; 1027 1026 reg = <0x0 0x1f80000 0x0 0x10000>; 1028 1028 - interrupts = <0 23 0x4>; 1027 1027 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1029 1028 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 1030 1029 fsl,tmu-calibration = 1031 1030 <0x00000000 0x00000024>, ··· 1326 1325 little-endian; 1327 1326 }; 1328 1327 1329 1329 - ftm_alarm0: timer@2800000 { 1328 1328 + ftm_alarm0: rtc@2800000 { 1330 1329 compatible = "fsl,ls1028a-ftm-alarm"; 1331 1330 reg = <0x0 0x2800000 0x0 0x10000>; 1332 1331 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; ··· 1334 1333 status = "disabled"; 1335 1334 }; 1336 1335 1337 1337 - ftm_alarm1: timer@2810000 { 1336 1336 + ftm_alarm1: rtc@2810000 { 1338 1337 compatible = "fsl,ls1028a-ftm-alarm"; 1339 1338 reg = <0x0 0x2810000 0x0 0x10000>; 1340 1339 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts

reviewed

··· 64 64 0x2 0x0 0x0 0x7fb00000 0x00000100>; 65 65 status = "okay"; 66 66 67 67 - nor@0,0 { 67 67 + flash@0,0 { 68 68 compatible = "cfi-flash"; 69 69 reg = <0x0 0x0 0x8000000>; 70 70 big-endian;

+19 -1

arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts

reviewed

··· 71 71 0x1 0x0 0x0 0x7e800000 0x00010000 72 72 0x2 0x0 0x0 0x7fb00000 0x00000100>; 73 73 74 74 - nor@0,0 { 74 74 + flash@0,0 { 75 75 compatible = "cfi-flash"; 76 76 #address-cells = <1>; 77 77 #size-cells = <1>; ··· 104 104 compatible = "n25q128a13", "jedec,spi-nor"; /* 16MB */ 105 105 reg = <0>; 106 106 spi-max-frequency = <1000000>; /* input clock */ 107 107 + /* 108 108 + * Standard CS timing properties replace the deprecated vendor 109 109 + * variants below. 110 110 + */ 111 111 + spi-cs-setup-delay-ns = <100>; 112 112 + spi-cs-hold-delay-ns = <100>; 107 113 fsl,spi-cs-sck-delay = <100>; 108 114 fsl,spi-sck-cs-delay = <100>; 109 115 }; ··· 118 112 compatible = "maxim,ds26522"; 119 113 reg = <2>; 120 114 spi-max-frequency = <2000000>; 115 115 + /* 116 116 + * Standard CS timing properties replace the deprecated vendor 117 117 + * variants below. 118 118 + */ 119 119 + spi-cs-setup-delay-ns = <100>; 120 120 + spi-cs-hold-delay-ns = <50>; 121 121 fsl,spi-cs-sck-delay = <100>; 122 122 fsl,spi-sck-cs-delay = <50>; 123 123 }; ··· 132 120 compatible = "maxim,ds26522"; 133 121 reg = <3>; 134 122 spi-max-frequency = <2000000>; 123 123 + /* 124 124 + * Standard CS timing properties replace the deprecated vendor 125 125 + * variants below. 126 126 + */ 127 127 + spi-cs-setup-delay-ns = <100>; 128 128 + spi-cs-hold-delay-ns = <50>; 135 129 fsl,spi-cs-sck-delay = <100>; 136 130 fsl,spi-sck-cs-delay = <50>; 137 131 };

+69 -69

arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi

reviewed

··· 154 154 }; 155 155 156 156 thermal-zones { 157 157 - ddr-controller { 157 157 + ddr-thermal { 158 158 polling-delay-passive = <1000>; 159 159 polling-delay = <5000>; 160 160 thermal-sensors = <&tmu 0>; ··· 174 174 }; 175 175 }; 176 176 177 177 - serdes { 177 177 + serdes-thermal { 178 178 polling-delay-passive = <1000>; 179 179 polling-delay = <5000>; 180 180 thermal-sensors = <&tmu 1>; ··· 194 194 }; 195 195 }; 196 196 197 197 - fman { 197 197 + fman-thermal { 198 198 polling-delay-passive = <1000>; 199 199 polling-delay = <5000>; 200 200 thermal-sensors = <&tmu 2>; ··· 214 214 }; 215 215 }; 216 216 217 217 - core-cluster { 217 217 + core-cluster-thermal { 218 218 polling-delay-passive = <1000>; 219 219 polling-delay = <5000>; 220 220 thermal-sensors = <&tmu 3>; ··· 245 245 }; 246 246 }; 247 247 248 248 - sec { 248 248 + sec-thermal { 249 249 polling-delay-passive = <1000>; 250 250 polling-delay = <5000>; 251 251 thermal-sensors = <&tmu 4>; ··· 268 268 269 269 timer { 270 270 compatible = "arm,armv8-timer"; 271 271 - interrupts = <1 13 0xf08>, /* Physical Secure PPI */ 272 272 - <1 14 0xf08>, /* Physical Non-Secure PPI */ 273 273 - <1 11 0xf08>, /* Virtual PPI */ 274 274 - <1 10 0xf08>; /* Hypervisor PPI */ 271 271 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 272 272 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 273 273 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 274 274 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 275 275 fsl,erratum-a008585; 276 276 }; 277 277 278 278 pmu { 279 279 compatible = "arm,cortex-a53-pmu"; 280 280 - interrupts = <0 106 0x4>, 281 281 - <0 107 0x4>, 282 282 - <0 95 0x4>, 283 283 - <0 97 0x4>; 280 280 + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 281 281 + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 282 282 + <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 283 283 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 284 284 interrupt-affinity = <&cpu0>, 285 285 <&cpu1>, 286 286 <&cpu2>, ··· 295 295 <0x0 0x1402000 0 0x2000>, /* GICC */ 296 296 <0x0 0x1404000 0 0x2000>, /* GICH */ 297 297 <0x0 0x1406000 0 0x2000>; /* GICV */ 298 298 - interrupts = <1 9 0xf08>; 298 298 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 299 299 }; 300 300 301 301 soc: soc { ··· 352 352 #size-cells = <1>; 353 353 ranges = <0x0 0x00 0x1700000 0x100000>; 354 354 reg = <0x00 0x1700000 0x0 0x100000>; 355 355 - interrupts = <0 75 0x4>; 355 355 + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 356 356 dma-coherent; 357 357 358 358 sec_jr0: jr@10000 { ··· 360 360 "fsl,sec-v5.0-job-ring", 361 361 "fsl,sec-v4.0-job-ring"; 362 362 reg = <0x10000 0x10000>; 363 363 - interrupts = <0 71 0x4>; 363 363 + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 364 364 }; 365 365 366 366 sec_jr1: jr@20000 { ··· 368 368 "fsl,sec-v5.0-job-ring", 369 369 "fsl,sec-v4.0-job-ring"; 370 370 reg = <0x20000 0x10000>; 371 371 - interrupts = <0 72 0x4>; 371 371 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 372 372 }; 373 373 374 374 sec_jr2: jr@30000 { ··· 376 376 "fsl,sec-v5.0-job-ring", 377 377 "fsl,sec-v4.0-job-ring"; 378 378 reg = <0x30000 0x10000>; 379 379 - interrupts = <0 73 0x4>; 379 379 + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 380 380 }; 381 381 382 382 sec_jr3: jr@40000 { ··· 384 384 "fsl,sec-v5.0-job-ring", 385 385 "fsl,sec-v4.0-job-ring"; 386 386 reg = <0x40000 0x10000>; 387 387 - interrupts = <0 74 0x4>; 387 387 + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 388 388 }; 389 389 }; 390 390 ··· 405 405 ifc: memory-controller@1530000 { 406 406 compatible = "fsl,ifc"; 407 407 reg = <0x0 0x1530000 0x0 0x10000>; 408 408 - interrupts = <0 43 0x4>; 408 408 + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 409 409 }; 410 410 411 411 qspi: spi@1550000 { ··· 415 415 reg = <0x0 0x1550000 0x0 0x10000>, 416 416 <0x0 0x40000000 0x0 0x4000000>; 417 417 reg-names = "QuadSPI", "QuadSPI-memory"; 418 418 - interrupts = <0 99 0x4>; 418 418 + interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 419 419 clock-names = "qspi_en", "qspi"; 420 420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 421 421 QORIQ_CLK_PLL_DIV(1)>, ··· 424 424 status = "disabled"; 425 425 }; 426 426 427 427 - esdhc: esdhc@1560000 { 427 427 + esdhc: mmc@1560000 { 428 428 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc"; 429 429 reg = <0x0 0x1560000 0x0 0x10000>; 430 430 - interrupts = <0 62 0x4>; 430 430 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 431 431 clock-frequency = <0>; 432 432 voltage-ranges = <1800 1800 3300 3300>; 433 433 sdhci,auto-cmd12; ··· 438 438 ddr: memory-controller@1080000 { 439 439 compatible = "fsl,qoriq-memory-controller"; 440 440 reg = <0x0 0x1080000 0x0 0x1000>; 441 441 - interrupts = <0 144 0x4>; 441 441 + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 442 442 big-endian; 443 443 }; 444 444 445 445 tmu: tmu@1f00000 { 446 446 compatible = "fsl,qoriq-tmu"; 447 447 reg = <0x0 0x1f00000 0x0 0x10000>; 448 448 - interrupts = <0 33 0x4>; 448 448 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 449 449 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 450 450 fsl,tmu-calibration = 451 451 <0x00000000 0x00000023>, ··· 505 505 memory-region = <&bman_fbpr>; 506 506 }; 507 507 508 508 - bportals: bman-portals@508000000 { 508 508 + bportals: bman-portals-bus@508000000 { 509 509 ranges = <0x0 0x5 0x08000000 0x8000000>; 510 510 }; 511 511 512 512 - qportals: qman-portals@500000000 { 512 512 + qportals: qman-portals-bus@500000000 { 513 513 ranges = <0x0 0x5 0x00000000 0x8000000>; 514 514 }; 515 515 ··· 518 518 #address-cells = <1>; 519 519 #size-cells = <0>; 520 520 reg = <0x0 0x2100000 0x0 0x10000>; 521 521 - interrupts = <0 64 0x4>; 521 521 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 522 522 clock-names = "dspi"; 523 523 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 524 524 QORIQ_CLK_PLL_DIV(1)>; ··· 532 532 #address-cells = <1>; 533 533 #size-cells = <0>; 534 534 reg = <0x0 0x2180000 0x0 0x10000>; 535 535 - interrupts = <0 56 0x4>; 536 536 - clock-names = "i2c"; 535 535 + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 536 536 + clock-names = "ipg"; 537 537 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 538 538 QORIQ_CLK_PLL_DIV(1)>; 539 539 dmas = <&edma0 1 38>, ··· 547 547 #address-cells = <1>; 548 548 #size-cells = <0>; 549 549 reg = <0x0 0x2190000 0x0 0x10000>; 550 550 - interrupts = <0 57 0x4>; 551 551 - clock-names = "i2c"; 550 550 + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 551 551 + clock-names = "ipg"; 552 552 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 553 553 QORIQ_CLK_PLL_DIV(1)>; 554 554 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ··· 560 560 #address-cells = <1>; 561 561 #size-cells = <0>; 562 562 reg = <0x0 0x21a0000 0x0 0x10000>; 563 563 - interrupts = <0 58 0x4>; 564 564 - clock-names = "i2c"; 563 563 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 564 564 + clock-names = "ipg"; 565 565 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 566 566 QORIQ_CLK_PLL_DIV(1)>; 567 567 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ··· 573 573 #address-cells = <1>; 574 574 #size-cells = <0>; 575 575 reg = <0x0 0x21b0000 0x0 0x10000>; 576 576 - interrupts = <0 59 0x4>; 577 577 - clock-names = "i2c"; 576 576 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 577 577 + clock-names = "ipg"; 578 578 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 579 579 QORIQ_CLK_PLL_DIV(1)>; 580 580 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; ··· 584 584 duart0: serial@21c0500 { 585 585 compatible = "fsl,ns16550", "ns16550a"; 586 586 reg = <0x00 0x21c0500 0x0 0x100>; 587 587 - interrupts = <0 54 0x4>; 587 587 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 588 588 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 589 589 QORIQ_CLK_PLL_DIV(1)>; 590 590 }; ··· 592 592 duart1: serial@21c0600 { 593 593 compatible = "fsl,ns16550", "ns16550a"; 594 594 reg = <0x00 0x21c0600 0x0 0x100>; 595 595 - interrupts = <0 54 0x4>; 595 595 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 596 596 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 597 597 QORIQ_CLK_PLL_DIV(1)>; 598 598 }; ··· 600 600 duart2: serial@21d0500 { 601 601 compatible = "fsl,ns16550", "ns16550a"; 602 602 reg = <0x0 0x21d0500 0x0 0x100>; 603 603 - interrupts = <0 55 0x4>; 603 603 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 604 604 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 605 605 QORIQ_CLK_PLL_DIV(1)>; 606 606 }; ··· 608 608 duart3: serial@21d0600 { 609 609 compatible = "fsl,ns16550", "ns16550a"; 610 610 reg = <0x0 0x21d0600 0x0 0x100>; 611 611 - interrupts = <0 55 0x4>; 611 611 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 612 612 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 613 613 QORIQ_CLK_PLL_DIV(1)>; 614 614 }; ··· 616 616 gpio1: gpio@2300000 { 617 617 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 618 618 reg = <0x0 0x2300000 0x0 0x10000>; 619 619 - interrupts = <0 66 0x4>; 619 619 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 620 620 gpio-controller; 621 621 #gpio-cells = <2>; 622 622 interrupt-controller; ··· 626 626 gpio2: gpio@2310000 { 627 627 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 628 628 reg = <0x0 0x2310000 0x0 0x10000>; 629 629 - interrupts = <0 67 0x4>; 629 629 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 630 630 gpio-controller; 631 631 #gpio-cells = <2>; 632 632 interrupt-controller; ··· 636 636 gpio3: gpio@2320000 { 637 637 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 638 638 reg = <0x0 0x2320000 0x0 0x10000>; 639 639 - interrupts = <0 68 0x4>; 639 639 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 640 640 gpio-controller; 641 641 #gpio-cells = <2>; 642 642 interrupt-controller; ··· 646 646 gpio4: gpio@2330000 { 647 647 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio"; 648 648 reg = <0x0 0x2330000 0x0 0x10000>; 649 649 - interrupts = <0 134 0x4>; 649 649 + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 650 650 gpio-controller; 651 651 #gpio-cells = <2>; 652 652 interrupt-controller; ··· 721 721 lpuart0: serial@2950000 { 722 722 compatible = "fsl,ls1021a-lpuart"; 723 723 reg = <0x0 0x2950000 0x0 0x1000>; 724 724 - interrupts = <0 48 0x4>; 724 724 + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 725 725 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>; 726 726 clock-names = "ipg"; 727 727 status = "disabled"; ··· 730 730 lpuart1: serial@2960000 { 731 731 compatible = "fsl,ls1021a-lpuart"; 732 732 reg = <0x0 0x2960000 0x0 0x1000>; 733 733 - interrupts = <0 49 0x4>; 733 733 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 734 734 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 735 735 QORIQ_CLK_PLL_DIV(1)>; 736 736 clock-names = "ipg"; ··· 740 740 lpuart2: serial@2970000 { 741 741 compatible = "fsl,ls1021a-lpuart"; 742 742 reg = <0x0 0x2970000 0x0 0x1000>; 743 743 - interrupts = <0 50 0x4>; 743 743 + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 744 744 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 745 745 QORIQ_CLK_PLL_DIV(1)>; 746 746 clock-names = "ipg"; ··· 750 750 lpuart3: serial@2980000 { 751 751 compatible = "fsl,ls1021a-lpuart"; 752 752 reg = <0x0 0x2980000 0x0 0x1000>; 753 753 - interrupts = <0 51 0x4>; 753 753 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 754 754 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 755 755 QORIQ_CLK_PLL_DIV(1)>; 756 756 clock-names = "ipg"; ··· 760 760 lpuart4: serial@2990000 { 761 761 compatible = "fsl,ls1021a-lpuart"; 762 762 reg = <0x0 0x2990000 0x0 0x1000>; 763 763 - interrupts = <0 52 0x4>; 763 763 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 764 764 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 765 765 QORIQ_CLK_PLL_DIV(1)>; 766 766 clock-names = "ipg"; ··· 770 770 lpuart5: serial@29a0000 { 771 771 compatible = "fsl,ls1021a-lpuart"; 772 772 reg = <0x0 0x29a0000 0x0 0x1000>; 773 773 - interrupts = <0 53 0x4>; 773 773 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 774 774 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 775 775 QORIQ_CLK_PLL_DIV(1)>; 776 776 clock-names = "ipg"; ··· 780 780 wdog0: watchdog@2ad0000 { 781 781 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; 782 782 reg = <0x0 0x2ad0000 0x0 0x10000>; 783 783 - interrupts = <0 83 0x4>; 783 783 + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 784 784 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 785 785 QORIQ_CLK_PLL_DIV(1)>; 786 786 - clock-names = "wdog"; 787 786 big-endian; 788 787 }; 789 788 ··· 792 793 reg = <0x0 0x2c00000 0x0 0x10000>, 793 794 <0x0 0x2c10000 0x0 0x10000>, 794 795 <0x0 0x2c20000 0x0 0x10000>; 795 795 - interrupts = <0 103 0x4>, 796 796 - <0 103 0x4>; 796 796 + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 797 797 + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 797 798 interrupt-names = "edma-tx", "edma-err"; 798 799 dma-channels = <32>; 799 800 big-endian; ··· 804 805 QORIQ_CLK_PLL_DIV(1)>; 805 806 }; 806 807 807 807 - aux_bus: aux_bus { 808 808 + aux_bus: aux-bus { 808 809 #address-cells = <2>; 809 810 #size-cells = <2>; 810 811 compatible = "simple-bus"; ··· 814 815 usb0: usb@2f00000 { 815 816 compatible = "snps,dwc3"; 816 817 reg = <0x0 0x2f00000 0x0 0x10000>; 817 817 - interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>; 818 818 + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 818 819 dr_mode = "host"; 819 820 snps,quirk-frame-length-adjustment = <0x20>; 820 821 snps,dis_rxdet_inp3_quirk; ··· 826 827 usb1: usb@3000000 { 827 828 compatible = "snps,dwc3"; 828 829 reg = <0x0 0x3000000 0x0 0x10000>; 829 829 - interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 830 830 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 830 831 dr_mode = "host"; 831 832 snps,quirk-frame-length-adjustment = <0x20>; 832 833 snps,dis_rxdet_inp3_quirk; ··· 838 839 usb2: usb@3100000 { 839 840 compatible = "snps,dwc3"; 840 841 reg = <0x0 0x3100000 0x0 0x10000>; 841 841 - interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 842 842 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 842 843 dr_mode = "host"; 843 844 snps,quirk-frame-length-adjustment = <0x20>; 844 845 snps,dis_rxdet_inp3_quirk; ··· 852 853 reg = <0x0 0x3200000 0x0 0x10000>, 853 854 <0x0 0x20140520 0x0 0x4>; 854 855 reg-names = "ahci", "sata-ecc"; 855 855 - interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 856 856 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 856 857 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 857 858 QORIQ_CLK_PLL_DIV(1)>; 858 859 dma-coherent; ··· 863 864 compatible = "fsl,ls1043a-msi"; 864 865 reg = <0x0 0x1571000 0x0 0x8>; 865 866 msi-controller; 866 866 - interrupts = <0 116 0x4>; 867 867 + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 867 868 }; 868 869 869 870 msi2: msi-controller2@1572000 { 870 871 compatible = "fsl,ls1043a-msi"; 871 872 reg = <0x0 0x1572000 0x0 0x8>; 872 873 msi-controller; 873 873 - interrupts = <0 126 0x4>; 874 874 + interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 874 875 }; 875 876 876 877 msi3: msi-controller3@1573000 { 877 878 compatible = "fsl,ls1043a-msi"; 878 879 reg = <0x0 0x1573000 0x0 0x8>; 879 880 msi-controller; 880 880 - interrupts = <0 160 0x4>; 881 881 + interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 881 882 }; 882 883 883 884 pcie1: pcie@3400000 { ··· 885 886 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 886 887 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 887 888 reg-names = "regs", "config"; 888 888 - interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>, 889 889 - <0 118 IRQ_TYPE_LEVEL_HIGH>; 889 889 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 890 890 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 890 891 interrupt-names = "pme", "aer"; 891 892 #address-cells = <3>; 892 893 #size-cells = <2>; ··· 912 913 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 913 914 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 914 915 reg-names = "regs", "config"; 915 915 - interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>, 916 916 - <0 128 IRQ_TYPE_LEVEL_HIGH>; 916 916 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 917 917 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 917 918 interrupt-names = "pme", "aer"; 918 919 #address-cells = <3>; 919 920 #size-cells = <2>; ··· 939 940 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 940 941 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 941 942 reg-names = "regs", "config"; 942 942 - interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>, 943 943 - <0 162 IRQ_TYPE_LEVEL_HIGH>; 943 943 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 944 944 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 944 945 interrupt-names = "pme", "aer"; 945 946 #address-cells = <3>; 946 947 #size-cells = <2>; ··· 973 974 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 974 975 interrupt-names = "qdma-error", "qdma-queue0", 975 976 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 977 977 + #dma-cells = <1>; 976 978 dma-channels = <8>; 977 979 block-number = <1>; 978 980 block-offset = <0x10000>; ··· 989 989 #fsl,rcpm-wakeup-cells = <1>; 990 990 }; 991 991 992 992 - ftm_alarm0: timer@29d0000 { 992 992 + ftm_alarm0: rtc@29d0000 { 993 993 compatible = "fsl,ls1043a-ftm-alarm"; 994 994 reg = <0x0 0x29d0000 0x0 0x10000>; 995 995 fsl,rcpm-wakeup = <&rcpm 0x20000>;

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts

reviewed

··· 151 151 0x2 0x0 0x0 0x7fb00000 0x00000100>; 152 152 status = "okay"; 153 153 154 154 - nor@0,0 { 154 154 + flash@0,0 { 155 155 compatible = "cfi-flash"; 156 156 reg = <0x0 0x0 0x8000000>; 157 157 big-endian;

+25 -24

arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi

reviewed

··· 122 122 }; 123 123 124 124 thermal-zones { 125 125 - ddr-controller { 125 125 + ddr-thermal { 126 126 polling-delay-passive = <1000>; 127 127 polling-delay = <5000>; 128 128 thermal-sensors = <&tmu 0>; ··· 142 142 }; 143 143 }; 144 144 145 145 - serdes { 145 145 + serdes-thermal { 146 146 polling-delay-passive = <1000>; 147 147 polling-delay = <5000>; 148 148 thermal-sensors = <&tmu 1>; ··· 162 162 }; 163 163 }; 164 164 165 165 - fman { 165 165 + fman-thermal { 166 166 polling-delay-passive = <1000>; 167 167 polling-delay = <5000>; 168 168 thermal-sensors = <&tmu 2>; ··· 182 182 }; 183 183 }; 184 184 185 185 - core-cluster { 185 185 + core-cluster-thermal { 186 186 polling-delay-passive = <1000>; 187 187 polling-delay = <5000>; 188 188 thermal-sensors = <&tmu 3>; ··· 213 213 }; 214 214 }; 215 215 216 216 - sec { 216 216 + sec-thermal { 217 217 polling-delay-passive = <1000>; 218 218 polling-delay = <5000>; 219 219 thermal-sensors = <&tmu 4>; ··· 308 308 status = "disabled"; 309 309 }; 310 310 311 311 - esdhc: esdhc@1560000 { 311 311 + esdhc: mmc@1560000 { 312 312 compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; 313 313 reg = <0x0 0x1560000 0x0 0x10000>; 314 314 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; ··· 409 409 410 410 }; 411 411 412 412 - qportals: qman-portals@500000000 { 412 412 + qportals: qman-portals-bus@500000000 { 413 413 ranges = <0x0 0x5 0x00000000 0x8000000>; 414 414 }; 415 415 416 416 - bportals: bman-portals@508000000 { 416 416 + bportals: bman-portals-bus@508000000 { 417 417 ranges = <0x0 0x5 0x08000000 0x8000000>; 418 418 }; 419 419 ··· 441 441 tmu: tmu@1f00000 { 442 442 compatible = "fsl,qoriq-tmu"; 443 443 reg = <0x0 0x1f00000 0x0 0x10000>; 444 444 - interrupts = <0 33 0x4>; 444 444 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 445 445 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 446 446 fsl,tmu-calibration = 447 447 /* Calibration data group 1 */ ··· 589 589 }; 590 590 591 591 gpio0: gpio@2300000 { 592 592 - compatible = "fsl,qoriq-gpio"; 592 592 + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 593 593 reg = <0x0 0x2300000 0x0 0x10000>; 594 594 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 595 595 gpio-controller; ··· 599 599 }; 600 600 601 601 gpio1: gpio@2310000 { 602 602 - compatible = "fsl,qoriq-gpio"; 602 602 + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 603 603 reg = <0x0 0x2310000 0x0 0x10000>; 604 604 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 605 605 gpio-controller; ··· 609 609 }; 610 610 611 611 gpio2: gpio@2320000 { 612 612 - compatible = "fsl,qoriq-gpio"; 612 612 + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 613 613 reg = <0x0 0x2320000 0x0 0x10000>; 614 614 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 615 615 gpio-controller; ··· 619 619 }; 620 620 621 621 gpio3: gpio@2330000 { 622 622 - compatible = "fsl,qoriq-gpio"; 622 622 + compatible = "fsl,ls1046a-gpio", "fsl,qoriq-gpio"; 623 623 reg = <0x0 0x2330000 0x0 0x10000>; 624 624 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 625 625 gpio-controller; ··· 715 715 QORIQ_CLK_PLL_DIV(2)>; 716 716 }; 717 717 718 718 - aux_bus: aux_bus { 718 718 + aux_bus: aux-bus { 719 719 #address-cells = <2>; 720 720 #size-cells = <2>; 721 721 compatible = "simple-bus"; ··· 801 801 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 802 802 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */ 803 803 reg-names = "regs", "config"; 804 804 - interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 805 805 - <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 806 806 - interrupt-names = "aer", "pme"; 804 804 + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 805 805 + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 806 806 + interrupt-names = "pme", "aer"; 807 807 #address-cells = <3>; 808 808 #size-cells = <2>; 809 809 device_type = "pci"; ··· 840 840 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 841 841 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */ 842 842 reg-names = "regs", "config"; 843 843 - interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 844 844 - <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 845 845 - interrupt-names = "aer", "pme"; 843 843 + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 844 844 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 845 845 + interrupt-names = "pme", "aer"; 846 846 #address-cells = <3>; 847 847 #size-cells = <2>; 848 848 device_type = "pci"; ··· 879 879 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 880 880 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */ 881 881 reg-names = "regs", "config"; 882 882 - interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 883 883 - <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */ 884 884 - interrupt-names = "aer", "pme"; 882 882 + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 883 883 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 884 884 + interrupt-names = "pme", "aer"; 885 885 #address-cells = <3>; 886 886 #size-cells = <2>; 887 887 device_type = "pci"; ··· 925 925 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 926 926 interrupt-names = "qdma-error", "qdma-queue0", 927 927 "qdma-queue1", "qdma-queue2", "qdma-queue3"; 928 928 + #dma-cells = <1>; 928 929 dma-channels = <8>; 929 930 block-number = <1>; 930 931 block-offset = <0x10000>; ··· 941 940 #fsl,rcpm-wakeup-cells = <1>; 942 941 }; 943 942 944 944 - ftm_alarm0: timer@29d0000 { 943 943 + ftm_alarm0: rtc@29d0000 { 945 944 compatible = "fsl,ls1046a-ftm-alarm"; 946 945 reg = <0x0 0x29d0000 0x0 0x10000>; 947 946 fsl,rcpm-wakeup = <&rcpm 0x20000>;

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts

reviewed

··· 113 113 3 0 0x5 0x20000000 0x00010000>; 114 114 status = "okay"; 115 115 116 116 - nor@0,0 { 116 116 + flash@0,0 { 117 117 compatible = "cfi-flash"; 118 118 reg = <0x0 0x0 0x8000000>; 119 119 bank-width = <2>;

+36 -36

arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi

reviewed

··· 118 118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */ 119 119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */ 120 120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */ 121 121 - interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; 121 121 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 122 122 #address-cells = <2>; 123 123 #size-cells = <2>; 124 124 ranges; ··· 131 131 }; 132 132 133 133 thermal-zones { 134 134 - core-cluster { 134 134 + core-cluster-thermal { 135 135 polling-delay-passive = <1000>; 136 136 polling-delay = <5000>; 137 137 thermal-sensors = <&tmu 0>; ··· 166 166 }; 167 167 }; 168 168 169 169 - soc { 169 169 + soc-thermal { 170 170 polling-delay-passive = <1000>; 171 171 polling-delay = <5000>; 172 172 thermal-sensors = <&tmu 1>; ··· 183 183 184 184 timer { 185 185 compatible = "arm,armv8-timer"; 186 186 - interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 187 187 - <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 188 188 - <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 189 189 - <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 186 186 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ 187 187 + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ 188 188 + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ 189 189 + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ 190 190 }; 191 191 192 192 pmu { ··· 280 280 tmu: tmu@1f80000 { 281 281 compatible = "fsl,qoriq-tmu"; 282 282 reg = <0x0 0x1f80000 0x0 0x10000>; 283 283 - interrupts = <0 23 0x4>; 283 283 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 284 284 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; 285 285 fsl,tmu-calibration = 286 286 /* Calibration data group 1 */ ··· 347 347 reg = <0x0 0x21c0500 0x0 0x100>; 348 348 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 349 349 QORIQ_CLK_PLL_DIV(4)>; 350 350 - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 350 350 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 351 351 status = "disabled"; 352 352 }; 353 353 ··· 356 356 reg = <0x0 0x21c0600 0x0 0x100>; 357 357 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 358 358 QORIQ_CLK_PLL_DIV(4)>; 359 359 - interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 359 359 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 360 360 status = "disabled"; 361 361 }; 362 362 363 363 gpio0: gpio@2300000 { 364 364 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 365 365 reg = <0x0 0x2300000 0x0 0x10000>; 366 366 - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 366 366 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 367 367 little-endian; 368 368 gpio-controller; 369 369 #gpio-cells = <2>; ··· 374 374 gpio1: gpio@2310000 { 375 375 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 376 376 reg = <0x0 0x2310000 0x0 0x10000>; 377 377 - interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 377 377 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 378 378 little-endian; 379 379 gpio-controller; 380 380 #gpio-cells = <2>; ··· 385 385 gpio2: gpio@2320000 { 386 386 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 387 387 reg = <0x0 0x2320000 0x0 0x10000>; 388 388 - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 388 388 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 389 389 little-endian; 390 390 gpio-controller; 391 391 #gpio-cells = <2>; ··· 396 396 gpio3: gpio@2330000 { 397 397 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 398 398 reg = <0x0 0x2330000 0x0 0x10000>; 399 399 - interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 399 399 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 400 400 little-endian; 401 401 gpio-controller; 402 402 #gpio-cells = <2>; ··· 407 407 ifc: memory-controller@2240000 { 408 408 compatible = "fsl,ifc"; 409 409 reg = <0x0 0x2240000 0x0 0x20000>; 410 410 - interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; 410 410 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 411 411 little-endian; 412 412 #address-cells = <2>; 413 413 #size-cells = <1>; ··· 419 419 #address-cells = <1>; 420 420 #size-cells = <0>; 421 421 reg = <0x0 0x2000000 0x0 0x10000>; 422 422 - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 422 422 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 423 423 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 424 424 QORIQ_CLK_PLL_DIV(8)>; 425 425 status = "disabled"; ··· 430 430 #address-cells = <1>; 431 431 #size-cells = <0>; 432 432 reg = <0x0 0x2010000 0x0 0x10000>; 433 433 - interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 433 433 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 434 434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 435 435 QORIQ_CLK_PLL_DIV(8)>; 436 436 status = "disabled"; ··· 441 441 #address-cells = <1>; 442 442 #size-cells = <0>; 443 443 reg = <0x0 0x2020000 0x0 0x10000>; 444 444 - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 444 444 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 445 445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 446 446 QORIQ_CLK_PLL_DIV(8)>; 447 447 status = "disabled"; ··· 452 452 #address-cells = <1>; 453 453 #size-cells = <0>; 454 454 reg = <0x0 0x2030000 0x0 0x10000>; 455 455 - interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; 455 455 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 456 456 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 457 457 QORIQ_CLK_PLL_DIV(8)>; 458 458 status = "disabled"; ··· 474 474 status = "disabled"; 475 475 }; 476 476 477 477 - esdhc: esdhc@2140000 { 477 477 + esdhc: mmc@2140000 { 478 478 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; 479 479 reg = <0x0 0x2140000 0x0 0x10000>; 480 480 - interrupts = <0 28 0x4>; /* Level high type */ 480 480 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 481 481 clock-frequency = <0>; 482 482 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; 483 483 voltage-ranges = <1800 1800 3300 3300>; ··· 490 490 usb0: usb@3100000 { 491 491 compatible = "snps,dwc3"; 492 492 reg = <0x0 0x3100000 0x0 0x10000>; 493 493 - interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 493 493 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 494 494 dr_mode = "host"; 495 495 snps,quirk-frame-length-adjustment = <0x20>; 496 496 snps,dis_rxdet_inp3_quirk; ··· 501 501 usb1: usb@3110000 { 502 502 compatible = "snps,dwc3"; 503 503 reg = <0x0 0x3110000 0x0 0x10000>; 504 504 - interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 504 504 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 505 505 dr_mode = "host"; 506 506 snps,quirk-frame-length-adjustment = <0x20>; 507 507 snps,dis_rxdet_inp3_quirk; ··· 514 514 reg = <0x0 0x3200000 0x0 0x10000>, 515 515 <0x7 0x100520 0x0 0x4>; 516 516 reg-names = "ahci", "sata-ecc"; 517 517 - interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; 517 517 + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 518 518 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 519 519 QORIQ_CLK_PLL_DIV(4)>; 520 520 dma-coherent; ··· 565 565 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ 566 566 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ 567 567 reg-names = "regs", "config"; 568 568 - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 568 568 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 569 569 interrupt-names = "aer"; 570 570 #address-cells = <3>; 571 571 #size-cells = <2>; ··· 604 604 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ 605 605 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */ 606 606 reg-names = "regs", "config"; 607 607 - interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 607 607 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 608 608 interrupt-names = "aer"; 609 609 #address-cells = <3>; 610 610 #size-cells = <2>; ··· 642 642 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */ 643 643 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */ 644 644 reg-names = "regs", "config"; 645 645 - interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 645 645 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ 646 646 interrupt-names = "aer"; 647 647 #address-cells = <3>; 648 648 #size-cells = <2>; ··· 880 880 }; 881 881 }; 882 882 883 883 - cluster1_core0_watchdog: wdt@c000000 { 883 883 + cluster1_core0_watchdog: watchdog@c000000 { 884 884 compatible = "arm,sp805", "arm,primecell"; 885 885 reg = <0x0 0xc000000 0x0 0x1000>; 886 886 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 890 890 clock-names = "wdog_clk", "apb_pclk"; 891 891 }; 892 892 893 893 - cluster1_core1_watchdog: wdt@c010000 { 893 893 + cluster1_core1_watchdog: watchdog@c010000 { 894 894 compatible = "arm,sp805", "arm,primecell"; 895 895 reg = <0x0 0xc010000 0x0 0x1000>; 896 896 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 900 900 clock-names = "wdog_clk", "apb_pclk"; 901 901 }; 902 902 903 903 - cluster1_core2_watchdog: wdt@c020000 { 903 903 + cluster1_core2_watchdog: watchdog@c020000 { 904 904 compatible = "arm,sp805", "arm,primecell"; 905 905 reg = <0x0 0xc020000 0x0 0x1000>; 906 906 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 910 910 clock-names = "wdog_clk", "apb_pclk"; 911 911 }; 912 912 913 913 - cluster1_core3_watchdog: wdt@c030000 { 913 913 + cluster1_core3_watchdog: watchdog@c030000 { 914 914 compatible = "arm,sp805", "arm,primecell"; 915 915 reg = <0x0 0xc030000 0x0 0x1000>; 916 916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 920 920 clock-names = "wdog_clk", "apb_pclk"; 921 921 }; 922 922 923 923 - cluster2_core0_watchdog: wdt@c100000 { 923 923 + cluster2_core0_watchdog: watchdog@c100000 { 924 924 compatible = "arm,sp805", "arm,primecell"; 925 925 reg = <0x0 0xc100000 0x0 0x1000>; 926 926 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 930 930 clock-names = "wdog_clk", "apb_pclk"; 931 931 }; 932 932 933 933 - cluster2_core1_watchdog: wdt@c110000 { 933 933 + cluster2_core1_watchdog: watchdog@c110000 { 934 934 compatible = "arm,sp805", "arm,primecell"; 935 935 reg = <0x0 0xc110000 0x0 0x1000>; 936 936 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 940 940 clock-names = "wdog_clk", "apb_pclk"; 941 941 }; 942 942 943 943 - cluster2_core2_watchdog: wdt@c120000 { 943 943 + cluster2_core2_watchdog: watchdog@c120000 { 944 944 compatible = "arm,sp805", "arm,primecell"; 945 945 reg = <0x0 0xc120000 0x0 0x1000>; 946 946 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 950 950 clock-names = "wdog_clk", "apb_pclk"; 951 951 }; 952 952 953 953 - cluster2_core3_watchdog: wdt@c130000 { 953 953 + cluster2_core3_watchdog: watchdog@c130000 { 954 954 compatible = "arm,sp805", "arm,primecell"; 955 955 reg = <0x0 0xc130000 0x0 0x1000>; 956 956 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 1040 1040 little-endian; 1041 1041 }; 1042 1042 1043 1043 - ftm_alarm0: timer@2800000 { 1043 1043 + ftm_alarm0: rtc@2800000 { 1044 1044 compatible = "fsl,ls1088a-ftm-alarm"; 1045 1045 reg = <0x0 0x2800000 0x0 0x10000>; 1046 1046 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi

reviewed

··· 15 15 / { 16 16 pmu { 17 17 compatible = "arm,cortex-a57-pmu"; 18 18 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 18 18 + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 19 19 }; 20 20 }; 21 21

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi

reviewed

··· 15 15 / { 16 16 pmu { 17 17 compatible = "arm,cortex-a72-pmu"; 18 18 - interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ 18 18 + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 19 19 }; 20 20 }; 21 21

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi

reviewed

··· 43 43 0x2 0x0 0x5 0x30000000 0x00010000 44 44 0x3 0x0 0x5 0x20000000 0x00010000>; 45 45 46 46 - nor@0,0 { 46 46 + flash@0,0 { 47 47 #address-cells = <1>; 48 48 #size-cells = <1>; 49 49 compatible = "cfi-flash";

+1 -1

arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi

reviewed

··· 21 21 0x2 0x0 0x5 0x30000000 0x00010000 22 22 0x3 0x0 0x5 0x20000000 0x00010000>; 23 23 24 24 - nor@0,0 { 24 24 + flash@0,0 { 25 25 #address-cells = <1>; 26 26 #size-cells = <1>; 27 27 compatible = "cfi-flash";

+93 -93

arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi

reviewed

··· 58 58 #size-cells = <2>; 59 59 ranges; 60 60 interrupt-controller; 61 61 - interrupts = <1 9 0x4>; 61 61 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 62 62 63 63 its: msi-controller@6020000 { 64 64 compatible = "arm,gic-v3-its"; ··· 80 80 }; 81 81 82 82 thermal-zones { 83 83 - ddr-controller1 { 83 83 + ddr-ctrl1-thermal { 84 84 polling-delay-passive = <1000>; 85 85 polling-delay = <5000>; 86 86 thermal-sensors = <&tmu 1>; ··· 94 94 }; 95 95 }; 96 96 97 97 - ddr-controller2 { 97 97 + ddr-ctrl2-thermal { 98 98 polling-delay-passive = <1000>; 99 99 polling-delay = <5000>; 100 100 thermal-sensors = <&tmu 2>; ··· 108 108 }; 109 109 }; 110 110 111 111 - ddr-controller3 { 111 111 + ddr-ctrl3-thermal { 112 112 polling-delay-passive = <1000>; 113 113 polling-delay = <5000>; 114 114 thermal-sensors = <&tmu 3>; ··· 122 122 }; 123 123 }; 124 124 125 125 - core-cluster1 { 125 125 + core-cluster1-thermal { 126 126 polling-delay-passive = <1000>; 127 127 polling-delay = <5000>; 128 128 thermal-sensors = <&tmu 4>; ··· 151 151 }; 152 152 }; 153 153 154 154 - core-cluster2 { 154 154 + core-cluster2-thermal { 155 155 polling-delay-passive = <1000>; 156 156 polling-delay = <5000>; 157 157 thermal-sensors = <&tmu 5>; ··· 180 180 }; 181 181 }; 182 182 183 183 - core-cluster3 { 183 183 + core-cluster3-thermal { 184 184 polling-delay-passive = <1000>; 185 185 polling-delay = <5000>; 186 186 thermal-sensors = <&tmu 6>; ··· 209 209 }; 210 210 }; 211 211 212 212 - core-cluster4 { 212 212 + core-cluster4-thermal { 213 213 polling-delay-passive = <1000>; 214 214 polling-delay = <5000>; 215 215 thermal-sensors = <&tmu 7>; ··· 241 241 242 242 timer: timer { 243 243 compatible = "arm,armv8-timer"; 244 244 - interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ 245 245 - <1 14 4>, /* Physical Non-Secure PPI, active-low */ 246 246 - <1 11 4>, /* Virtual PPI, active-low */ 247 247 - <1 10 4>; /* Hypervisor PPI, active-low */ 244 244 + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, /* Physical Secure PPI */ 245 245 + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, /* Physical Non-Secure PPI */ 246 246 + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, /* Virtual PPI */ 247 247 + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; /* Hypervisor PPI */ 248 248 }; 249 249 250 250 psci { ··· 314 314 tmu: tmu@1f80000 { 315 315 compatible = "fsl,qoriq-tmu"; 316 316 reg = <0x0 0x1f80000 0x0 0x10000>; 317 317 - interrupts = <0 23 0x4>; 317 317 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 318 318 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; 319 319 fsl,tmu-calibration = 320 320 <0x00000000 0x00000026>, ··· 362 362 reg = <0x0 0x21c0500 0x0 0x100>; 363 363 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 364 364 QORIQ_CLK_PLL_DIV(4)>; 365 365 - interrupts = <0 32 0x4>; /* Level high type */ 365 365 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 366 366 }; 367 367 368 368 serial1: serial@21c0600 { ··· 370 370 reg = <0x0 0x21c0600 0x0 0x100>; 371 371 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 372 372 QORIQ_CLK_PLL_DIV(4)>; 373 373 - interrupts = <0 32 0x4>; /* Level high type */ 373 373 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 374 374 }; 375 375 376 376 serial2: serial@21d0500 { ··· 378 378 reg = <0x0 0x21d0500 0x0 0x100>; 379 379 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 380 380 QORIQ_CLK_PLL_DIV(4)>; 381 381 - interrupts = <0 33 0x4>; /* Level high type */ 381 381 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 382 382 }; 383 383 384 384 serial3: serial@21d0600 { ··· 386 386 reg = <0x0 0x21d0600 0x0 0x100>; 387 387 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 388 388 QORIQ_CLK_PLL_DIV(4)>; 389 389 - interrupts = <0 33 0x4>; /* Level high type */ 389 389 + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 390 390 }; 391 391 392 392 - cluster1_core0_watchdog: wdt@c000000 { 392 392 + cluster1_core0_watchdog: watchdog@c000000 { 393 393 compatible = "arm,sp805", "arm,primecell"; 394 394 reg = <0x0 0xc000000 0x0 0x1000>; 395 395 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 399 399 clock-names = "wdog_clk", "apb_pclk"; 400 400 }; 401 401 402 402 - cluster1_core1_watchdog: wdt@c010000 { 402 402 + cluster1_core1_watchdog: watchdog@c010000 { 403 403 compatible = "arm,sp805", "arm,primecell"; 404 404 reg = <0x0 0xc010000 0x0 0x1000>; 405 405 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 409 409 clock-names = "wdog_clk", "apb_pclk"; 410 410 }; 411 411 412 412 - cluster2_core0_watchdog: wdt@c100000 { 412 412 + cluster2_core0_watchdog: watchdog@c100000 { 413 413 compatible = "arm,sp805", "arm,primecell"; 414 414 reg = <0x0 0xc100000 0x0 0x1000>; 415 415 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 419 419 clock-names = "wdog_clk", "apb_pclk"; 420 420 }; 421 421 422 422 - cluster2_core1_watchdog: wdt@c110000 { 422 422 + cluster2_core1_watchdog: watchdog@c110000 { 423 423 compatible = "arm,sp805", "arm,primecell"; 424 424 reg = <0x0 0xc110000 0x0 0x1000>; 425 425 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 429 429 clock-names = "wdog_clk", "apb_pclk"; 430 430 }; 431 431 432 432 - cluster3_core0_watchdog: wdt@c200000 { 432 432 + cluster3_core0_watchdog: watchdog@c200000 { 433 433 compatible = "arm,sp805", "arm,primecell"; 434 434 reg = <0x0 0xc200000 0x0 0x1000>; 435 435 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 439 439 clock-names = "wdog_clk", "apb_pclk"; 440 440 }; 441 441 442 442 - cluster3_core1_watchdog: wdt@c210000 { 442 442 + cluster3_core1_watchdog: watchdog@c210000 { 443 443 compatible = "arm,sp805", "arm,primecell"; 444 444 reg = <0x0 0xc210000 0x0 0x1000>; 445 445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 449 449 clock-names = "wdog_clk", "apb_pclk"; 450 450 }; 451 451 452 452 - cluster4_core0_watchdog: wdt@c300000 { 452 452 + cluster4_core0_watchdog: watchdog@c300000 { 453 453 compatible = "arm,sp805", "arm,primecell"; 454 454 reg = <0x0 0xc300000 0x0 0x1000>; 455 455 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 459 459 clock-names = "wdog_clk", "apb_pclk"; 460 460 }; 461 461 462 462 - cluster4_core1_watchdog: wdt@c310000 { 462 462 + cluster4_core1_watchdog: watchdog@c310000 { 463 463 compatible = "arm,sp805", "arm,primecell"; 464 464 reg = <0x0 0xc310000 0x0 0x1000>; 465 465 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL ··· 883 883 #iommu-cells = <1>; 884 884 stream-match-mask = <0x7C00>; 885 885 dma-coherent; 886 886 - interrupts = <0 13 4>, /* global secure fault */ 887 887 - <0 14 4>, /* combined secure interrupt */ 888 888 - <0 15 4>, /* global non-secure fault */ 889 889 - <0 16 4>, /* combined non-secure interrupt */ 886 886 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, /* global secure fault */ 887 887 + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, /* combined secure interrupt */ 888 888 + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, /* global non-secure fault */ 889 889 + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, /* combined non-secure interrupt */ 890 890 /* performance counter interrupts 0-7 */ 891 891 - <0 211 4>, <0 212 4>, 892 892 - <0 213 4>, <0 214 4>, 893 893 - <0 215 4>, <0 216 4>, 894 894 - <0 217 4>, <0 218 4>, 891 891 + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 892 892 + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 893 893 + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 894 894 + <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 895 895 /* per context interrupt, 64 interrupts */ 896 896 - <0 146 4>, <0 147 4>, 897 897 - <0 148 4>, <0 149 4>, 898 898 - <0 150 4>, <0 151 4>, 899 899 - <0 152 4>, <0 153 4>, 900 900 - <0 154 4>, <0 155 4>, 901 901 - <0 156 4>, <0 157 4>, 902 902 - <0 158 4>, <0 159 4>, 903 903 - <0 160 4>, <0 161 4>, 904 904 - <0 162 4>, <0 163 4>, 905 905 - <0 164 4>, <0 165 4>, 906 906 - <0 166 4>, <0 167 4>, 907 907 - <0 168 4>, <0 169 4>, 908 908 - <0 170 4>, <0 171 4>, 909 909 - <0 172 4>, <0 173 4>, 910 910 - <0 174 4>, <0 175 4>, 911 911 - <0 176 4>, <0 177 4>, 912 912 - <0 178 4>, <0 179 4>, 913 913 - <0 180 4>, <0 181 4>, 914 914 - <0 182 4>, <0 183 4>, 915 915 - <0 184 4>, <0 185 4>, 916 916 - <0 186 4>, <0 187 4>, 917 917 - <0 188 4>, <0 189 4>, 918 918 - <0 190 4>, <0 191 4>, 919 919 - <0 192 4>, <0 193 4>, 920 920 - <0 194 4>, <0 195 4>, 921 921 - <0 196 4>, <0 197 4>, 922 922 - <0 198 4>, <0 199 4>, 923 923 - <0 200 4>, <0 201 4>, 924 924 - <0 202 4>, <0 203 4>, 925 925 - <0 204 4>, <0 205 4>, 926 926 - <0 206 4>, <0 207 4>, 927 927 - <0 208 4>, <0 209 4>; 896 896 + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 897 897 + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 898 898 + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 899 899 + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 900 900 + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 901 901 + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 902 902 + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 903 903 + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 904 904 + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 905 905 + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 906 906 + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 907 907 + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 908 908 + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 909 909 + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 910 910 + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 911 911 + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 912 912 + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 913 913 + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 914 914 + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 915 915 + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 916 916 + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 917 917 + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 918 918 + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 919 919 + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 920 920 + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 921 921 + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 922 922 + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 923 923 + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 924 924 + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 925 925 + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 926 926 + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 927 927 + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 928 928 }; 929 929 930 930 dspi: spi@2100000 { ··· 933 933 #address-cells = <1>; 934 934 #size-cells = <0>; 935 935 reg = <0x0 0x2100000 0x0 0x10000>; 936 936 - interrupts = <0 26 0x4>; /* Level high type */ 936 936 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 937 937 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 938 938 QORIQ_CLK_PLL_DIV(4)>; 939 939 clock-names = "dspi"; 940 940 spi-num-chipselects = <5>; 941 941 }; 942 942 943 943 - esdhc: esdhc@2140000 { 943 943 + esdhc: mmc@2140000 { 944 944 status = "disabled"; 945 945 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 946 946 reg = <0x0 0x2140000 0x0 0x10000>; 947 947 - interrupts = <0 28 0x4>; /* Level high type */ 947 947 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 948 948 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 949 949 QORIQ_CLK_PLL_DIV(2)>; 950 950 voltage-ranges = <1800 1800 3300 3300>; ··· 956 956 gpio0: gpio@2300000 { 957 957 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 958 958 reg = <0x0 0x2300000 0x0 0x10000>; 959 959 - interrupts = <0 36 0x4>; /* Level high type */ 959 959 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 960 960 gpio-controller; 961 961 little-endian; 962 962 #gpio-cells = <2>; ··· 967 967 gpio1: gpio@2310000 { 968 968 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 969 969 reg = <0x0 0x2310000 0x0 0x10000>; 970 970 - interrupts = <0 36 0x4>; /* Level high type */ 970 970 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 971 971 gpio-controller; 972 972 little-endian; 973 973 #gpio-cells = <2>; ··· 978 978 gpio2: gpio@2320000 { 979 979 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 980 980 reg = <0x0 0x2320000 0x0 0x10000>; 981 981 - interrupts = <0 37 0x4>; /* Level high type */ 981 981 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 982 982 gpio-controller; 983 983 little-endian; 984 984 #gpio-cells = <2>; ··· 989 989 gpio3: gpio@2330000 { 990 990 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 991 991 reg = <0x0 0x2330000 0x0 0x10000>; 992 992 - interrupts = <0 37 0x4>; /* Level high type */ 992 992 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 993 993 gpio-controller; 994 994 little-endian; 995 995 #gpio-cells = <2>; ··· 1003 1003 #address-cells = <1>; 1004 1004 #size-cells = <0>; 1005 1005 reg = <0x0 0x2000000 0x0 0x10000>; 1006 1006 - interrupts = <0 34 0x4>; /* Level high type */ 1007 1007 - clock-names = "i2c"; 1006 1006 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1007 1007 + clock-names = "ipg"; 1008 1008 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1009 1009 QORIQ_CLK_PLL_DIV(4)>; 1010 1010 }; ··· 1015 1015 #address-cells = <1>; 1016 1016 #size-cells = <0>; 1017 1017 reg = <0x0 0x2010000 0x0 0x10000>; 1018 1018 - interrupts = <0 34 0x4>; /* Level high type */ 1019 1019 - clock-names = "i2c"; 1018 1018 + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1019 1019 + clock-names = "ipg"; 1020 1020 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1021 1021 QORIQ_CLK_PLL_DIV(4)>; 1022 1022 }; ··· 1027 1027 #address-cells = <1>; 1028 1028 #size-cells = <0>; 1029 1029 reg = <0x0 0x2020000 0x0 0x10000>; 1030 1030 - interrupts = <0 35 0x4>; /* Level high type */ 1031 1031 - clock-names = "i2c"; 1030 1030 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1031 1031 + clock-names = "ipg"; 1032 1032 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1033 1033 QORIQ_CLK_PLL_DIV(4)>; 1034 1034 }; ··· 1039 1039 #address-cells = <1>; 1040 1040 #size-cells = <0>; 1041 1041 reg = <0x0 0x2030000 0x0 0x10000>; 1042 1042 - interrupts = <0 35 0x4>; /* Level high type */ 1043 1043 - clock-names = "i2c"; 1042 1042 + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1043 1043 + clock-names = "ipg"; 1044 1044 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1045 1045 QORIQ_CLK_PLL_DIV(4)>; 1046 1046 }; ··· 1048 1048 ifc: memory-controller@2240000 { 1049 1049 compatible = "fsl,ifc"; 1050 1050 reg = <0x0 0x2240000 0x0 0x20000>; 1051 1051 - interrupts = <0 21 0x4>; /* Level high type */ 1051 1051 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1052 1052 little-endian; 1053 1053 #address-cells = <2>; 1054 1054 #size-cells = <1>; ··· 1077 1077 pcie1: pcie@3400000 { 1078 1078 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1079 1079 reg-names = "regs", "config"; 1080 1080 - interrupts = <0 108 0x4>; /* Level high type */ 1080 1080 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1081 1081 interrupt-names = "intr"; 1082 1082 #address-cells = <3>; 1083 1083 #size-cells = <2>; ··· 1099 1099 pcie2: pcie@3500000 { 1100 1100 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1101 1101 reg-names = "regs", "config"; 1102 1102 - interrupts = <0 113 0x4>; /* Level high type */ 1102 1102 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1103 1103 interrupt-names = "intr"; 1104 1104 #address-cells = <3>; 1105 1105 #size-cells = <2>; ··· 1121 1121 pcie3: pcie@3600000 { 1122 1122 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1123 1123 reg-names = "regs", "config"; 1124 1124 - interrupts = <0 118 0x4>; /* Level high type */ 1124 1124 + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1125 1125 interrupt-names = "intr"; 1126 1126 #address-cells = <3>; 1127 1127 #size-cells = <2>; ··· 1143 1143 pcie4: pcie@3700000 { 1144 1144 compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"; 1145 1145 reg-names = "regs", "config"; 1146 1146 - interrupts = <0 123 0x4>; /* Level high type */ 1146 1146 + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1147 1147 interrupt-names = "intr"; 1148 1148 #address-cells = <3>; 1149 1149 #size-cells = <2>; ··· 1166 1166 status = "disabled"; 1167 1167 compatible = "fsl,ls2080a-ahci"; 1168 1168 reg = <0x0 0x3200000 0x0 0x10000>; 1169 1169 - interrupts = <0 133 0x4>; /* Level high type */ 1169 1169 + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1170 1170 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1171 1171 QORIQ_CLK_PLL_DIV(4)>; 1172 1172 dma-coherent; ··· 1176 1176 status = "disabled"; 1177 1177 compatible = "fsl,ls2080a-ahci"; 1178 1178 reg = <0x0 0x3210000 0x0 0x10000>; 1179 1179 - interrupts = <0 136 0x4>; /* Level high type */ 1179 1179 + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1180 1180 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 1181 1181 QORIQ_CLK_PLL_DIV(4)>; 1182 1182 dma-coherent; ··· 1192 1192 usb0: usb@3100000 { 1193 1193 compatible = "snps,dwc3"; 1194 1194 reg = <0x0 0x3100000 0x0 0x10000>; 1195 1195 - interrupts = <0 80 0x4>; /* Level high type */ 1195 1195 + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1196 1196 dr_mode = "host"; 1197 1197 snps,quirk-frame-length-adjustment = <0x20>; 1198 1198 snps,dis_rxdet_inp3_quirk; ··· 1203 1203 usb1: usb@3110000 { 1204 1204 compatible = "snps,dwc3"; 1205 1205 reg = <0x0 0x3110000 0x0 0x10000>; 1206 1206 - interrupts = <0 81 0x4>; /* Level high type */ 1206 1206 + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1207 1207 dr_mode = "host"; 1208 1208 snps,quirk-frame-length-adjustment = <0x20>; 1209 1209 snps,dis_rxdet_inp3_quirk; ··· 1215 1215 ccn@4000000 { 1216 1216 compatible = "arm,ccn-504"; 1217 1217 reg = <0x0 0x04000000 0x0 0x01000000>; 1218 1218 - interrupts = <0 12 4>; 1218 1218 + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1219 1219 }; 1220 1220 1221 1221 rcpm: power-controller@1e34040 { ··· 1225 1225 little-endian; 1226 1226 }; 1227 1227 1228 1228 - ftm_alarm0: timer@2800000 { 1228 1228 + ftm_alarm0: rtc@2800000 { 1229 1229 compatible = "fsl,ls208xa-ftm-alarm"; 1230 1230 reg = <0x0 0x2800000 0x0 0x10000>; 1231 1231 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>; ··· 1236 1236 ddr1: memory-controller@1080000 { 1237 1237 compatible = "fsl,qoriq-memory-controller"; 1238 1238 reg = <0x0 0x1080000 0x0 0x1000>; 1239 1239 - interrupts = <0 17 0x4>; 1239 1239 + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1240 1240 little-endian; 1241 1241 }; 1242 1242 1243 1243 ddr2: memory-controller@1090000 { 1244 1244 compatible = "fsl,qoriq-memory-controller"; 1245 1245 reg = <0x0 0x1090000 0x0 0x1000>; 1246 1246 - interrupts = <0 18 0x4>; 1246 1246 + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1247 1247 little-endian; 1248 1248 }; 1249 1249

+28 -28

arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi

reviewed

··· 449 449 }; 450 450 451 451 thermal-zones { 452 452 - cluster6-7 { 452 452 + cluster6-7-thermal { 453 453 polling-delay-passive = <1000>; 454 454 polling-delay = <5000>; 455 455 thermal-sensors = <&tmu 0>; ··· 492 492 }; 493 493 }; 494 494 495 495 - ddr-cluster5 { 495 495 + ddr-cluster5-thermal { 496 496 polling-delay-passive = <1000>; 497 497 polling-delay = <5000>; 498 498 thermal-sensors = <&tmu 1>; ··· 512 512 }; 513 513 }; 514 514 515 515 - wriop { 515 515 + wriop-thermal { 516 516 polling-delay-passive = <1000>; 517 517 polling-delay = <5000>; 518 518 thermal-sensors = <&tmu 2>; ··· 532 532 }; 533 533 }; 534 534 535 535 - dce-qbman-hsio2 { 535 535 + dce-thermal { 536 536 polling-delay-passive = <1000>; 537 537 polling-delay = <5000>; 538 538 thermal-sensors = <&tmu 3>; ··· 552 552 }; 553 553 }; 554 554 555 555 - ccn-dpaa-tbu { 555 555 + ccn-thermal { 556 556 polling-delay-passive = <1000>; 557 557 polling-delay = <5000>; 558 558 thermal-sensors = <&tmu 4>; ··· 572 572 }; 573 573 }; 574 574 575 575 - cluster4-hsio3 { 575 575 + cluster4-thermal { 576 576 polling-delay-passive = <1000>; 577 577 polling-delay = <5000>; 578 578 thermal-sensors = <&tmu 5>; ··· 592 592 }; 593 593 }; 594 594 595 595 - cluster2-3 { 595 595 + cluster2-3-thermal { 596 596 polling-delay-passive = <1000>; 597 597 polling-delay = <5000>; 598 598 thermal-sensors = <&tmu 6>; ··· 745 745 #size-cells = <0>; 746 746 reg = <0x0 0x2000000 0x0 0x10000>; 747 747 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 748 748 - clock-names = "i2c"; 748 748 + clock-names = "ipg"; 749 749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 750 750 QORIQ_CLK_PLL_DIV(16)>; 751 751 pinctrl-names = "default", "gpio"; ··· 761 761 #size-cells = <0>; 762 762 reg = <0x0 0x2010000 0x0 0x10000>; 763 763 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 764 764 - clock-names = "i2c"; 764 764 + clock-names = "ipg"; 765 765 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 766 766 QORIQ_CLK_PLL_DIV(16)>; 767 767 pinctrl-names = "default", "gpio"; ··· 777 777 #size-cells = <0>; 778 778 reg = <0x0 0x2020000 0x0 0x10000>; 779 779 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 780 780 - clock-names = "i2c"; 780 780 + clock-names = "ipg"; 781 781 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 782 782 QORIQ_CLK_PLL_DIV(16)>; 783 783 pinctrl-names = "default", "gpio"; ··· 793 793 #size-cells = <0>; 794 794 reg = <0x0 0x2030000 0x0 0x10000>; 795 795 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 796 796 - clock-names = "i2c"; 796 796 + clock-names = "ipg"; 797 797 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 798 798 QORIQ_CLK_PLL_DIV(16)>; 799 799 pinctrl-names = "default", "gpio"; ··· 809 809 #size-cells = <0>; 810 810 reg = <0x0 0x2040000 0x0 0x10000>; 811 811 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 812 812 - clock-names = "i2c"; 812 812 + clock-names = "ipg"; 813 813 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 814 814 QORIQ_CLK_PLL_DIV(16)>; 815 815 pinctrl-names = "default", "gpio"; ··· 825 825 #size-cells = <0>; 826 826 reg = <0x0 0x2050000 0x0 0x10000>; 827 827 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 828 828 - clock-names = "i2c"; 828 828 + clock-names = "ipg"; 829 829 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 830 830 QORIQ_CLK_PLL_DIV(16)>; 831 831 pinctrl-names = "default", "gpio"; ··· 841 841 #size-cells = <0>; 842 842 reg = <0x0 0x2060000 0x0 0x10000>; 843 843 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 844 844 - clock-names = "i2c"; 844 844 + clock-names = "ipg"; 845 845 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 846 846 QORIQ_CLK_PLL_DIV(16)>; 847 847 pinctrl-names = "default", "gpio"; ··· 857 857 #size-cells = <0>; 858 858 reg = <0x0 0x2070000 0x0 0x10000>; 859 859 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 860 860 - clock-names = "i2c"; 860 860 + clock-names = "ipg"; 861 861 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 862 862 QORIQ_CLK_PLL_DIV(16)>; 863 863 pinctrl-names = "default", "gpio"; ··· 925 925 status = "disabled"; 926 926 }; 927 927 928 928 - esdhc0: esdhc@2140000 { 929 929 - compatible = "fsl,esdhc"; 928 928 + esdhc0: mmc@2140000 { 929 929 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 930 930 reg = <0x0 0x2140000 0x0 0x10000>; 931 931 - interrupts = <0 28 0x4>; /* Level high type */ 931 931 + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 932 932 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 933 933 QORIQ_CLK_PLL_DIV(2)>; 934 934 dma-coherent; ··· 939 939 status = "disabled"; 940 940 }; 941 941 942 942 - esdhc1: esdhc@2150000 { 943 943 - compatible = "fsl,esdhc"; 942 942 + esdhc1: mmc@2150000 { 943 943 + compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; 944 944 reg = <0x0 0x2150000 0x0 0x10000>; 945 945 - interrupts = <0 63 0x4>; /* Level high type */ 945 945 + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 946 946 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL 947 947 QORIQ_CLK_PLL_DIV(2)>; 948 948 dma-coherent; ··· 1027 1027 }; 1028 1028 1029 1029 gpio0: gpio@2300000 { 1030 1030 - compatible = "fsl,qoriq-gpio"; 1030 1030 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1031 1031 reg = <0x0 0x2300000 0x0 0x10000>; 1032 1032 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1033 1033 gpio-controller; ··· 1038 1038 }; 1039 1039 1040 1040 gpio1: gpio@2310000 { 1041 1041 - compatible = "fsl,qoriq-gpio"; 1041 1041 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1042 1042 reg = <0x0 0x2310000 0x0 0x10000>; 1043 1043 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1044 1044 gpio-controller; ··· 1049 1049 }; 1050 1050 1051 1051 gpio2: gpio@2320000 { 1052 1052 - compatible = "fsl,qoriq-gpio"; 1052 1052 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1053 1053 reg = <0x0 0x2320000 0x0 0x10000>; 1054 1054 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1055 1055 gpio-controller; ··· 1060 1060 }; 1061 1061 1062 1062 gpio3: gpio@2330000 { 1063 1063 - compatible = "fsl,qoriq-gpio"; 1063 1063 + compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 1064 1064 reg = <0x0 0x2330000 0x0 0x10000>; 1065 1065 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1066 1066 gpio-controller; ··· 1085 1085 little-endian; 1086 1086 }; 1087 1087 1088 1088 - ftm_alarm0: timer@2800000 { 1088 1088 + ftm_alarm0: rtc@2800000 { 1089 1089 compatible = "fsl,lx2160a-ftm-alarm"; 1090 1090 reg = <0x0 0x2800000 0x0 0x10000>; 1091 1091 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; ··· 1702 1702 pinmux_i2crv: pinmux@70010012c { 1703 1703 compatible = "pinctrl-single"; 1704 1704 reg = <0x00000007 0x0010012c 0x0 0xc>; 1705 1705 - #address-cells = <2>; 1706 1706 - #size-cells = <2>; 1705 1705 + #address-cells = <1>; 1706 1706 + #size-cells = <0>; 1707 1707 pinctrl-single,bit-per-mux; 1708 1708 pinctrl-single,register-width = <32>; 1709 1709 pinctrl-single,function-mask = <0x7>;

-1

arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi

reviewed

··· 447 447 <&lsio_mu13 2 1>, 448 448 <&lsio_mu13 3 0>, 449 449 <&lsio_mu13 3 1>; 450 450 - memory-region = <&dsp_reserved>; 451 450 status = "disabled"; 452 451 }; 453 452

+68

arch/arm64/boot/dts/freescale/imx8-ss-cm41.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + * Dong Aisheng <aisheng.dong@nxp.com> 5 5 + */ 6 6 + 7 7 + #include <dt-bindings/firmware/imx/rsrc.h> 8 8 + #include <dt-bindings/clock/imx8-lpcg.h> 9 9 + 10 10 + cm41_ipg_clk: clock-cm41-ipg { 11 11 + compatible = "fixed-clock"; 12 12 + #clock-cells = <0>; 13 13 + clock-frequency = <132000000>; 14 14 + clock-output-names = "cm41_ipg_clk"; 15 15 + }; 16 16 + 17 17 + cm41_subsys: bus@38000000 { 18 18 + compatible = "simple-bus"; 19 19 + #address-cells = <1>; 20 20 + #size-cells = <1>; 21 21 + ranges = <0x38000000 0x0 0x38000000 0x4000000>; 22 22 + interrupt-parent = <&cm41_intmux>; 23 23 + 24 24 + cm41_i2c: i2c@3b230000 { 25 25 + compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; 26 26 + reg = <0x3b230000 0x1000>; 27 27 + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 28 28 + clocks = <&cm41_i2c_lpcg IMX_LPCG_CLK_0>, 29 29 + <&cm41_i2c_lpcg IMX_LPCG_CLK_4>; 30 30 + clock-names = "per", "ipg"; 31 31 + assigned-clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>; 32 32 + assigned-clock-rates = <24000000>; 33 33 + power-domains = <&pd IMX_SC_R_M4_1_I2C>; 34 34 + status = "disabled"; 35 35 + }; 36 36 + 37 37 + cm41_intmux: intmux@3b400000 { 38 38 + compatible = "fsl,imx-intmux"; 39 39 + reg = <0x3b400000 0x1000>; 40 40 + interrupt-parent = <&gic>; 41 41 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 42 42 + <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 43 43 + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 44 44 + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 45 45 + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 46 46 + <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 47 47 + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 48 48 + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 49 49 + interrupt-controller; 50 50 + #interrupt-cells = <2>; 51 51 + clocks = <&cm41_ipg_clk>; 52 52 + clock-names = "ipg"; 53 53 + power-domains = <&pd IMX_SC_R_M4_1_INTMUX>; 54 54 + status = "disabled"; 55 55 + }; 56 56 + 57 57 + cm41_i2c_lpcg: clock-controller@3b630000 { 58 58 + compatible = "fsl,imx8qxp-lpcg"; 59 59 + reg = <0x3b630000 0x1000>; 60 60 + #clock-cells = <1>; 61 61 + clocks = <&clk IMX_SC_R_M4_1_I2C IMX_SC_PM_CLK_PER>, 62 62 + <&cm41_ipg_clk>; 63 63 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; 64 64 + clock-output-names = "cm41_lpcg_i2c_clk", 65 65 + "cm41_lpcg_i2c_ipg_clk"; 66 66 + power-domains = <&pd IMX_SC_R_M4_1_I2C>; 67 67 + }; 68 68 + };

+69

arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi

reviewed

··· 28 28 clock-output-names = "conn_ipg_clk"; 29 29 }; 30 30 31 31 + conn_bch_clk: clock-conn-bch { 32 32 + compatible = "fixed-clock"; 33 33 + #clock-cells = <0>; 34 34 + clock-frequency = <400000000>; 35 35 + clock-output-names = "conn_bch_clk"; 36 36 + }; 37 37 + 31 38 conn_subsys: bus@5b000000 { 32 39 compatible = "simple-bus"; 33 40 #address-cells = <1>; ··· 308 301 "usb3_phy_clk", 309 302 "usb3_aclk"; 310 303 power-domains = <&pd IMX_SC_R_USB_2_PHY>; 304 304 + }; 305 305 + 306 306 + rawnand_0_lpcg: clock-controller@5b290000 { 307 307 + compatible = "fsl,imx8qxp-lpcg"; 308 308 + reg = <0x5b290000 0x4>; 309 309 + #clock-cells = <1>; 310 310 + clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>, 311 311 + <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>, 312 312 + <&conn_axi_clk>, 313 313 + <&conn_axi_clk>; 314 314 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>, 315 315 + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>; 316 316 + clock-output-names = "gpmi_bch", 317 317 + "gpmi_io", 318 318 + "gpmi_apb", 319 319 + "gpmi_bch_apb"; 320 320 + power-domains = <&pd IMX_SC_R_NAND>; 321 321 + }; 322 322 + 323 323 + rawnand_4_lpcg: clock-controller@5b290004 { 324 324 + compatible = "fsl,imx8qxp-lpcg"; 325 325 + reg = <0x5b290004 0x10000>; 326 326 + #clock-cells = <1>; 327 327 + clocks = <&conn_axi_clk>; 328 328 + clock-indices = <IMX_LPCG_CLK_4>; 329 329 + clock-output-names = "apbhdma_hclk"; 330 330 + power-domains = <&pd IMX_SC_R_NAND>; 331 331 + }; 332 332 + 333 333 + dma_apbh: dma-controller@5b810000 { 334 334 + compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh"; 335 335 + reg = <0x5b810000 0x2000>; 336 336 + interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 337 337 + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 338 338 + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 339 339 + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 340 340 + #dma-cells = <1>; 341 341 + dma-channels = <4>; 342 342 + clocks = <&rawnand_4_lpcg IMX_LPCG_CLK_0>; 343 343 + power-domains = <&pd IMX_SC_R_NAND>; 344 344 + }; 345 345 + 346 346 + gpmi: nand-controller@5b812000{ 347 347 + compatible = "fsl,imx8qxp-gpmi-nand"; 348 348 + reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>; 349 349 + reg-names = "gpmi-nand", "bch"; 350 350 + #address-cells = <1>; 351 351 + #size-cells = <0>; 352 352 + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 353 353 + interrupt-names = "bch"; 354 354 + clocks = <&rawnand_0_lpcg IMX_LPCG_CLK_1>, 355 355 + <&rawnand_0_lpcg IMX_LPCG_CLK_4>, 356 356 + <&rawnand_0_lpcg IMX_LPCG_CLK_0>, 357 357 + <&rawnand_0_lpcg IMX_LPCG_CLK_5>; 358 358 + clock-names = "gpmi_io", "gpmi_apb", 359 359 + "gpmi_bch", "gpmi_bch_apb"; 360 360 + dmas = <&dma_apbh 0>; 361 361 + dma-names = "rx-tx"; 362 362 + power-domains = <&pd IMX_SC_R_NAND>; 363 363 + assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>; 364 364 + assigned-clock-rates = <50000000>; 365 365 + status = "disabled"; 311 366 }; 312 367 };

+277

arch/arm64/boot/dts/freescale/imx8dxl-evk.dts

reviewed

··· 24 24 stdout-path = &lpuart0; 25 25 }; 26 26 27 27 + imx8dxl-cm4 { 28 28 + compatible = "fsl,imx8qxp-cm4"; 29 29 + clocks = <&clk_dummy>; 30 30 + mbox-names = "tx", "rx", "rxdb"; 31 31 + mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>; 32 32 + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 33 33 + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 34 34 + power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>; 35 35 + fsl,resource-id = <IMX_SC_R_M4_0_PID0>; 36 36 + fsl,entry-address = <0x34fe0000>; 37 37 + }; 38 38 + 39 39 + 27 40 memory@80000000 { 28 41 device_type = "memory"; 29 42 reg = <0x00000000 0x80000000 0 0x40000000>; ··· 63 50 size = <0 0x14000000>; 64 51 alloc-ranges = <0 0x98000000 0 0x14000000>; 65 52 linux,cma-default; 53 53 + }; 54 54 + 55 55 + vdev0vring0: memory0@90000000 { 56 56 + reg = <0 0x90000000 0 0x8000>; 57 57 + no-map; 58 58 + }; 59 59 + 60 60 + vdev0vring1: memory@90008000 { 61 61 + reg = <0 0x90008000 0 0x8000>; 62 62 + no-map; 63 63 + }; 64 64 + 65 65 + vdev1vring0: memory@90010000 { 66 66 + reg = <0 0x90010000 0 0x8000>; 67 67 + no-map; 68 68 + }; 69 69 + 70 70 + vdev1vring1: memory@90018000 { 71 71 + reg = <0 0x90018000 0 0x8000>; 72 72 + no-map; 73 73 + }; 74 74 + 75 75 + rsc_table: memory-rsc-table@900ff000 { 76 76 + reg = <0 0x900ff000 0 0x1000>; 77 77 + no-map; 78 78 + }; 79 79 + 80 80 + vdevbuffer: memory-vdevbuffer@90400000 { 81 81 + compatible = "shared-dma-pool"; 82 82 + reg = <0 0x90400000 0 0x100000>; 83 83 + no-map; 66 84 }; 67 85 }; 68 86 ··· 181 137 enable-active-high; 182 138 regulator-always-on; 183 139 }; 140 140 + 141 141 + bt_sco_codec: audio-codec-bt { 142 142 + compatible = "linux,bt-sco"; 143 143 + #sound-dai-cells = <1>; 144 144 + }; 145 145 + 146 146 + sound-bt-sco { 147 147 + compatible = "simple-audio-card"; 148 148 + simple-audio-card,name = "bt-sco-audio"; 149 149 + simple-audio-card,format = "dsp_a"; 150 150 + simple-audio-card,bitclock-inversion; 151 151 + simple-audio-card,frame-master = <&btcpu>; 152 152 + simple-audio-card,bitclock-master = <&btcpu>; 153 153 + 154 154 + btcpu: simple-audio-card,cpu { 155 155 + sound-dai = <&sai0>; 156 156 + dai-tdm-slot-num = <2>; 157 157 + dai-tdm-slot-width = <16>; 158 158 + }; 159 159 + 160 160 + simple-audio-card,codec { 161 161 + sound-dai = <&bt_sco_codec 1>; 162 162 + }; 163 163 + }; 164 164 + 165 165 + sound-wm8960-1 { 166 166 + compatible = "fsl,imx-audio-wm8960"; 167 167 + model = "wm8960-audio"; 168 168 + audio-cpu = <&sai1>; 169 169 + audio-codec = <&wm8960_1>; 170 170 + audio-asrc = <&asrc0>; 171 171 + audio-routing = "Headphone Jack", "HP_L", 172 172 + "Headphone Jack", "HP_R", 173 173 + "Ext Spk", "SPK_LP", 174 174 + "Ext Spk", "SPK_LN", 175 175 + "Ext Spk", "SPK_RP", 176 176 + "Ext Spk", "SPK_RN", 177 177 + "LINPUT1", "Mic Jack", 178 178 + "Mic Jack", "MICB"; 179 179 + }; 180 180 + 181 181 + sound-wm8960-2 { 182 182 + compatible = "fsl,imx-audio-wm8960"; 183 183 + model = "wm8960-audio-2"; 184 184 + audio-cpu = <&sai2>; 185 185 + audio-codec = <&wm8960_2>; 186 186 + audio-routing = "Headphone Jack", "HP_L", 187 187 + "Headphone Jack", "HP_R", 188 188 + "Ext Spk", "SPK_LP", 189 189 + "Ext Spk", "SPK_LN", 190 190 + "Ext Spk", "SPK_RP", 191 191 + "Ext Spk", "SPK_RN", 192 192 + "LINPUT1", "Mic Jack", 193 193 + "Mic Jack", "MICB"; 194 194 + }; 195 195 + 196 196 + sound-wm8960-3 { 197 197 + compatible = "fsl,imx-audio-wm8960"; 198 198 + model = "wm8960-audio-3"; 199 199 + audio-cpu = <&sai3>; 200 200 + audio-codec = <&wm8960_3>; 201 201 + audio-routing = "Headphone Jack", "HP_L", 202 202 + "Headphone Jack", "HP_R", 203 203 + "Ext Spk", "SPK_LP", 204 204 + "Ext Spk", "SPK_LN", 205 205 + "Ext Spk", "SPK_RP", 206 206 + "Ext Spk", "SPK_RN", 207 207 + "LINPUT1", "Mic Jack", 208 208 + "Mic Jack", "MICB"; 209 209 + }; 184 210 }; 185 211 186 212 &adc0 { 187 213 vref-supply = <&reg_vref_1v8>; 214 214 + status = "okay"; 215 215 + }; 216 216 + 217 217 + &asrc0 { 218 218 + fsl,asrc-rate = <48000>; 188 219 status = "okay"; 189 220 }; 190 221 ··· 390 271 }; 391 272 }; 392 273 274 274 + i2c@1 { 275 275 + #address-cells = <1>; 276 276 + #size-cells = <0>; 277 277 + reg = <0x1>; 278 278 + 279 279 + wm8960_1: audio-codec@1a { 280 280 + compatible = "wlf,wm8960"; 281 281 + reg = <0x1a>; 282 282 + clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; 283 283 + clock-names = "mclk"; 284 284 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 285 285 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 286 286 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 287 287 + <&mclkout1_lpcg IMX_LPCG_CLK_0>; 288 288 + assigned-clock-rates = <786432000>, 289 289 + <49152000>, 290 290 + <12288000>, 291 291 + <12288000>; 292 292 + wlf,shared-lrclk; 293 293 + wlf,hp-cfg = <2 2 3>; 294 294 + wlf,gpio-cfg = <1 3>; 295 295 + }; 296 296 + }; 297 297 + 298 298 + i2c@2 { 299 299 + #address-cells = <1>; 300 300 + #size-cells = <0>; 301 301 + reg = <0x2>; 302 302 + 303 303 + wm8960_2: audio-codec@1a { 304 304 + compatible = "wlf,wm8960"; 305 305 + reg = <0x1a>; 306 306 + clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; 307 307 + clock-names = "mclk"; 308 308 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 309 309 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 310 310 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 311 311 + <&mclkout1_lpcg IMX_LPCG_CLK_0>; 312 312 + assigned-clock-rates = <786432000>, 313 313 + <49152000>, 314 314 + <12288000>, 315 315 + <12288000>; 316 316 + wlf,shared-lrclk; 317 317 + wlf,hp-cfg = <2 2 3>; 318 318 + wlf,gpio-cfg = <1 3>; 319 319 + }; 320 320 + }; 321 321 + 322 322 + i2c@3 { 323 323 + #address-cells = <1>; 324 324 + #size-cells = <0>; 325 325 + reg = <0x3>; 326 326 + 327 327 + wm8960_3: audio-codec@1a { 328 328 + compatible = "wlf,wm8960"; 329 329 + reg = <0x1a>; 330 330 + clocks = <&mclkout1_lpcg IMX_LPCG_CLK_0>; 331 331 + clock-names = "mclk"; 332 332 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 333 333 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 334 334 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 335 335 + <&mclkout1_lpcg IMX_LPCG_CLK_0>; 336 336 + assigned-clock-rates = <786432000>, 337 337 + <49152000>, 338 338 + <12288000>, 339 339 + <12288000>; 340 340 + wlf,shared-lrclk; 341 341 + wlf,hp-cfg = <2 2 3>; 342 342 + wlf,gpio-cfg = <1 3>; 343 343 + }; 344 344 + }; 345 345 + 393 346 i2c@4 { 394 347 #address-cells = <1>; 395 348 #size-cells = <0>; ··· 549 358 status = "okay"; 550 359 }; 551 360 361 361 + &lsio_mu5 { 362 362 + status = "okay"; 363 363 + }; 364 364 + 552 365 &flexcan2 { 553 366 pinctrl-names = "default"; 554 367 pinctrl-0 = <&pinctrl_flexcan2>; ··· 582 387 }; 583 388 584 389 &lsio_gpio5 { 390 390 + status = "okay"; 391 391 + }; 392 392 + 393 393 + &sai0 { 394 394 + pinctrl-names = "default"; 395 395 + pinctrl-0 = <&pinctrl_sai0>; 396 396 + #sound-dai-cells = <0>; 397 397 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 398 398 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 399 399 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 400 400 + <&sai0_lpcg IMX_LPCG_CLK_0>; 401 401 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 402 402 + status = "okay"; 403 403 + }; 404 404 + 405 405 + &sai1 { 406 406 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 407 407 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 408 408 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 409 409 + <&sai1_lpcg IMX_LPCG_CLK_0>; 410 410 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 411 411 + pinctrl-names = "default"; 412 412 + pinctrl-0 = <&pinctrl_sai1>; 413 413 + status = "okay"; 414 414 + }; 415 415 + 416 416 + &sai2 { 417 417 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 418 418 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 419 419 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 420 420 + <&sai2_lpcg IMX_LPCG_CLK_0>; 421 421 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 422 422 + pinctrl-names = "default"; 423 423 + pinctrl-0 = <&pinctrl_sai2>; 424 424 + fsl,sai-asynchronous; 425 425 + status = "okay"; 426 426 + }; 427 427 + 428 428 + &sai3 { 429 429 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 430 430 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 431 431 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 432 432 + <&sai3_lpcg IMX_LPCG_CLK_0>; 433 433 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 434 434 + pinctrl-names = "default"; 435 435 + pinctrl-0 = <&pinctrl_sai3>; 436 436 + fsl,sai-asynchronous; 585 437 status = "okay"; 586 438 }; 587 439 ··· 871 629 IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020 872 630 IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 873 631 IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 632 632 + >; 633 633 + }; 634 634 + 635 635 + pinctrl_sai0: sai0grp { 636 636 + fsl,pins = < 637 637 + IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060 638 638 + IMX8DXL_SPI0_CS1_ADMA_SAI0_RXC 0x06000040 639 639 + IMX8DXL_SPI0_SCK_ADMA_SAI0_TXC 0x06000060 640 640 + IMX8DXL_SPI0_SDI_ADMA_SAI0_TXD 0x06000060 641 641 + IMX8DXL_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 642 642 + >; 643 643 + }; 644 644 + 645 645 + pinctrl_sai1: sai1grp { 646 646 + fsl,pins = < 647 647 + IMX8DXL_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000040 648 648 + IMX8DXL_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000040 649 649 + IMX8DXL_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000060 650 650 + IMX8DXL_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000060 651 651 + >; 652 652 + }; 653 653 + 654 654 + pinctrl_sai2: sai2grp { 655 655 + fsl,pins = < 656 656 + IMX8DXL_SNVS_TAMPER_OUT3_ADMA_SAI2_RXC 0x06000040 657 657 + IMX8DXL_SNVS_TAMPER_IN0_ADMA_SAI2_RXFS 0x06000040 658 658 + IMX8DXL_SNVS_TAMPER_OUT4_ADMA_SAI2_RXD 0x06000060 659 659 + >; 660 660 + }; 661 661 + 662 662 + pinctrl_sai3: sai3grp { 663 663 + fsl,pins = < 664 664 + IMX8DXL_SNVS_TAMPER_IN1_ADMA_SAI3_RXC 0x06000040 665 665 + IMX8DXL_SNVS_TAMPER_IN3_ADMA_SAI3_RXFS 0x06000040 666 666 + IMX8DXL_SNVS_TAMPER_IN2_ADMA_SAI3_RXD 0x06000060 874 667 >; 875 668 }; 876 669

+78

arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi

reviewed

··· 3 3 * Copyright 2019~2020, 2022 NXP 4 4 */ 5 5 6 6 + /delete-node/ &asrc1; 7 7 + /delete-node/ &asrc1_lpcg; 8 8 + /delete-node/ &adc1; 9 9 + /delete-node/ &adc1_lpcg; 10 10 + /delete-node/ &amix; 11 11 + /delete-node/ &amix_lpcg; 12 12 + /delete-node/ &edma1; 13 13 + /delete-node/ &esai0; 14 14 + /delete-node/ &esai0_lpcg; 15 15 + /delete-node/ &sai4; 16 16 + /delete-node/ &sai4_lpcg; 17 17 + /delete-node/ &sai5; 18 18 + /delete-node/ &sai5_lpcg; 19 19 + 20 20 + &acm { 21 21 + compatible = "fsl,imx8dxl-acm"; 22 22 + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, 23 23 + <&pd IMX_SC_R_AUDIO_CLK_1>, 24 24 + <&pd IMX_SC_R_MCLK_OUT_0>, 25 25 + <&pd IMX_SC_R_MCLK_OUT_1>, 26 26 + <&pd IMX_SC_R_AUDIO_PLL_0>, 27 27 + <&pd IMX_SC_R_AUDIO_PLL_1>, 28 28 + <&pd IMX_SC_R_ASRC_0>, 29 29 + <&pd IMX_SC_R_SAI_0>, 30 30 + <&pd IMX_SC_R_SAI_1>, 31 31 + <&pd IMX_SC_R_SAI_2>, 32 32 + <&pd IMX_SC_R_SAI_3>, 33 33 + <&pd IMX_SC_R_SPDIF_0>, 34 34 + <&pd IMX_SC_R_MQS_0>; 35 35 + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, 36 36 + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, 37 37 + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 38 38 + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 39 39 + <&clk_ext_aud_mclk0>, 40 40 + <&clk_ext_aud_mclk1>, 41 41 + <&clk_spdif0_rx>, 42 42 + <&clk_sai0_rx_bclk>, 43 43 + <&clk_sai0_tx_bclk>, 44 44 + <&clk_sai1_rx_bclk>, 45 45 + <&clk_sai1_tx_bclk>, 46 46 + <&clk_sai2_rx_bclk>, 47 47 + <&clk_sai3_rx_bclk>; 48 48 + clock-names = "aud_rec_clk0_lpcg_clk", 49 49 + "aud_rec_clk1_lpcg_clk", 50 50 + "aud_pll_div_clk0_lpcg_clk", 51 51 + "aud_pll_div_clk1_lpcg_clk", 52 52 + "ext_aud_mclk0", 53 53 + "ext_aud_mclk1", 54 54 + "spdif0_rx", 55 55 + "sai0_rx_bclk", 56 56 + "sai0_tx_bclk", 57 57 + "sai1_rx_bclk", 58 58 + "sai1_tx_bclk", 59 59 + "sai2_rx_bclk", 60 60 + "sai3_rx_bclk"; 61 61 + }; 62 62 + 6 63 &audio_ipg_clk { 7 64 clock-frequency = <160000000>; 8 65 }; ··· 233 176 234 177 &lpspi3 { 235 178 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 179 179 + }; 180 180 + 181 181 + &sai0 { 182 182 + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 183 183 + }; 184 184 + 185 185 + &sai1 { 186 186 + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 187 187 + }; 188 188 + 189 189 + &sai2 { 190 190 + interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 191 191 + }; 192 192 + 193 193 + &sai3 { 194 194 + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 195 195 + }; 196 196 + 197 197 + &spdif0 { 198 198 + interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* rx */ 199 199 + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* tx */ 236 200 };

+11

arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi

reviewed

··· 108 108 109 109 }; 110 110 111 111 + &dma_apbh { 112 112 + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 113 113 + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 114 114 + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 115 115 + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 116 116 + }; 117 117 + 111 118 &enet0_lpcg { 112 119 clocks = <&conn_enet0_root_clk>, 113 120 <&conn_enet0_root_clk>, ··· 132 125 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 133 126 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>; 134 127 assigned-clock-rates = <125000000>; 128 128 + }; 129 129 + 130 130 + &gpmi { 131 131 + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 135 132 }; 136 133 137 134 &usdhc1 {

+1 -1

arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

reviewed

··· 400 400 pinctrl-0 = <&pinctrl_typec1>; 401 401 reg = <0x50>; 402 402 interrupt-parent = <&gpio2>; 403 403 - interrupts = <11 8>; 403 403 + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 404 404 status = "okay"; 405 405 406 406 typec1_con: connector {

+218

arch/arm64/boot/dts/freescale/imx8mm-iot-gateway.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + // 3 3 + // Copyright 2020 CompuLab 4 4 + 5 5 + #include "imx8mm-ucm-som.dtsi" 6 6 + #include <dt-bindings/phy/phy-imx8-pcie.h> 7 7 + / { 8 8 + model = "CompuLab i.MX8MM IoT Gateway"; 9 9 + compatible = "compulab,imx8mm-iot-gateway", "compulab,imx8mm-ucm-som", "fsl,imx8mm"; 10 10 + 11 11 + regulator-usbhub-ena { 12 12 + compatible = "regulator-fixed"; 13 13 + regulator-name = "usbhub_ena"; 14 14 + regulator-min-microvolt = <3300000>; 15 15 + regulator-max-microvolt = <3300000>; 16 16 + gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>; 17 17 + enable-active-high; 18 18 + regulator-always-on; 19 19 + }; 20 20 + 21 21 + regulator-usbhub-rst { 22 22 + compatible = "regulator-fixed"; 23 23 + regulator-name = "usbhub_rst"; 24 24 + regulator-min-microvolt = <3300000>; 25 25 + regulator-max-microvolt = <3300000>; 26 26 + gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>; 27 27 + enable-active-high; 28 28 + regulator-always-on; 29 29 + }; 30 30 + 31 31 + regulator-uart1-mode { 32 32 + compatible = "regulator-fixed"; 33 33 + regulator-name = "uart1_mode"; 34 34 + regulator-min-microvolt = <3300000>; 35 35 + regulator-max-microvolt = <3300000>; 36 36 + gpio = <&gpio4 26 GPIO_ACTIVE_HIGH>; 37 37 + enable-active-high; 38 38 + regulator-always-on; 39 39 + }; 40 40 + 41 41 + regulator-uart1-duplex { 42 42 + compatible = "regulator-fixed"; 43 43 + regulator-name = "uart1_duplex"; 44 44 + regulator-min-microvolt = <3300000>; 45 45 + regulator-max-microvolt = <3300000>; 46 46 + gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>; 47 47 + enable-active-high; 48 48 + regulator-always-on; 49 49 + }; 50 50 + 51 51 + regulator-uart1-shdn { 52 52 + compatible = "regulator-fixed"; 53 53 + regulator-name = "uart1_shdn"; 54 54 + regulator-min-microvolt = <3300000>; 55 55 + regulator-max-microvolt = <3300000>; 56 56 + gpio = <&gpio5 5 GPIO_ACTIVE_HIGH>; 57 57 + enable-active-high; 58 58 + regulator-always-on; 59 59 + }; 60 60 + 61 61 + regulator-uart1-trmen { 62 62 + compatible = "regulator-fixed"; 63 63 + regulator-name = "uart1_trmen"; 64 64 + regulator-min-microvolt = <3300000>; 65 65 + regulator-max-microvolt = <3300000>; 66 66 + gpio = <&gpio4 25 GPIO_ACTIVE_LOW>; 67 67 + regulator-always-on; 68 68 + }; 69 69 + 70 70 + regulator-usdhc2-v { 71 71 + compatible = "regulator-fixed"; 72 72 + regulator-name = "usdhc2_v"; 73 73 + regulator-min-microvolt = <3300000>; 74 74 + regulator-max-microvolt = <3300000>; 75 75 + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; 76 76 + enable-active-high; 77 77 + regulator-always-on; 78 78 + }; 79 79 + 80 80 + regulator-mpcie2-rst { 81 81 + compatible = "regulator-fixed"; 82 82 + regulator-name = "mpcie2_rst"; 83 83 + regulator-min-microvolt = <3300000>; 84 84 + regulator-max-microvolt = <3300000>; 85 85 + gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 86 86 + enable-active-high; 87 87 + regulator-always-on; 88 88 + }; 89 89 + 90 90 + regulator-mpcie2lora-dis { 91 91 + compatible = "regulator-fixed"; 92 92 + regulator-name = "mpcie2lora_dis"; 93 93 + regulator-min-microvolt = <3300000>; 94 94 + regulator-max-microvolt = <3300000>; 95 95 + gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; 96 96 + enable-active-high; 97 97 + regulator-always-on; 98 98 + }; 99 99 + 100 100 + pcie0_refclk: clock-pcie0-refclk { 101 101 + compatible = "fixed-clock"; 102 102 + #clock-cells = <0>; 103 103 + clock-frequency = <100000000>; 104 104 + }; 105 105 + }; 106 106 + 107 107 + &i2c1 { 108 108 + clock-frequency = <100000>; 109 109 + pinctrl-names = "default"; 110 110 + pinctrl-0 = <&pinctrl_i2c1>; 111 111 + status = "okay"; 112 112 + 113 113 + eeprom@54 { 114 114 + compatible = "atmel,24c08"; 115 115 + reg = <0x54>; 116 116 + pagesize = <16>; 117 117 + }; 118 118 + }; 119 119 + 120 120 + &ecspi1 { 121 121 + pinctrl-names = "default"; 122 122 + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 123 123 + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 124 124 + status = "okay"; 125 125 + }; 126 126 + 127 127 + &pcie_phy { 128 128 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 129 129 + fsl,tx-deemph-gen1 = <0x2d>; 130 130 + fsl,tx-deemph-gen2 = <0xf>; 131 131 + fsl,clkreq-unsupported; 132 132 + clocks = <&pcie0_refclk>; 133 133 + clock-names = "ref"; 134 134 + status = "okay"; 135 135 + }; 136 136 + 137 137 + &pcie0 { 138 138 + pinctrl-names = "default"; 139 139 + pinctrl-0 = <&pinctrl_pcie0>; 140 140 + reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; 141 141 + status = "okay"; 142 142 + }; 143 143 + 144 144 + &usbotg1 { 145 145 + dr_mode = "host"; 146 146 + status = "okay"; 147 147 + }; 148 148 + 149 149 + &usbotg2 { 150 150 + #address-cells = <1>; 151 151 + #size-cells = <0>; 152 152 + dr_mode = "host"; 153 153 + usb-role-switch; 154 154 + status = "okay"; 155 155 + 156 156 + usbhub@1 { 157 157 + compatible = "usb424,9514"; 158 158 + reg = <1>; 159 159 + pinctrl-names = "default"; 160 160 + pinctrl-0 = <&pinctrl_usb9514>; 161 161 + #address-cells = <1>; 162 162 + #size-cells = <0>; 163 163 + 164 164 + ethernet: ethernet@1 { 165 165 + compatible = "usb424,ec00"; 166 166 + reg = <1>; 167 167 + }; 168 168 + }; 169 169 + }; 170 170 + 171 171 + &usdhc2 { 172 172 + pinctrl-names = "default"; 173 173 + pinctrl-0 = <&pinctrl_usdhc2>; 174 174 + bus-width = <4>; 175 175 + mmc-ddr-1_8v; 176 176 + non-removable; 177 177 + status = "okay"; 178 178 + }; 179 179 + 180 180 + &iomuxc { 181 181 + pinctrl-names = "default"; 182 182 + pinctrl-0 = <&pinctrl_hog>; 183 183 + 184 184 + pinctrl_hog: hoggrp { 185 185 + fsl,pins = < 186 186 + /* mPCIe2 */ 187 187 + MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x140 188 188 + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x140 189 189 + >; 190 190 + }; 191 191 + 192 192 + pinctrl_ecspi1: ecspi1grp { 193 193 + fsl,pins = < 194 194 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 195 195 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 196 196 + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 197 197 + >; 198 198 + }; 199 199 + 200 200 + pinctrl_ecspi1_cs: ecspi1csgrp { 201 201 + fsl,pins = < 202 202 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000 203 203 + >; 204 204 + }; 205 205 + 206 206 + pinctrl_pcie0: pcie0grp { 207 207 + fsl,pins = < 208 208 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x140 209 209 + >; 210 210 + }; 211 211 + 212 212 + pinctrl_usb9514: usb9514grp { 213 213 + fsl,pins = < 214 214 + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x140 /* USB_PS_EN */ 215 215 + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140 /* HUB_RSTn */ 216 216 + >; 217 217 + }; 218 218 + };

+72

arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs232.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + /* 3 3 + * Copyright (C) 2021 PHYTEC Messtechnik GmbH 4 4 + * Author: Jens Lang <j.lang@phytec.de> 5 5 + * 6 6 + * Tauri-L 2 x RS232: 7 7 + * - GPIO3_20 uart4_rs485_en needs to be driven low (inactive) 8 8 + */ 9 9 + 10 10 + #include <dt-bindings/clock/imx8mm-clock.h> 11 11 + #include <dt-bindings/gpio/gpio.h> 12 12 + #include "imx8mm-pinfunc.h" 13 13 + 14 14 + /dts-v1/; 15 15 + /plugin/; 16 16 + 17 17 + &{/} { 18 18 + compatible = "phytec,imx8mm-phygate-tauri-l"; 19 19 + 20 20 + }; 21 21 + 22 22 + &gpio3 { 23 23 + pinctrl-names = "default"; 24 24 + pinctrcl-0 = <&pinctrl_gpio3_hog>; 25 25 + 26 26 + uart4_rs485_en { 27 27 + gpio-hog; 28 28 + gpios = <20 GPIO_ACTIVE_HIGH>; 29 29 + output-low; 30 30 + line-name = "uart4_rs485_en"; 31 31 + }; 32 32 + }; 33 33 + 34 34 + /* UART2 - RS232 */ 35 35 + &uart2 { 36 36 + pinctrl-names = "default"; 37 37 + pinctrl-0 = <&pinctrl_uart2>; 38 38 + assigned-clocks = <&clk IMX8MM_CLK_UART2>; 39 39 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 40 40 + status = "okay"; 41 41 + }; 42 42 + 43 43 + /* UART4 - RS232 */ 44 44 + &uart4 { 45 45 + pinctrl-names = "default"; 46 46 + pinctrl-0 = <&pinctrl_uart4>; 47 47 + assigned-clocks = <&clk IMX8MM_CLK_UART4>; 48 48 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 49 49 + status = "okay"; 50 50 + }; 51 51 + 52 52 + &iomuxc { 53 53 + pinctrl_gpio3_hog: gpio3hoggrp { 54 54 + fsl,pins = < 55 55 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 56 56 + >; 57 57 + }; 58 58 + 59 59 + pinctrl_uart2: uart2grp { 60 60 + fsl,pins = < 61 61 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 62 62 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 63 63 + >; 64 64 + }; 65 65 + 66 66 + pinctrl_uart4: uart4grp { 67 67 + fsl,pins = < 68 68 + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 69 69 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 70 70 + >; 71 71 + }; 72 72 + };

+76

arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rs485.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + /* 3 3 + * Copyright (C) 2021 PHYTEC Messtechnik GmbH 4 4 + * Author: Jens Lang <j.lang@phytec.de> 5 5 + * 6 6 + * Tauri-L RS232 + RS485: 7 7 + * - GPIO3_20 uart4_rs485_en needs to be driven high (active) 8 8 + * - GPIO3_25 RS485_DE Driver enable 9 9 + */ 10 10 + 11 11 + #include <dt-bindings/clock/imx8mm-clock.h> 12 12 + #include <dt-bindings/gpio/gpio.h> 13 13 + #include "imx8mm-pinfunc.h" 14 14 + 15 15 + /dts-v1/; 16 16 + /plugin/; 17 17 + 18 18 + &{/} { 19 19 + compatible = "phytec,imx8mm-phygate-tauri-l"; 20 20 + 21 21 + }; 22 22 + 23 23 + &gpio3 { 24 24 + pinctrl-names = "default"; 25 25 + pinctrcl-0 = <&pinctrl_gpio3_hog>; 26 26 + 27 27 + uart4_rs485_en { 28 28 + gpio-hog; 29 29 + gpios = <20 GPIO_ACTIVE_HIGH>; 30 30 + output-high; 31 31 + line-name = "uart4_rs485_en"; 32 32 + }; 33 33 + }; 34 34 + 35 35 + /* UART2 - RS232 */ 36 36 + &uart2 { 37 37 + pinctrl-names = "default"; 38 38 + pinctrl-0 = <&pinctrl_uart2>; 39 39 + assigned-clocks = <&clk IMX8MM_CLK_UART2>; 40 40 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 41 41 + status = "okay"; 42 42 + }; 43 43 + 44 44 + /* UART4 - RS485 */ 45 45 + &uart4 { 46 46 + pinctrl-names = "default"; 47 47 + pinctrl-0 = <&pinctrl_uart4>; 48 48 + assigned-clocks = <&clk IMX8MM_CLK_UART4>; 49 49 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 50 50 + rts-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>; 51 51 + linux,rs485-enabled-at-boot-time; 52 52 + status = "okay"; 53 53 + }; 54 54 + 55 55 + &iomuxc { 56 56 + pinctrl_gpio3_hog: gpio3hoggrp { 57 57 + fsl,pins = < 58 58 + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x49 59 59 + >; 60 60 + }; 61 61 + 62 62 + pinctrl_uart2: uart2grp { 63 63 + fsl,pins = < 64 64 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 65 65 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 66 66 + >; 67 67 + }; 68 68 + 69 69 + pinctrl_uart4: uart4grp { 70 70 + fsl,pins = < 71 71 + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x49 72 72 + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x49 73 73 + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x49 74 74 + >; 75 75 + }; 76 76 + };

+41

arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l-rs232-rts-cts.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + /* 3 3 + * Copyright (C) 2023 PHYTEC Messtechnik GmbH 4 4 + * Author: Jens Lang <j.lang@phytec.de> 5 5 + * 6 6 + * Tauri-L RS232 with RTS/CTS hardware flow control: 7 7 + * - UART4_TX becomes RTS 8 8 + * - UART4_RX becomes CTS 9 9 + */ 10 10 + 11 11 + #include <dt-bindings/clock/imx8mm-clock.h> 12 12 + #include "imx8mm-pinfunc.h" 13 13 + 14 14 + /dts-v1/; 15 15 + /plugin/; 16 16 + 17 17 + 18 18 + &{/} { 19 19 + compatible = "phytec,imx8mm-phygate-tauri-l"; 20 20 + 21 21 + }; 22 22 + 23 23 + &uart2 { 24 24 + pinctrl-names = "default"; 25 25 + pinctrl-0 = <&pinctrl_uart2>; 26 26 + assigned-clocks = <&clk IMX8MM_CLK_UART2>; 27 27 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 28 28 + uart-has-rtscts; 29 29 + status = "okay"; 30 30 + }; 31 31 + 32 32 + &iomuxc { 33 33 + pinctrl_uart2: uart2grp { 34 34 + fsl,pins = < 35 35 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 36 36 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 37 37 + MX8MM_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x00 38 38 + MX8MM_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x00 39 39 + >; 40 40 + }; 41 41 + };

+10

arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts

reviewed

··· 7 7 8 8 #include <dt-bindings/input/linux-event-codes.h> 9 9 #include <dt-bindings/leds/common.h> 10 10 + #include <dt-bindings/phy/phy-imx8-pcie.h> 10 11 #include "imx8mm-phycore-som.dtsi" 11 12 12 13 / { ··· 183 182 pinctrl-names = "default"; 184 183 pinctrl-0 = <&pinctrl_pcie>; 185 184 reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 185 185 + status = "okay"; 186 186 + }; 187 187 + 188 188 + &pcie_phy { 189 189 + clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; 190 190 + fsl,clkreq-unsupported; 191 191 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 192 192 + fsl,tx-deemph-gen1 = <0x2d>; 193 193 + fsl,tx-deemph-gen2 = <0xf>; 186 194 status = "okay"; 187 195 }; 188 196

+6 -2

arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi

reviewed

··· 62 62 flash0: flash@0 { 63 63 compatible = "jedec,spi-nor"; 64 64 reg = <0>; 65 65 - #address-cells = <1>; 66 66 - #size-cells = <1>; 67 65 spi-max-frequency = <84000000>; 68 66 spi-tx-bus-width = <1>; 69 67 spi-rx-bus-width = <4>; 68 68 + 69 69 + partitions { 70 70 + compatible = "fixed-partitions"; 71 71 + #address-cells = <1>; 72 72 + #size-cells = <1>; 73 73 + }; 70 74 }; 71 75 }; 72 76

+679

arch/arm64/boot/dts/freescale/imx8mm-ucm-som.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + // 3 3 + // Copyright 2018 CompuLab 4 4 + 5 5 + /dts-v1/; 6 6 + 7 7 + #include "imx8mm.dtsi" 8 8 + #include <dt-bindings/leds/common.h> 9 9 + 10 10 + / { 11 11 + aliases { 12 12 + rtc0 = &rtc_i2c; 13 13 + rtc1 = &snvs_rtc; 14 14 + mmc0 = &usdhc3; 15 15 + }; 16 16 + 17 17 + chosen { 18 18 + stdout-path = &uart3; 19 19 + }; 20 20 + 21 21 + backlight { 22 22 + compatible = "pwm-backlight"; 23 23 + pwms = <&pwm2 0 3000000 0>; 24 24 + brightness-levels = <0 255>; 25 25 + num-interpolated-steps = <255>; 26 26 + default-brightness-level = <222>; 27 27 + status = "okay"; 28 28 + }; 29 29 + 30 30 + leds { 31 31 + compatible = "gpio-leds"; 32 32 + pinctrl-names = "default"; 33 33 + pinctrl-0 = <&pinctrl_gpio_led>; 34 34 + 35 35 + heartbeat-led { 36 36 + function = LED_FUNCTION_STATUS; 37 37 + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; 38 38 + linux,default-trigger = "heartbeat"; 39 39 + }; 40 40 + }; 41 41 + 42 42 + pmic_osc: clock-pmic { 43 43 + compatible = "fixed-clock"; 44 44 + #clock-cells = <0>; 45 45 + clock-frequency = <32768>; 46 46 + clock-output-names = "pmic_osc"; 47 47 + }; 48 48 + 49 49 + wlreg_on: regulator-wlreg-on { 50 50 + compatible = "regulator-fixed"; 51 51 + regulator-min-microvolt = <3300000>; 52 52 + regulator-max-microvolt = <3300000>; 53 53 + regulator-name = "wlreg_on"; 54 54 + gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; 55 55 + startup-delay-us = <100>; 56 56 + enable-active-high; 57 57 + regulator-always-on; 58 58 + status = "okay"; 59 59 + }; 60 60 + 61 61 + reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 62 62 + compatible = "regulator-fixed"; 63 63 + regulator-name = "VSD_3V3"; 64 64 + regulator-min-microvolt = <3300000>; 65 65 + regulator-max-microvolt = <3300000>; 66 66 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 67 67 + enable-active-high; 68 68 + startup-delay-us = <100>; 69 69 + off-on-delay-us = <12000>; 70 70 + }; 71 71 + 72 72 + regulator-usdhc3rst { 73 73 + compatible = "regulator-fixed"; 74 74 + regulator-name = "usdhc3_rst"; 75 75 + regulator-min-microvolt = <3300000>; 76 76 + regulator-max-microvolt = <3300000>; 77 77 + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; 78 78 + regulator-always-on; 79 79 + enable-active-high; 80 80 + }; 81 81 + 82 82 + regulator-fec1rst { 83 83 + compatible = "regulator-fixed"; 84 84 + regulator-name = "fec1_rst"; 85 85 + regulator-min-microvolt = <3300000>; 86 86 + regulator-max-microvolt = <3300000>; 87 87 + gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>; 88 88 + regulator-always-on; 89 89 + enable-active-high; 90 90 + startup-delay-us = <500>; 91 91 + regulator-boot-on; 92 92 + }; 93 93 + }; 94 94 + 95 95 + &A53_0 { 96 96 + arm-supply = <&buck2>; 97 97 + }; 98 98 + 99 99 + &cpu_alert0 { 100 100 + temperature = <105000>; 101 101 + }; 102 102 + 103 103 + &cpu_crit0 { 104 104 + temperature = <115000>; 105 105 + }; 106 106 + 107 107 + &fec1 { 108 108 + pinctrl-names = "default"; 109 109 + pinctrl-0 = <&pinctrl_fec1>; 110 110 + phy-mode = "rgmii-id"; 111 111 + phy-handle = <&ethphy0>; 112 112 + fsl,magic-packet; 113 113 + status = "okay"; 114 114 + 115 115 + mdio { 116 116 + #address-cells = <1>; 117 117 + #size-cells = <0>; 118 118 + 119 119 + ethphy0: ethernet-phy@0 { 120 120 + compatible = "ethernet-phy-ieee802.3-c22"; 121 121 + reg = <0>; 122 122 + }; 123 123 + }; 124 124 + }; 125 125 + 126 126 + &i2c2 { 127 127 + clock-frequency = <400000>; 128 128 + pinctrl-names = "default"; 129 129 + pinctrl-0 = <&pinctrl_i2c2>; 130 130 + status = "okay"; 131 131 + 132 132 + pmic@4b { 133 133 + reg = <0x4b>; 134 134 + compatible = "rohm,bd71837"; 135 135 + pinctrl-names = "default"; 136 136 + pinctrl-0 = <&pinctrl_pmic>; 137 137 + #clock-cells = <0>; 138 138 + clocks = <&pmic_osc>; 139 139 + clock-names = "osc"; 140 140 + clock-output-names = "pmic_clk"; 141 141 + interrupt-parent = <&gpio1>; 142 142 + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 143 143 + rohm,reset-snvs-powered; 144 144 + 145 145 + regulators { 146 146 + buck1: BUCK1 { 147 147 + regulator-name = "buck1"; 148 148 + regulator-min-microvolt = <700000>; 149 149 + regulator-max-microvolt = <1300000>; 150 150 + regulator-boot-on; 151 151 + regulator-always-on; 152 152 + regulator-ramp-delay = <1250>; 153 153 + }; 154 154 + 155 155 + buck2: BUCK2 { 156 156 + regulator-name = "buck2"; 157 157 + regulator-min-microvolt = <700000>; 158 158 + regulator-max-microvolt = <1300000>; 159 159 + regulator-boot-on; 160 160 + regulator-always-on; 161 161 + regulator-ramp-delay = <1250>; 162 162 + rohm,dvs-run-voltage = <1000000>; 163 163 + rohm,dvs-idle-voltage = <900000>; 164 164 + }; 165 165 + 166 166 + buck3: BUCK3 { 167 167 + regulator-name = "buck3"; 168 168 + regulator-min-microvolt = <700000>; 169 169 + regulator-max-microvolt = <1300000>; 170 170 + regulator-boot-on; 171 171 + regulator-always-on; 172 172 + }; 173 173 + 174 174 + buck4: BUCK4 { 175 175 + regulator-name = "buck4"; 176 176 + regulator-min-microvolt = <700000>; 177 177 + regulator-max-microvolt = <1300000>; 178 178 + regulator-boot-on; 179 179 + regulator-always-on; 180 180 + }; 181 181 + 182 182 + buck5: BUCK5 { 183 183 + regulator-name = "buck5"; 184 184 + regulator-min-microvolt = <700000>; 185 185 + regulator-max-microvolt = <1350000>; 186 186 + regulator-boot-on; 187 187 + regulator-always-on; 188 188 + }; 189 189 + 190 190 + buck6: BUCK6 { 191 191 + regulator-name = "buck6"; 192 192 + regulator-min-microvolt = <3000000>; 193 193 + regulator-max-microvolt = <3300000>; 194 194 + regulator-boot-on; 195 195 + regulator-always-on; 196 196 + }; 197 197 + 198 198 + buck7: BUCK7 { 199 199 + regulator-name = "buck7"; 200 200 + regulator-min-microvolt = <1605000>; 201 201 + regulator-max-microvolt = <1995000>; 202 202 + regulator-boot-on; 203 203 + regulator-always-on; 204 204 + }; 205 205 + 206 206 + buck8: BUCK8 { 207 207 + regulator-name = "buck8"; 208 208 + regulator-min-microvolt = <800000>; 209 209 + regulator-max-microvolt = <1400000>; 210 210 + regulator-boot-on; 211 211 + regulator-always-on; 212 212 + }; 213 213 + 214 214 + ldo1: LDO1 { 215 215 + regulator-name = "ldo1"; 216 216 + regulator-min-microvolt = <1600000>; 217 217 + regulator-max-microvolt = <1900000>; 218 218 + regulator-boot-on; 219 219 + regulator-always-on; 220 220 + }; 221 221 + 222 222 + ldo2: LDO2 { 223 223 + regulator-name = "ldo2"; 224 224 + regulator-min-microvolt = <800000>; 225 225 + regulator-max-microvolt = <900000>; 226 226 + regulator-boot-on; 227 227 + regulator-always-on; 228 228 + }; 229 229 + 230 230 + ldo3: LDO3 { 231 231 + regulator-name = "ldo3"; 232 232 + regulator-min-microvolt = <1800000>; 233 233 + regulator-max-microvolt = <3300000>; 234 234 + regulator-boot-on; 235 235 + regulator-always-on; 236 236 + }; 237 237 + 238 238 + ldo4: LDO4 { 239 239 + regulator-name = "ldo4"; 240 240 + regulator-min-microvolt = <900000>; 241 241 + regulator-max-microvolt = <1800000>; 242 242 + regulator-boot-on; 243 243 + regulator-always-on; 244 244 + }; 245 245 + 246 246 + ldo5: LDO5 { 247 247 + regulator-name = "ldo5"; 248 248 + regulator-min-microvolt = <1800000>; 249 249 + regulator-max-microvolt = <3300000>; 250 250 + }; 251 251 + 252 252 + ldo6: LDO6 { 253 253 + regulator-name = "ldo6"; 254 254 + regulator-min-microvolt = <900000>; 255 255 + regulator-max-microvolt = <1800000>; 256 256 + regulator-boot-on; 257 257 + regulator-always-on; 258 258 + }; 259 259 + 260 260 + ldo7: LDO7 { 261 261 + regulator-name = "ldo7"; 262 262 + regulator-min-microvolt = <1800000>; 263 263 + regulator-max-microvolt = <3300000>; 264 264 + }; 265 265 + }; 266 266 + }; 267 267 + 268 268 + eeprom@50 { 269 269 + compatible = "atmel,24c08"; 270 270 + reg = <0x50>; 271 271 + pagesize = <16>; 272 272 + }; 273 273 + 274 274 + rtc_i2c: rtc@69 { 275 275 + compatible = "abracon,ab1805"; 276 276 + reg = <0x69>; 277 277 + }; 278 278 + }; 279 279 + 280 280 + &i2c3 { 281 281 + clock-frequency = <100000>; 282 282 + pinctrl-names = "default"; 283 283 + pinctrl-0 = <&pinctrl_i2c3>; 284 284 + status = "disabled"; 285 285 + }; 286 286 + 287 287 + &pwm2 { 288 288 + pinctrl-names = "default"; 289 289 + pinctrl-0 = <&pinctrl_pwm_backlight>; 290 290 + status = "okay"; 291 291 + }; 292 292 + 293 293 + &sai2 { 294 294 + #sound-dai-cells = <0>; 295 295 + pinctrl-names = "default"; 296 296 + pinctrl-0 = <&pinctrl_sai2>; 297 297 + assigned-clocks = <&clk IMX8MM_CLK_SAI2>; 298 298 + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; 299 299 + assigned-clock-rates = <49152000>; 300 300 + clocks = <&clk IMX8MM_CLK_SAI2_IPG>, <&clk IMX8MM_CLK_DUMMY>, 301 301 + <&clk IMX8MM_CLK_SAI2_ROOT>, <&clk IMX8MM_CLK_DUMMY>, 302 302 + <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>, 303 303 + <&clk IMX8MM_AUDIO_PLL2_OUT>; 304 304 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; 305 305 + fsl,sai-asynchronous; 306 306 + status = "okay"; 307 307 + }; 308 308 + 309 309 + &snvs { 310 310 + status = "okay"; 311 311 + }; 312 312 + 313 313 + &snvs_pwrkey { 314 314 + status = "okay"; 315 315 + }; 316 316 + 317 317 + &uart1 { 318 318 + pinctrl-names = "default"; 319 319 + pinctrl-0 = <&pinctrl_uart1>; 320 320 + assigned-clocks = <&clk IMX8MM_CLK_UART1>; 321 321 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 322 322 + status = "disabled"; 323 323 + }; 324 324 + 325 325 + &uart2 { 326 326 + pinctrl-names = "default"; 327 327 + pinctrl-0 = <&pinctrl_uart2>; 328 328 + assigned-clocks = <&clk IMX8MM_CLK_UART2>; 329 329 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 330 330 + status = "disabled"; 331 331 + }; 332 332 + 333 333 + &uart3 { /* console */ 334 334 + pinctrl-names = "default"; 335 335 + pinctrl-0 = <&pinctrl_uart3>; 336 336 + status = "okay"; 337 337 + }; 338 338 + 339 339 + &uart4 { /* bluetooth */ 340 340 + pinctrl-names = "default"; 341 341 + pinctrl-0 = <&pinctrl_uart4>; 342 342 + assigned-clocks = <&clk IMX8MM_CLK_UART4>; 343 343 + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; 344 344 + uart-has-rtscts; 345 345 + status = "disabled"; 346 346 + 347 347 + bluetooth { 348 348 + compatible = "brcm,bcm4330-bt"; 349 349 + pinctrl-names = "default"; 350 350 + pinctrl-0 = <&pinctrl_bt>; 351 351 + max-speed = <3000000>; 352 352 + device-wakeup-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 353 353 + host-wakeup-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 354 354 + shutdown-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 355 355 + }; 356 356 + }; 357 357 + 358 358 + &usbotg1 { 359 359 + dr_mode = "otg"; 360 360 + hnp-disable; 361 361 + srp-disable; 362 362 + disable-over-current; 363 363 + status = "disabled"; 364 364 + }; 365 365 + 366 366 + &usbotg2 { 367 367 + dr_mode = "host"; 368 368 + hnp-disable; 369 369 + srp-disable; 370 370 + disable-over-current; 371 371 + status = "disabled"; 372 372 + }; 373 373 + 374 374 + &usdhc1 { 375 375 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 376 376 + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; 377 377 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; 378 378 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; 379 379 + bus-width = <4>; 380 380 + non-removable; 381 381 + }; 382 382 + 383 383 + &usdhc2 { 384 384 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 385 385 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 386 386 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 387 387 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 388 388 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 389 389 + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; 390 390 + no-1-8-v; 391 391 + bus-width = <4>; 392 392 + vmmc-supply = <&reg_usdhc2_vmmc>; 393 393 + status = "okay"; 394 394 + }; 395 395 + 396 396 + &usdhc3 { 397 397 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 398 398 + pinctrl-0 = <&pinctrl_usdhc3>; 399 399 + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 400 400 + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 401 401 + bus-width = <8>; 402 402 + non-removable; 403 403 + no-1-8-v; 404 404 + status = "okay"; 405 405 + }; 406 406 + 407 407 + &wdog1 { 408 408 + pinctrl-names = "default"; 409 409 + pinctrl-0 = <&pinctrl_wdog>; 410 410 + fsl,ext-reset-output; 411 411 + status = "okay"; 412 412 + }; 413 413 + 414 414 + &iomuxc { 415 415 + pinctrl-names = "default"; 416 416 + pinctrl-0 = <&pinctrl_hog_1>; 417 417 + 418 418 + pinctrl_hog: hoggrp { 419 419 + fsl,pins = < 420 420 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 421 421 + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x190 422 422 + >; 423 423 + }; 424 424 + 425 425 + pinctrl_bt: bt0grp { 426 426 + fsl,pins = < 427 427 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 /* BT_REG_ON */ 428 428 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 /* BT_DEV_WU */ 429 429 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 /* BT_HST_WU */ 430 430 + >; 431 431 + }; 432 432 + 433 433 + pinctrl_fec1: fec1grp { 434 434 + fsl,pins = < 435 435 + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 436 436 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 437 437 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f 438 438 + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f 439 439 + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f 440 440 + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f 441 441 + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 442 442 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 443 443 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 444 444 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 445 445 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f 446 446 + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 447 447 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 448 448 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f 449 449 + >; 450 450 + }; 451 451 + 452 452 + pinctrl_gpio_led: gpioledgrp { 453 453 + fsl,pins = < 454 454 + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 455 455 + >; 456 456 + }; 457 457 + 458 458 + pinctrl_i2c1: i2c1grp { 459 459 + fsl,pins = < 460 460 + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 461 461 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 462 462 + >; 463 463 + }; 464 464 + 465 465 + pinctrl_i2c2: i2c2grp { 466 466 + fsl,pins = < 467 467 + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 468 468 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 469 469 + >; 470 470 + }; 471 471 + 472 472 + pinctrl_i2c3: i2c3grp { 473 473 + fsl,pins = < 474 474 + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 475 475 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 476 476 + >; 477 477 + }; 478 478 + 479 479 + pinctrl_i2c4: i2c4grp { 480 480 + fsl,pins = < 481 481 + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 482 482 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 483 483 + >; 484 484 + }; 485 485 + 486 486 + pinctrl_pmic: pmicgrp { 487 487 + fsl,pins = < 488 488 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 489 489 + >; 490 490 + }; 491 491 + 492 492 + pinctrl_pwm_backlight: pwmbacklightgrp { 493 493 + fsl,pins = < 494 494 + MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x03 495 495 + >; 496 496 + }; 497 497 + 498 498 + 499 499 + pinctrl_sai2: sai2grp { 500 500 + fsl,pins = < 501 501 + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 502 502 + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 503 503 + MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 504 504 + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 505 505 + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 506 506 + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 507 507 + >; 508 508 + }; 509 509 + 510 510 + pinctrl_uart1: uart1grp { 511 511 + fsl,pins = < 512 512 + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 513 513 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 514 514 + >; 515 515 + }; 516 516 + 517 517 + pinctrl_uart2: uart2grp { 518 518 + fsl,pins = < 519 519 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 520 520 + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 521 521 + >; 522 522 + }; 523 523 + 524 524 + pinctrl_uart3: uart3grp { 525 525 + fsl,pins = < 526 526 + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 527 527 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 528 528 + >; 529 529 + }; 530 530 + 531 531 + pinctrl_uart4: uart4grp { 532 532 + fsl,pins = < 533 533 + MX8MM_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B 0x140 534 534 + MX8MM_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX 0x140 535 535 + MX8MM_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B 0x140 536 536 + MX8MM_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX 0x140 537 537 + >; 538 538 + }; 539 539 + 540 540 + pinctrl_usdhc1_gpio: usdhc1grpgpiogrp { 541 541 + fsl,pins = < 542 542 + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 543 543 + >; 544 544 + }; 545 545 + 546 546 + pinctrl_usdhc1: usdhc1grp { 547 547 + fsl,pins = < 548 548 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 549 549 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 550 550 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 551 551 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 552 552 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 553 553 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 554 554 + MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 555 555 + >; 556 556 + }; 557 557 + 558 558 + pinctrl_usdhc1_100mhz: usdhc1grp100mhzgrp { 559 559 + fsl,pins = < 560 560 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 561 561 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 562 562 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 563 563 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 564 564 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 565 565 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 566 566 + MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 567 567 + >; 568 568 + }; 569 569 + 570 570 + pinctrl_usdhc1_200mhz: usdhc1grp200mhzgrp { 571 571 + fsl,pins = < 572 572 + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 573 573 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 574 574 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 575 575 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 576 576 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 577 577 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 578 578 + MX8MM_IOMUXC_GPIO1_IO03_USDHC1_VSELECT 0x1d0 579 579 + >; 580 580 + }; 581 581 + 582 582 + pinctrl_usdhc2_gpio: usdhc2grpgpiogrp { 583 583 + fsl,pins = < 584 584 + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 585 585 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 586 586 + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x00 587 587 + >; 588 588 + }; 589 589 + 590 590 + pinctrl_usdhc2: usdhc2grp { 591 591 + fsl,pins = < 592 592 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 593 593 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 594 594 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 595 595 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 596 596 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 597 597 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 598 598 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 599 599 + >; 600 600 + }; 601 601 + 602 602 + pinctrl_usdhc2_100mhz: usdhc2grp100mhzgrp { 603 603 + fsl,pins = < 604 604 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 605 605 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 606 606 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 607 607 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 608 608 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 609 609 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 610 610 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 611 611 + >; 612 612 + }; 613 613 + 614 614 + pinctrl_usdhc2_200mhz: usdhc2grp200mhzgrp { 615 615 + fsl,pins = < 616 616 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 617 617 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 618 618 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 619 619 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 620 620 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 621 621 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 622 622 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 623 623 + >; 624 624 + }; 625 625 + 626 626 + pinctrl_usdhc3: usdhc3grp { 627 627 + fsl,pins = < 628 628 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190 629 629 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 630 630 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 631 631 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 632 632 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 633 633 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 634 634 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 635 635 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 636 636 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 637 637 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 638 638 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 639 639 + >; 640 640 + }; 641 641 + 642 642 + pinctrl_usdhc3_100mhz: usdhc3grp100mhzgrp { 643 643 + fsl,pins = < 644 644 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194 645 645 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 646 646 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 647 647 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 648 648 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 649 649 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 650 650 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 651 651 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 652 652 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 653 653 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 654 654 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 655 655 + >; 656 656 + }; 657 657 + 658 658 + pinctrl_usdhc3_200mhz: usdhc3grp200mhzgrp { 659 659 + fsl,pins = < 660 660 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196 661 661 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 662 662 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 663 663 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 664 664 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 665 665 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 666 666 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 667 667 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 668 668 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 669 669 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 670 670 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 671 671 + >; 672 672 + }; 673 673 + 674 674 + pinctrl_wdog: wdoggrp { 675 675 + fsl,pins = < 676 676 + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 677 677 + >; 678 678 + }; 679 679 + };

+20

arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi

reviewed

··· 5 5 6 6 #include <dt-bindings/gpio/gpio.h> 7 7 #include <dt-bindings/input/linux-event-codes.h> 8 8 + #include <dt-bindings/leds/common.h> 8 9 #include <dt-bindings/net/ti-dp83867.h> 9 10 10 11 / { ··· 114 113 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 115 114 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 116 115 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 116 116 + 117 117 + leds { 118 118 + #address-cells = <1>; 119 119 + #size-cells = <0>; 120 120 + 121 121 + led@1 { 122 122 + reg = <1>; 123 123 + color = <LED_COLOR_ID_AMBER>; 124 124 + function = LED_FUNCTION_LAN; 125 125 + default-state = "keep"; 126 126 + }; 127 127 + 128 128 + led@2 { 129 129 + reg = <2>; 130 130 + color = <LED_COLOR_ID_GREEN>; 131 131 + function = LED_FUNCTION_LAN; 132 132 + default-state = "keep"; 133 133 + }; 134 134 + }; 117 135 }; 118 136 }; 119 137 };

-2

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts

reviewed

··· 364 364 interrupts = <16 IRQ_TYPE_EDGE_FALLING>; 365 365 interrupt-controller; 366 366 #interrupt-cells = <1>; 367 367 - #address-cells = <1>; 368 368 - #size-cells = <0>; 369 367 370 368 adc { 371 369 compatible = "gw,gsc-adc";

-2

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts

reviewed

··· 314 314 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 315 315 interrupt-controller; 316 316 #interrupt-cells = <1>; 317 317 - #address-cells = <1>; 318 318 - #size-cells = <0>; 319 317 320 318 adc { 321 319 compatible = "gw,gsc-adc";

-2

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts

reviewed

··· 280 280 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 281 281 interrupt-controller; 282 282 #interrupt-cells = <1>; 283 283 - #address-cells = <1>; 284 284 - #size-cells = <0>; 285 283 286 284 adc { 287 285 compatible = "gw,gsc-adc";

-2

arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts

reviewed

··· 330 330 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 331 331 interrupt-controller; 332 332 #interrupt-cells = <1>; 333 333 - #address-cells = <1>; 334 334 - #size-cells = <0>; 335 333 336 334 adc { 337 335 compatible = "gw,gsc-adc";

+13 -7

arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi

reviewed

··· 228 228 pinctrl-0 = <&pinctrl_ecspi2>; 229 229 }; 230 230 231 231 - /* Verdin CAN_1 (On-module) */ 231 231 + /* On-module SPI */ 232 232 &ecspi3 { 233 233 #address-cells = <1>; 234 234 #size-cells = <0>; 235 235 - cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; 235 235 + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio4 19 GPIO_ACTIVE_LOW>; 236 236 pinctrl-names = "default"; 237 237 - pinctrl-0 = <&pinctrl_ecspi3>; 237 237 + pinctrl-0 = <&pinctrl_ecspi3>, <&pinctrl_tpm_spi_cs>; 238 238 status = "okay"; 239 239 240 240 + /* Verdin CAN_1 */ 240 241 can1: can@0 { 241 242 compatible = "microchip,mcp251xfd"; 242 243 clocks = <&clk40m>; ··· 246 245 pinctrl-0 = <&pinctrl_can1_int>; 247 246 reg = <0>; 248 247 spi-max-frequency = <8500000>; 248 248 + }; 249 249 + 250 250 + verdin_som_tpm: tpm@1 { 251 251 + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 252 252 + reg = <0x1>; 253 253 + spi-max-frequency = <36000000>; 249 254 }; 250 255 }; 251 256 ··· 555 548 556 549 /* Verdin I2C_2_DSI */ 557 550 &i2c2 { 558 558 - clock-frequency = <10000>; 551 551 + clock-frequency = <400000>; 559 552 pinctrl-names = "default", "gpio"; 560 553 pinctrl-0 = <&pinctrl_i2c2>; 561 554 pinctrl-1 = <&pinctrl_i2c2_gpio>; ··· 815 808 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 816 809 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 817 810 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 818 818 - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 819 819 - <&pinctrl_pmic_tpm_ena>; 811 811 + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; 820 812 821 813 pinctrl_can1_int: can1intgrp { 822 814 fsl,pins = ··· 1117 1111 }; 1118 1112 1119 1113 /* control signal for optional ATTPM20P or SE050 */ 1120 1120 - pinctrl_pmic_tpm_ena: pmictpmenagrp { 1114 1114 + pinctrl_tpm_spi_cs: tpmspicsgrp { 1121 1115 fsl,pins = 1122 1116 <MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106>; /* PMIC_TPM_ENA */ 1123 1117 };

+6 -2

arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi

reviewed

··· 60 60 flash0: flash@0 { 61 61 compatible = "jedec,spi-nor"; 62 62 reg = <0>; 63 63 - #address-cells = <1>; 64 64 - #size-cells = <1>; 65 63 spi-max-frequency = <84000000>; 66 64 spi-tx-bus-width = <1>; 67 65 spi-rx-bus-width = <4>; 66 66 + 67 67 + partitions { 68 68 + compatible = "fixed-partitions"; 69 69 + #address-cells = <1>; 70 70 + #size-cells = <1>; 71 71 + }; 68 72 }; 69 73 }; 70 74

-2

arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts

reviewed

··· 312 312 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 313 313 interrupt-controller; 314 314 #interrupt-cells = <1>; 315 315 - #address-cells = <1>; 316 316 - #size-cells = <0>; 317 315 318 316 adc { 319 317 compatible = "gw,gsc-adc";

+10 -2

arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts

reviewed

··· 302 302 303 303 adv_bridge: hdmi@3d { 304 304 compatible = "adi,adv7535"; 305 305 - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; 306 306 - reg-names = "main", "cec", "edid", "packet"; 305 305 + reg = <0x3d>; 306 306 + reg-names = "main"; 307 307 + interrupt-parent = <&gpio4>; 308 308 + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 307 309 adi,dsi-lanes = <4>; 308 310 #sound-dai-cells = <0>; 311 311 + avdd-supply = <&buck5>; 312 312 + dvdd-supply = <&buck5>; 313 313 + pvdd-supply = <&buck5>; 314 314 + a2vdd-supply = <&buck5>; 315 315 + v1p2-supply = <&buck5>; 316 316 + v3p3-supply = <&buck4>; 309 317 310 318 ports { 311 319 #address-cells = <1>;

-2

arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi

reviewed

··· 71 71 72 72 mtl_rx_setup: rx-queues-config { 73 73 snps,rx-queues-to-use = <5>; 74 74 - snps,rx-sched-sp; 75 74 76 75 queue0 { 77 76 snps,dcb-algorithm; ··· 105 106 106 107 mtl_tx_setup: tx-queues-config { 107 108 snps,tx-queues-to-use = <5>; 108 108 - snps,tx-sched-sp; 109 109 110 110 queue0 { 111 111 snps,dcb-algorithm;

+47

arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts

reviewed

··· 20 20 stdout-path = &uart2; 21 21 }; 22 22 23 23 + hdmi-connector { 24 24 + compatible = "hdmi-connector"; 25 25 + label = "hdmi"; 26 26 + type = "a"; 27 27 + 28 28 + port { 29 29 + hdmi_connector_in: endpoint { 30 30 + remote-endpoint = <&hdmi_tx_out>; 31 31 + }; 32 32 + }; 33 33 + }; 34 34 + 23 35 leds { 24 36 compatible = "gpio-leds"; 25 37 pinctrl-names = "default"; ··· 104 92 reset-deassert-us = <200000>; 105 93 }; 106 94 }; 95 95 + }; 96 96 + 97 97 + &hdmi_pvi { 98 98 + status = "okay"; 99 99 + }; 100 100 + 101 101 + &hdmi_tx { 102 102 + pinctrl-names = "default"; 103 103 + pinctrl-0 = <&pinctrl_hdmi>; 104 104 + status = "okay"; 105 105 + 106 106 + ports { 107 107 + port@1 { 108 108 + hdmi_tx_out: endpoint { 109 109 + remote-endpoint = <&hdmi_connector_in>; 110 110 + }; 111 111 + }; 112 112 + }; 113 113 + }; 114 114 + 115 115 + &hdmi_tx_phy { 116 116 + status = "okay"; 107 117 }; 108 118 109 119 &i2c1 { ··· 273 239 status = "okay"; 274 240 }; 275 241 242 242 + &lcdif3 { 243 243 + status = "okay"; 244 244 + }; 245 245 + 276 246 &snvs_pwrkey { 277 247 status = "okay"; 278 248 }; ··· 391 353 pinctrl_gpio_led: gpioledgrp { 392 354 fsl,pins = < 393 355 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 356 356 + >; 357 357 + }; 358 358 + 359 359 + pinctrl_hdmi: hdmigrp { 360 360 + fsl,pins = < 361 361 + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 362 362 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 363 363 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 364 364 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x19 394 365 >; 395 366 }; 396 367

+39

arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts

reviewed

··· 69 69 }; 70 70 }; 71 71 72 72 + hdmi-connector { 73 73 + compatible = "hdmi-connector"; 74 74 + label = "X38"; 75 75 + type = "a"; 76 76 + 77 77 + port { 78 78 + hdmi_connector_in: endpoint { 79 79 + remote-endpoint = <&hdmi_tx_out>; 80 80 + }; 81 81 + }; 82 82 + }; 83 83 + 72 84 led { 73 85 compatible = "gpio-leds"; 74 86 ··· 193 181 }; 194 182 195 183 &flexcan1 { 184 184 + status = "okay"; 185 185 + }; 186 186 + 187 187 + &hdmi_pvi { 188 188 + status = "okay"; 189 189 + }; 190 190 + 191 191 + &hdmi_tx { 192 192 + ddc-i2c-bus = <&i2c5>; 193 193 + pinctrl-names = "default"; 194 194 + pinctrl-0 = <&pinctrl_hdmi>; 195 195 + status = "okay"; 196 196 + 197 197 + ports { 198 198 + port@1 { 199 199 + hdmi_tx_out: endpoint { 200 200 + remote-endpoint = <&hdmi_connector_in>; 201 201 + }; 202 202 + }; 203 203 + }; 204 204 + }; 205 205 + 206 206 + &hdmi_tx_phy { 207 207 + status = "okay"; 208 208 + }; 209 209 + 210 210 + &lcdif3 { 196 211 status = "okay"; 197 212 }; 198 213

+39

arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts

reviewed

··· 75 75 }; 76 76 }; 77 77 78 78 + hdmi-connector { 79 79 + compatible = "hdmi-connector"; 80 80 + label = "X28"; 81 81 + type = "a"; 82 82 + 83 83 + port { 84 84 + hdmi_connector_in: endpoint { 85 85 + remote-endpoint = <&hdmi_tx_out>; 86 86 + }; 87 87 + }; 88 88 + }; 89 89 + 78 90 led { 79 91 compatible = "gpio-leds"; 80 92 ··· 257 245 }; 258 246 259 247 &flexcan1 { 248 248 + status = "okay"; 249 249 + }; 250 250 + 251 251 + &hdmi_pvi { 252 252 + status = "okay"; 253 253 + }; 254 254 + 255 255 + &hdmi_tx { 256 256 + ddc-i2c-bus = <&i2cmuxed1>; 257 257 + pinctrl-names = "default"; 258 258 + pinctrl-0 = <&pinctrl_hdmi>; 259 259 + status = "okay"; 260 260 + 261 261 + ports { 262 262 + port@1 { 263 263 + hdmi_tx_out: endpoint { 264 264 + remote-endpoint = <&hdmi_connector_in>; 265 265 + }; 266 266 + }; 267 267 + }; 268 268 + }; 269 269 + 270 270 + &hdmi_tx_phy { 271 271 + status = "okay"; 272 272 + }; 273 273 + 274 274 + &lcdif3 { 260 275 status = "okay"; 261 276 }; 262 277

+9 -4

arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi

reviewed

··· 78 78 cpu-supply = <&buck2>; 79 79 }; 80 80 81 81 + &audio_blk_ctrl { 82 82 + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>; 83 83 + assigned-clock-rates = <393216000>; 84 84 + }; 85 85 + 81 86 &ecspi1 { 82 87 pinctrl-names = "default"; 83 88 pinctrl-0 = <&pinctrl_ecspi1>; ··· 110 105 #size-cells = <0>; 111 106 112 107 /* Up to one of these two PHYs may be populated. */ 113 113 - ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */ 108 108 + ethphy0f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 114 109 compatible = "ethernet-phy-id0007.c110", 115 110 "ethernet-phy-ieee802.3-c22"; 116 111 interrupt-parent = <&gpio3>; 117 112 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 118 113 pinctrl-0 = <&pinctrl_ethphy0>; 119 114 pinctrl-names = "default"; 120 120 - reg = <0>; 115 115 + reg = <1>; 121 116 reset-assert-us = <1000>; 122 117 reset-deassert-us = <1000>; 123 118 reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; ··· 156 151 #size-cells = <0>; 157 152 158 153 /* Up to one PHY may be populated. */ 159 159 - ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */ 154 154 + ethphy1f: ethernet-phy@2 { /* SMSC LAN8740Ai */ 160 155 compatible = "ethernet-phy-id0007.c110", 161 156 "ethernet-phy-ieee802.3-c22"; 162 157 interrupt-parent = <&gpio4>; 163 158 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 164 159 pinctrl-0 = <&pinctrl_ethphy1>; 165 160 pinctrl-names = "default"; 166 166 - reg = <1>; 161 161 + reg = <2>; 167 162 reset-assert-us = <1000>; 168 163 reset-deassert-us = <1000>; 169 164 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;

+77

arch/arm64/boot/dts/freescale/imx8mp-evk-mx8-dlvds-lcd1.dtso

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + /dts-v1/; 7 7 + /plugin/; 8 8 + 9 9 + &{/} { 10 10 + panel-lvds { 11 11 + compatible = "koe,tx26d202vm0bwa"; 12 12 + backlight = <&backlight_lvds>; 13 13 + power-supply = <&reg_vext_3v3>; 14 14 + 15 15 + panel-timing { 16 16 + clock-frequency = <148500000>; 17 17 + hactive = <1920>; 18 18 + vactive = <1200>; 19 19 + hfront-porch = <130>; 20 20 + hback-porch = <70>; 21 21 + hsync-len = <30>; 22 22 + vfront-porch = <5>; 23 23 + vback-porch = <5>; 24 24 + vsync-len = <5>; 25 25 + de-active = <1>; 26 26 + }; 27 27 + 28 28 + ports { 29 29 + #address-cells = <1>; 30 30 + #size-cells = <0>; 31 31 + 32 32 + port@0 { 33 33 + reg = <0>; 34 34 + dual-lvds-odd-pixels; 35 35 + 36 36 + panel_in_odd: endpoint { 37 37 + remote-endpoint = <&ldb_lvds_ch0>; 38 38 + }; 39 39 + }; 40 40 + 41 41 + port@1 { 42 42 + reg = <1>; 43 43 + dual-lvds-even-pixels; 44 44 + 45 45 + panel_in_even: endpoint { 46 46 + remote-endpoint = <&ldb_lvds_ch1>; 47 47 + }; 48 48 + }; 49 49 + }; 50 50 + }; 51 51 + }; 52 52 + 53 53 + &backlight_lvds { 54 54 + status = "okay"; 55 55 + }; 56 56 + 57 57 + &lcdif2 { 58 58 + status = "okay"; 59 59 + }; 60 60 + 61 61 + &lvds_bridge { 62 62 + status = "okay"; 63 63 + 64 64 + ports { 65 65 + port@1 { 66 66 + ldb_lvds_ch0: endpoint { 67 67 + remote-endpoint = <&panel_in_odd>; 68 68 + }; 69 69 + }; 70 70 + 71 71 + port@2 { 72 72 + ldb_lvds_ch1: endpoint { 73 73 + remote-endpoint = <&panel_in_even>; 74 74 + }; 75 75 + }; 76 76 + }; 77 77 + };

+90 -1

arch/arm64/boot/dts/freescale/imx8mp-evk.dts

reviewed

··· 16 16 stdout-path = &uart2; 17 17 }; 18 18 19 19 + backlight_lvds: backlight-lvds { 20 20 + compatible = "pwm-backlight"; 21 21 + pwms = <&pwm2 0 100000 0>; 22 22 + brightness-levels = <0 100>; 23 23 + num-interpolated-steps = <100>; 24 24 + default-brightness-level = <100>; 25 25 + power-supply = <&reg_per_12v>; 26 26 + status = "disabled"; 27 27 + }; 28 28 + 19 29 hdmi-connector { 20 30 compatible = "hdmi-connector"; 21 31 label = "hdmi"; ··· 106 96 enable-active-high; 107 97 }; 108 98 99 99 + reg_per_12v: regulator-per-12v { 100 100 + compatible = "regulator-fixed"; 101 101 + regulator-name = "PER_12V"; 102 102 + regulator-min-microvolt = <12000000>; 103 103 + regulator-max-microvolt = <12000000>; 104 104 + gpio = <&pca6416 1 GPIO_ACTIVE_HIGH>; 105 105 + enable-active-high; 106 106 + }; 107 107 + 109 108 reg_usdhc2_vmmc: regulator-usdhc2 { 110 109 compatible = "regulator-fixed"; 111 110 pinctrl-names = "default"; ··· 131 112 regulator-name = "VEXT_3V3"; 132 113 regulator-min-microvolt = <3300000>; 133 114 regulator-max-microvolt = <3300000>; 115 115 + }; 116 116 + 117 117 + audio_codec_bt_sco: audio-codec-bt-sco { 118 118 + compatible = "linux,bt-sco"; 119 119 + #sound-dai-cells = <1>; 134 120 }; 135 121 136 122 sound { ··· 169 145 170 146 }; 171 147 148 148 + sound-bt-sco { 149 149 + compatible = "simple-audio-card"; 150 150 + simple-audio-card,name = "bt-sco-audio"; 151 151 + simple-audio-card,format = "dsp_a"; 152 152 + simple-audio-card,bitclock-inversion; 153 153 + simple-audio-card,frame-master = <&btcpu>; 154 154 + simple-audio-card,bitclock-master = <&btcpu>; 155 155 + 156 156 + btcpu: simple-audio-card,cpu { 157 157 + sound-dai = <&sai2>; 158 158 + dai-tdm-slot-num = <2>; 159 159 + dai-tdm-slot-width = <16>; 160 160 + }; 161 161 + 162 162 + simple-audio-card,codec { 163 163 + sound-dai = <&audio_codec_bt_sco 1>; 164 164 + }; 165 165 + }; 166 166 + 172 167 sound-hdmi { 173 168 compatible = "fsl,imx-audio-hdmi"; 174 169 model = "audio-hdmi"; ··· 205 162 206 163 cpu { 207 164 sound-dai = <&micfil>; 165 165 + }; 166 166 + }; 167 167 + }; 168 168 + 169 169 + sound-xcvr { 170 170 + compatible = "fsl,imx-audio-card"; 171 171 + model = "imx-audio-xcvr"; 172 172 + 173 173 + pri-dai-link { 174 174 + link-name = "XCVR PCM"; 175 175 + 176 176 + cpu { 177 177 + sound-dai = <&xcvr>; 208 178 }; 209 179 }; 210 180 }; ··· 307 251 308 252 mtl_tx_setup: tx-queues-config { 309 253 snps,tx-queues-to-use = <5>; 310 310 - snps,tx-sched-sp; 311 254 312 255 queue0 { 313 256 snps,dcb-algorithm; ··· 663 608 status = "okay"; 664 609 }; 665 610 611 611 + &sai2 { 612 612 + #sound-dai-cells = <0>; 613 613 + pinctrl-names = "default"; 614 614 + pinctrl-0 = <&pinctrl_sai2>; 615 615 + assigned-clocks = <&clk IMX8MP_CLK_SAI2>; 616 616 + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 617 617 + assigned-clock-rates = <12288000>; 618 618 + fsl,sai-mclk-direction-output; 619 619 + status = "okay"; 620 620 + }; 621 621 + 666 622 &sai3 { 667 623 pinctrl-names = "default"; 668 624 pinctrl-0 = <&pinctrl_sai3>; ··· 760 694 status = "okay"; 761 695 }; 762 696 697 697 + &xcvr { 698 698 + #sound-dai-cells = <0>; 699 699 + status = "okay"; 700 700 + }; 701 701 + 763 702 &iomuxc { 703 703 + pinctrl-names = "default"; 704 704 + pinctrl-0 = <&pinctrl_hog>; 705 705 + 764 706 pinctrl_audio_pwr_reg: audiopwrreggrp { 765 707 fsl,pins = < 766 708 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0xd6 ··· 855 781 pinctrl_gpio_led: gpioledgrp { 856 782 fsl,pins = < 857 783 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140 784 784 + >; 785 785 + }; 786 786 + 787 787 + pinctrl_hog: hoggrp { 788 788 + fsl,pins = < 789 789 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 858 790 >; 859 791 }; 860 792 ··· 957 877 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 958 878 MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 959 879 MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 880 880 + >; 881 881 + }; 882 882 + 883 883 + pinctrl_sai2: sai2grp { 884 884 + fsl,pins = < 885 885 + MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6 886 886 + MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6 887 887 + MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6 888 888 + MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0xd6 960 889 >; 961 890 }; 962 891

+27

arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts

reviewed

··· 46 46 }; 47 47 }; 48 48 49 49 + &hdmi_pvi { 50 50 + status = "okay"; 51 51 + }; 52 52 + 53 53 + &hdmi_tx { 54 54 + pinctrl-names = "default"; 55 55 + pinctrl-0 = <&pinctrl_hdmi>; 56 56 + status = "okay"; 57 57 + }; 58 58 + 59 59 + &hdmi_tx_phy { 60 60 + status = "okay"; 61 61 + }; 62 62 + 63 63 + &lcdif3 { 64 64 + status = "okay"; 65 65 + }; 66 66 + 49 67 &i2c1 { 50 68 sgtl5000: audio-codec@a { 51 69 compatible = "fsl,sgtl5000"; ··· 109 91 &iomuxc { 110 92 pinctrl-names = "default"; 111 93 pinctrl-0 = <&pinctrl_smarc_gpio>; 94 94 + 95 95 + pinctrl_hdmi: hdmigrp { 96 96 + fsl,pins = < 97 97 + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2 98 98 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2 99 99 + MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 100 100 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10 101 101 + >; 102 102 + }; 112 103 113 104 pinctrl_sai2: sai2grp { 114 105 fsl,pins = <

+906

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mp-ras314.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2 2 + /* 3 3 + * Copyright (c) 2023-2024 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 4 + * D-82229 Seefeld, Germany. 5 5 + * Author: Martin Schmiedel 6 6 + * Author: Alexander Stein 7 7 + */ 8 8 + 9 9 + /dts-v1/; 10 10 + 11 11 + #include <dt-bindings/leds/common.h> 12 12 + #include <dt-bindings/net/ti-dp83867.h> 13 13 + #include <dt-bindings/phy/phy-imx8-pcie.h> 14 14 + #include <dt-bindings/pwm/pwm.h> 15 15 + #include "imx8mp-tqma8mpql.dtsi" 16 16 + 17 17 + / { 18 18 + model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MP-RAS314"; 19 19 + compatible = "tq,imx8mp-tqma8mpql-mba8mp-ras314", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; 20 20 + chassis-type = "embedded"; 21 21 + 22 22 + chosen { 23 23 + stdout-path = &uart4; 24 24 + }; 25 25 + 26 26 + aliases { 27 27 + mmc0 = &usdhc3; 28 28 + mmc1 = &usdhc2; 29 29 + mmc2 = &usdhc1; 30 30 + rtc0 = &pcf85063; 31 31 + rtc1 = &snvs_rtc; 32 32 + }; 33 33 + 34 34 + /* X8 */ 35 35 + backlight_lvds: backlight { 36 36 + compatible = "pwm-backlight"; 37 37 + pinctrl-names = "default"; 38 38 + pinctrl-0 = <&pinctrl_backlight>; 39 39 + pwms = <&pwm2 0 5000000 0>; 40 40 + brightness-levels = <0 4 8 16 32 64 128 255>; 41 41 + default-brightness-level = <7>; 42 42 + power-supply = <&reg_vcc_12v0>; 43 43 + enable-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; 44 44 + status = "disabled"; 45 45 + }; 46 46 + 47 47 + /* X7 + X8 */ 48 48 + display: display { 49 49 + /* 50 50 + * Display is not fixed, so compatible has to be added from 51 51 + * DT overlay 52 52 + */ 53 53 + pinctrl-names = "default"; 54 54 + pinctrl-0 = <&pinctrl_lvdsdisplay>; 55 55 + power-supply = <&reg_vcc_3v3>; 56 56 + enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; 57 57 + backlight = <&backlight_lvds>; 58 58 + status = "disabled"; 59 59 + }; 60 60 + 61 61 + gpio-leds { 62 62 + compatible = "gpio-leds"; 63 63 + pinctrl-names = "default"; 64 64 + pinctrl-0 = <&pinctrl_gpioled>; 65 65 + 66 66 + led-1 { 67 67 + color = <LED_COLOR_ID_GREEN>; 68 68 + function = LED_FUNCTION_STATUS; 69 69 + function-enumerator = <0>; 70 70 + gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>; 71 71 + }; 72 72 + 73 73 + led-2 { 74 74 + color = <LED_COLOR_ID_YELLOW>; 75 75 + function = LED_FUNCTION_STATUS; 76 76 + function-enumerator = <1>; 77 77 + gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; 78 78 + }; 79 79 + }; 80 80 + 81 81 + hdmi-connector { 82 82 + compatible = "hdmi-connector"; 83 83 + label = "X9"; 84 84 + type = "a"; 85 85 + 86 86 + port { 87 87 + hdmi_connector_in: endpoint { 88 88 + remote-endpoint = <&hdmi_tx_out>; 89 89 + }; 90 90 + }; 91 91 + }; 92 92 + 93 93 + reg_usdhc2_vmmc: regulator-usdhc2 { 94 94 + compatible = "regulator-fixed"; 95 95 + pinctrl-names = "default"; 96 96 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 97 97 + regulator-name = "VSD_3V3"; 98 98 + regulator-min-microvolt = <3300000>; 99 99 + regulator-max-microvolt = <3300000>; 100 100 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 101 101 + enable-active-high; 102 102 + startup-delay-us = <100>; 103 103 + off-on-delay-us = <12000>; 104 104 + }; 105 105 + 106 106 + reg_vcc_3v3: regulator-3v3 { 107 107 + compatible = "regulator-fixed"; 108 108 + regulator-name = "V_3V3"; 109 109 + regulator-min-microvolt = <3300000>; 110 110 + regulator-max-microvolt = <3300000>; 111 111 + }; 112 112 + 113 113 + reg_vcc_5v0: regulator-5v0 { 114 114 + compatible = "regulator-fixed"; 115 115 + regulator-name = "V_5V0"; 116 116 + regulator-min-microvolt = <5000000>; 117 117 + regulator-max-microvolt = <5000000>; 118 118 + }; 119 119 + 120 120 + reg_vcc_12v0: regulator-12v0 { 121 121 + compatible = "regulator-fixed"; 122 122 + regulator-name = "V_12V"; 123 123 + regulator-min-microvolt = <12000000>; 124 124 + regulator-max-microvolt = <12000000>; 125 125 + }; 126 126 + 127 127 + reserved-memory { 128 128 + #address-cells = <2>; 129 129 + #size-cells = <2>; 130 130 + ranges; 131 131 + 132 132 + /* global autoconfigured region for contiguous allocations */ 133 133 + linux,cma { 134 134 + compatible = "shared-dma-pool"; 135 135 + reusable; 136 136 + size = <0 0x38000000>; 137 137 + alloc-ranges = <0 0x40000000 0 0xB0000000>; 138 138 + linux,cma-default; 139 139 + }; 140 140 + }; 141 141 + 142 142 + rfkill { 143 143 + compatible = "rfkill-gpio"; 144 144 + pinctrl-names = "default"; 145 145 + pinctrl-0 = <&pinctrl_rfkill>; 146 146 + label = "rfkill-pcie-wlan"; 147 147 + radio-type = "wlan"; 148 148 + shutdown-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; 149 149 + }; 150 150 + 151 151 + sound { 152 152 + compatible = "fsl,imx-audio-tlv320aic32x4"; 153 153 + model = "tq-mba8mp-ras314"; 154 154 + audio-cpu = <&sai5>; 155 155 + audio-codec = <&tlv320aic3x04>; 156 156 + audio-routing = 157 157 + "IN3_L", "Mic Jack", 158 158 + "Mic Jack", "Mic Bias", 159 159 + "Headphone Jack", "HPL", 160 160 + "Headphone Jack", "HPR"; 161 161 + }; 162 162 + }; 163 163 + 164 164 + &ecspi3 { 165 165 + pinctrl-names = "default"; 166 166 + pinctrl-0 = <&pinctrl_ecspi3>; 167 167 + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, <&gpio1 6 GPIO_ACTIVE_LOW>; 168 168 + status = "okay"; 169 169 + }; 170 170 + 171 171 + &eqos { 172 172 + pinctrl-names = "default"; 173 173 + pinctrl-0 = <&pinctrl_eqos>; 174 174 + phy-mode = "rgmii-id"; 175 175 + phy-handle = <&ethphy3>; 176 176 + status = "okay"; 177 177 + 178 178 + mdio { 179 179 + compatible = "snps,dwmac-mdio"; 180 180 + #address-cells = <1>; 181 181 + #size-cells = <0>; 182 182 + 183 183 + ethphy3: ethernet-phy@3 { 184 184 + compatible = "ethernet-phy-ieee802.3-c22"; 185 185 + reg = <3>; 186 186 + pinctrl-names = "default"; 187 187 + pinctrl-0 = <&pinctrl_eqos_phy>; 188 188 + reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 189 189 + reset-assert-us = <500000>; 190 190 + reset-deassert-us = <50000>; 191 191 + enet-phy-lane-no-swap; 192 192 + interrupt-parent = <&gpio4>; 193 193 + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; 194 194 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 195 195 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 196 196 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 197 197 + ti,dp83867-rxctrl-strap-quirk; 198 198 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 199 199 + }; 200 200 + }; 201 201 + }; 202 202 + 203 203 + &fec { 204 204 + pinctrl-names = "default"; 205 205 + pinctrl-0 = <&pinctrl_fec>; 206 206 + phy-mode = "rgmii-id"; 207 207 + phy-handle = <&ethphy0>; 208 208 + fsl,magic-packet; 209 209 + status = "okay"; 210 210 + 211 211 + mdio { 212 212 + #address-cells = <1>; 213 213 + #size-cells = <0>; 214 214 + 215 215 + ethphy0: ethernet-phy@0 { 216 216 + compatible = "ethernet-phy-ieee802.3-c22"; 217 217 + reg = <0>; 218 218 + pinctrl-names = "default"; 219 219 + pinctrl-0 = <&pinctrl_fec_phy>; 220 220 + reset-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>; 221 221 + reset-assert-us = <500000>; 222 222 + reset-deassert-us = <50000>; 223 223 + enet-phy-lane-no-swap; 224 224 + interrupt-parent = <&gpio4>; 225 225 + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 226 226 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 227 227 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 228 228 + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 229 229 + ti,dp83867-rxctrl-strap-quirk; 230 230 + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 231 231 + }; 232 232 + }; 233 233 + }; 234 234 + 235 235 + &gpio1 { 236 236 + pinctrl-names = "default"; 237 237 + pinctrl-0 = <&pinctrl_gpio1>; 238 238 + 239 239 + gpio-line-names = "WIFI_PMIC_EN", "LVDS_RESET#", "", "", 240 240 + "", "", "GPIO8", "", 241 241 + "", "", "", "", 242 242 + "", "", "GPIO12", "GPIO13", 243 243 + "", "", "", "", 244 244 + "", "", "", "", 245 245 + "", "", "", "", 246 246 + "", "", "", ""; 247 247 + 248 248 + wifi-pmic-en-hog { 249 249 + gpio-hog; 250 250 + gpios = <0 0>; 251 251 + output-high; 252 252 + line-name = "WIFI_PMIC_EN"; 253 253 + }; 254 254 + }; 255 255 + 256 256 + &gpio2 { 257 257 + pinctrl-names = "default"; 258 258 + pinctrl-0 = <&pinctrl_gpio2>; 259 259 + 260 260 + gpio-line-names = "GPIO22", "GPIO23", "GPIO24", "GPIO25", 261 261 + "GPIO26", "GPIO27", "CAM_GPIO1", "CAM_GPIO2", 262 262 + "", "", "GPIO1", "GPIO0", 263 263 + "", "", "", "", 264 264 + "", "", "", "", 265 265 + "", "", "", "", 266 266 + "", "", "", "", 267 267 + "", "", "", ""; 268 268 + }; 269 269 + 270 270 + &gpio3 { 271 271 + pinctrl-names = "default"; 272 272 + pinctrl-0 = <&pinctrl_gpio3>; 273 273 + 274 274 + gpio-line-names = "", "", "", "", 275 275 + "", "", "", "", 276 276 + "", "", "", "", 277 277 + "", "", "", "", 278 278 + "", "", "", "", 279 279 + "TEMP_EVENT#", "", "", "", 280 280 + "", "", "", "", 281 281 + "", "", "", ""; 282 282 + }; 283 283 + 284 284 + &gpio4 { 285 285 + pinctrl-names = "default"; 286 286 + pinctrl-0 = <&pinctrl_gpio4>; 287 287 + 288 288 + gpio-line-names = "", "", "", "", 289 289 + "", "", "", "", 290 290 + "", "", "", "", 291 291 + "", "", "", "", 292 292 + "", "", "", "", 293 293 + "HDMI_OC#", "GPIO14", "GPIO15", "GPIO16", 294 294 + "GPIO17", "PCIE_WAKE#", "GPIO19", "GPIO20", 295 295 + "PCIE_PERST#", "", "", ""; 296 296 + 297 297 + pewake-hog { 298 298 + gpio-hog; 299 299 + gpios = <25 0>; 300 300 + input; 301 301 + line-name = "PCIE_WAKE#"; 302 302 + }; 303 303 + }; 304 304 + 305 305 + &gpio5 { 306 306 + pinctrl-names = "default"; 307 307 + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpt1_gpio>, 308 308 + <&pinctrl_gpt2_gpio>, <&pinctrl_gpt3_gpio>; 309 309 + 310 310 + gpio-line-names = "", "GPIO18", "", "GPIO3", 311 311 + "GPIO2", "GPIO21", "", "", 312 312 + "", "", "", "", 313 313 + "", "", "", "", 314 314 + "", "", "GPIO5", "GPIO6", 315 315 + "", "", "GPIO11", "GPIO10", 316 316 + "GPIO9", "GPIO7", "", "GPIO4", 317 317 + "", "", "", ""; 318 318 + }; 319 319 + 320 320 + &gpt1 { 321 321 + pinctrl-names = "default"; 322 322 + pinctrl-0 = <&pinctrl_gpt1>; 323 323 + status = "disabled"; 324 324 + }; 325 325 + 326 326 + &gpt2 { 327 327 + pinctrl-names = "default"; 328 328 + pinctrl-0 = <&pinctrl_gpt2>; 329 329 + status = "disabled"; 330 330 + }; 331 331 + 332 332 + &gpt3 { 333 333 + pinctrl-names = "default"; 334 334 + pinctrl-0 = <&pinctrl_gpt3>; 335 335 + status = "disabled"; 336 336 + }; 337 337 + 338 338 + &hdmi_pvi { 339 339 + status = "okay"; 340 340 + }; 341 341 + 342 342 + &hdmi_tx { 343 343 + pinctrl-names = "default"; 344 344 + pinctrl-0 = <&pinctrl_hdmi>; 345 345 + status = "okay"; 346 346 + 347 347 + ports { 348 348 + port@1 { 349 349 + hdmi_tx_out: endpoint { 350 350 + remote-endpoint = <&hdmi_connector_in>; 351 351 + }; 352 352 + }; 353 353 + }; 354 354 + }; 355 355 + 356 356 + &hdmi_tx_phy { 357 357 + status = "okay"; 358 358 + }; 359 359 + 360 360 + /* X5 + X6 Camera & Display interface */ 361 361 + &i2c2 { 362 362 + clock-frequency = <384000>; 363 363 + pinctrl-names = "default", "gpio"; 364 364 + pinctrl-0 = <&pinctrl_i2c2>; 365 365 + pinctrl-1 = <&pinctrl_i2c2_gpio>; 366 366 + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 367 367 + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 368 368 + status = "okay"; 369 369 + }; 370 370 + 371 371 + /* X1 ID_I2C */ 372 372 + &i2c3 { 373 373 + clock-frequency = <384000>; 374 374 + pinctrl-names = "default", "gpio"; 375 375 + pinctrl-0 = <&pinctrl_i2c3>; 376 376 + pinctrl-1 = <&pinctrl_i2c3_gpio>; 377 377 + scl-gpios = <&gpio2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 378 378 + sda-gpios = <&gpio2 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 379 379 + status = "okay"; 380 380 + }; 381 381 + 382 382 + &i2c4 { 383 383 + clock-frequency = <384000>; 384 384 + pinctrl-names = "default", "gpio"; 385 385 + pinctrl-0 = <&pinctrl_i2c4>; 386 386 + pinctrl-1 = <&pinctrl_i2c4_gpio>; 387 387 + scl-gpios = <&gpio5 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 388 388 + sda-gpios = <&gpio5 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 389 389 + status = "okay"; 390 390 + 391 391 + tlv320aic3x04: audio-codec@18 { 392 392 + compatible = "ti,tlv320aic32x4"; 393 393 + pinctrl-names = "default"; 394 394 + pinctrl-0 = <&pinctrl_tlv320aic3x04>; 395 395 + reg = <0x18>; 396 396 + clock-names = "mclk"; 397 397 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>; 398 398 + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 399 399 + iov-supply = <&reg_vcc_3v3>; 400 400 + ldoin-supply = <&reg_vcc_3v3>; 401 401 + }; 402 402 + }; 403 403 + 404 404 + /* X1 I2C */ 405 405 + &i2c5 { 406 406 + clock-frequency = <384000>; 407 407 + pinctrl-names = "default", "gpio"; 408 408 + pinctrl-0 = <&pinctrl_i2c5>; 409 409 + pinctrl-1 = <&pinctrl_i2c5_gpio>; 410 410 + scl-gpios = <&gpio5 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 411 411 + sda-gpios = <&gpio5 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 412 412 + status = "okay"; 413 413 + }; 414 414 + 415 415 + /* X1 I2C on GPIO24/GPIO25 */ 416 416 + &i2c6 { 417 417 + clock-frequency = <384000>; 418 418 + pinctrl-names = "default", "gpio"; 419 419 + pinctrl-0 = <&pinctrl_i2c6>; 420 420 + pinctrl-1 = <&pinctrl_i2c6_gpio>; 421 421 + scl-gpios = <&gpio2 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 422 422 + sda-gpios = <&gpio2 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 423 423 + status = "disabled"; 424 424 + }; 425 425 + 426 426 + &lcdif3 { 427 427 + status = "okay"; 428 428 + }; 429 429 + 430 430 + &pcf85063 { 431 431 + /* RTC_EVENT# is connected on MBa8MP-RAS314 */ 432 432 + pinctrl-names = "default"; 433 433 + pinctrl-0 = <&pinctrl_pcf85063>; 434 434 + interrupt-parent = <&gpio3>; 435 435 + interrupts = <19 IRQ_TYPE_EDGE_FALLING>; 436 436 + }; 437 437 + 438 438 + &pcie_phy { 439 439 + clocks = <&hsio_blk_ctrl>; 440 440 + clock-names = "ref"; 441 441 + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; 442 442 + status = "okay"; 443 443 + }; 444 444 + 445 445 + &pcie { 446 446 + pinctrl-names = "default"; 447 447 + pinctrl-0 = <&pinctrl_pcie>; 448 448 + reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>; 449 449 + status = "okay"; 450 450 + }; 451 451 + 452 452 + &pwm2 { 453 453 + pinctrl-names = "default"; 454 454 + pinctrl-0 = <&pinctrl_pwm2>; 455 455 + status = "disabled"; 456 456 + }; 457 457 + 458 458 + &pwm3 { 459 459 + pinctrl-names = "default"; 460 460 + pinctrl-0 = <&pinctrl_pwm3>; 461 461 + status = "okay"; 462 462 + }; 463 463 + 464 464 + &pwm4 { 465 465 + pinctrl-names = "default"; 466 466 + pinctrl-0 = <&pinctrl_pwm4>; 467 467 + status = "okay"; 468 468 + }; 469 469 + 470 470 + &sai5 { 471 471 + pinctrl-names = "default"; 472 472 + pinctrl-0 = <&pinctrl_sai5>; 473 473 + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; 474 474 + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; 475 475 + assigned-clock-rates = <12288000>; 476 476 + fsl,sai-mclk-direction-output; 477 477 + status = "okay"; 478 478 + }; 479 479 + 480 480 + &snvs_pwrkey { 481 481 + status = "okay"; 482 482 + }; 483 483 + 484 484 + /* X1 UART1 */ 485 485 + &uart1 { 486 486 + pinctrl-names = "default"; 487 487 + pinctrl-0 = <&pinctrl_uart1>; 488 488 + uart-has-rtscts; 489 489 + assigned-clocks = <&clk IMX8MP_CLK_UART1>; 490 490 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 491 491 + status = "okay"; 492 492 + }; 493 493 + 494 494 + &uart2 { 495 495 + pinctrl-names = "default"; 496 496 + pinctrl-0 = <&pinctrl_uart2>; 497 497 + uart-has-rtscts; 498 498 + assigned-clocks = <&clk IMX8MP_CLK_UART2>; 499 499 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 500 500 + status = "okay"; 501 501 + 502 502 + bluetooth { 503 503 + compatible = "nxp,88w8987-bt"; 504 504 + }; 505 505 + }; 506 506 + 507 507 + &uart3 { 508 508 + pinctrl-names = "default"; 509 509 + pinctrl-0 = <&pinctrl_uart3>; 510 510 + assigned-clocks = <&clk IMX8MP_CLK_UART3>; 511 511 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 512 512 + status = "okay"; 513 513 + }; 514 514 + 515 515 + &uart4 { 516 516 + /* console */ 517 517 + pinctrl-names = "default"; 518 518 + pinctrl-0 = <&pinctrl_uart4>; 519 519 + status = "okay"; 520 520 + }; 521 521 + 522 522 + &usb3_0 { 523 523 + fsl,disable-port-power-control; 524 524 + status = "okay"; 525 525 + }; 526 526 + 527 527 + &usb3_1 { 528 528 + fsl,disable-port-power-control; 529 529 + fsl,permanently-attached; 530 530 + status = "okay"; 531 531 + }; 532 532 + 533 533 + &usb3_phy0 { 534 534 + vbus-supply = <&reg_vcc_5v0>; 535 535 + status = "okay"; 536 536 + }; 537 537 + 538 538 + &usb3_phy1 { 539 539 + vbus-supply = <&reg_vcc_5v0>; 540 540 + status = "okay"; 541 541 + }; 542 542 + 543 543 + &usb_dwc3_0 { 544 544 + dr_mode = "peripheral"; 545 545 + status = "okay"; 546 546 + }; 547 547 + 548 548 + &usb_dwc3_1 { 549 549 + dr_mode = "host"; 550 550 + #address-cells = <1>; 551 551 + #size-cells = <0>; 552 552 + pinctrl-names = "default"; 553 553 + pinctrl-0 = <&pinctrl_usbhub>; 554 554 + status = "okay"; 555 555 + 556 556 + hub_2_0: hub@1 { 557 557 + compatible = "usb451,8142"; 558 558 + reg = <1>; 559 559 + peer-hub = <&hub_3_0>; 560 560 + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 561 561 + vdd-supply = <&reg_vcc_3v3>; 562 562 + }; 563 563 + 564 564 + hub_3_0: hub@2 { 565 565 + compatible = "usb451,8140"; 566 566 + reg = <2>; 567 567 + peer-hub = <&hub_2_0>; 568 568 + reset-gpios = <&gpio5 26 GPIO_ACTIVE_LOW>; 569 569 + vdd-supply = <&reg_vcc_3v3>; 570 570 + }; 571 571 + }; 572 572 + 573 573 + /* X1 SD card on GPIO22-GPIO27 */ 574 574 + &usdhc1 { 575 575 + pinctrl-names = "default"; 576 576 + pinctrl-0 = <&pinctrl_usdhc1>; 577 577 + disable-wp; 578 578 + bus-width = <4>; 579 579 + status = "disabled"; 580 580 + }; 581 581 + 582 582 + &usdhc2 { 583 583 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 584 584 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 585 585 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 586 586 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 587 587 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 588 588 + vmmc-supply = <&reg_usdhc2_vmmc>; 589 589 + no-mmc; 590 590 + no-sdio; 591 591 + disable-wp; 592 592 + bus-width = <4>; 593 593 + status = "okay"; 594 594 + }; 595 595 + 596 596 + &iomuxc { 597 597 + pinctrl_backlight: backlightgrp { 598 598 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x14>; 599 599 + }; 600 600 + 601 601 + pinctrl_ecspi3: ecspi3grp { 602 602 + fsl,pins = <MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x140>, 603 603 + <MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x140>, 604 604 + <MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x1c0>, 605 605 + <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x140>, 606 606 + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140>; 607 607 + }; 608 608 + 609 609 + pinctrl_ecspi3_gpio: ecspi3gpiogrp { 610 610 + fsl,pins = <MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x80>, 611 611 + <MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x80>, 612 612 + <MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x80>, 613 613 + <MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x80>, 614 614 + <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x80>; 615 615 + }; 616 616 + 617 617 + pinctrl_eqos: eqosgrp { 618 618 + fsl,pins = <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x40000044>, 619 619 + <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x40000044>, 620 620 + <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90>, 621 621 + <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90>, 622 622 + <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90>, 623 623 + <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90>, 624 624 + <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90>, 625 625 + <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90>, 626 626 + <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12>, 627 627 + <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12>, 628 628 + <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12>, 629 629 + <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12>, 630 630 + <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12>, 631 631 + <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x14>; 632 632 + }; 633 633 + 634 634 + pinctrl_eqos_phy: eqosphygrp { 635 635 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x100>, 636 636 + <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x1c0>; 637 637 + }; 638 638 + 639 639 + pinctrl_fec: fecgrp { 640 640 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x40000044>, 641 641 + <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x40000044>, 642 642 + <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90>, 643 643 + <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90>, 644 644 + <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90>, 645 645 + <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90>, 646 646 + <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90>, 647 647 + <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90>, 648 648 + <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12>, 649 649 + <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12>, 650 650 + <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x12>, 651 651 + <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x12>, 652 652 + <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x12>, 653 653 + <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14>; 654 654 + }; 655 655 + 656 656 + pinctrl_fec_phy: fecphygrp { 657 657 + fsl,pins = <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x100>, 658 658 + <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x1c0>; 659 659 + }; 660 660 + 661 661 + pinctrl_gpioled: gpioledgrp { 662 662 + fsl,pins = <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x14>, 663 663 + <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x14>; 664 664 + }; 665 665 + 666 666 + pinctrl_gpio1: gpio1grp { 667 667 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x14>, 668 668 + <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x14>; 669 669 + }; 670 670 + 671 671 + pinctrl_gpio2: gpio2grp { 672 672 + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x94>, 673 673 + <MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x94>, 674 674 + <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x94>, 675 675 + <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x94>, 676 676 + <MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x94>, 677 677 + <MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x94>, 678 678 + <MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x94>, 679 679 + <MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x94>; 680 680 + }; 681 681 + 682 682 + pinctrl_gpio3: gpio3grp { 683 683 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x180>; 684 684 + }; 685 685 + 686 686 + pinctrl_gpio4: gpio4grp { 687 687 + fsl,pins = <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x80>, 688 688 + /* PCIE_WAKE# */ 689 689 + <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x180>, 690 690 + <MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x94>, 691 691 + <MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x94>; 692 692 + }; 693 693 + 694 694 + pinctrl_gpio5: gpio5grp { 695 695 + fsl,pins = <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x80>, 696 696 + <MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x80>; 697 697 + }; 698 698 + 699 699 + pinctrl_hdmi: hdmigrp { 700 700 + fsl,pins = <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c2>, 701 701 + <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c2>, 702 702 + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010>, 703 703 + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000154>; 704 704 + }; 705 705 + 706 706 + pinctrl_gpt1: gpt1grp { 707 707 + fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x14>; 708 708 + }; 709 709 + 710 710 + pinctrl_gpt1_gpio: gpt1gpiogrp { 711 711 + fsl,pins = <MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x80>; 712 712 + }; 713 713 + 714 714 + pinctrl_gpt2: gpt2grp { 715 715 + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x14>; 716 716 + }; 717 717 + 718 718 + pinctrl_gpt2_gpio: gpt2gpiogrp { 719 719 + fsl,pins = <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x80>; 720 720 + }; 721 721 + 722 722 + pinctrl_gpt3: gpt3grp { 723 723 + fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x14>; 724 724 + }; 725 725 + 726 726 + pinctrl_gpt3_gpio: gpt3gpiogrp { 727 727 + fsl,pins = <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x80>; 728 728 + }; 729 729 + 730 730 + pinctrl_i2c2: i2c2grp { 731 731 + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001e2>, 732 732 + <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001e2>; 733 733 + }; 734 734 + 735 735 + pinctrl_i2c2_gpio: i2c2-gpiogrp { 736 736 + fsl,pins = <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001e2>, 737 737 + <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001e2>; 738 738 + }; 739 739 + 740 740 + pinctrl_i2c3: i2c3grp { 741 741 + fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x400001e2>, 742 742 + <MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x400001e2>; 743 743 + }; 744 744 + 745 745 + pinctrl_i2c3_gpio: i2c3-gpiogrp { 746 746 + fsl,pins = <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x400001e2>, 747 747 + <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x400001e2>; 748 748 + }; 749 749 + 750 750 + pinctrl_i2c4: i2c4grp { 751 751 + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x400001e2>, 752 752 + <MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x400001e2>; 753 753 + }; 754 754 + 755 755 + pinctrl_i2c4_gpio: i2c4-gpiogrp { 756 756 + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x400001e2>, 757 757 + <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x400001e2>; 758 758 + }; 759 759 + 760 760 + pinctrl_i2c5: i2c5grp { 761 761 + fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001e2>, 762 762 + <MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001e2>; 763 763 + }; 764 764 + 765 765 + pinctrl_i2c5_gpio: i2c5-gpiogrp { 766 766 + fsl,pins = <MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x400001e2>, 767 767 + <MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x400001e2>; 768 768 + }; 769 769 + 770 770 + pinctrl_i2c6: i2c6grp { 771 771 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x400001e2>, 772 772 + <MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x400001e2>; 773 773 + }; 774 774 + 775 775 + pinctrl_i2c6_gpio: i2c6-gpiogrp { 776 776 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x400001e2>, 777 777 + <MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x400001e2>; 778 778 + }; 779 779 + 780 780 + pinctrl_pcf85063: pcf85063grp { 781 781 + fsl,pins = <MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x80>; 782 782 + }; 783 783 + 784 784 + pinctrl_pcie: pciegrp { 785 785 + fsl,pins = <MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x60>, 786 786 + <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x94>; 787 787 + }; 788 788 + 789 789 + pinctrl_lvdsdisplay: lvdsdisplaygrp { 790 790 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x10>; 791 791 + }; 792 792 + 793 793 + pinctrl_pwm2: pwm2grp { 794 794 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x14>; 795 795 + }; 796 796 + 797 797 + pinctrl_pwm3: pwm3grp { 798 798 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x14>; 799 799 + }; 800 800 + 801 801 + pinctrl_pwm3_gpio: pwm3grpiogrp { 802 802 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x80>; 803 803 + }; 804 804 + 805 805 + pinctrl_pwm4: pwm4grp { 806 806 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x14>; 807 807 + }; 808 808 + 809 809 + pinctrl_pwm4_gpio: pwm4grpiogrp { 810 810 + fsl,pins = <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x80>; 811 811 + }; 812 812 + 813 813 + pinctrl_rfkill: rfkillgrp { 814 814 + fsl,pins = <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x14>; 815 815 + }; 816 816 + 817 817 + pinctrl_sai5: sai5grp { 818 818 + fsl,pins = <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x94>, 819 819 + <MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x94>, 820 820 + <MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x94>, 821 821 + <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x94>, 822 822 + <MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x94>; 823 823 + }; 824 824 + 825 825 + pinctrl_tlv320aic3x04: tlv320aic3x04grp { 826 826 + fsl,pins = <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x180>; 827 827 + }; 828 828 + 829 829 + pinctrl_uart1: uart1grp { 830 830 + fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x14>, 831 831 + <MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x14>, 832 832 + <MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x14>, 833 833 + <MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x14>; 834 834 + }; 835 835 + 836 836 + pinctrl_uart1_gpio: uart1gpiogrp { 837 837 + fsl,pins = <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x80>, 838 838 + <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x80>, 839 839 + <MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x80>, 840 840 + <MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x80>; 841 841 + }; 842 842 + 843 843 + pinctrl_uart2: uart2grp { 844 844 + fsl,pins = <MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x14>, 845 845 + <MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x14>, 846 846 + <MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x14>, 847 847 + <MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x14>; 848 848 + }; 849 849 + 850 850 + pinctrl_uart3: uart3grp { 851 851 + fsl,pins = <MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x140>, 852 852 + <MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x140>; 853 853 + }; 854 854 + 855 855 + pinctrl_uart4: uart4grp { 856 856 + fsl,pins = <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140>, 857 857 + <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140>; 858 858 + }; 859 859 + 860 860 + pinctrl_usbhub: usbhubgrp { 861 861 + fsl,pins = <MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x10>; 862 862 + }; 863 863 + 864 864 + pinctrl_usdhc1: usdhc1grp { 865 865 + fsl,pins = <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x192>, 866 866 + <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d2>, 867 867 + <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d2>, 868 868 + <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d2>, 869 869 + <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d2>, 870 870 + <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d2>; 871 871 + }; 872 872 + 873 873 + pinctrl_usdhc2: usdhc2grp { 874 874 + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x192>, 875 875 + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d2>, 876 876 + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d2>, 877 877 + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d2>, 878 878 + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d2>, 879 879 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d2>, 880 880 + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 881 881 + }; 882 882 + 883 883 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 884 884 + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 885 885 + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 886 886 + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 887 887 + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 888 888 + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 889 889 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 890 890 + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 891 891 + }; 892 892 + 893 893 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 894 894 + fsl,pins = <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>, 895 895 + <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>, 896 896 + <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>, 897 897 + <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>, 898 898 + <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>, 899 899 + <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>, 900 900 + <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0>; 901 901 + }; 902 902 + 903 903 + pinctrl_usdhc2_gpio: usdhc2-gpiogrp { 904 904 + fsl,pins = <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c0>; 905 905 + }; 906 906 + };

-5

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts

reviewed

··· 222 222 #size-cells = <2>; 223 223 ranges; 224 224 225 225 - ocram: ocram@900000 { 226 226 - no-map; 227 227 - reg = <0 0x900000 0 0x70000>; 228 228 - }; 229 229 - 230 225 /* global autoconfigured region for contiguous allocations */ 231 226 linux,cma { 232 227 compatible = "shared-dma-pool";

+6 -2

arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql.dtsi

reviewed

··· 45 45 46 46 flash0: flash@0 { 47 47 reg = <0>; 48 48 - #address-cells = <1>; 49 49 - #size-cells = <1>; 50 48 compatible = "jedec,spi-nor"; 51 49 spi-max-frequency = <80000000>; 52 50 spi-tx-bus-width = <1>; 53 51 spi-rx-bus-width = <4>; 52 52 + 53 53 + partitions { 54 54 + compatible = "fixed-partitions"; 55 55 + #address-cells = <1>; 56 56 + #size-cells = <1>; 57 57 + }; 54 58 }; 55 59 }; 56 60

+20

arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi

reviewed

··· 5 5 6 6 #include <dt-bindings/gpio/gpio.h> 7 7 #include <dt-bindings/input/linux-event-codes.h> 8 8 + #include <dt-bindings/leds/common.h> 8 9 #include <dt-bindings/net/ti-dp83867.h> 9 10 10 11 / { ··· 103 102 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 104 103 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 105 104 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 105 105 + 106 106 + leds { 107 107 + #address-cells = <1>; 108 108 + #size-cells = <0>; 109 109 + 110 110 + led@1 { 111 111 + reg = <1>; 112 112 + color = <LED_COLOR_ID_AMBER>; 113 113 + function = LED_FUNCTION_LAN; 114 114 + default-state = "keep"; 115 115 + }; 116 116 + 117 117 + led@2 { 118 118 + reg = <2>; 119 119 + color = <LED_COLOR_ID_GREEN>; 120 120 + function = LED_FUNCTION_LAN; 121 121 + default-state = "keep"; 122 122 + }; 123 123 + }; 106 124 }; 107 125 }; 108 126 };

+24

arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts

reviewed

··· 9 9 #include <dt-bindings/input/linux-event-codes.h> 10 10 #include <dt-bindings/leds/common.h> 11 11 #include <dt-bindings/phy/phy-imx8-pcie.h> 12 12 + #include <dt-bindings/net/ti-dp83867.h> 12 13 13 14 #include "imx8mp.dtsi" 14 15 ··· 226 225 ethphy0: ethernet-phy@0 { 227 226 compatible = "ethernet-phy-ieee802.3-c22"; 228 227 reg = <0x0>; 228 228 + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 229 229 + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 230 230 + tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 231 231 + rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 232 232 + 233 233 + leds { 234 234 + #address-cells = <1>; 235 235 + #size-cells = <0>; 236 236 + 237 237 + led@1 { 238 238 + reg = <1>; 239 239 + color = <LED_COLOR_ID_AMBER>; 240 240 + function = LED_FUNCTION_LAN; 241 241 + default-state = "keep"; 242 242 + }; 243 243 + 244 244 + led@2 { 245 245 + reg = <2>; 246 246 + color = <LED_COLOR_ID_GREEN>; 247 247 + function = LED_FUNCTION_LAN; 248 248 + default-state = "keep"; 249 249 + }; 250 250 + }; 229 251 }; 230 252 }; 231 253 };

+37

arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi

reviewed

··· 4 4 */ 5 5 6 6 / { 7 7 + native-hdmi-connector { 8 8 + compatible = "hdmi-connector"; 9 9 + label = "X21"; 10 10 + type = "a"; 11 11 + 12 12 + port { 13 13 + native_hdmi_connector_in: endpoint { 14 14 + remote-endpoint = <&hdmi_tx_out>; 15 15 + }; 16 16 + }; 17 17 + }; 18 18 + 7 19 sound { 8 20 compatible = "simple-audio-card"; 9 21 simple-audio-card,bitclock-master = <&codec_dai>; ··· 106 94 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 107 95 }; 108 96 97 97 + /* Verdin HDMI_1 */ 98 98 + &hdmi_pvi { 99 99 + status = "okay"; 100 100 + }; 101 101 + 102 102 + &hdmi_tx { 103 103 + status = "okay"; 104 104 + 105 105 + ports { 106 106 + port@1 { 107 107 + hdmi_tx_out: endpoint { 108 108 + remote-endpoint = <&native_hdmi_connector_in>; 109 109 + }; 110 110 + }; 111 111 + }; 112 112 + }; 113 113 + 114 114 + &hdmi_tx_phy { 115 115 + status = "okay"; 116 116 + }; 117 117 + 109 118 /* Current measurement into module VCC */ 110 119 &hwmon { 111 120 status = "okay"; ··· 169 136 170 137 /* Verdin I2C_3_HDMI */ 171 138 &i2c5 { 139 139 + status = "okay"; 140 140 + }; 141 141 + 142 142 + &lcdif3 { 172 143 status = "okay"; 173 144 }; 174 145

+37

arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi

reviewed

··· 4 4 */ 5 5 6 6 / { 7 7 + native-hdmi-connector { 8 8 + compatible = "hdmi-connector"; 9 9 + label = "X37"; 10 10 + type = "a"; 11 11 + 12 12 + port { 13 13 + native_hdmi_connector_in: endpoint { 14 14 + remote-endpoint = <&hdmi_tx_out>; 15 15 + }; 16 16 + }; 17 17 + }; 18 18 + 7 19 reg_eth2phy: regulator-eth2phy { 8 20 compatible = "regulator-fixed"; 9 21 enable-active-high; ··· 115 103 vcc-supply = <&reg_1p8v>; 116 104 }; 117 105 106 106 + /* Verdin HDMI_1 */ 107 107 + &hdmi_pvi { 108 108 + status = "okay"; 109 109 + }; 110 110 + 111 111 + &hdmi_tx { 112 112 + status = "okay"; 113 113 + 114 114 + ports { 115 115 + port@1 { 116 116 + hdmi_tx_out: endpoint { 117 117 + remote-endpoint = <&native_hdmi_connector_in>; 118 118 + }; 119 119 + }; 120 120 + }; 121 121 + }; 122 122 + 123 123 + &hdmi_tx_phy { 124 124 + status = "okay"; 125 125 + }; 126 126 + 118 127 /* Current measurement into module VCC */ 119 128 &hwmon { 120 129 status = "okay"; ··· 171 138 172 139 /* Verdin I2C_3_HDMI */ 173 140 &i2c5 { 141 141 + status = "okay"; 142 142 + }; 143 143 + 144 144 + &lcdif3 { 174 145 status = "okay"; 175 146 }; 176 147

+37

arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi

reviewed

··· 11 11 #include <dt-bindings/leds/common.h> 12 12 13 13 / { 14 14 + native-hdmi-connector { 15 15 + compatible = "hdmi-connector"; 16 16 + label = "X14"; 17 17 + type = "a"; 18 18 + 19 19 + port { 20 20 + native_hdmi_connector_in: endpoint { 21 21 + remote-endpoint = <&hdmi_tx_out>; 22 22 + }; 23 23 + }; 24 24 + }; 25 25 + 14 26 leds { 15 27 compatible = "gpio-leds"; 16 28 pinctrl-names = "default"; ··· 103 91 status = "okay"; 104 92 }; 105 93 94 94 + /* Verdin HDMI_1 */ 95 95 + &hdmi_pvi { 96 96 + status = "okay"; 97 97 + }; 98 98 + 99 99 + &hdmi_tx { 100 100 + status = "okay"; 101 101 + 102 102 + ports { 103 103 + port@1 { 104 104 + hdmi_tx_out: endpoint { 105 105 + remote-endpoint = <&native_hdmi_connector_in>; 106 106 + }; 107 107 + }; 108 108 + }; 109 109 + }; 110 110 + 111 111 + &hdmi_tx_phy { 112 112 + status = "okay"; 113 113 + }; 114 114 + 106 115 /* Temperature sensor on Mallow */ 107 116 &hwmon_temp { 108 117 compatible = "ti,tmp1075"; ··· 147 114 148 115 /* Verdin I2C_3_HDMI */ 149 116 &i2c5 { 117 117 + status = "okay"; 118 118 + }; 119 119 + 120 120 + &lcdif3 { 150 121 status = "okay"; 151 122 }; 152 123

+1 -2

arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi

reviewed

··· 41 41 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 42 42 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 43 43 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 44 44 - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, 45 45 - <&pinctrl_hdmi_hog>; 44 44 + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; 46 45 }; 47 46 48 47 /*

+1 -2

arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi

reviewed

··· 55 55 pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, 56 56 <&pinctrl_gpio3>, <&pinctrl_gpio4>, 57 57 <&pinctrl_gpio7>, <&pinctrl_gpio8>, 58 58 - <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, 59 59 - <&pinctrl_hdmi_hog>; 58 58 + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>; 60 59 }; 61 60 62 61 /* On-module Bluetooth */

+37

arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi

reviewed

··· 6 6 #include <dt-bindings/leds/common.h> 7 7 8 8 / { 9 9 + native-hdmi-connector { 10 10 + compatible = "hdmi-connector"; 11 11 + label = "J15"; 12 12 + type = "a"; 13 13 + 14 14 + port { 15 15 + native_hdmi_connector_in: endpoint { 16 16 + remote-endpoint = <&hdmi_tx_out>; 17 17 + }; 18 18 + }; 19 19 + }; 20 20 + 9 21 /* Carrier Board Supply +V1.8 */ 10 22 reg_1p8v: regulator-1p8v { 11 23 compatible = "regulator-fixed"; ··· 117 105 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>; 118 106 }; 119 107 108 108 + /* Verdin HDMI_1 */ 109 109 + &hdmi_pvi { 110 110 + status = "okay"; 111 111 + }; 112 112 + 113 113 + &hdmi_tx { 114 114 + status = "okay"; 115 115 + 116 116 + ports { 117 117 + port@1 { 118 118 + hdmi_tx_out: endpoint { 119 119 + remote-endpoint = <&native_hdmi_connector_in>; 120 120 + }; 121 121 + }; 122 122 + }; 123 123 + }; 124 124 + 125 125 + &hdmi_tx_phy { 126 126 + status = "okay"; 127 127 + }; 128 128 + 120 129 &hwmon_temp { 121 130 status = "okay"; 122 131 }; ··· 157 124 158 125 /* Verdin I2C_3_HDMI */ 159 126 &i2c5 { 127 127 + status = "okay"; 128 128 + }; 129 129 + 130 130 + &lcdif3 { 160 131 status = "okay"; 161 132 }; 162 133

+11 -7

arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi

reviewed

··· 241 241 242 242 mtl_rx_setup: rx-queues-config { 243 243 snps,rx-queues-to-use = <5>; 244 244 - snps,rx-sched-sp; 245 244 246 245 queue0 { 247 246 snps,dcb-algorithm; ··· 275 276 276 277 mtl_tx_setup: tx-queues-config { 277 278 snps,tx-queues-to-use = <5>; 278 278 - snps,tx-sched-sp; 279 279 280 280 queue0 { 281 281 snps,dcb-algorithm; ··· 453 455 "SODIMM_256", 454 456 "SODIMM_48", 455 457 "SODIMM_44"; 458 458 + }; 459 459 + 460 460 + /* Verdin HDMI_1 */ 461 461 + &hdmi_tx { 462 462 + ddc-i2c-bus = <&i2c5>; 463 463 + pinctrl-names = "default"; 464 464 + pinctrl-0 = <&pinctrl_hdmi>; 456 465 }; 457 466 458 467 /* On-module I2C */ ··· 655 650 656 651 /* Verdin I2C_2_DSI */ 657 652 &i2c2 { 658 658 - /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */ 659 659 - clock-frequency = <10000>; 653 653 + clock-frequency = <400000>; 660 654 pinctrl-names = "default", "gpio"; 661 655 pinctrl-0 = <&pinctrl_i2c2>; 662 656 pinctrl-1 = <&pinctrl_i2c2_gpio>; ··· 1121 1117 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */ 1122 1118 }; 1123 1119 1124 1124 - pinctrl_hdmi_hog: hdmihoggrp { 1120 1120 + pinctrl_hdmi: hdmigrp { 1125 1121 fsl,pins = 1126 1126 - <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */ 1127 1127 - <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */ 1122 1122 + <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x140>, /* SODIMM 63 */ 1123 1123 + <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x180>; /* SODIMM 61 */ 1128 1124 }; 1129 1125 1130 1126 /* On-module I2C */

+75 -45

arch/arm64/boot/dts/freescale/imx8mp.dtsi

reviewed

··· 789 789 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 790 790 }; 791 791 792 792 + pgc_mlmix: power-domain@4 { 793 793 + #power-domain-cells = <0>; 794 794 + reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 795 795 + clocks = <&clk IMX8MP_CLK_ML_AXI>, 796 796 + <&clk IMX8MP_CLK_ML_AHB>, 797 797 + <&clk IMX8MP_CLK_NPU_ROOT>; 798 798 + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 799 799 + <&clk IMX8MP_CLK_ML_AXI>, 800 800 + <&clk IMX8MP_CLK_ML_AHB>; 801 801 + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 802 802 + <&clk IMX8MP_SYS_PLL1_800M>, 803 803 + <&clk IMX8MP_SYS_PLL1_800M>; 804 804 + assigned-clock-rates = <800000000>, 805 805 + <800000000>, 806 806 + <300000000>; 807 807 + }; 808 808 + 792 809 pgc_audio: power-domain@5 { 793 810 #power-domain-cells = <0>; 794 811 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; ··· 838 821 assigned-clock-rates = <800000000>, <400000000>; 839 822 }; 840 823 824 824 + pgc_vpumix: power-domain@8 { 825 825 + #power-domain-cells = <0>; 826 826 + reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 827 827 + clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 828 828 + }; 829 829 + 841 830 pgc_gpu3d: power-domain@9 { 842 831 #power-domain-cells = <0>; 843 832 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; ··· 857 834 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 858 835 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 859 836 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 837 837 + }; 838 838 + 839 839 + pgc_vpu_g1: power-domain@11 { 840 840 + #power-domain-cells = <0>; 841 841 + power-domains = <&pgc_vpumix>; 842 842 + reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 843 843 + clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 844 844 + }; 845 845 + 846 846 + pgc_vpu_g2: power-domain@12 { 847 847 + #power-domain-cells = <0>; 848 848 + power-domains = <&pgc_vpumix>; 849 849 + reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 850 850 + clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 851 851 + 852 852 + }; 853 853 + 854 854 + pgc_vpu_vc8000e: power-domain@13 { 855 855 + #power-domain-cells = <0>; 856 856 + power-domains = <&pgc_vpumix>; 857 857 + reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 858 858 + clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 860 859 }; 861 860 862 861 pgc_hdmimix: power-domain@14 { ··· 917 872 #power-domain-cells = <0>; 918 873 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 919 874 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 920 920 - }; 921 921 - 922 922 - pgc_vpumix: power-domain@19 { 923 923 - #power-domain-cells = <0>; 924 924 - reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 925 925 - clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 926 926 - }; 927 927 - 928 928 - pgc_vpu_g1: power-domain@20 { 929 929 - #power-domain-cells = <0>; 930 930 - power-domains = <&pgc_vpumix>; 931 931 - reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 932 932 - clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 933 933 - }; 934 934 - 935 935 - pgc_vpu_g2: power-domain@21 { 936 936 - #power-domain-cells = <0>; 937 937 - power-domains = <&pgc_vpumix>; 938 938 - reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 939 939 - clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 940 940 - }; 941 941 - 942 942 - pgc_vpu_vc8000e: power-domain@22 { 943 943 - #power-domain-cells = <0>; 944 944 - power-domains = <&pgc_vpumix>; 945 945 - reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 946 946 - clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 947 947 - }; 948 948 - 949 949 - pgc_mlmix: power-domain@24 { 950 950 - #power-domain-cells = <0>; 951 951 - reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 952 952 - clocks = <&clk IMX8MP_CLK_ML_AXI>, 953 953 - <&clk IMX8MP_CLK_ML_AHB>, 954 954 - <&clk IMX8MP_CLK_NPU_ROOT>; 955 955 - assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 956 956 - <&clk IMX8MP_CLK_ML_AXI>, 957 957 - <&clk IMX8MP_CLK_ML_AHB>; 958 958 - assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 959 959 - <&clk IMX8MP_SYS_PLL1_800M>, 960 960 - <&clk IMX8MP_SYS_PLL1_800M>; 961 961 - assigned-clock-rates = <800000000>, 962 962 - <800000000>, 963 963 - <300000000>; 964 875 }; 965 876 }; 966 877 }; ··· 1541 1540 dma-names = "tx"; 1542 1541 status = "disabled"; 1543 1542 }; 1543 1543 + 1544 1544 + xcvr: xcvr@30cc0000 { 1545 1545 + compatible = "fsl,imx8mp-xcvr"; 1546 1546 + reg = <0x30cc0000 0x800>, 1547 1547 + <0x30cc0800 0x400>, 1548 1548 + <0x30cc0c00 0x080>, 1549 1549 + <0x30cc0e00 0x080>; 1550 1550 + reg-names = "ram", "regs", "rxfifo", 1551 1551 + "txfifo"; 1552 1552 + interrupts = /* XCVR IRQ 0 */ 1553 1553 + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1554 1554 + /* XCVR IRQ 1 */ 1555 1555 + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1556 1556 + /* XCVR PHY - SPDIF wakeup IRQ */ 1557 1557 + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1558 1558 + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, 1559 1559 + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, 1560 1560 + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, 1561 1561 + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; 1562 1562 + clock-names = "ipg", "phy", "spba", "pll_ipg"; 1563 1563 + dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; 1564 1564 + dma-names = "rx", "tx"; 1565 1565 + resets = <&audio_blk_ctrl 0>; 1566 1566 + status = "disabled"; 1567 1567 + }; 1544 1568 }; 1545 1569 1546 1570 sdma3: dma-controller@30e00000 { ··· 1594 1568 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1595 1569 reg = <0x30e20000 0x10000>; 1596 1570 #clock-cells = <1>; 1571 1571 + #reset-cells = <1>; 1597 1572 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1598 1573 <&clk IMX8MP_CLK_SAI1>, 1599 1574 <&clk IMX8MP_CLK_SAI2>, ··· 1606 1579 "sai1", "sai2", "sai3", 1607 1580 "sai5", "sai6", "sai7"; 1608 1581 power-domains = <&pgc_audio>; 1582 1582 + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 1583 1583 + <&clk IMX8MP_AUDIO_PLL2>; 1584 1584 + assigned-clock-rates = <393216000>, <361267200>; 1609 1585 }; 1610 1586 }; 1611 1587 ··· 1976 1946 }; 1977 1947 1978 1948 irqsteer_hdmi: interrupt-controller@32fc2000 { 1979 1979 - compatible = "fsl,imx-irqsteer"; 1949 1949 + compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; 1980 1950 reg = <0x32fc2000 0x1000>; 1981 1951 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1982 1952 interrupt-controller;

-2

arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi

reviewed

··· 45 45 gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; 46 46 linux,code = <KEY_VOLUMEDOWN>; 47 47 debounce-interval = <50>; 48 48 - wakeup-source; 49 48 }; 50 49 51 50 key-vol-up { ··· 52 53 gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; 53 54 linux,code = <KEY_VOLUMEUP>; 54 55 debounce-interval = <50>; 55 55 - wakeup-source; 56 56 }; 57 57 }; 58 58

+6 -2

arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi

reviewed

··· 251 251 flash0: flash@0 { 252 252 compatible = "jedec,spi-nor"; 253 253 reg = <0>; 254 254 - #address-cells = <1>; 255 255 - #size-cells = <1>; 256 254 spi-max-frequency = <84000000>; 257 255 spi-tx-bus-width = <1>; 258 256 spi-rx-bus-width = <4>; 257 257 + 258 258 + partitions { 259 259 + compatible = "fixed-partitions"; 260 260 + #address-cells = <1>; 261 261 + #size-cells = <1>; 262 262 + }; 259 263 }; 260 264 }; 261 265

+344

arch/arm64/boot/dts/freescale/imx8qm-mek.dts

reviewed

··· 40 40 enable-active-high; 41 41 }; 42 42 43 43 + reg_fec2_supply: regulator-fec2-nvcc { 44 44 + compatible = "regulator-fixed"; 45 45 + regulator-name = "fec2_nvcc"; 46 46 + regulator-min-microvolt = <1800000>; 47 47 + regulator-max-microvolt = <1800000>; 48 48 + gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; 49 49 + enable-active-high; 50 50 + }; 51 51 + 52 52 + reg_can01_en: regulator-can01-gen { 53 53 + compatible = "regulator-fixed"; 54 54 + regulator-name = "can01-en"; 55 55 + regulator-min-microvolt = <3300000>; 56 56 + regulator-max-microvolt = <3300000>; 57 57 + gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; 58 58 + enable-active-high; 59 59 + }; 60 60 + 61 61 + reg_can2_en: regulator-can2-gen { 62 62 + compatible = "regulator-fixed"; 63 63 + regulator-name = "can2-en"; 64 64 + regulator-min-microvolt = <3300000>; 65 65 + regulator-max-microvolt = <3300000>; 66 66 + gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>; 67 67 + enable-active-high; 68 68 + }; 69 69 + 70 70 + reg_can01_stby: regulator-can01-stby { 71 71 + compatible = "regulator-fixed"; 72 72 + regulator-name = "can01-stby"; 73 73 + regulator-min-microvolt = <3300000>; 74 74 + regulator-max-microvolt = <3300000>; 75 75 + gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; 76 76 + enable-active-high; 77 77 + vin-supply = <&reg_can01_en>; 78 78 + }; 79 79 + 80 80 + reg_can2_stby: regulator-can2-stby { 81 81 + compatible = "regulator-fixed"; 82 82 + regulator-name = "can2-stby"; 83 83 + regulator-min-microvolt = <3300000>; 84 84 + regulator-max-microvolt = <3300000>; 85 85 + gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>; 86 86 + enable-active-high; 87 87 + vin-supply = <&reg_can2_en>; 88 88 + }; 89 89 + 43 90 reg_vref_1v8: regulator-adc-vref { 44 91 compatible = "regulator-fixed"; 45 92 regulator-name = "vref_1v8"; 46 93 regulator-min-microvolt = <1800000>; 47 94 regulator-max-microvolt = <1800000>; 95 95 + }; 96 96 + 97 97 + bt_sco_codec: audio-codec-bt { 98 98 + compatible = "linux,bt-sco"; 99 99 + #sound-dai-cells = <1>; 100 100 + }; 101 101 + 102 102 + sound-bt-sco { 103 103 + compatible = "simple-audio-card"; 104 104 + simple-audio-card,name = "bt-sco-audio"; 105 105 + simple-audio-card,format = "dsp_a"; 106 106 + simple-audio-card,bitclock-inversion; 107 107 + simple-audio-card,frame-master = <&btcpu>; 108 108 + simple-audio-card,bitclock-master = <&btcpu>; 109 109 + 110 110 + btcpu: simple-audio-card,cpu { 111 111 + sound-dai = <&sai0>; 112 112 + dai-tdm-slot-num = <2>; 113 113 + dai-tdm-slot-width = <16>; 114 114 + }; 115 115 + 116 116 + simple-audio-card,codec { 117 117 + sound-dai = <&bt_sco_codec 1>; 118 118 + }; 119 119 + }; 120 120 + 121 121 + sound-wm8960 { 122 122 + compatible = "fsl,imx-audio-wm8960"; 123 123 + model = "wm8960-audio"; 124 124 + audio-cpu = <&sai1>; 125 125 + audio-codec = <&wm8960>; 126 126 + hp-det-gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; 127 127 + audio-routing = "Headphone Jack", "HP_L", 128 128 + "Headphone Jack", "HP_R", 129 129 + "Ext Spk", "SPK_LP", 130 130 + "Ext Spk", "SPK_LN", 131 131 + "Ext Spk", "SPK_RP", 132 132 + "Ext Spk", "SPK_RN", 133 133 + "LINPUT1", "Mic Jack", 134 134 + "Mic Jack", "MICB"; 48 135 }; 49 136 }; 50 137 ··· 140 53 pinctrl-0 = <&pinctrl_adc0>; 141 54 vref-supply = <&reg_vref_1v8>; 142 55 status = "okay"; 56 56 + }; 57 57 + 58 58 + &amix { 59 59 + status = "okay"; 60 60 + }; 61 61 + 62 62 + &asrc0 { 63 63 + fsl,asrc-rate = <48000>; 64 64 + status = "okay"; 65 65 + }; 66 66 + 67 67 + &cm41_i2c { 68 68 + #address-cells = <1>; 69 69 + #size-cells = <0>; 70 70 + clock-frequency = <100000>; 71 71 + pinctrl-names = "default"; 72 72 + pinctrl-0 = <&pinctrl_cm41_i2c>; 73 73 + status = "okay"; 74 74 + 75 75 + pca6416: gpio@20 { 76 76 + compatible = "ti,tca6416"; 77 77 + reg = <0x20>; 78 78 + gpio-controller; 79 79 + #gpio-cells = <2>; 80 80 + }; 81 81 + }; 82 82 + 83 83 + &cm41_intmux { 84 84 + status = "okay"; 85 85 + }; 86 86 + 87 87 + &i2c0 { 88 88 + #address-cells = <1>; 89 89 + #size-cells = <0>; 90 90 + clock-frequency = <100000>; 91 91 + pinctrl-names = "default"; 92 92 + pinctrl-0 = <&pinctrl_i2c0>; 93 93 + status = "okay"; 94 94 + 95 95 + accelerometer@19 { 96 96 + compatible = "st,lsm303agr-accel"; 97 97 + reg = <0x19>; 98 98 + }; 99 99 + 100 100 + gyrometer@20 { 101 101 + compatible = "nxp,fxas21002c"; 102 102 + reg = <0x20>; 103 103 + }; 104 104 + 105 105 + light-sensor@44 { 106 106 + compatible = "isil,isl29023"; 107 107 + reg = <0x44>; 108 108 + interrupt-parent = <&lsio_gpio4>; 109 109 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 110 110 + }; 111 111 + 112 112 + pressure-sensor@60 { 113 113 + compatible = "fsl,mpl3115"; 114 114 + reg = <0x60>; 115 115 + }; 116 116 + 117 117 + max7322: gpio@68 { 118 118 + compatible = "maxim,max7322"; 119 119 + reg = <0x68>; 120 120 + gpio-controller; 121 121 + #gpio-cells = <2>; 122 122 + }; 123 123 + 124 124 + gyrometer@69 { 125 125 + compatible = "st,l3g4200d-gyro"; 126 126 + reg = <0x69>; 127 127 + }; 143 128 }; 144 129 145 130 &i2c1 { ··· 223 64 pinctrl-1 = <&pinctrl_i2c1_gpio>; 224 65 scl-gpios = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>; 225 66 sda-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_HIGH>; 67 67 + status = "okay"; 68 68 + 69 69 + wm8960: audio-codec@1a { 70 70 + compatible = "wlf,wm8960"; 71 71 + reg = <0x1a>; 72 72 + clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>; 73 73 + clock-names = "mclk"; 74 74 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 75 75 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 76 76 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 77 77 + <&mclkout0_lpcg IMX_LPCG_CLK_0>; 78 78 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; 79 79 + wlf,shared-lrclk; 80 80 + wlf,hp-cfg = <2 2 3>; 81 81 + wlf,gpio-cfg = <1 3>; 82 82 + }; 83 83 + }; 84 84 + 85 85 + &flexcan1 { 86 86 + pinctrl-names = "default"; 87 87 + pinctrl-0 = <&pinctrl_flexcan1>; 88 88 + xceiver-supply = <&reg_can01_stby>; 89 89 + status = "okay"; 90 90 + }; 91 91 + 92 92 + &flexcan2 { 93 93 + pinctrl-names = "default"; 94 94 + pinctrl-0 = <&pinctrl_flexcan2>; 95 95 + xceiver-supply = <&reg_can01_stby>; 96 96 + status = "okay"; 97 97 + }; 98 98 + 99 99 + &flexcan3 { 100 100 + pinctrl-names = "default"; 101 101 + pinctrl-0 = <&pinctrl_flexcan3>; 102 102 + xceiver-supply = <&reg_can2_stby>; 226 103 status = "okay"; 227 104 }; 228 105 ··· 293 98 compatible = "rohm,dh2228fv"; 294 99 spi-max-frequency = <30000000>; 295 100 }; 101 101 + }; 102 102 + 103 103 + &lsio_mu5 { 104 104 + status = "okay"; 105 105 + }; 106 106 + 107 107 + &lsio_mu6 { 108 108 + status = "okay"; 296 109 }; 297 110 298 111 &flexspi0 { ··· 343 140 }; 344 141 }; 345 142 143 143 + &fec2 { 144 144 + pinctrl-names = "default"; 145 145 + pinctrl-0 = <&pinctrl_fec2>; 146 146 + phy-mode = "rgmii-txid"; 147 147 + phy-handle = <&ethphy1>; 148 148 + phy-supply = <&reg_fec2_supply>; 149 149 + nvmem-cells = <&fec_mac1>; 150 150 + nvmem-cell-names = "mac-address"; 151 151 + rx-internal-delay-ps = <2000>; 152 152 + fsl,magic-packet; 153 153 + status = "okay"; 154 154 + }; 155 155 + 346 156 &usdhc1 { 347 157 pinctrl-names = "default"; 348 158 pinctrl-0 = <&pinctrl_usdhc1>; ··· 376 160 status = "okay"; 377 161 }; 378 162 163 163 + &sai0 { 164 164 + #sound-dai-cells = <0>; 165 165 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 166 166 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 167 167 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 168 168 + <&sai0_lpcg IMX_LPCG_CLK_4>; 169 169 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 170 170 + pinctrl-names = "default"; 171 171 + pinctrl-0 = <&pinctrl_sai0>; 172 172 + status = "okay"; 173 173 + }; 174 174 + 175 175 + &sai1 { 176 176 + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, 177 177 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, 178 178 + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, 179 179 + <&sai1_lpcg IMX_LPCG_CLK_4>; 180 180 + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; 181 181 + pinctrl-names = "default"; 182 182 + pinctrl-0 = <&pinctrl_sai1>; 183 183 + status = "okay"; 184 184 + }; 185 185 + 186 186 + &sai6 { 187 187 + assigned-clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 188 188 + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 189 189 + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 190 190 + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 191 191 + <&sai6_lpcg IMX_LPCG_CLK_4>; 192 192 + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 193 193 + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 194 194 + fsl,sai-asynchronous; 195 195 + status = "okay"; 196 196 + }; 197 197 + 198 198 + &sai7 { 199 199 + assigned-clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 200 200 + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_PLL>, 201 201 + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_SLV_BUS>, 202 202 + <&clk IMX_SC_R_AUDIO_PLL_1 IMX_SC_PM_CLK_MST_BUS>, 203 203 + <&sai7_lpcg IMX_LPCG_CLK_4>; 204 204 + assigned-clock-parents = <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>; 205 205 + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; 206 206 + fsl,sai-asynchronous; 207 207 + status = "okay"; 208 208 + }; 209 209 + 379 210 &iomuxc { 211 211 + pinctrl-names = "default"; 212 212 + pinctrl-0 = <&pinctrl_hog>; 213 213 + 214 214 + pinctrl_hog: hoggrp { 215 215 + fsl,pins = < 216 216 + IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c 217 217 + IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c 218 218 + >; 219 219 + }; 220 220 + 221 221 + pinctrl_i2c0: i2c0grp { 222 222 + fsl,pins = < 223 223 + IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 224 224 + IMX8QM_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021 225 225 + >; 226 226 + }; 227 227 + 380 228 pinctrl_i2c1: i2c1grp { 381 229 fsl,pins = < 382 230 IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x0600004c ··· 458 178 pinctrl_adc0: adc0grp { 459 179 fsl,pins = < 460 180 IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060 181 181 + >; 182 182 + }; 183 183 + 184 184 + pinctrl_cm41_i2c: cm41i2cgrp { 185 185 + fsl,pins = < 186 186 + IMX8QM_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c 187 187 + IMX8QM_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c 461 188 >; 462 189 }; 463 190 ··· 522 235 >; 523 236 }; 524 237 238 238 + pinctrl_fec2: fec2grp { 239 239 + fsl,pins = < 240 240 + IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 241 241 + IMX8QM_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 242 242 + IMX8QM_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 243 243 + IMX8QM_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 244 244 + IMX8QM_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 245 245 + IMX8QM_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 246 246 + IMX8QM_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 247 247 + IMX8QM_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 248 248 + IMX8QM_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 249 249 + IMX8QM_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 250 250 + IMX8QM_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 251 251 + IMX8QM_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 252 252 + IMX8QM_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 253 253 + >; 254 254 + }; 255 255 + 256 256 + pinctrl_flexcan1: flexcan0grp { 257 257 + fsl,pins = < 258 258 + IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 259 259 + IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 260 260 + >; 261 261 + }; 262 262 + 263 263 + pinctrl_flexcan2: flexcan1grp { 264 264 + fsl,pins = < 265 265 + IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 266 266 + IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 267 267 + >; 268 268 + }; 269 269 + 270 270 + pinctrl_flexcan3: flexcan3grp { 271 271 + fsl,pins = < 272 272 + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 273 273 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 274 274 + >; 275 275 + }; 276 276 + 525 277 pinctrl_lpuart0: lpuart0grp { 526 278 fsl,pins = < 527 279 IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020 ··· 579 253 fsl,pins = < 580 254 IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 581 255 IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 256 256 + >; 257 257 + }; 258 258 + 259 259 + pinctrl_sai0: sai0grp { 260 260 + fsl,pins = < 261 261 + IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0x0600004c 262 262 + IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0x0600004c 263 263 + IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0x0600004c 264 264 + IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0x0600006c 265 265 + >; 266 266 + }; 267 267 + 268 268 + pinctrl_sai1: sai1grp { 269 269 + fsl,pins = < 270 270 + IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0x06000040 271 271 + IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0x06000040 272 272 + IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0x06000060 273 273 + IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0x06000040 582 274 >; 583 275 }; 584 276

+473

arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + * Dong Aisheng <aisheng.dong@nxp.com> 5 5 + */ 6 6 + 7 7 + /delete-node/ &acm; 8 8 + /delete-node/ &sai4; 9 9 + /delete-node/ &sai5; 10 10 + /delete-node/ &sai4_lpcg; 11 11 + /delete-node/ &sai5_lpcg; 12 12 + 13 13 + &amix { 14 14 + dais = <&sai6>, <&sai7>; 15 15 + }; 16 16 + 17 17 + &asrc0 { 18 18 + clocks = <&asrc0_lpcg IMX_LPCG_CLK_0>, 19 19 + <&asrc0_lpcg IMX_LPCG_CLK_2>, 20 20 + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 21 21 + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 22 22 + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, 23 23 + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, 24 24 + <&clk_dummy>, 25 25 + <&clk_dummy>, 26 26 + <&clk_dummy>, 27 27 + <&clk_dummy>, 28 28 + <&clk_dummy>, 29 29 + <&clk_dummy>, 30 30 + <&clk_dummy>, 31 31 + <&clk_dummy>, 32 32 + <&clk_dummy>, 33 33 + <&clk_dummy>, 34 34 + <&clk_dummy>, 35 35 + <&clk_dummy>, 36 36 + <&clk_dummy>; 37 37 + power-domains = <&pd IMX_SC_R_ASRC_0>; 38 38 + }; 39 39 + 40 40 + &asrc0_lpcg { 41 41 + clocks = <&audio_ipg_clk>, 42 42 + <&audio_ipg_clk>; 43 43 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>; 44 44 + clock-output-names = "asrc0_lpcg_ipg_clk", "asrc0_lpcg_mem_clk"; 45 45 + }; 46 46 + 47 47 + &asrc1 { 48 48 + clocks = <&asrc1_lpcg IMX_LPCG_CLK_0>, 49 49 + <&asrc1_lpcg IMX_LPCG_CLK_2>, 50 50 + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 51 51 + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 52 52 + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, 53 53 + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, 54 54 + <&clk_dummy>, 55 55 + <&clk_dummy>, 56 56 + <&clk_dummy>, 57 57 + <&clk_dummy>, 58 58 + <&clk_dummy>, 59 59 + <&clk_dummy>, 60 60 + <&clk_dummy>, 61 61 + <&clk_dummy>, 62 62 + <&clk_dummy>, 63 63 + <&clk_dummy>, 64 64 + <&clk_dummy>, 65 65 + <&clk_dummy>, 66 66 + <&clk_dummy>; 67 67 + power-domains = <&pd IMX_SC_R_ASRC_1>; 68 68 + }; 69 69 + 70 70 + &asrc1_lpcg { 71 71 + clocks = <&audio_ipg_clk>, <&audio_ipg_clk>; 72 72 + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_2>; 73 73 + clock-output-names = "asrc1_lpcg_ipg_clk", "asrc1_lpcg_mem_clk"; 74 74 + }; 75 75 + 76 76 + &audio_subsys { 77 77 + 78 78 + sai4: sai@59080000 { 79 79 + compatible = "fsl,imx8qm-sai"; 80 80 + reg = <0x59080000 0x10000>; 81 81 + interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 82 82 + clocks = <&sai4_lpcg IMX_LPCG_CLK_0>, 83 83 + <&clk_dummy>, 84 84 + <&sai4_lpcg IMX_LPCG_CLK_4>, 85 85 + <&clk_dummy>, 86 86 + <&clk_dummy>; 87 87 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 88 88 + dma-names = "rx"; 89 89 + dmas = <&edma0 18 0 1>; 90 90 + fsl,dataline = <0 0xf 0x0>; 91 91 + power-domains = <&pd IMX_SC_R_SAI_4>; 92 92 + status = "disabled"; 93 93 + }; 94 94 + 95 95 + sai5: sai@59090000 { 96 96 + compatible = "fsl,imx8qm-sai"; 97 97 + reg = <0x59090000 0x10000>; 98 98 + interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 99 99 + clocks = <&sai5_lpcg IMX_LPCG_CLK_0>, 100 100 + <&clk_dummy>, 101 101 + <&sai5_lpcg IMX_LPCG_CLK_4>, 102 102 + <&clk_dummy>, 103 103 + <&clk_dummy>; 104 104 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 105 105 + dma-names = "tx"; 106 106 + dmas = <&edma0 19 0 0>; 107 107 + fsl,dataline = <0 0x0 0xf>; 108 108 + power-domains = <&pd IMX_SC_R_SAI_5>; 109 109 + status = "disabled"; 110 110 + }; 111 111 + 112 112 + sai4_lpcg: clock-controller@59480000 { 113 113 + compatible = "fsl,imx8qxp-lpcg"; 114 114 + reg = <0x59480000 0x10000>; 115 115 + #clock-cells = <1>; 116 116 + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, 117 117 + <&audio_ipg_clk>; 118 118 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 119 119 + clock-output-names = "sai4_lpcg_mclk", "sai4_lpcg_ipg_clk"; 120 120 + power-domains = <&pd IMX_SC_R_SAI_4>; 121 121 + status = "disabled"; 122 122 + }; 123 123 + 124 124 + sai5_lpcg: clock-controller@59490000 { 125 125 + compatible = "fsl,imx8qxp-lpcg"; 126 126 + reg = <0x59490000 0x10000>; 127 127 + #clock-cells = <1>; 128 128 + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, 129 129 + <&audio_ipg_clk>; 130 130 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 131 131 + clock-output-names = "sai5_lpcg_mclk", "sai5_lpcg_ipg_clk"; 132 132 + power-domains = <&pd IMX_SC_R_SAI_5>; 133 133 + status = "disabled"; 134 134 + }; 135 135 + 136 136 + esai1: esai@59810000 { 137 137 + compatible = "fsl,imx8qm-esai"; 138 138 + reg = <0x59810000 0x10000>; 139 139 + interrupts = <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>; 140 140 + clocks = <&esai1_lpcg IMX_LPCG_CLK_0>, 141 141 + <&esai1_lpcg IMX_LPCG_CLK_4>, 142 142 + <&esai1_lpcg IMX_LPCG_CLK_0>, 143 143 + <&clk_dummy>; 144 144 + clock-names = "core", "extal", "fsys", "spba"; 145 145 + dmas = <&edma1 6 0 1>, <&edma1 7 0 0>; 146 146 + dma-names = "rx", "tx"; 147 147 + power-domains = <&pd IMX_SC_R_ESAI_1>; 148 148 + status = "disabled"; 149 149 + }; 150 150 + 151 151 + sai6: sai@59820000 { 152 152 + compatible = "fsl,imx8qm-sai"; 153 153 + reg = <0x59820000 0x10000>; 154 154 + interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 155 155 + clocks = <&sai6_lpcg IMX_LPCG_CLK_0>, 156 156 + <&clk_dummy>, 157 157 + <&sai6_lpcg IMX_LPCG_CLK_4>, 158 158 + <&clk_dummy>, 159 159 + <&clk_dummy>; 160 160 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 161 161 + dma-names = "rx", "tx"; 162 162 + dmas = <&edma1 8 0 1>, <&edma1 9 0 0>; 163 163 + power-domains = <&pd IMX_SC_R_SAI_6>; 164 164 + status = "disabled"; 165 165 + }; 166 166 + 167 167 + sai7: sai@59830000 { 168 168 + compatible = "fsl,imx8qm-sai"; 169 169 + reg = <0x59830000 0x10000>; 170 170 + interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 171 171 + clocks = <&sai7_lpcg IMX_LPCG_CLK_0>, 172 172 + <&clk_dummy>, 173 173 + <&sai7_lpcg IMX_LPCG_CLK_4>, 174 174 + <&clk_dummy>, 175 175 + <&clk_dummy>; 176 176 + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 177 177 + dma-names = "tx"; 178 178 + dmas = <&edma1 10 0 0>; 179 179 + power-domains = <&pd IMX_SC_R_SAI_7>; 180 180 + status = "disabled"; 181 181 + }; 182 182 + 183 183 + esai1_lpcg: clock-controller@59c10000 { 184 184 + compatible = "fsl,imx8qxp-lpcg"; 185 185 + reg = <0x59c10000 0x10000>; 186 186 + #clock-cells = <1>; 187 187 + clocks = <&acm IMX_ADMA_ACM_ESAI1_MCLK_SEL>, 188 188 + <&audio_ipg_clk>; 189 189 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 190 190 + clock-output-names = "esai1_lpcg_extal_clk", "esai1_lpcg_ipg_clk"; 191 191 + power-domains = <&pd IMX_SC_R_ESAI_1>; 192 192 + }; 193 193 + 194 194 + sai6_lpcg: clock-controller@59c20000 { 195 195 + compatible = "fsl,imx8qxp-lpcg"; 196 196 + reg = <0x59c20000 0x10000>; 197 197 + #clock-cells = <1>; 198 198 + clocks = <&acm IMX_ADMA_ACM_SAI6_MCLK_SEL>, 199 199 + <&audio_ipg_clk>; 200 200 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 201 201 + clock-output-names = "sai6_lpcg_mclk", "sai6_lpcg_ipg_clk"; 202 202 + power-domains = <&pd IMX_SC_R_SAI_6>; 203 203 + }; 204 204 + 205 205 + sai7_lpcg: clock-controller@59c30000 { 206 206 + compatible = "fsl,imx8qxp-lpcg"; 207 207 + reg = <0x59c30000 0x10000>; 208 208 + #clock-cells = <1>; 209 209 + clocks = <&acm IMX_ADMA_ACM_SAI7_MCLK_SEL>, 210 210 + <&audio_ipg_clk>; 211 211 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 212 212 + clock-output-names = "sai7_lpcg_mclk", "sai7_lpcg_ipg_clk"; 213 213 + power-domains = <&pd IMX_SC_R_SAI_7>; 214 214 + }; 215 215 + 216 216 + acm: acm@59e00000 { 217 217 + compatible = "fsl,imx8qm-acm"; 218 218 + reg = <0x59e00000 0x1d0000>; 219 219 + #clock-cells = <1>; 220 220 + power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>, 221 221 + <&pd IMX_SC_R_AUDIO_CLK_1>, 222 222 + <&pd IMX_SC_R_MCLK_OUT_0>, 223 223 + <&pd IMX_SC_R_MCLK_OUT_1>, 224 224 + <&pd IMX_SC_R_AUDIO_PLL_0>, 225 225 + <&pd IMX_SC_R_AUDIO_PLL_1>, 226 226 + <&pd IMX_SC_R_ASRC_0>, 227 227 + <&pd IMX_SC_R_ASRC_1>, 228 228 + <&pd IMX_SC_R_ESAI_0>, 229 229 + <&pd IMX_SC_R_ESAI_1>, 230 230 + <&pd IMX_SC_R_SAI_0>, 231 231 + <&pd IMX_SC_R_SAI_1>, 232 232 + <&pd IMX_SC_R_SAI_2>, 233 233 + <&pd IMX_SC_R_SAI_3>, 234 234 + <&pd IMX_SC_R_SAI_4>, 235 235 + <&pd IMX_SC_R_SAI_5>, 236 236 + <&pd IMX_SC_R_SAI_6>, 237 237 + <&pd IMX_SC_R_SAI_7>, 238 238 + <&pd IMX_SC_R_SPDIF_0>, 239 239 + <&pd IMX_SC_R_SPDIF_1>, 240 240 + <&pd IMX_SC_R_MQS_0>; 241 241 + clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_0>, 242 242 + <&aud_rec1_lpcg IMX_LPCG_CLK_0>, 243 243 + <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>, 244 244 + <&aud_pll_div1_lpcg IMX_LPCG_CLK_0>, 245 245 + <&clk_mlb_clk>, 246 246 + <&clk_hdmi_rx_mclk>, 247 247 + <&clk_ext_aud_mclk0>, 248 248 + <&clk_ext_aud_mclk1>, 249 249 + <&clk_esai0_rx_clk>, 250 250 + <&clk_esai0_rx_hf_clk>, 251 251 + <&clk_esai0_tx_clk>, 252 252 + <&clk_esai0_tx_hf_clk>, 253 253 + <&clk_esai1_rx_clk>, 254 254 + <&clk_esai1_rx_hf_clk>, 255 255 + <&clk_esai1_tx_clk>, 256 256 + <&clk_esai1_tx_hf_clk>, 257 257 + <&clk_spdif0_rx>, 258 258 + <&clk_spdif0_rx>, 259 259 + <&clk_sai0_rx_bclk>, 260 260 + <&clk_sai0_tx_bclk>, 261 261 + <&clk_sai1_rx_bclk>, 262 262 + <&clk_sai1_tx_bclk>, 263 263 + <&clk_sai2_rx_bclk>, 264 264 + <&clk_sai3_rx_bclk>, 265 265 + <&clk_sai4_rx_bclk>, 266 266 + <&clk_sai5_rx_bclk>, 267 267 + <&clk_sai6_rx_bclk>; 268 268 + clock-names = "aud_rec_clk0_lpcg_clk", 269 269 + "aud_rec_clk1_lpcg_clk", 270 270 + "aud_pll_div_clk0_lpcg_clk", 271 271 + "aud_pll_div_clk1_lpcg_clk", 272 272 + "mlb_clk", 273 273 + "hdmi_rx_mclk", 274 274 + "ext_aud_mclk0", 275 275 + "ext_aud_mclk1", 276 276 + "esai0_rx_clk", 277 277 + "esai0_rx_hf_clk", 278 278 + "esai0_tx_clk", 279 279 + "esai0_tx_hf_clk", 280 280 + "esai1_rx_clk", 281 281 + "esai1_rx_hf_clk", 282 282 + "esai1_tx_clk", 283 283 + "esai1_tx_hf_clk", 284 284 + "spdif0_rx", 285 285 + "spdif1_rx", 286 286 + "sai0_rx_bclk", 287 287 + "sai0_tx_bclk", 288 288 + "sai1_rx_bclk", 289 289 + "sai1_tx_bclk", 290 290 + "sai2_rx_bclk", 291 291 + "sai3_rx_bclk", 292 292 + "sai4_rx_bclk", 293 293 + "sai5_tx_bclk", 294 294 + "sai6_rx_bclk"; 295 295 + }; 296 296 + }; 297 297 + 298 298 + &dsp_lpcg { 299 299 + status = "disabled"; 300 300 + }; 301 301 + 302 302 + &dsp_ram_lpcg { 303 303 + status = "disabled"; 304 304 + }; 305 305 + 306 306 + /* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */ 307 307 + &edma0{ 308 308 + reg = <0x591f0000 0x150000>; 309 309 + dma-channels = <20>; 310 310 + dma-channel-mask = <0>; 311 311 + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ 312 312 + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 313 313 + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 314 314 + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 315 315 + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 316 316 + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 317 317 + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ 318 318 + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 319 319 + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ 320 320 + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 321 321 + <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, /* spdif1 */ 322 322 + <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 323 323 + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ 324 324 + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 325 325 + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ 326 326 + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 327 327 + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */ 328 328 + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */ 329 329 + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ 330 330 + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ 331 331 + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, 332 332 + <&pd IMX_SC_R_DMA_2_CH1>, 333 333 + <&pd IMX_SC_R_DMA_2_CH2>, 334 334 + <&pd IMX_SC_R_DMA_2_CH3>, 335 335 + <&pd IMX_SC_R_DMA_2_CH4>, 336 336 + <&pd IMX_SC_R_DMA_2_CH5>, 337 337 + <&pd IMX_SC_R_DMA_2_CH6>, 338 338 + <&pd IMX_SC_R_DMA_2_CH7>, 339 339 + <&pd IMX_SC_R_DMA_2_CH8>, 340 340 + <&pd IMX_SC_R_DMA_2_CH9>, 341 341 + <&pd IMX_SC_R_DMA_2_CH10>, 342 342 + <&pd IMX_SC_R_DMA_2_CH11>, 343 343 + <&pd IMX_SC_R_DMA_2_CH12>, 344 344 + <&pd IMX_SC_R_DMA_2_CH13>, 345 345 + <&pd IMX_SC_R_DMA_2_CH14>, 346 346 + <&pd IMX_SC_R_DMA_2_CH15>, 347 347 + <&pd IMX_SC_R_DMA_2_CH16>, 348 348 + <&pd IMX_SC_R_DMA_2_CH17>, 349 349 + <&pd IMX_SC_R_DMA_2_CH18>, 350 350 + <&pd IMX_SC_R_DMA_2_CH19>; 351 351 + }; 352 352 + 353 353 + /* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */ 354 354 + &edma1{ 355 355 + reg = <0x599f0000 0xc0000>; 356 356 + dma-channels = <11>; 357 357 + dma-channel-mask = <0xc0>; 358 358 + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc1 */ 359 359 + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 360 360 + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 361 361 + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 362 362 + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 363 363 + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 364 364 + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */ 365 365 + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* no used */ 366 366 + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai6 */ 367 367 + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 368 368 + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai7 */ 369 369 + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, 370 370 + <&pd IMX_SC_R_DMA_3_CH1>, 371 371 + <&pd IMX_SC_R_DMA_3_CH2>, 372 372 + <&pd IMX_SC_R_DMA_3_CH3>, 373 373 + <&pd IMX_SC_R_DMA_3_CH4>, 374 374 + <&pd IMX_SC_R_DMA_3_CH5>, 375 375 + <&pd IMX_SC_R_DMA_3_CH6>, 376 376 + <&pd IMX_SC_R_DMA_3_CH7>, 377 377 + <&pd IMX_SC_R_DMA_3_CH8>, 378 378 + <&pd IMX_SC_R_DMA_3_CH9>, 379 379 + <&pd IMX_SC_R_DMA_3_CH10>; 380 380 + }; 381 381 + 382 382 + &esai0 { 383 383 + clocks = <&esai0_lpcg IMX_LPCG_CLK_0>, 384 384 + <&esai0_lpcg IMX_LPCG_CLK_4>, 385 385 + <&esai0_lpcg IMX_LPCG_CLK_0>, 386 386 + <&clk_dummy>; 387 387 + power-domains = <&pd IMX_SC_R_ESAI_0>; 388 388 + }; 389 389 + 390 390 + &esai0_lpcg { 391 391 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 392 392 + clock-output-names = "esai0_lpcg_extal_clk", "esai0_lpcg_ipg_clk"; 393 393 + }; 394 394 + 395 395 + &mqs0_lpcg { 396 396 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 397 397 + clock-output-names = "mqs0_lpcg_mclk", "mqs0_lpcg_ipg_clk"; 398 398 + }; 399 399 + 400 400 + &sai0 { 401 401 + clocks = <&sai0_lpcg IMX_LPCG_CLK_0>, 402 402 + <&clk_dummy>, 403 403 + <&sai0_lpcg IMX_LPCG_CLK_4>, 404 404 + <&clk_dummy>, 405 405 + <&clk_dummy>; 406 406 + power-domains = <&pd IMX_SC_R_SAI_0>; 407 407 + }; 408 408 + 409 409 + &sai0_lpcg { 410 410 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 411 411 + clock-output-names = "sai0_lpcg_mclk", "sai0_lpcg_ipg_clk"; 412 412 + }; 413 413 + 414 414 + &sai1 { 415 415 + clocks = <&sai1_lpcg IMX_LPCG_CLK_0>, 416 416 + <&clk_dummy>, 417 417 + <&sai1_lpcg IMX_LPCG_CLK_4>, 418 418 + <&clk_dummy>, 419 419 + <&clk_dummy>; 420 420 + power-domains = <&pd IMX_SC_R_SAI_1>; 421 421 + }; 422 422 + 423 423 + &sai1_lpcg { 424 424 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 425 425 + clock-output-names = "sai1_lpcg_mclk", "sai1_lpcg_ipg_clk"; 426 426 + }; 427 427 + 428 428 + &sai2 { 429 429 + clocks = <&sai2_lpcg IMX_LPCG_CLK_0>, 430 430 + <&clk_dummy>, 431 431 + <&sai2_lpcg IMX_LPCG_CLK_4>, 432 432 + <&clk_dummy>, 433 433 + <&clk_dummy>; 434 434 + power-domains = <&pd IMX_SC_R_SAI_2>; 435 435 + }; 436 436 + 437 437 + &sai2_lpcg { 438 438 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 439 439 + clock-output-names = "sai2_lpcg_mclk", "sai2_lpcg_ipg_clk"; 440 440 + }; 441 441 + 442 442 + &sai3 { 443 443 + clocks = <&sai3_lpcg IMX_LPCG_CLK_0>, 444 444 + <&clk_dummy>, 445 445 + <&sai3_lpcg IMX_LPCG_CLK_4>, 446 446 + <&clk_dummy>, 447 447 + <&clk_dummy>; 448 448 + power-domains = <&pd IMX_SC_R_SAI_3>; 449 449 + }; 450 450 + 451 451 + &sai3_lpcg { 452 452 + clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_0>; 453 453 + clock-output-names = "sai3_lpcg_mclk", "sai3_lpcg_ipg_clk"; 454 454 + }; 455 455 + 456 456 + &spdif0 { 457 457 + clocks = <&spdif0_lpcg IMX_LPCG_CLK_4>, /* core */ 458 458 + <&clk_dummy>, /* rxtx0 */ 459 459 + <&spdif0_lpcg IMX_LPCG_CLK_5>, /* rxtx1 */ 460 460 + <&clk_dummy>, /* rxtx2 */ 461 461 + <&clk_dummy>, /* rxtx3 */ 462 462 + <&clk_dummy>, /* rxtx4 */ 463 463 + <&audio_ipg_clk>, /* rxtx5 */ 464 464 + <&clk_dummy>, /* rxtx6 */ 465 465 + <&clk_dummy>, /* rxtx7 */ 466 466 + <&clk_dummy>; /* spba */ 467 467 + power-domains = <&pd IMX_SC_R_SPDIF_0>; 468 468 + }; 469 469 + 470 470 + &spdif0_lpcg { 471 471 + clock-indices = <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_4>; 472 472 + clock-output-names = "spdif0_lpcg_tx_clk", "spdif0_lpcg_gclkw"; 473 473 + };

+103

arch/arm64/boot/dts/freescale/imx8qm.dtsi

reviewed

··· 333 333 compatible = "fsl,imx8qxp-sc-rtc"; 334 334 }; 335 335 336 336 + ocotp: ocotp { 337 337 + compatible = "fsl,imx8qm-scu-ocotp"; 338 338 + #address-cells = <1>; 339 339 + #size-cells = <1>; 340 340 + read-only; 341 341 + 342 342 + fec_mac0: mac@1c4 { 343 343 + reg = <0x1c4 6>; 344 344 + }; 345 345 + 346 346 + fec_mac1: mac@1c6 { 347 347 + reg = <0x1c6 6>; 348 348 + }; 349 349 + }; 350 350 + 336 351 tsens: thermal-sensor { 337 352 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal"; 338 353 #thermal-sensor-cells = <1>; ··· 476 461 }; 477 462 }; 478 463 464 464 + clk_dummy: clock-dummy { 465 465 + compatible = "fixed-clock"; 466 466 + #clock-cells = <0>; 467 467 + clock-frequency = <0>; 468 468 + clock-output-names = "clk_dummy"; 469 469 + }; 470 470 + 471 471 + clk_esai1_rx_clk: clock-esai1-rx { 472 472 + compatible = "fixed-clock"; 473 473 + #clock-cells = <0>; 474 474 + clock-frequency = <0>; 475 475 + clock-output-names = "esai1_rx_clk"; 476 476 + }; 477 477 + 478 478 + clk_esai1_rx_hf_clk: clock-esai1-rx-hf { 479 479 + compatible = "fixed-clock"; 480 480 + #clock-cells = <0>; 481 481 + clock-frequency = <0>; 482 482 + clock-output-names = "esai1_rx_hf_clk"; 483 483 + }; 484 484 + 485 485 + clk_esai1_tx_clk: clock-esai1-tx { 486 486 + compatible = "fixed-clock"; 487 487 + #clock-cells = <0>; 488 488 + clock-frequency = <0>; 489 489 + clock-output-names = "esai1_tx_clk"; 490 490 + }; 491 491 + 492 492 + clk_esai1_tx_hf_clk: clock-esai1-tx-hf { 493 493 + compatible = "fixed-clock"; 494 494 + #clock-cells = <0>; 495 495 + clock-frequency = <0>; 496 496 + clock-output-names = "esai1_tx_hf_clk"; 497 497 + }; 498 498 + 499 499 + clk_hdmi_rx_mclk: clock-hdmi-rx-mclk { 500 500 + compatible = "fixed-clock"; 501 501 + #clock-cells = <0>; 502 502 + clock-frequency = <0>; 503 503 + clock-output-names = "hdmi-rx-mclk"; 504 504 + }; 505 505 + 506 506 + clk_mlb_clk: clock-mlb-clk { 507 507 + compatible = "fixed-clock"; 508 508 + #clock-cells = <0>; 509 509 + clock-frequency = <0>; 510 510 + clock-output-names = "mlb_clk"; 511 511 + }; 512 512 + 513 513 + clk_sai5_rx_bclk: clock-sai5-rx-bclk { 514 514 + compatible = "fixed-clock"; 515 515 + #clock-cells = <0>; 516 516 + clock-frequency = <0>; 517 517 + clock-output-names = "sai5_rx_bclk"; 518 518 + }; 519 519 + 520 520 + clk_sai5_tx_bclk: clock-sai5-tx-bclk { 521 521 + compatible = "fixed-clock"; 522 522 + #clock-cells = <0>; 523 523 + clock-frequency = <0>; 524 524 + clock-output-names = "sai5_tx_bclk"; 525 525 + }; 526 526 + 527 527 + clk_sai6_rx_bclk: clock-sai6-rx-bclk { 528 528 + compatible = "fixed-clock"; 529 529 + #clock-cells = <0>; 530 530 + clock-frequency = <0>; 531 531 + clock-output-names = "sai6_rx_bclk"; 532 532 + }; 533 533 + 534 534 + clk_sai6_tx_bclk: clock-sai6-tx-bclk { 535 535 + compatible = "fixed-clock"; 536 536 + #clock-cells = <0>; 537 537 + clock-frequency = <0>; 538 538 + clock-output-names = "sai6_tx_bclk"; 539 539 + }; 540 540 + 541 541 + clk_spdif1_rx: clock-spdif1-rx { 542 542 + compatible = "fixed-clock"; 543 543 + #clock-cells = <0>; 544 544 + clock-frequency = <0>; 545 545 + clock-output-names = "spdif1_rx"; 546 546 + }; 547 547 + 479 548 /* sorted in register address */ 549 549 + #include "imx8-ss-cm41.dtsi" 550 550 + #include "imx8-ss-audio.dtsi" 480 551 #include "imx8-ss-vpu.dtsi" 552 552 + #include "imx8-ss-gpu0.dtsi" 481 553 #include "imx8-ss-img.dtsi" 482 554 #include "imx8-ss-dma.dtsi" 483 555 #include "imx8-ss-conn.dtsi" ··· 575 473 #include "imx8qm-ss-dma.dtsi" 576 474 #include "imx8qm-ss-conn.dtsi" 577 475 #include "imx8qm-ss-lsio.dtsi" 476 476 + #include "imx8qm-ss-audio.dtsi"

+1

arch/arm64/boot/dts/freescale/imx8qxp-mek.dts

reviewed

··· 63 63 }; 64 64 65 65 &dsp { 66 66 + memory-region = <&dsp_reserved>; 66 67 status = "okay"; 67 68 }; 68 69

+151 -158

arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts

reviewed

··· 97 97 status = "okay"; 98 98 }; 99 99 100 100 - &mu1 { 101 101 - status = "okay"; 102 102 - }; 103 103 - 104 104 - &mu2 { 105 105 - status = "okay"; 106 106 - }; 107 107 - 108 108 - &lpi2c3 { 109 109 - #address-cells = <1>; 110 110 - #size-cells = <0>; 111 111 - clock-frequency = <400000>; 112 112 - pinctrl-names = "default"; 113 113 - pinctrl-0 = <&pinctrl_lpi2c3>; 114 114 - status = "okay"; 115 115 - 116 116 - ptn5110: tcpc@50 { 117 117 - compatible = "nxp,ptn5110", "tcpci"; 118 118 - reg = <0x50>; 119 119 - interrupt-parent = <&gpio3>; 120 120 - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 121 121 - 122 122 - typec1_con: connector { 123 123 - compatible = "usb-c-connector"; 124 124 - label = "USB-C"; 125 125 - power-role = "dual"; 126 126 - data-role = "dual"; 127 127 - try-power-role = "sink"; 128 128 - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 129 129 - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 130 130 - PDO_VAR(5000, 20000, 3000)>; 131 131 - op-sink-microwatt = <15000000>; 132 132 - self-powered; 133 133 - 134 134 - ports { 135 135 - #address-cells = <1>; 136 136 - #size-cells = <0>; 137 137 - 138 138 - port@0 { 139 139 - reg = <0>; 140 140 - 141 141 - typec1_dr_sw: endpoint { 142 142 - remote-endpoint = <&usb1_drd_sw>; 143 143 - }; 144 144 - }; 145 145 - }; 146 146 - }; 147 147 - }; 148 148 - 149 149 - ptn5110_2: tcpc@51 { 150 150 - compatible = "nxp,ptn5110", "tcpci"; 151 151 - reg = <0x51>; 152 152 - interrupt-parent = <&gpio3>; 153 153 - interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 154 154 - 155 155 - typec2_con: connector { 156 156 - compatible = "usb-c-connector"; 157 157 - label = "USB-C"; 158 158 - power-role = "dual"; 159 159 - data-role = "dual"; 160 160 - try-power-role = "sink"; 161 161 - source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 162 162 - sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 163 163 - PDO_VAR(5000, 20000, 3000)>; 164 164 - op-sink-microwatt = <15000000>; 165 165 - self-powered; 166 166 - 167 167 - ports { 168 168 - #address-cells = <1>; 169 169 - #size-cells = <0>; 170 170 - 171 171 - port@0 { 172 172 - reg = <0>; 173 173 - 174 174 - typec2_dr_sw: endpoint { 175 175 - remote-endpoint = <&usb2_drd_sw>; 176 176 - }; 177 177 - }; 178 178 - }; 179 179 - }; 180 180 - }; 181 181 - }; 182 182 - 183 100 &eqos { 184 101 pinctrl-names = "default", "sleep"; 185 102 pinctrl-0 = <&pinctrl_eqos>; ··· 143 226 reset-deassert-us = <80000>; 144 227 }; 145 228 }; 146 146 - }; 147 147 - 148 148 - &lpuart1 { /* console */ 149 149 - pinctrl-names = "default"; 150 150 - pinctrl-0 = <&pinctrl_uart1>; 151 151 - status = "okay"; 152 152 - }; 153 153 - 154 154 - &lpuart5 { 155 155 - pinctrl-names = "default"; 156 156 - pinctrl-0 = <&pinctrl_uart5>; 157 157 - status = "okay"; 158 158 - }; 159 159 - 160 160 - &usbotg1 { 161 161 - dr_mode = "otg"; 162 162 - hnp-disable; 163 163 - srp-disable; 164 164 - adp-disable; 165 165 - usb-role-switch; 166 166 - disable-over-current; 167 167 - samsung,picophy-pre-emp-curr-control = <3>; 168 168 - samsung,picophy-dc-vol-level-adjust = <7>; 169 169 - status = "okay"; 170 170 - 171 171 - port { 172 172 - usb1_drd_sw: endpoint { 173 173 - remote-endpoint = <&typec1_dr_sw>; 174 174 - }; 175 175 - }; 176 176 - }; 177 177 - 178 178 - &usbotg2 { 179 179 - dr_mode = "otg"; 180 180 - hnp-disable; 181 181 - srp-disable; 182 182 - adp-disable; 183 183 - usb-role-switch; 184 184 - disable-over-current; 185 185 - samsung,picophy-pre-emp-curr-control = <3>; 186 186 - samsung,picophy-dc-vol-level-adjust = <7>; 187 187 - status = "okay"; 188 188 - 189 189 - port { 190 190 - usb2_drd_sw: endpoint { 191 191 - remote-endpoint = <&typec2_dr_sw>; 192 192 - }; 193 193 - }; 194 194 - }; 195 195 - 196 196 - &usdhc1 { 197 197 - pinctrl-names = "default", "state_100mhz", "state_200mhz"; 198 198 - pinctrl-0 = <&pinctrl_usdhc1>; 199 199 - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 200 200 - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 201 201 - bus-width = <8>; 202 202 - non-removable; 203 203 - status = "okay"; 204 204 - }; 205 205 - 206 206 - &usdhc2 { 207 207 - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 208 208 - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 209 209 - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 210 210 - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 211 211 - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 212 212 - cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 213 213 - vmmc-supply = <&reg_usdhc2_vmmc>; 214 214 - bus-width = <4>; 215 215 - status = "okay"; 216 216 - no-mmc; 217 217 - }; 218 218 - 219 219 - &wdog3 { 220 220 - status = "okay"; 221 229 }; 222 230 223 231 &lpi2c2 { ··· 244 402 }; 245 403 246 404 &lpi2c3 { 405 405 + #address-cells = <1>; 406 406 + #size-cells = <0>; 247 407 clock-frequency = <400000>; 248 408 pinctrl-names = "default"; 249 409 pinctrl-0 = <&pinctrl_lpi2c3>; 250 410 status = "okay"; 411 411 + 412 412 + ptn5110: tcpc@50 { 413 413 + compatible = "nxp,ptn5110", "tcpci"; 414 414 + reg = <0x50>; 415 415 + interrupt-parent = <&gpio3>; 416 416 + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 417 417 + 418 418 + typec1_con: connector { 419 419 + compatible = "usb-c-connector"; 420 420 + label = "USB-C"; 421 421 + power-role = "dual"; 422 422 + data-role = "dual"; 423 423 + try-power-role = "sink"; 424 424 + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 425 425 + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 426 426 + PDO_VAR(5000, 20000, 3000)>; 427 427 + op-sink-microwatt = <15000000>; 428 428 + self-powered; 429 429 + 430 430 + ports { 431 431 + #address-cells = <1>; 432 432 + #size-cells = <0>; 433 433 + 434 434 + port@0 { 435 435 + reg = <0>; 436 436 + 437 437 + typec1_dr_sw: endpoint { 438 438 + remote-endpoint = <&usb1_drd_sw>; 439 439 + }; 440 440 + }; 441 441 + }; 442 442 + }; 443 443 + }; 444 444 + 445 445 + ptn5110_2: tcpc@51 { 446 446 + compatible = "nxp,ptn5110", "tcpci"; 447 447 + reg = <0x51>; 448 448 + interrupt-parent = <&gpio3>; 449 449 + interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 450 450 + 451 451 + typec2_con: connector { 452 452 + compatible = "usb-c-connector"; 453 453 + label = "USB-C"; 454 454 + power-role = "dual"; 455 455 + data-role = "dual"; 456 456 + try-power-role = "sink"; 457 457 + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 458 458 + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 459 459 + PDO_VAR(5000, 20000, 3000)>; 460 460 + op-sink-microwatt = <15000000>; 461 461 + self-powered; 462 462 + 463 463 + ports { 464 464 + #address-cells = <1>; 465 465 + #size-cells = <0>; 466 466 + 467 467 + port@0 { 468 468 + reg = <0>; 469 469 + 470 470 + typec2_dr_sw: endpoint { 471 471 + remote-endpoint = <&usb2_drd_sw>; 472 472 + }; 473 473 + }; 474 474 + }; 475 475 + }; 476 476 + }; 251 477 252 478 pcf2131: rtc@53 { 253 479 compatible = "nxp,pcf2131"; ··· 323 413 interrupt-parent = <&pcal6524>; 324 414 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 325 415 }; 416 416 + }; 417 417 + 418 418 + &lpuart1 { /* console */ 419 419 + pinctrl-names = "default"; 420 420 + pinctrl-0 = <&pinctrl_uart1>; 421 421 + status = "okay"; 422 422 + }; 423 423 + 424 424 + &lpuart5 { 425 425 + pinctrl-names = "default"; 426 426 + pinctrl-0 = <&pinctrl_uart5>; 427 427 + status = "okay"; 428 428 + }; 429 429 + 430 430 + &mu1 { 431 431 + status = "okay"; 432 432 + }; 433 433 + 434 434 + &mu2 { 435 435 + status = "okay"; 436 436 + }; 437 437 + 438 438 + &usbotg1 { 439 439 + dr_mode = "otg"; 440 440 + hnp-disable; 441 441 + srp-disable; 442 442 + adp-disable; 443 443 + usb-role-switch; 444 444 + disable-over-current; 445 445 + samsung,picophy-pre-emp-curr-control = <3>; 446 446 + samsung,picophy-dc-vol-level-adjust = <7>; 447 447 + status = "okay"; 448 448 + 449 449 + port { 450 450 + usb1_drd_sw: endpoint { 451 451 + remote-endpoint = <&typec1_dr_sw>; 452 452 + }; 453 453 + }; 454 454 + }; 455 455 + 456 456 + &usbotg2 { 457 457 + dr_mode = "otg"; 458 458 + hnp-disable; 459 459 + srp-disable; 460 460 + adp-disable; 461 461 + usb-role-switch; 462 462 + disable-over-current; 463 463 + samsung,picophy-pre-emp-curr-control = <3>; 464 464 + samsung,picophy-dc-vol-level-adjust = <7>; 465 465 + status = "okay"; 466 466 + 467 467 + port { 468 468 + usb2_drd_sw: endpoint { 469 469 + remote-endpoint = <&typec2_dr_sw>; 470 470 + }; 471 471 + }; 472 472 + }; 473 473 + 474 474 + &usdhc1 { 475 475 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 476 476 + pinctrl-0 = <&pinctrl_usdhc1>; 477 477 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 478 478 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 479 479 + bus-width = <8>; 480 480 + non-removable; 481 481 + status = "okay"; 482 482 + }; 483 483 + 484 484 + &usdhc2 { 485 485 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 486 486 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 487 487 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 488 488 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 489 489 + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 490 490 + cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 491 491 + vmmc-supply = <&reg_usdhc2_vmmc>; 492 492 + bus-width = <4>; 493 493 + status = "okay"; 494 494 + no-mmc; 495 495 + }; 496 496 + 497 497 + &wdog3 { 498 498 + status = "okay"; 326 499 }; 327 500 328 501 &iomuxc {

+492

arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + /dts-v1/; 7 7 + 8 8 + #include <dt-bindings/usb/pd.h> 9 9 + #include "imx93.dtsi" 10 10 + 11 11 + / { 12 12 + model = "NXP i.MX93 9x9 Quick Start Board"; 13 13 + compatible = "fsl,imx93-9x9-qsb", "fsl,imx93"; 14 14 + 15 15 + chosen { 16 16 + stdout-path = &lpuart1; 17 17 + }; 18 18 + 19 19 + reserved-memory { 20 20 + #address-cells = <2>; 21 21 + #size-cells = <2>; 22 22 + ranges; 23 23 + 24 24 + linux,cma { 25 25 + compatible = "shared-dma-pool"; 26 26 + reusable; 27 27 + size = <0 0x10000000>; 28 28 + linux,cma-default; 29 29 + }; 30 30 + 31 31 + vdev0vring0: vdev0vring0@a4000000 { 32 32 + reg = <0 0xa4000000 0 0x8000>; 33 33 + no-map; 34 34 + }; 35 35 + 36 36 + vdev0vring1: vdev0vring1@a4008000 { 37 37 + reg = <0 0xa4008000 0 0x8000>; 38 38 + no-map; 39 39 + }; 40 40 + 41 41 + vdev1vring0: vdev1vring0@a4010000 { 42 42 + reg = <0 0xa4010000 0 0x8000>; 43 43 + no-map; 44 44 + }; 45 45 + 46 46 + vdev1vring1: vdev1vring1@a4018000 { 47 47 + reg = <0 0xa4018000 0 0x8000>; 48 48 + no-map; 49 49 + }; 50 50 + 51 51 + rsc_table: rsc-table@2021e000 { 52 52 + reg = <0 0x2021e000 0 0x1000>; 53 53 + no-map; 54 54 + }; 55 55 + 56 56 + vdevbuffer: vdevbuffer@a4020000 { 57 57 + compatible = "shared-dma-pool"; 58 58 + reg = <0 0xa4020000 0 0x100000>; 59 59 + no-map; 60 60 + }; 61 61 + 62 62 + }; 63 63 + 64 64 + reg_vref_1v8: regulator-adc-vref { 65 65 + compatible = "regulator-fixed"; 66 66 + regulator-name = "VREF_1V8"; 67 67 + regulator-min-microvolt = <1800000>; 68 68 + regulator-max-microvolt = <1800000>; 69 69 + }; 70 70 + 71 71 + reg_rpi_3v3: regulator-rpi { 72 72 + compatible = "regulator-fixed"; 73 73 + regulator-name = "VDD_RPI_3V3"; 74 74 + regulator-min-microvolt = <3300000>; 75 75 + regulator-max-microvolt = <3300000>; 76 76 + gpio = <&pcal6524 21 GPIO_ACTIVE_HIGH>; 77 77 + enable-active-high; 78 78 + }; 79 79 + 80 80 + reg_usdhc2_vmmc: regulator-usdhc2 { 81 81 + compatible = "regulator-fixed"; 82 82 + pinctrl-names = "default"; 83 83 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 84 84 + regulator-name = "VSD_3V3"; 85 85 + regulator-min-microvolt = <3300000>; 86 86 + regulator-max-microvolt = <3300000>; 87 87 + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 88 88 + enable-active-high; 89 89 + off-on-delay-us = <12000>; 90 90 + }; 91 91 + }; 92 92 + 93 93 + &adc1 { 94 94 + vref-supply = <&reg_vref_1v8>; 95 95 + status = "okay"; 96 96 + }; 97 97 + 98 98 + &cm33 { 99 99 + mbox-names = "tx", "rx", "rxdb"; 100 100 + mboxes = <&mu1 0 1>, 101 101 + <&mu1 1 1>, 102 102 + <&mu1 3 1>; 103 103 + memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 104 104 + <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>; 105 105 + status = "okay"; 106 106 + }; 107 107 + 108 108 + &eqos { 109 109 + pinctrl-names = "default"; 110 110 + pinctrl-0 = <&pinctrl_eqos>; 111 111 + phy-mode = "rgmii-id"; 112 112 + phy-handle = <&ethphy1>; 113 113 + status = "okay"; 114 114 + 115 115 + mdio { 116 116 + compatible = "snps,dwmac-mdio"; 117 117 + #address-cells = <1>; 118 118 + #size-cells = <0>; 119 119 + clock-frequency = <5000000>; 120 120 + 121 121 + ethphy1: ethernet-phy@1 { 122 122 + compatible = "ethernet-phy-ieee802.3-c22"; 123 123 + reg = <1>; 124 124 + eee-broken-1000t; 125 125 + reset-gpios = <&pcal6524 15 GPIO_ACTIVE_LOW>; 126 126 + reset-assert-us = <10000>; 127 127 + reset-deassert-us = <80000>; 128 128 + realtek,clkout-disable; 129 129 + }; 130 130 + }; 131 131 + }; 132 132 + 133 133 + &lpi2c1 { 134 134 + clock-frequency = <400000>; 135 135 + pinctrl-names = "default"; 136 136 + pinctrl-0 = <&pinctrl_lpi2c1>; 137 137 + status = "okay"; 138 138 + 139 139 + ptn5110: tcpc@50 { 140 140 + compatible = "nxp,ptn5110", "tcpci"; 141 141 + reg = <0x50>; 142 142 + interrupt-parent = <&gpio3>; 143 143 + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 144 144 + 145 145 + typec1_con: connector { 146 146 + compatible = "usb-c-connector"; 147 147 + label = "USB-C"; 148 148 + power-role = "dual"; 149 149 + data-role = "dual"; 150 150 + try-power-role = "sink"; 151 151 + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 152 152 + sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 153 153 + PDO_VAR(5000, 20000, 3000)>; 154 154 + op-sink-microwatt = <15000000>; 155 155 + self-powered; 156 156 + 157 157 + ports { 158 158 + #address-cells = <1>; 159 159 + #size-cells = <0>; 160 160 + 161 161 + port@0 { 162 162 + reg = <0>; 163 163 + 164 164 + typec1_dr_sw: endpoint { 165 165 + remote-endpoint = <&usb1_drd_sw>; 166 166 + }; 167 167 + }; 168 168 + }; 169 169 + }; 170 170 + }; 171 171 + 172 172 + rtc@53 { 173 173 + compatible = "nxp,pcf2131"; 174 174 + reg = <0x53>; 175 175 + interrupt-parent = <&pcal6524>; 176 176 + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 177 177 + }; 178 178 + }; 179 179 + 180 180 + &lpi2c2 { 181 181 + #address-cells = <1>; 182 182 + #size-cells = <0>; 183 183 + clock-frequency = <400000>; 184 184 + pinctrl-names = "default"; 185 185 + pinctrl-0 = <&pinctrl_lpi2c2>; 186 186 + status = "okay"; 187 187 + 188 188 + pcal6524: gpio@22 { 189 189 + compatible = "nxp,pcal6524"; 190 190 + reg = <0x22>; 191 191 + gpio-controller; 192 192 + #gpio-cells = <2>; 193 193 + interrupt-controller; 194 194 + #interrupt-cells = <2>; 195 195 + interrupt-parent = <&gpio3>; 196 196 + interrupts = <26 IRQ_TYPE_LEVEL_LOW>; 197 197 + pinctrl-names = "default"; 198 198 + pinctrl-0 = <&pinctrl_pcal6524>; 199 199 + }; 200 200 + 201 201 + pmic@25 { 202 202 + compatible = "nxp,pca9451a"; 203 203 + reg = <0x25>; 204 204 + interrupt-parent = <&pcal6524>; 205 205 + interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 206 206 + 207 207 + regulators { 208 208 + buck1: BUCK1 { 209 209 + regulator-name = "BUCK1"; 210 210 + regulator-min-microvolt = <650000>; 211 211 + regulator-max-microvolt = <2237500>; 212 212 + regulator-boot-on; 213 213 + regulator-always-on; 214 214 + regulator-ramp-delay = <3125>; 215 215 + }; 216 216 + 217 217 + buck2: BUCK2 { 218 218 + regulator-name = "BUCK2"; 219 219 + regulator-min-microvolt = <600000>; 220 220 + regulator-max-microvolt = <2187500>; 221 221 + regulator-boot-on; 222 222 + regulator-always-on; 223 223 + regulator-ramp-delay = <3125>; 224 224 + }; 225 225 + 226 226 + buck4: BUCK4{ 227 227 + regulator-name = "BUCK4"; 228 228 + regulator-min-microvolt = <600000>; 229 229 + regulator-max-microvolt = <3400000>; 230 230 + regulator-boot-on; 231 231 + regulator-always-on; 232 232 + }; 233 233 + 234 234 + buck5: BUCK5{ 235 235 + regulator-name = "BUCK5"; 236 236 + regulator-min-microvolt = <600000>; 237 237 + regulator-max-microvolt = <3400000>; 238 238 + regulator-boot-on; 239 239 + regulator-always-on; 240 240 + }; 241 241 + 242 242 + buck6: BUCK6 { 243 243 + regulator-name = "BUCK6"; 244 244 + regulator-min-microvolt = <600000>; 245 245 + regulator-max-microvolt = <3400000>; 246 246 + regulator-boot-on; 247 247 + regulator-always-on; 248 248 + }; 249 249 + 250 250 + ldo1: LDO1 { 251 251 + regulator-name = "LDO1"; 252 252 + regulator-min-microvolt = <1600000>; 253 253 + regulator-max-microvolt = <3300000>; 254 254 + regulator-boot-on; 255 255 + regulator-always-on; 256 256 + }; 257 257 + 258 258 + ldo4: LDO4 { 259 259 + regulator-name = "LDO4"; 260 260 + regulator-min-microvolt = <800000>; 261 261 + regulator-max-microvolt = <3300000>; 262 262 + regulator-boot-on; 263 263 + regulator-always-on; 264 264 + }; 265 265 + 266 266 + ldo5: LDO5 { 267 267 + regulator-name = "LDO5"; 268 268 + regulator-min-microvolt = <1800000>; 269 269 + regulator-max-microvolt = <3300000>; 270 270 + regulator-boot-on; 271 271 + regulator-always-on; 272 272 + }; 273 273 + }; 274 274 + }; 275 275 + }; 276 276 + 277 277 + &lpuart1 { /* console */ 278 278 + pinctrl-names = "default"; 279 279 + pinctrl-0 = <&pinctrl_uart1>; 280 280 + status = "okay"; 281 281 + }; 282 282 + 283 283 + &mu1 { 284 284 + status = "okay"; 285 285 + }; 286 286 + 287 287 + &mu2 { 288 288 + status = "okay"; 289 289 + }; 290 290 + 291 291 + &usbotg1 { 292 292 + dr_mode = "otg"; 293 293 + hnp-disable; 294 294 + srp-disable; 295 295 + adp-disable; 296 296 + usb-role-switch; 297 297 + disable-over-current; 298 298 + samsung,picophy-pre-emp-curr-control = <3>; 299 299 + samsung,picophy-dc-vol-level-adjust = <7>; 300 300 + status = "okay"; 301 301 + 302 302 + port { 303 303 + usb1_drd_sw: endpoint { 304 304 + remote-endpoint = <&typec1_dr_sw>; 305 305 + }; 306 306 + }; 307 307 + }; 308 308 + 309 309 + &usdhc1 { 310 310 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 311 311 + pinctrl-0 = <&pinctrl_usdhc1>; 312 312 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 313 313 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 314 314 + bus-width = <8>; 315 315 + non-removable; 316 316 + status = "okay"; 317 317 + }; 318 318 + 319 319 + &usdhc2 { 320 320 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; 321 321 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 322 322 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 323 323 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 324 324 + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 325 325 + vmmc-supply = <&reg_usdhc2_vmmc>; 326 326 + bus-width = <4>; 327 327 + no-mmc; 328 328 + status = "okay"; 329 329 + }; 330 330 + 331 331 + &wdog3 { 332 332 + status = "okay"; 333 333 + }; 334 334 + 335 335 + &iomuxc { 336 336 + pinctrl_eqos: eqosgrp { 337 337 + fsl,pins = < 338 338 + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e 339 339 + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 340 340 + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 341 341 + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 342 342 + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 343 343 + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 344 344 + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e 345 345 + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 346 346 + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 347 347 + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e 348 348 + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 349 349 + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 350 350 + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e 351 351 + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 352 352 + >; 353 353 + }; 354 354 + 355 355 + pinctrl_lpi2c1: lpi2c1grp { 356 356 + fsl,pins = < 357 357 + MX93_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 358 358 + MX93_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 359 359 + >; 360 360 + }; 361 361 + 362 362 + pinctrl_lpi2c2: lpi2c2grp { 363 363 + fsl,pins = < 364 364 + MX93_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 365 365 + MX93_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 366 366 + >; 367 367 + }; 368 368 + 369 369 + pinctrl_pcal6524: pcal6524grp { 370 370 + fsl,pins = < 371 371 + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e 372 372 + >; 373 373 + }; 374 374 + 375 375 + pinctrl_uart1: uart1grp { 376 376 + fsl,pins = < 377 377 + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e 378 378 + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e 379 379 + >; 380 380 + }; 381 381 + 382 382 + pinctrl_uart5: uart5grp { 383 383 + fsl,pins = < 384 384 + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 385 385 + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e 386 386 + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 387 387 + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 388 388 + >; 389 389 + }; 390 390 + 391 391 + /* need to config the SION for data and cmd pad, refer to ERR052021 */ 392 392 + pinctrl_usdhc1: usdhc1grp { 393 393 + fsl,pins = < 394 394 + MX93_PAD_SD1_CLK__USDHC1_CLK 0x1582 395 395 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x40001382 396 396 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x40001382 397 397 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x40001382 398 398 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x40001382 399 399 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x40001382 400 400 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x40001382 401 401 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x40001382 402 402 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x40001382 403 403 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x40001382 404 404 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 405 405 + >; 406 406 + }; 407 407 + 408 408 + /* need to config the SION for data and cmd pad, refer to ERR052021 */ 409 409 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 410 410 + fsl,pins = < 411 411 + MX93_PAD_SD1_CLK__USDHC1_CLK 0x158e 412 412 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x4000138e 413 413 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x4000138e 414 414 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x4000138e 415 415 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x4000138e 416 416 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x4000138e 417 417 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x4000138e 418 418 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x4000138e 419 419 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x4000138e 420 420 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x4000138e 421 421 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 422 422 + >; 423 423 + }; 424 424 + 425 425 + /* need to config the SION for data and cmd pad, refer to ERR052021 */ 426 426 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 427 427 + fsl,pins = < 428 428 + MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe 429 429 + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe 430 430 + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe 431 431 + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe 432 432 + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe 433 433 + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe 434 434 + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe 435 435 + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe 436 436 + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe 437 437 + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe 438 438 + MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 439 439 + >; 440 440 + }; 441 441 + 442 442 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 443 443 + fsl,pins = < 444 444 + MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e 445 445 + >; 446 446 + }; 447 447 + 448 448 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 449 449 + fsl,pins = < 450 450 + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e 451 451 + >; 452 452 + }; 453 453 + 454 454 + /* need to config the SION for data and cmd pad, refer to ERR052021 */ 455 455 + pinctrl_usdhc2: usdhc2grp { 456 456 + fsl,pins = < 457 457 + MX93_PAD_SD2_CLK__USDHC2_CLK 0x1582 458 458 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x40001382 459 459 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x40001382 460 460 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x40001382 461 461 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x40001382 462 462 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x40001382 463 463 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 464 464 + >; 465 465 + }; 466 466 + 467 467 + /* need to config the SION for data and cmd pad, refer to ERR052021 */ 468 468 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 469 469 + fsl,pins = < 470 470 + MX93_PAD_SD2_CLK__USDHC2_CLK 0x158e 471 471 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000138e 472 472 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e 473 473 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e 474 474 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e 475 475 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e 476 476 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 477 477 + >; 478 478 + }; 479 479 + 480 480 + /* need to config the SION for data and cmd pad, refer to ERR052021 */ 481 481 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 482 482 + fsl,pins = < 483 483 + MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe 484 484 + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe 485 485 + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe 486 486 + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe 487 487 + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe 488 488 + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe 489 489 + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 490 490 + >; 491 491 + }; 492 492 + };

+61 -12

arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts

reviewed

··· 303 303 reg = <0x1c>; 304 304 }; 305 305 306 306 + ptn5110: usb-typec@50 { 307 307 + compatible = "nxp,ptn5110", "tcpci"; 308 308 + reg = <0x50>; 309 309 + pinctrl-names = "default"; 310 310 + pinctrl-0 = <&pinctrl_typec>; 311 311 + interrupt-parent = <&gpio1>; 312 312 + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 313 313 + 314 314 + connector { 315 315 + compatible = "usb-c-connector"; 316 316 + label = "X17"; 317 317 + power-role = "dual"; 318 318 + data-role = "dual"; 319 319 + try-power-role = "sink"; 320 320 + typec-power-opmode = "default"; 321 321 + pd-disable; 322 322 + self-powered; 323 323 + 324 324 + port { 325 325 + typec_con_hs: endpoint { 326 326 + remote-endpoint = <&typec_hs>; 327 327 + }; 328 328 + }; 329 329 + }; 330 330 + }; 331 331 + 306 332 eeprom2: eeprom@54 { 307 333 compatible = "nxp,se97b", "atmel,24c02"; 308 334 reg = <0x54>; ··· 395 369 "USB_RESET#", "", 396 370 "WLAN_PD#", "WLAN_W_DISABLE#", 397 371 "WLAN_PERST#", "12V_EN"; 398 398 - 399 399 - /* 400 400 - * Controls the on board USB Hub reset which is low 401 401 - * active as reset signal. The output-low states, the 402 402 - * signal is inactive, e.g. no reset 403 403 - */ 404 404 - usb-reset-hog { 405 405 - gpio-hog; 406 406 - gpios = <2 GPIO_ACTIVE_LOW>; 407 407 - output-low; 408 408 - line-name = "USB_RESET#"; 409 409 - }; 410 372 411 373 /* 412 374 * Controls the WiFi card PD pin which is low active ··· 504 490 pinctrl-names = "default"; 505 491 pinctrl-0 = <&pinctrl_tpm6>; 506 492 status = "okay"; 493 493 + }; 494 494 + 495 495 + &usbotg1 { 496 496 + dr_mode = "otg"; 497 497 + hnp-disable; 498 498 + srp-disable; 499 499 + adp-disable; 500 500 + usb-role-switch; 501 501 + disable-over-current; 502 502 + samsung,picophy-pre-emp-curr-control = <3>; 503 503 + samsung,picophy-dc-vol-level-adjust = <7>; 504 504 + status = "okay"; 505 505 + 506 506 + port { 507 507 + typec_hs: endpoint { 508 508 + remote-endpoint = <&typec_con_hs>; 509 509 + }; 510 510 + }; 511 511 + }; 512 512 + 513 513 + &usbotg2 { 514 514 + dr_mode = "host"; 515 515 + #address-cells = <1>; 516 516 + #size-cells = <0>; 517 517 + disable-over-current; 518 518 + samsung,picophy-pre-emp-curr-control = <3>; 519 519 + samsung,picophy-dc-vol-level-adjust = <7>; 520 520 + status = "okay"; 521 521 + 522 522 + hub_2_0: hub@1 { 523 523 + compatible = "usb424,2517"; 524 524 + reg = <1>; 525 525 + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; 526 526 + vdd-supply = <&reg_3v3>; 527 527 + }; 507 528 }; 508 529 509 530 &usdhc2 {

+61

arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts

reviewed

··· 252 252 reg = <0x1c>; 253 253 }; 254 254 255 255 + ptn5110: usb-typec@50 { 256 256 + compatible = "nxp,ptn5110", "tcpci"; 257 257 + reg = <0x50>; 258 258 + pinctrl-names = "default"; 259 259 + pinctrl-0 = <&pinctrl_typec>; 260 260 + interrupt-parent = <&gpio1>; 261 261 + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; 262 262 + 263 263 + connector { 264 264 + compatible = "usb-c-connector"; 265 265 + label = "X17"; 266 266 + power-role = "dual"; 267 267 + data-role = "dual"; 268 268 + try-power-role = "sink"; 269 269 + typec-power-opmode = "default"; 270 270 + pd-disable; 271 271 + self-powered; 272 272 + 273 273 + port { 274 274 + typec_con_hs: endpoint { 275 275 + remote-endpoint = <&typec_hs>; 276 276 + }; 277 277 + }; 278 278 + }; 279 279 + }; 280 280 + 255 281 eeprom2: eeprom@54 { 256 282 compatible = "nxp,se97b", "atmel,24c02"; 257 283 reg = <0x54>; ··· 457 431 &tpm5 { 458 432 pinctrl-names = "default"; 459 433 pinctrl-0 = <&pinctrl_tpm5>; 434 434 + }; 435 435 + 436 436 + &usbotg1 { 437 437 + dr_mode = "otg"; 438 438 + hnp-disable; 439 439 + srp-disable; 440 440 + adp-disable; 441 441 + usb-role-switch; 442 442 + disable-over-current; 443 443 + samsung,picophy-pre-emp-curr-control = <3>; 444 444 + samsung,picophy-dc-vol-level-adjust = <7>; 445 445 + status = "okay"; 446 446 + 447 447 + port { 448 448 + typec_hs: endpoint { 449 449 + remote-endpoint = <&typec_con_hs>; 450 450 + }; 451 451 + }; 452 452 + }; 453 453 + 454 454 + &usbotg2 { 455 455 + dr_mode = "host"; 456 456 + #address-cells = <1>; 457 457 + #size-cells = <0>; 458 458 + disable-over-current; 459 459 + samsung,picophy-pre-emp-curr-control = <3>; 460 460 + samsung,picophy-dc-vol-level-adjust = <7>; 461 461 + status = "okay"; 462 462 + 463 463 + hub_2_0: hub@1 { 464 464 + compatible = "usb424,2517"; 465 465 + reg = <1>; 466 466 + reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; 467 467 + vdd-supply = <&reg_3v3>; 468 468 + }; 460 469 }; 461 470 462 471 &usdhc2 {

+6

arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi

reviewed

··· 75 75 spi-max-frequency = <62000000>; 76 76 spi-tx-bus-width = <4>; 77 77 spi-rx-bus-width = <4>; 78 78 + 79 79 + partitions { 80 80 + compatible = "fixed-partitions"; 81 81 + #address-cells = <1>; 82 82 + #size-cells = <1>; 83 83 + }; 78 84 }; 79 85 }; 80 86

+289

arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + /dts-v1/; 7 7 + 8 8 + #include "imx95.dtsi" 9 9 + 10 10 + / { 11 11 + model = "NXP i.MX95 19X19 board"; 12 12 + compatible = "fsl,imx95-19x19-evk", "fsl,imx95"; 13 13 + 14 14 + aliases { 15 15 + mmc0 = &usdhc1; 16 16 + mmc1 = &usdhc2; 17 17 + serial0 = &lpuart1; 18 18 + }; 19 19 + 20 20 + chosen { 21 21 + stdout-path = &lpuart1; 22 22 + }; 23 23 + 24 24 + memory@80000000 { 25 25 + device_type = "memory"; 26 26 + reg = <0x0 0x80000000 0 0x80000000>; 27 27 + }; 28 28 + 29 29 + reserved-memory { 30 30 + #address-cells = <2>; 31 31 + #size-cells = <2>; 32 32 + ranges; 33 33 + 34 34 + linux_cma: linux,cma { 35 35 + compatible = "shared-dma-pool"; 36 36 + alloc-ranges = <0 0x80000000 0 0x7f000000>; 37 37 + size = <0 0x3c000000>; 38 38 + linux,cma-default; 39 39 + reusable; 40 40 + }; 41 41 + }; 42 42 + 43 43 + reg_m2_pwr: regulator-m2-pwr { 44 44 + compatible = "regulator-fixed"; 45 45 + regulator-name = "M.2-power"; 46 46 + regulator-min-microvolt = <3300000>; 47 47 + regulator-max-microvolt = <3300000>; 48 48 + gpio = <&i2c7_pcal6524 20 GPIO_ACTIVE_HIGH>; 49 49 + enable-active-high; 50 50 + }; 51 51 + 52 52 + reg_pcie0: regulator-pcie { 53 53 + compatible = "regulator-fixed"; 54 54 + regulator-name = "PCIE_WLAN_EN"; 55 55 + regulator-min-microvolt = <3300000>; 56 56 + regulator-max-microvolt = <3300000>; 57 57 + vin-supply = <&reg_m2_pwr>; 58 58 + gpio = <&i2c7_pcal6524 6 GPIO_ACTIVE_HIGH>; 59 59 + enable-active-high; 60 60 + }; 61 61 + 62 62 + reg_slot_pwr: regulator-slot-pwr { 63 63 + compatible = "regulator-fixed"; 64 64 + regulator-name = "PCIe slot-power"; 65 65 + regulator-min-microvolt = <3300000>; 66 66 + regulator-max-microvolt = <3300000>; 67 67 + gpio = <&i2c7_pcal6524 14 GPIO_ACTIVE_HIGH>; 68 68 + enable-active-high; 69 69 + }; 70 70 + 71 71 + reg_usdhc2_vmmc: regulator-usdhc2 { 72 72 + compatible = "regulator-fixed"; 73 73 + pinctrl-names = "default"; 74 74 + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 75 75 + regulator-name = "VDD_SD2_3V3"; 76 76 + regulator-min-microvolt = <3300000>; 77 77 + regulator-max-microvolt = <3300000>; 78 78 + gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 79 79 + enable-active-high; 80 80 + off-on-delay-us = <12000>; 81 81 + }; 82 82 + }; 83 83 + 84 84 + &lpi2c7 { 85 85 + clock-frequency = <1000000>; 86 86 + pinctrl-names = "default"; 87 87 + pinctrl-0 = <&pinctrl_lpi2c7>; 88 88 + status = "okay"; 89 89 + 90 90 + i2c7_pcal6524: i2c7-gpio@22 { 91 91 + compatible = "nxp,pcal6524"; 92 92 + reg = <0x22>; 93 93 + pinctrl-names = "default"; 94 94 + pinctrl-0 = <&pinctrl_i2c7_pcal6524>; 95 95 + gpio-controller; 96 96 + #gpio-cells = <2>; 97 97 + interrupt-controller; 98 98 + #interrupt-cells = <2>; 99 99 + interrupt-parent = <&gpio5>; 100 100 + interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 101 101 + }; 102 102 + }; 103 103 + 104 104 + &lpuart1 { 105 105 + /* console */ 106 106 + pinctrl-names = "default"; 107 107 + pinctrl-0 = <&pinctrl_uart1>; 108 108 + status = "okay"; 109 109 + }; 110 110 + 111 111 + &mu7 { 112 112 + status = "okay"; 113 113 + }; 114 114 + 115 115 + &pcie0 { 116 116 + pinctrl-0 = <&pinctrl_pcie0>; 117 117 + pinctrl-names = "default"; 118 118 + reset-gpio = <&i2c7_pcal6524 5 GPIO_ACTIVE_LOW>; 119 119 + vpcie-supply = <&reg_pcie0>; 120 120 + status = "okay"; 121 121 + }; 122 122 + 123 123 + &pcie1 { 124 124 + pinctrl-0 = <&pinctrl_pcie1>; 125 125 + pinctrl-names = "default"; 126 126 + reset-gpio = <&i2c7_pcal6524 16 GPIO_ACTIVE_LOW>; 127 127 + vpcie-supply = <&reg_slot_pwr>; 128 128 + status = "okay"; 129 129 + }; 130 130 + 131 131 + &usdhc1 { 132 132 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 133 133 + pinctrl-0 = <&pinctrl_usdhc1>; 134 134 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 135 135 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 136 136 + pinctrl-3 = <&pinctrl_usdhc1>; 137 137 + bus-width = <8>; 138 138 + non-removable; 139 139 + no-sdio; 140 140 + no-sd; 141 141 + status = "okay"; 142 142 + }; 143 143 + 144 144 + &usdhc2 { 145 145 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 146 146 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 147 147 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 148 148 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 149 149 + pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 150 150 + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 151 151 + vmmc-supply = <&reg_usdhc2_vmmc>; 152 152 + bus-width = <4>; 153 153 + status = "okay"; 154 154 + }; 155 155 + 156 156 + &wdog3 { 157 157 + fsl,ext-reset-output; 158 158 + status = "okay"; 159 159 + }; 160 160 + 161 161 + &scmi_iomuxc { 162 162 + pinctrl_i2c7_pcal6524: i2c7pcal6524grp { 163 163 + fsl,pins = < 164 164 + IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x31e 165 165 + >; 166 166 + }; 167 167 + 168 168 + pinctrl_lpi2c7: lpi2c7grp { 169 169 + fsl,pins = < 170 170 + IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e 171 171 + IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40000b9e 172 172 + >; 173 173 + }; 174 174 + 175 175 + pinctrl_pcie0: pcie0grp { 176 176 + fsl,pins = < 177 177 + IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x4000031e 178 178 + >; 179 179 + }; 180 180 + 181 181 + pinctrl_pcie1: pcie1grp { 182 182 + fsl,pins = < 183 183 + IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e 184 184 + >; 185 185 + }; 186 186 + 187 187 + pinctrl_uart1: uart1grp { 188 188 + fsl,pins = < 189 189 + IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 190 190 + IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 191 191 + >; 192 192 + }; 193 193 + 194 194 + pinctrl_usdhc1: usdhc1grp { 195 195 + fsl,pins = < 196 196 + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 197 197 + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 198 198 + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 199 199 + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 200 200 + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 201 201 + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 202 202 + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 203 203 + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 204 204 + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 205 205 + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 206 206 + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 207 207 + >; 208 208 + }; 209 209 + 210 210 + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 211 211 + fsl,pins = < 212 212 + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e 213 213 + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e 214 214 + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 215 215 + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 216 216 + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 217 217 + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 218 218 + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 219 219 + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 220 220 + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 221 221 + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 222 222 + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 223 223 + >; 224 224 + }; 225 225 + 226 226 + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 227 227 + fsl,pins = < 228 228 + IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe 229 229 + IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe 230 230 + IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 231 231 + IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 232 232 + IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 233 233 + IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 234 234 + IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 235 235 + IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 236 236 + IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 237 237 + IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 238 238 + IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 239 239 + >; 240 240 + }; 241 241 + 242 242 + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 243 243 + fsl,pins = < 244 244 + IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x31e 245 245 + >; 246 246 + }; 247 247 + 248 248 + pinctrl_usdhc2_gpio: usdhc2gpiogrp { 249 249 + fsl,pins = < 250 250 + IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x31e 251 251 + >; 252 252 + }; 253 253 + 254 254 + pinctrl_usdhc2: usdhc2grp { 255 255 + fsl,pins = < 256 256 + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 257 257 + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 258 258 + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 259 259 + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 260 260 + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 261 261 + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 262 262 + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 263 263 + >; 264 264 + }; 265 265 + 266 266 + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 267 267 + fsl,pins = < 268 268 + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e 269 269 + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e 270 270 + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 271 271 + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 272 272 + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 273 273 + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 274 274 + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 275 275 + >; 276 276 + }; 277 277 + 278 278 + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 279 279 + fsl,pins = < 280 280 + IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe 281 281 + IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe 282 282 + IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 283 283 + IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 284 284 + IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 285 285 + IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 286 286 + IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 287 287 + >; 288 288 + }; 289 289 + };

+187

arch/arm64/boot/dts/freescale/imx95-clock.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only OR MIT */ 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + #ifndef __CLOCK_IMX95_H 7 7 + #define __CLOCK_IMX95_H 8 8 + 9 9 + /* The index should match i.MX95 SCMI Firmware */ 10 10 + #define IMX95_CLK_32K 1 11 11 + #define IMX95_CLK_24M 2 12 12 + #define IMX95_CLK_FRO 3 13 13 + #define IMX95_CLK_SYSPLL1_VCO 4 14 14 + #define IMX95_CLK_SYSPLL1_PFD0_UNGATED 5 15 15 + #define IMX95_CLK_SYSPLL1_PFD0 6 16 16 + #define IMX95_CLK_SYSPLL1_PFD0_DIV2 7 17 17 + #define IMX95_CLK_SYSPLL1_PFD1_UNGATED 8 18 18 + #define IMX95_CLK_SYSPLL1_PFD1 9 19 19 + #define IMX95_CLK_SYSPLL1_PFD1_DIV2 10 20 20 + #define IMX95_CLK_SYSPLL1_PFD2_UNGATED 11 21 21 + #define IMX95_CLK_SYSPLL1_PFD2 12 22 22 + #define IMX95_CLK_SYSPLL1_PFD2_DIV2 13 23 23 + #define IMX95_CLK_AUDIOPLL1_VCO 14 24 24 + #define IMX95_CLK_AUDIOPLL1 15 25 25 + #define IMX95_CLK_AUDIOPLL2_VCO 16 26 26 + #define IMX95_CLK_AUDIOPLL2 17 27 27 + #define IMX95_CLK_VIDEOPLL1_VCO 18 28 28 + #define IMX95_CLK_VIDEOPLL1 19 29 29 + #define IMX95_CLK_RESERVED20 20 30 30 + #define IMX95_CLK_RESERVED21 21 31 31 + #define IMX95_CLK_RESERVED22 22 32 32 + #define IMX95_CLK_RESERVED23 23 33 33 + #define IMX95_CLK_ARMPLL_VCO 24 34 34 + #define IMX95_CLK_ARMPLL_PFD0_UNGATED 25 35 35 + #define IMX95_CLK_ARMPLL_PFD0 26 36 36 + #define IMX95_CLK_ARMPLL_PFD1_UNGATED 27 37 37 + #define IMX95_CLK_ARMPLL_PFD1 28 38 38 + #define IMX95_CLK_ARMPLL_PFD2_UNGATED 29 39 39 + #define IMX95_CLK_ARMPLL_PFD2 30 40 40 + #define IMX95_CLK_ARMPLL_PFD3_UNGATED 31 41 41 + #define IMX95_CLK_ARMPLL_PFD3 32 42 42 + #define IMX95_CLK_DRAMPLL_VCO 33 43 43 + #define IMX95_CLK_DRAMPLL 34 44 44 + #define IMX95_CLK_HSIOPLL_VCO 35 45 45 + #define IMX95_CLK_HSIOPLL 36 46 46 + #define IMX95_CLK_LDBPLL_VCO 37 47 47 + #define IMX95_CLK_LDBPLL 38 48 48 + #define IMX95_CLK_EXT1 39 49 49 + #define IMX95_CLK_EXT2 40 50 50 + 51 51 + #define IMX95_CCM_NUM_CLK_SRC 41 52 52 + 53 53 + #define IMX95_CLK_ADC (IMX95_CCM_NUM_CLK_SRC + 0) 54 54 + #define IMX95_CLK_TMU (IMX95_CCM_NUM_CLK_SRC + 1) 55 55 + #define IMX95_CLK_BUSAON (IMX95_CCM_NUM_CLK_SRC + 2) 56 56 + #define IMX95_CLK_CAN1 (IMX95_CCM_NUM_CLK_SRC + 3) 57 57 + #define IMX95_CLK_I3C1 (IMX95_CCM_NUM_CLK_SRC + 4) 58 58 + #define IMX95_CLK_I3C1SLOW (IMX95_CCM_NUM_CLK_SRC + 5) 59 59 + #define IMX95_CLK_LPI2C1 (IMX95_CCM_NUM_CLK_SRC + 6) 60 60 + #define IMX95_CLK_LPI2C2 (IMX95_CCM_NUM_CLK_SRC + 7) 61 61 + #define IMX95_CLK_LPSPI1 (IMX95_CCM_NUM_CLK_SRC + 8) 62 62 + #define IMX95_CLK_LPSPI2 (IMX95_CCM_NUM_CLK_SRC + 9) 63 63 + #define IMX95_CLK_LPTMR1 (IMX95_CCM_NUM_CLK_SRC + 10) 64 64 + #define IMX95_CLK_LPUART1 (IMX95_CCM_NUM_CLK_SRC + 11) 65 65 + #define IMX95_CLK_LPUART2 (IMX95_CCM_NUM_CLK_SRC + 12) 66 66 + #define IMX95_CLK_M33 (IMX95_CCM_NUM_CLK_SRC + 13) 67 67 + #define IMX95_CLK_M33SYSTICK (IMX95_CCM_NUM_CLK_SRC + 14) 68 68 + #define IMX95_CLK_MQS1 (IMX95_CCM_NUM_CLK_SRC + 15) 69 69 + #define IMX95_CLK_PDM (IMX95_CCM_NUM_CLK_SRC + 16) 70 70 + #define IMX95_CLK_SAI1 (IMX95_CCM_NUM_CLK_SRC + 17) 71 71 + #define IMX95_CLK_SENTINEL (IMX95_CCM_NUM_CLK_SRC + 18) 72 72 + #define IMX95_CLK_TPM2 (IMX95_CCM_NUM_CLK_SRC + 19) 73 73 + #define IMX95_CLK_TSTMR1 (IMX95_CCM_NUM_CLK_SRC + 20) 74 74 + #define IMX95_CLK_CAMAPB (IMX95_CCM_NUM_CLK_SRC + 21) 75 75 + #define IMX95_CLK_CAMAXI (IMX95_CCM_NUM_CLK_SRC + 22) 76 76 + #define IMX95_CLK_CAMCM0 (IMX95_CCM_NUM_CLK_SRC + 23) 77 77 + #define IMX95_CLK_CAMISI (IMX95_CCM_NUM_CLK_SRC + 24) 78 78 + #define IMX95_CLK_MIPIPHYCFG (IMX95_CCM_NUM_CLK_SRC + 25) 79 79 + #define IMX95_CLK_MIPIPHYPLLBYPASS (IMX95_CCM_NUM_CLK_SRC + 26) 80 80 + #define IMX95_CLK_MIPIPHYPLLREF (IMX95_CCM_NUM_CLK_SRC + 27) 81 81 + #define IMX95_CLK_MIPITESTBYTE (IMX95_CCM_NUM_CLK_SRC + 28) 82 82 + #define IMX95_CLK_A55 (IMX95_CCM_NUM_CLK_SRC + 29) 83 83 + #define IMX95_CLK_A55MTRBUS (IMX95_CCM_NUM_CLK_SRC + 30) 84 84 + #define IMX95_CLK_A55PERIPH (IMX95_CCM_NUM_CLK_SRC + 31) 85 85 + #define IMX95_CLK_DRAMALT (IMX95_CCM_NUM_CLK_SRC + 32) 86 86 + #define IMX95_CLK_DRAMAPB (IMX95_CCM_NUM_CLK_SRC + 33) 87 87 + #define IMX95_CLK_DISPAPB (IMX95_CCM_NUM_CLK_SRC + 34) 88 88 + #define IMX95_CLK_DISPAXI (IMX95_CCM_NUM_CLK_SRC + 35) 89 89 + #define IMX95_CLK_DISPDP (IMX95_CCM_NUM_CLK_SRC + 36) 90 90 + #define IMX95_CLK_DISPOCRAM (IMX95_CCM_NUM_CLK_SRC + 37) 91 91 + #define IMX95_CLK_DISPUSB31 (IMX95_CCM_NUM_CLK_SRC + 38) 92 92 + #define IMX95_CLK_DISP1PIX (IMX95_CCM_NUM_CLK_SRC + 39) 93 93 + #define IMX95_CLK_DISP2PIX (IMX95_CCM_NUM_CLK_SRC + 40) 94 94 + #define IMX95_CLK_DISP3PIX (IMX95_CCM_NUM_CLK_SRC + 41) 95 95 + #define IMX95_CLK_GPUAPB (IMX95_CCM_NUM_CLK_SRC + 42) 96 96 + #define IMX95_CLK_GPU (IMX95_CCM_NUM_CLK_SRC + 43) 97 97 + #define IMX95_CLK_HSIOACSCAN480M (IMX95_CCM_NUM_CLK_SRC + 44) 98 98 + #define IMX95_CLK_HSIOACSCAN80M (IMX95_CCM_NUM_CLK_SRC + 45) 99 99 + #define IMX95_CLK_HSIO (IMX95_CCM_NUM_CLK_SRC + 46) 100 100 + #define IMX95_CLK_HSIOPCIEAUX (IMX95_CCM_NUM_CLK_SRC + 47) 101 101 + #define IMX95_CLK_HSIOPCIETEST160M (IMX95_CCM_NUM_CLK_SRC + 48) 102 102 + #define IMX95_CLK_HSIOPCIETEST400M (IMX95_CCM_NUM_CLK_SRC + 49) 103 103 + #define IMX95_CLK_HSIOPCIETEST500M (IMX95_CCM_NUM_CLK_SRC + 50) 104 104 + #define IMX95_CLK_HSIOUSBTEST50M (IMX95_CCM_NUM_CLK_SRC + 51) 105 105 + #define IMX95_CLK_HSIOUSBTEST60M (IMX95_CCM_NUM_CLK_SRC + 52) 106 106 + #define IMX95_CLK_BUSM7 (IMX95_CCM_NUM_CLK_SRC + 53) 107 107 + #define IMX95_CLK_M7 (IMX95_CCM_NUM_CLK_SRC + 54) 108 108 + #define IMX95_CLK_M7SYSTICK (IMX95_CCM_NUM_CLK_SRC + 55) 109 109 + #define IMX95_CLK_BUSNETCMIX (IMX95_CCM_NUM_CLK_SRC + 56) 110 110 + #define IMX95_CLK_ENET (IMX95_CCM_NUM_CLK_SRC + 57) 111 111 + #define IMX95_CLK_ENETPHYTEST200M (IMX95_CCM_NUM_CLK_SRC + 58) 112 112 + #define IMX95_CLK_ENETPHYTEST500M (IMX95_CCM_NUM_CLK_SRC + 59) 113 113 + #define IMX95_CLK_ENETPHYTEST667M (IMX95_CCM_NUM_CLK_SRC + 60) 114 114 + #define IMX95_CLK_ENETREF (IMX95_CCM_NUM_CLK_SRC + 61) 115 115 + #define IMX95_CLK_ENETTIMER1 (IMX95_CCM_NUM_CLK_SRC + 62) 116 116 + #define IMX95_CLK_MQS2 (IMX95_CCM_NUM_CLK_SRC + 63) 117 117 + #define IMX95_CLK_SAI2 (IMX95_CCM_NUM_CLK_SRC + 64) 118 118 + #define IMX95_CLK_NOCAPB (IMX95_CCM_NUM_CLK_SRC + 65) 119 119 + #define IMX95_CLK_NOC (IMX95_CCM_NUM_CLK_SRC + 66) 120 120 + #define IMX95_CLK_NPUAPB (IMX95_CCM_NUM_CLK_SRC + 67) 121 121 + #define IMX95_CLK_NPU (IMX95_CCM_NUM_CLK_SRC + 68) 122 122 + #define IMX95_CLK_CCMCKO1 (IMX95_CCM_NUM_CLK_SRC + 69) 123 123 + #define IMX95_CLK_CCMCKO2 (IMX95_CCM_NUM_CLK_SRC + 70) 124 124 + #define IMX95_CLK_CCMCKO3 (IMX95_CCM_NUM_CLK_SRC + 71) 125 125 + #define IMX95_CLK_CCMCKO4 (IMX95_CCM_NUM_CLK_SRC + 72) 126 126 + #define IMX95_CLK_VPUAPB (IMX95_CCM_NUM_CLK_SRC + 73) 127 127 + #define IMX95_CLK_VPU (IMX95_CCM_NUM_CLK_SRC + 74) 128 128 + #define IMX95_CLK_VPUDSP (IMX95_CCM_NUM_CLK_SRC + 75) 129 129 + #define IMX95_CLK_VPUJPEG (IMX95_CCM_NUM_CLK_SRC + 76) 130 130 + #define IMX95_CLK_AUDIOXCVR (IMX95_CCM_NUM_CLK_SRC + 77) 131 131 + #define IMX95_CLK_BUSWAKEUP (IMX95_CCM_NUM_CLK_SRC + 78) 132 132 + #define IMX95_CLK_CAN2 (IMX95_CCM_NUM_CLK_SRC + 79) 133 133 + #define IMX95_CLK_CAN3 (IMX95_CCM_NUM_CLK_SRC + 80) 134 134 + #define IMX95_CLK_CAN4 (IMX95_CCM_NUM_CLK_SRC + 81) 135 135 + #define IMX95_CLK_CAN5 (IMX95_CCM_NUM_CLK_SRC + 82) 136 136 + #define IMX95_CLK_FLEXIO1 (IMX95_CCM_NUM_CLK_SRC + 83) 137 137 + #define IMX95_CLK_FLEXIO2 (IMX95_CCM_NUM_CLK_SRC + 84) 138 138 + #define IMX95_CLK_FLEXSPI1 (IMX95_CCM_NUM_CLK_SRC + 85) 139 139 + #define IMX95_CLK_I3C2 (IMX95_CCM_NUM_CLK_SRC + 86) 140 140 + #define IMX95_CLK_I3C2SLOW (IMX95_CCM_NUM_CLK_SRC + 87) 141 141 + #define IMX95_CLK_LPI2C3 (IMX95_CCM_NUM_CLK_SRC + 88) 142 142 + #define IMX95_CLK_LPI2C4 (IMX95_CCM_NUM_CLK_SRC + 89) 143 143 + #define IMX95_CLK_LPI2C5 (IMX95_CCM_NUM_CLK_SRC + 90) 144 144 + #define IMX95_CLK_LPI2C6 (IMX95_CCM_NUM_CLK_SRC + 91) 145 145 + #define IMX95_CLK_LPI2C7 (IMX95_CCM_NUM_CLK_SRC + 92) 146 146 + #define IMX95_CLK_LPI2C8 (IMX95_CCM_NUM_CLK_SRC + 93) 147 147 + #define IMX95_CLK_LPSPI3 (IMX95_CCM_NUM_CLK_SRC + 94) 148 148 + #define IMX95_CLK_LPSPI4 (IMX95_CCM_NUM_CLK_SRC + 95) 149 149 + #define IMX95_CLK_LPSPI5 (IMX95_CCM_NUM_CLK_SRC + 96) 150 150 + #define IMX95_CLK_LPSPI6 (IMX95_CCM_NUM_CLK_SRC + 97) 151 151 + #define IMX95_CLK_LPSPI7 (IMX95_CCM_NUM_CLK_SRC + 98) 152 152 + #define IMX95_CLK_LPSPI8 (IMX95_CCM_NUM_CLK_SRC + 99) 153 153 + #define IMX95_CLK_LPTMR2 (IMX95_CCM_NUM_CLK_SRC + 100) 154 154 + #define IMX95_CLK_LPUART3 (IMX95_CCM_NUM_CLK_SRC + 101) 155 155 + #define IMX95_CLK_LPUART4 (IMX95_CCM_NUM_CLK_SRC + 102) 156 156 + #define IMX95_CLK_LPUART5 (IMX95_CCM_NUM_CLK_SRC + 103) 157 157 + #define IMX95_CLK_LPUART6 (IMX95_CCM_NUM_CLK_SRC + 104) 158 158 + #define IMX95_CLK_LPUART7 (IMX95_CCM_NUM_CLK_SRC + 105) 159 159 + #define IMX95_CLK_LPUART8 (IMX95_CCM_NUM_CLK_SRC + 106) 160 160 + #define IMX95_CLK_SAI3 (IMX95_CCM_NUM_CLK_SRC + 107) 161 161 + #define IMX95_CLK_SAI4 (IMX95_CCM_NUM_CLK_SRC + 108) 162 162 + #define IMX95_CLK_SAI5 (IMX95_CCM_NUM_CLK_SRC + 109) 163 163 + #define IMX95_CLK_SPDIF (IMX95_CCM_NUM_CLK_SRC + 110) 164 164 + #define IMX95_CLK_SWOTRACE (IMX95_CCM_NUM_CLK_SRC + 111) 165 165 + #define IMX95_CLK_TPM4 (IMX95_CCM_NUM_CLK_SRC + 112) 166 166 + #define IMX95_CLK_TPM5 (IMX95_CCM_NUM_CLK_SRC + 113) 167 167 + #define IMX95_CLK_TPM6 (IMX95_CCM_NUM_CLK_SRC + 114) 168 168 + #define IMX95_CLK_TSTMR2 (IMX95_CCM_NUM_CLK_SRC + 115) 169 169 + #define IMX95_CLK_USBPHYBURUNIN (IMX95_CCM_NUM_CLK_SRC + 116) 170 170 + #define IMX95_CLK_USDHC1 (IMX95_CCM_NUM_CLK_SRC + 117) 171 171 + #define IMX95_CLK_USDHC2 (IMX95_CCM_NUM_CLK_SRC + 118) 172 172 + #define IMX95_CLK_USDHC3 (IMX95_CCM_NUM_CLK_SRC + 119) 173 173 + #define IMX95_CLK_V2XPK (IMX95_CCM_NUM_CLK_SRC + 120) 174 174 + #define IMX95_CLK_WAKEUPAXI (IMX95_CCM_NUM_CLK_SRC + 121) 175 175 + #define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122) 176 176 + #define IMX95_CLK_SEL_EXT (IMX95_CCM_NUM_CLK_SRC + 123 + 0) 177 177 + #define IMX95_CLK_SEL_A55C0 (IMX95_CCM_NUM_CLK_SRC + 123 + 1) 178 178 + #define IMX95_CLK_SEL_A55C1 (IMX95_CCM_NUM_CLK_SRC + 123 + 2) 179 179 + #define IMX95_CLK_SEL_A55C2 (IMX95_CCM_NUM_CLK_SRC + 123 + 3) 180 180 + #define IMX95_CLK_SEL_A55C3 (IMX95_CCM_NUM_CLK_SRC + 123 + 4) 181 181 + #define IMX95_CLK_SEL_A55C4 (IMX95_CCM_NUM_CLK_SRC + 123 + 5) 182 182 + #define IMX95_CLK_SEL_A55C5 (IMX95_CCM_NUM_CLK_SRC + 123 + 6) 183 183 + #define IMX95_CLK_SEL_A55P (IMX95_CCM_NUM_CLK_SRC + 123 + 7) 184 184 + #define IMX95_CLK_SEL_DRAM (IMX95_CCM_NUM_CLK_SRC + 123 + 8) 185 185 + #define IMX95_CLK_SEL_TEMPSENSE (IMX95_CCM_NUM_CLK_SRC + 123 + 9) 186 186 + 187 187 + #endif /* __CLOCK_IMX95_H */

+865

arch/arm64/boot/dts/freescale/imx95-pinfunc.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + #ifndef __DTS_IMX95_PINFUNC_H 7 7 + #define __DTS_IMX95_PINFUNC_H 8 8 + 9 9 + /* 10 10 + * The pin function ID is a tuple of 11 11 + * <mux_reg conf_reg input_reg mux_mode input_val> 12 12 + */ 13 13 + #define IMX95_PAD_DAP_TDI__JTAG_MUX_TDI 0x0000 0x0204 0x0610 0x00 0x00 14 14 + #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_MQS2_LEFT 0x0000 0x0204 0x0000 0x01 0x00 15 15 + #define IMX95_PAD_DAP_TDI__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x0000 0x0204 0x0000 0x02 0x00 16 16 + #define IMX95_PAD_DAP_TDI__CAN2_TX 0x0000 0x0204 0x0000 0x03 0x00 17 17 + #define IMX95_PAD_DAP_TDI__FLEXIO2_FLEXIO_BIT30 0x0000 0x0204 0x0000 0x04 0x00 18 18 + #define IMX95_PAD_DAP_TDI__GPIO3_IO_BIT28 0x0000 0x0204 0x0000 0x05 0x00 19 19 + #define IMX95_PAD_DAP_TDI__LPUART5_RX 0x0000 0x0204 0x0570 0x06 0x00 20 20 + 21 21 + #define IMX95_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x0004 0x0208 0x0614 0x00 0x00 22 22 + #define IMX95_PAD_DAP_TMS_SWDIO__CAN4_TX 0x0004 0x0208 0x0000 0x02 0x00 23 23 + #define IMX95_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO_BIT31 0x0004 0x0208 0x0000 0x04 0x00 24 24 + #define IMX95_PAD_DAP_TMS_SWDIO__GPIO3_IO_BIT29 0x0004 0x0208 0x0000 0x05 0x00 25 25 + #define IMX95_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x0004 0x0208 0x0000 0x06 0x00 26 26 + 27 27 + #define IMX95_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x0008 0x020C 0x060C 0x00 0x00 28 28 + #define IMX95_PAD_DAP_TCLK_SWCLK__CAN4_RX 0x0008 0x020C 0x044C 0x02 0x00 29 29 + #define IMX95_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO_BIT30 0x0008 0x020C 0x0460 0x04 0x00 30 30 + #define IMX95_PAD_DAP_TCLK_SWCLK__GPIO3_IO_BIT30 0x0008 0x020C 0x0000 0x05 0x00 31 31 + #define IMX95_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x0008 0x020C 0x056C 0x06 0x00 32 32 + 33 33 + #define IMX95_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x000C 0x0210 0x0000 0x00 0x00 34 34 + #define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_MQS2_RIGHT 0x000C 0x0210 0x0000 0x01 0x00 35 35 + #define IMX95_PAD_DAP_TDO_TRACESWO__NETCMIX_TOP_NETC_TMR_1588_ALARM 0x000C 0x0210 0x0000 0x02 0x00 36 36 + #define IMX95_PAD_DAP_TDO_TRACESWO__CAN2_RX 0x000C 0x0210 0x0444 0x03 0x00 37 37 + #define IMX95_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO_BIT31 0x000C 0x0210 0x0464 0x04 0x00 38 38 + #define IMX95_PAD_DAP_TDO_TRACESWO__GPIO3_IO_BIT31 0x000C 0x0210 0x0000 0x05 0x00 39 39 + #define IMX95_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x000C 0x0210 0x0574 0x06 0x00 40 40 + 41 41 + #define IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x0010 0x0214 0x0000 0x00 0x00 42 42 + #define IMX95_PAD_GPIO_IO00__LPI2C3_SDA 0x0010 0x0214 0x0504 0x11 0x00 43 43 + #define IMX95_PAD_GPIO_IO00__LPSPI6_PCS0 0x0010 0x0214 0x0000 0x04 0x00 44 44 + #define IMX95_PAD_GPIO_IO00__LPUART5_TX 0x0010 0x0214 0x0574 0x05 0x01 45 45 + #define IMX95_PAD_GPIO_IO00__LPI2C5_SDA 0x0010 0x0214 0x0514 0x16 0x00 46 46 + #define IMX95_PAD_GPIO_IO00__FLEXIO1_FLEXIO_BIT0 0x0010 0x0214 0x0468 0x07 0x00 47 47 + 48 48 + #define IMX95_PAD_GPIO_IO01__GPIO2_IO_BIT1 0x0014 0x0218 0x0000 0x00 0x00 49 49 + #define IMX95_PAD_GPIO_IO01__LPI2C3_SCL 0x0014 0x0218 0x0500 0x11 0x00 50 50 + #define IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x0014 0x0218 0x0000 0x04 0x00 51 51 + #define IMX95_PAD_GPIO_IO01__LPUART5_RX 0x0014 0x0218 0x0570 0x05 0x01 52 52 + #define IMX95_PAD_GPIO_IO01__LPI2C5_SCL 0x0014 0x0218 0x0510 0x16 0x00 53 53 + #define IMX95_PAD_GPIO_IO01__FLEXIO1_FLEXIO_BIT1 0x0014 0x0218 0x046C 0x07 0x00 54 54 + 55 55 + #define IMX95_PAD_GPIO_IO02__GPIO2_IO_BIT2 0x0018 0x021C 0x0000 0x00 0x00 56 56 + #define IMX95_PAD_GPIO_IO02__LPI2C4_SDA 0x0018 0x021C 0x050C 0x11 0x00 57 57 + #define IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x0018 0x021C 0x0000 0x04 0x00 58 58 + #define IMX95_PAD_GPIO_IO02__LPUART5_CTS_B 0x0018 0x021C 0x056C 0x05 0x01 59 59 + #define IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x0018 0x021C 0x051C 0x16 0x00 60 60 + #define IMX95_PAD_GPIO_IO02__FLEXIO1_FLEXIO_BIT2 0x0018 0x021C 0x0470 0x07 0x00 61 61 + 62 62 + #define IMX95_PAD_GPIO_IO03__GPIO2_IO_BIT3 0x001C 0x0220 0x0000 0x00 0x00 63 63 + #define IMX95_PAD_GPIO_IO03__LPI2C4_SCL 0x001C 0x0220 0x0508 0x11 0x00 64 64 + #define IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x001C 0x0220 0x0000 0x04 0x00 65 65 + #define IMX95_PAD_GPIO_IO03__LPUART5_RTS_B 0x001C 0x0220 0x0000 0x05 0x00 66 66 + #define IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x001C 0x0220 0x0518 0x16 0x00 67 67 + #define IMX95_PAD_GPIO_IO03__FLEXIO1_FLEXIO_BIT3 0x001C 0x0220 0x0474 0x07 0x00 68 68 + 69 69 + #define IMX95_PAD_GPIO_IO04__GPIO2_IO_BIT4 0x0020 0x0224 0x0000 0x00 0x00 70 70 + #define IMX95_PAD_GPIO_IO04__TPM3_CH0 0x0020 0x0224 0x0000 0x01 0x00 71 71 + #define IMX95_PAD_GPIO_IO04__AONMIX_TOP_PDM_CLK 0x0020 0x0224 0x0000 0x02 0x00 72 72 + #define IMX95_PAD_GPIO_IO04__CAN4_TX 0x0020 0x0224 0x0000 0x03 0x00 73 73 + #define IMX95_PAD_GPIO_IO04__LPSPI7_PCS0 0x0020 0x0224 0x0000 0x04 0x00 74 74 + #define IMX95_PAD_GPIO_IO04__LPUART6_TX 0x0020 0x0224 0x0580 0x05 0x01 75 75 + #define IMX95_PAD_GPIO_IO04__LPI2C6_SDA 0x0020 0x0224 0x051C 0x16 0x01 76 76 + #define IMX95_PAD_GPIO_IO04__FLEXIO1_FLEXIO_BIT4 0x0020 0x0224 0x0478 0x07 0x00 77 77 + 78 78 + #define IMX95_PAD_GPIO_IO05__GPIO2_IO_BIT5 0x0024 0x0228 0x0000 0x00 0x00 79 79 + #define IMX95_PAD_GPIO_IO05__TPM4_CH0 0x0024 0x0228 0x0000 0x01 0x00 80 80 + #define IMX95_PAD_GPIO_IO05__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0024 0x0228 0x040C 0x02 0x01 81 81 + #define IMX95_PAD_GPIO_IO05__CAN4_RX 0x0024 0x0228 0x044C 0x03 0x01 82 82 + #define IMX95_PAD_GPIO_IO05__LPSPI7_SIN 0x0024 0x0228 0x0000 0x04 0x00 83 83 + #define IMX95_PAD_GPIO_IO05__LPUART6_RX 0x0024 0x0228 0x057C 0x05 0x01 84 84 + #define IMX95_PAD_GPIO_IO05__LPI2C6_SCL 0x0024 0x0228 0x0518 0x16 0x01 85 85 + #define IMX95_PAD_GPIO_IO05__FLEXIO1_FLEXIO_BIT5 0x0024 0x0228 0x047C 0x07 0x00 86 86 + 87 87 + #define IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x0028 0x022C 0x0000 0x00 0x00 88 88 + #define IMX95_PAD_GPIO_IO06__TPM5_CH0 0x0028 0x022C 0x0000 0x01 0x00 89 89 + #define IMX95_PAD_GPIO_IO06__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0028 0x022C 0x0410 0x02 0x01 90 90 + #define IMX95_PAD_GPIO_IO06__LPSPI7_SOUT 0x0028 0x022C 0x0000 0x04 0x00 91 91 + #define IMX95_PAD_GPIO_IO06__LPUART6_CTS_B 0x0028 0x022C 0x0578 0x05 0x01 92 92 + #define IMX95_PAD_GPIO_IO06__LPI2C7_SDA 0x0028 0x022C 0x0524 0x16 0x00 93 93 + #define IMX95_PAD_GPIO_IO06__FLEXIO1_FLEXIO_BIT6 0x0028 0x022C 0x0480 0x07 0x00 94 94 + 95 95 + #define IMX95_PAD_GPIO_IO07__GPIO2_IO_BIT7 0x002C 0x0230 0x0000 0x00 0x00 96 96 + #define IMX95_PAD_GPIO_IO07__LPSPI3_PCS1 0x002C 0x0230 0x0000 0x01 0x00 97 97 + #define IMX95_PAD_GPIO_IO07__LPSPI7_SCK 0x002C 0x0230 0x0000 0x04 0x00 98 98 + #define IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x002C 0x0230 0x0000 0x05 0x00 99 99 + #define IMX95_PAD_GPIO_IO07__LPI2C7_SCL 0x002C 0x0230 0x0520 0x16 0x00 100 100 + #define IMX95_PAD_GPIO_IO07__FLEXIO1_FLEXIO_BIT7 0x002C 0x0230 0x0484 0x07 0x00 101 101 + 102 102 + #define IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x0030 0x0234 0x0000 0x00 0x00 103 103 + #define IMX95_PAD_GPIO_IO08__LPSPI3_PCS0 0x0030 0x0234 0x0000 0x01 0x00 104 104 + #define IMX95_PAD_GPIO_IO08__TPM6_CH0 0x0030 0x0234 0x0000 0x04 0x00 105 105 + #define IMX95_PAD_GPIO_IO08__LPUART7_TX 0x0030 0x0234 0x0588 0x05 0x01 106 106 + #define IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x0030 0x0234 0x0524 0x16 0x01 107 107 + #define IMX95_PAD_GPIO_IO08__FLEXIO1_FLEXIO_BIT8 0x0030 0x0234 0x0488 0x07 0x00 108 108 + 109 109 + #define IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x0034 0x0238 0x0000 0x00 0x00 110 110 + #define IMX95_PAD_GPIO_IO09__LPSPI3_SIN 0x0034 0x0238 0x0000 0x01 0x00 111 111 + #define IMX95_PAD_GPIO_IO09__TPM3_EXTCLK 0x0034 0x0238 0x0000 0x04 0x00 112 112 + #define IMX95_PAD_GPIO_IO09__LPUART7_RX 0x0034 0x0238 0x0584 0x05 0x01 113 113 + #define IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x0034 0x0238 0x0520 0x16 0x01 114 114 + #define IMX95_PAD_GPIO_IO09__FLEXIO1_FLEXIO_BIT9 0x0034 0x0238 0x048C 0x07 0x00 115 115 + 116 116 + #define IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x0038 0x023C 0x0000 0x00 0x00 117 117 + #define IMX95_PAD_GPIO_IO10__LPSPI3_SOUT 0x0038 0x023C 0x0000 0x01 0x00 118 118 + #define IMX95_PAD_GPIO_IO10__TPM4_EXTCLK 0x0038 0x023C 0x0000 0x04 0x00 119 119 + #define IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x0038 0x023C 0x0000 0x05 0x00 120 120 + #define IMX95_PAD_GPIO_IO10__LPI2C8_SDA 0x0038 0x023C 0x052C 0x16 0x00 121 121 + #define IMX95_PAD_GPIO_IO10__FLEXIO1_FLEXIO_BIT10 0x0038 0x023C 0x0490 0x07 0x00 122 122 + 123 123 + #define IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x003C 0x0240 0x0000 0x00 0x00 124 124 + #define IMX95_PAD_GPIO_IO11__LPSPI3_SCK 0x003C 0x0240 0x0000 0x01 0x00 125 125 + #define IMX95_PAD_GPIO_IO11__TPM5_EXTCLK 0x003C 0x0240 0x0000 0x04 0x00 126 126 + #define IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x003C 0x0240 0x0000 0x05 0x00 127 127 + #define IMX95_PAD_GPIO_IO11__LPI2C8_SCL 0x003C 0x0240 0x0528 0x16 0x00 128 128 + #define IMX95_PAD_GPIO_IO11__FLEXIO1_FLEXIO_BIT11 0x003C 0x0240 0x0494 0x07 0x00 129 129 + 130 130 + #define IMX95_PAD_GPIO_IO12__GPIO2_IO_BIT12 0x0040 0x0244 0x0000 0x00 0x00 131 131 + #define IMX95_PAD_GPIO_IO12__TPM3_CH2 0x0040 0x0244 0x0000 0x01 0x00 132 132 + #define IMX95_PAD_GPIO_IO12__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0040 0x0244 0x0414 0x02 0x00 133 133 + #define IMX95_PAD_GPIO_IO12__FLEXIO1_FLEXIO_BIT12 0x0040 0x0244 0x0498 0x03 0x00 134 134 + #define IMX95_PAD_GPIO_IO12__LPSPI8_PCS0 0x0040 0x0244 0x0000 0x04 0x00 135 135 + #define IMX95_PAD_GPIO_IO12__LPUART8_TX 0x0040 0x0244 0x0000 0x05 0x00 136 136 + #define IMX95_PAD_GPIO_IO12__LPI2C8_SDA 0x0040 0x0244 0x052C 0x16 0x01 137 137 + #define IMX95_PAD_GPIO_IO12__SAI3_RX_SYNC 0x0040 0x0244 0x0590 0x07 0x00 138 138 + 139 139 + #define IMX95_PAD_GPIO_IO13__GPIO2_IO_BIT13 0x0044 0x0248 0x0000 0x00 0x00 140 140 + #define IMX95_PAD_GPIO_IO13__TPM4_CH2 0x0044 0x0248 0x0000 0x01 0x00 141 141 + #define IMX95_PAD_GPIO_IO13__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x0044 0x0248 0x0418 0x02 0x00 142 142 + #define IMX95_PAD_GPIO_IO13__LPSPI8_SIN 0x0044 0x0248 0x0000 0x04 0x00 143 143 + #define IMX95_PAD_GPIO_IO13__LPUART8_RX 0x0044 0x0248 0x0000 0x05 0x00 144 144 + #define IMX95_PAD_GPIO_IO13__LPI2C8_SCL 0x0044 0x0248 0x0528 0x16 0x01 145 145 + #define IMX95_PAD_GPIO_IO13__FLEXIO1_FLEXIO_BIT13 0x0044 0x0248 0x049C 0x07 0x00 146 146 + 147 147 + #define IMX95_PAD_GPIO_IO14__GPIO2_IO_BIT14 0x0048 0x024C 0x0000 0x00 0x00 148 148 + #define IMX95_PAD_GPIO_IO14__LPUART3_TX 0x0048 0x024C 0x055C 0x01 0x01 149 149 + #define IMX95_PAD_GPIO_IO14__LPSPI8_SOUT 0x0048 0x024C 0x0000 0x04 0x00 150 150 + #define IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x0048 0x024C 0x0000 0x05 0x00 151 151 + #define IMX95_PAD_GPIO_IO14__LPUART4_TX 0x0048 0x024C 0x0568 0x06 0x01 152 152 + #define IMX95_PAD_GPIO_IO14__FLEXIO1_FLEXIO_BIT14 0x0048 0x024C 0x04A0 0x07 0x00 153 153 + 154 154 + #define IMX95_PAD_GPIO_IO15__GPIO2_IO_BIT15 0x004C 0x0250 0x0000 0x00 0x00 155 155 + #define IMX95_PAD_GPIO_IO15__LPUART3_RX 0x004C 0x0250 0x0558 0x01 0x01 156 156 + #define IMX95_PAD_GPIO_IO15__LPSPI8_SCK 0x004C 0x0250 0x0000 0x04 0x00 157 157 + #define IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x004C 0x0250 0x0000 0x05 0x00 158 158 + #define IMX95_PAD_GPIO_IO15__LPUART4_RX 0x004C 0x0250 0x0564 0x06 0x01 159 159 + #define IMX95_PAD_GPIO_IO15__FLEXIO1_FLEXIO_BIT15 0x004C 0x0250 0x04A4 0x07 0x00 160 160 + 161 161 + #define IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x0050 0x0254 0x0000 0x00 0x00 162 162 + #define IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x0050 0x0254 0x0000 0x01 0x00 163 163 + #define IMX95_PAD_GPIO_IO16__AONMIX_TOP_PDM_BIT_STREAM_BIT2 0x0050 0x0254 0x0414 0x02 0x01 164 164 + #define IMX95_PAD_GPIO_IO16__LPUART3_CTS_B 0x0050 0x0254 0x0554 0x04 0x01 165 165 + #define IMX95_PAD_GPIO_IO16__LPSPI4_PCS2 0x0050 0x0254 0x0538 0x05 0x01 166 166 + #define IMX95_PAD_GPIO_IO16__LPUART4_CTS_B 0x0050 0x0254 0x0560 0x06 0x01 167 167 + #define IMX95_PAD_GPIO_IO16__FLEXIO1_FLEXIO_BIT16 0x0050 0x0254 0x04A8 0x07 0x00 168 168 + 169 169 + #define IMX95_PAD_GPIO_IO17__GPIO2_IO_BIT17 0x0054 0x0258 0x0000 0x00 0x00 170 170 + #define IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x0054 0x0258 0x0000 0x01 0x00 171 171 + #define IMX95_PAD_GPIO_IO17__LPUART3_RTS_B 0x0054 0x0258 0x0000 0x04 0x00 172 172 + #define IMX95_PAD_GPIO_IO17__LPSPI4_PCS1 0x0054 0x0258 0x0534 0x05 0x01 173 173 + #define IMX95_PAD_GPIO_IO17__LPUART4_RTS_B 0x0054 0x0258 0x0000 0x06 0x00 174 174 + #define IMX95_PAD_GPIO_IO17__FLEXIO1_FLEXIO_BIT17 0x0054 0x0258 0x04AC 0x07 0x00 175 175 + 176 176 + #define IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x0058 0x025C 0x0000 0x00 0x00 177 177 + #define IMX95_PAD_GPIO_IO18__SAI3_RX_BCLK 0x0058 0x025C 0x058C 0x01 0x00 178 178 + #define IMX95_PAD_GPIO_IO18__LPSPI5_PCS0 0x0058 0x025C 0x0000 0x04 0x00 179 179 + #define IMX95_PAD_GPIO_IO18__LPSPI4_PCS0 0x0058 0x025C 0x0530 0x05 0x01 180 180 + #define IMX95_PAD_GPIO_IO18__TPM5_CH2 0x0058 0x025C 0x0000 0x06 0x00 181 181 + #define IMX95_PAD_GPIO_IO18__FLEXIO1_FLEXIO_BIT18 0x0058 0x025C 0x04B0 0x07 0x00 182 182 + 183 183 + #define IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x005C 0x0260 0x0000 0x00 0x00 184 184 + #define IMX95_PAD_GPIO_IO19__SAI3_RX_SYNC 0x005C 0x0260 0x0590 0x01 0x01 185 185 + #define IMX95_PAD_GPIO_IO19__AONMIX_TOP_PDM_BIT_STREAM_BIT3 0x005C 0x0260 0x0418 0x02 0x01 186 186 + #define IMX95_PAD_GPIO_IO19__FLEXIO1_FLEXIO_BIT19 0x005C 0x0260 0x04B4 0x03 0x00 187 187 + #define IMX95_PAD_GPIO_IO19__LPSPI5_SIN 0x005C 0x0260 0x0000 0x04 0x00 188 188 + #define IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x005C 0x0260 0x0540 0x05 0x01 189 189 + #define IMX95_PAD_GPIO_IO19__TPM6_CH2 0x005C 0x0260 0x0000 0x06 0x00 190 190 + #define IMX95_PAD_GPIO_IO19__SAI3_TX_DATA_BIT0 0x005C 0x0260 0x0000 0x07 0x00 191 191 + 192 192 + #define IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x0060 0x0264 0x0000 0x00 0x00 193 193 + #define IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x0060 0x0264 0x0000 0x01 0x00 194 194 + #define IMX95_PAD_GPIO_IO20__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x0060 0x0264 0x040C 0x02 0x02 195 195 + #define IMX95_PAD_GPIO_IO20__LPSPI5_SOUT 0x0060 0x0264 0x0000 0x04 0x00 196 196 + #define IMX95_PAD_GPIO_IO20__LPSPI4_SOUT 0x0060 0x0264 0x0544 0x05 0x01 197 197 + #define IMX95_PAD_GPIO_IO20__TPM3_CH1 0x0060 0x0264 0x0000 0x06 0x00 198 198 + #define IMX95_PAD_GPIO_IO20__FLEXIO1_FLEXIO_BIT20 0x0060 0x0264 0x04B8 0x07 0x00 199 199 + 200 200 + #define IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x0064 0x0268 0x0000 0x00 0x00 201 201 + #define IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x0064 0x0268 0x0000 0x01 0x00 202 202 + #define IMX95_PAD_GPIO_IO21__AONMIX_TOP_PDM_CLK 0x0064 0x0268 0x0000 0x02 0x00 203 203 + #define IMX95_PAD_GPIO_IO21__FLEXIO1_FLEXIO_BIT21 0x0064 0x0268 0x04BC 0x03 0x00 204 204 + #define IMX95_PAD_GPIO_IO21__LPSPI5_SCK 0x0064 0x0268 0x0000 0x04 0x00 205 205 + #define IMX95_PAD_GPIO_IO21__LPSPI4_SCK 0x0064 0x0268 0x053C 0x05 0x01 206 206 + #define IMX95_PAD_GPIO_IO21__TPM4_CH1 0x0064 0x0268 0x0000 0x06 0x00 207 207 + #define IMX95_PAD_GPIO_IO21__SAI3_RX_BCLK 0x0064 0x0268 0x058C 0x07 0x01 208 208 + 209 209 + #define IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x0068 0x026C 0x0000 0x00 0x00 210 210 + #define IMX95_PAD_GPIO_IO22__USDHC3_CLK 0x0068 0x026C 0x05C8 0x01 0x00 211 211 + #define IMX95_PAD_GPIO_IO22__SPDIF_IN 0x0068 0x026C 0x0454 0x02 0x02 212 212 + #define IMX95_PAD_GPIO_IO22__CAN5_TX 0x0068 0x026C 0x0000 0x03 0x00 213 213 + #define IMX95_PAD_GPIO_IO22__TPM5_CH1 0x0068 0x026C 0x0000 0x04 0x00 214 214 + #define IMX95_PAD_GPIO_IO22__TPM6_EXTCLK 0x0068 0x026C 0x0000 0x05 0x00 215 215 + #define IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x0068 0x026C 0x0514 0x16 0x01 216 216 + #define IMX95_PAD_GPIO_IO22__FLEXIO1_FLEXIO_BIT22 0x0068 0x026C 0x04C0 0x07 0x00 217 217 + 218 218 + #define IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x006C 0x0270 0x0000 0x00 0x00 219 219 + #define IMX95_PAD_GPIO_IO23__USDHC3_CMD 0x006C 0x0270 0x05CC 0x01 0x00 220 220 + #define IMX95_PAD_GPIO_IO23__SPDIF_OUT 0x006C 0x0270 0x0000 0x02 0x00 221 221 + #define IMX95_PAD_GPIO_IO23__CAN5_RX 0x006C 0x0270 0x0450 0x03 0x00 222 222 + #define IMX95_PAD_GPIO_IO23__TPM6_CH1 0x006C 0x0270 0x0000 0x04 0x00 223 223 + #define IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x006C 0x0270 0x0510 0x16 0x01 224 224 + #define IMX95_PAD_GPIO_IO23__FLEXIO1_FLEXIO_BIT23 0x006C 0x0270 0x04C4 0x07 0x00 225 225 + 226 226 + #define IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x0070 0x0274 0x0000 0x00 0x00 227 227 + #define IMX95_PAD_GPIO_IO24__USDHC3_DATA0 0x0070 0x0274 0x05D0 0x01 0x00 228 228 + #define IMX95_PAD_GPIO_IO24__TPM3_CH3 0x0070 0x0274 0x0000 0x04 0x00 229 229 + #define IMX95_PAD_GPIO_IO24__JTAG_MUX_TDO 0x0070 0x0274 0x0000 0x05 0x00 230 230 + #define IMX95_PAD_GPIO_IO24__LPSPI6_PCS1 0x0070 0x0274 0x0000 0x06 0x00 231 231 + #define IMX95_PAD_GPIO_IO24__FLEXIO1_FLEXIO_BIT24 0x0070 0x0274 0x04C8 0x07 0x00 232 232 + 233 233 + #define IMX95_PAD_GPIO_IO25__GPIO2_IO_BIT25 0x0074 0x0278 0x0000 0x00 0x00 234 234 + #define IMX95_PAD_GPIO_IO25__USDHC3_DATA1 0x0074 0x0278 0x05D4 0x01 0x00 235 235 + #define IMX95_PAD_GPIO_IO25__CAN2_TX 0x0074 0x0278 0x0000 0x02 0x00 236 236 + #define IMX95_PAD_GPIO_IO25__TPM4_CH3 0x0074 0x0278 0x0000 0x04 0x00 237 237 + #define IMX95_PAD_GPIO_IO25__JTAG_MUX_TCK 0x0074 0x0278 0x060C 0x05 0x01 238 238 + #define IMX95_PAD_GPIO_IO25__LPSPI7_PCS1 0x0074 0x0278 0x0000 0x06 0x00 239 239 + #define IMX95_PAD_GPIO_IO25__FLEXIO1_FLEXIO_BIT25 0x0074 0x0278 0x04CC 0x07 0x00 240 240 + 241 241 + #define IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x0078 0x027C 0x0000 0x00 0x00 242 242 + #define IMX95_PAD_GPIO_IO26__USDHC3_DATA2 0x0078 0x027C 0x05D8 0x01 0x00 243 243 + #define IMX95_PAD_GPIO_IO26__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x0078 0x027C 0x0410 0x02 0x02 244 244 + #define IMX95_PAD_GPIO_IO26__FLEXIO1_FLEXIO_BIT26 0x0078 0x027C 0x0458 0x03 0x01 245 245 + #define IMX95_PAD_GPIO_IO26__TPM5_CH3 0x0078 0x027C 0x0000 0x04 0x00 246 246 + #define IMX95_PAD_GPIO_IO26__JTAG_MUX_TDI 0x0078 0x027C 0x0610 0x05 0x01 247 247 + #define IMX95_PAD_GPIO_IO26__LPSPI8_PCS1 0x0078 0x027C 0x0000 0x06 0x00 248 248 + #define IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x0078 0x027C 0x0000 0x07 0x00 249 249 + 250 250 + #define IMX95_PAD_GPIO_IO27__GPIO2_IO_BIT27 0x007C 0x0280 0x0000 0x00 0x00 251 251 + #define IMX95_PAD_GPIO_IO27__USDHC3_DATA3 0x007C 0x0280 0x05DC 0x01 0x00 252 252 + #define IMX95_PAD_GPIO_IO27__CAN2_RX 0x007C 0x0280 0x0444 0x02 0x02 253 253 + #define IMX95_PAD_GPIO_IO27__TPM6_CH3 0x007C 0x0280 0x0000 0x04 0x00 254 254 + #define IMX95_PAD_GPIO_IO27__JTAG_MUX_TMS 0x007C 0x0280 0x0614 0x05 0x01 255 255 + #define IMX95_PAD_GPIO_IO27__LPSPI5_PCS1 0x007C 0x0280 0x0000 0x06 0x00 256 256 + #define IMX95_PAD_GPIO_IO27__FLEXIO1_FLEXIO_BIT27 0x007C 0x0280 0x045C 0x07 0x01 257 257 + 258 258 + #define IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x0080 0x0284 0x0000 0x00 0x00 259 259 + #define IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x0080 0x0284 0x0504 0x11 0x01 260 260 + #define IMX95_PAD_GPIO_IO28__CAN3_TX 0x0080 0x0284 0x0000 0x02 0x00 261 261 + #define IMX95_PAD_GPIO_IO28__FLEXIO1_FLEXIO_BIT28 0x0080 0x0284 0x0000 0x07 0x00 262 262 + 263 263 + #define IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x0084 0x0288 0x0000 0x00 0x00 264 264 + #define IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x0084 0x0288 0x0500 0x11 0x01 265 265 + #define IMX95_PAD_GPIO_IO29__CAN3_RX 0x0084 0x0288 0x0448 0x02 0x01 266 266 + #define IMX95_PAD_GPIO_IO29__FLEXIO1_FLEXIO_BIT29 0x0084 0x0288 0x0000 0x07 0x00 267 267 + 268 268 + #define IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x0088 0x028C 0x0000 0x00 0x00 269 269 + #define IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x0088 0x028C 0x050C 0x11 0x01 270 270 + #define IMX95_PAD_GPIO_IO30__CAN5_TX 0x0088 0x028C 0x0000 0x02 0x00 271 271 + #define IMX95_PAD_GPIO_IO30__FLEXIO1_FLEXIO_BIT30 0x0088 0x028C 0x0460 0x07 0x01 272 272 + 273 273 + #define IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x008C 0x0290 0x0000 0x00 0x00 274 274 + #define IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x008C 0x0290 0x0508 0x11 0x01 275 275 + #define IMX95_PAD_GPIO_IO31__CAN5_RX 0x008C 0x0290 0x0450 0x02 0x01 276 276 + #define IMX95_PAD_GPIO_IO31__FLEXIO1_FLEXIO_BIT31 0x008C 0x0290 0x0464 0x07 0x01 277 277 + 278 278 + #define IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x0090 0x0294 0x0000 0x00 0x00 279 279 + #define IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x0090 0x0294 0x0000 0x01 0x00 280 280 + #define IMX95_PAD_GPIO_IO32__LPUART6_TX 0x0090 0x0294 0x0580 0x02 0x00 281 281 + #define IMX95_PAD_GPIO_IO32__LPSPI4_PCS2 0x0090 0x0294 0x0538 0x04 0x00 282 282 + 283 283 + #define IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x0094 0x0298 0x0000 0x00 0x00 284 284 + #define IMX95_PAD_GPIO_IO33__LPUART6_RX 0x0094 0x0298 0x057C 0x02 0x00 285 285 + #define IMX95_PAD_GPIO_IO33__LPSPI4_PCS1 0x0094 0x0298 0x0534 0x04 0x00 286 286 + 287 287 + #define IMX95_PAD_GPIO_IO34__GPIO5_IO_BIT14 0x0098 0x029C 0x0000 0x00 0x00 288 288 + #define IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x0098 0x029C 0x0578 0x02 0x00 289 289 + #define IMX95_PAD_GPIO_IO34__LPSPI4_PCS0 0x0098 0x029C 0x0530 0x04 0x00 290 290 + 291 291 + #define IMX95_PAD_GPIO_IO35__GPIO5_IO_BIT15 0x009C 0x02A0 0x0000 0x00 0x00 292 292 + #define IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x009C 0x02A0 0x0000 0x01 0x00 293 293 + #define IMX95_PAD_GPIO_IO35__LPUART6_RTS_B 0x009C 0x02A0 0x0000 0x02 0x00 294 294 + #define IMX95_PAD_GPIO_IO35__LPSPI4_SIN 0x009C 0x02A0 0x0540 0x04 0x00 295 295 + 296 296 + #define IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x00A0 0x02A4 0x0544 0x04 0x00 297 297 + #define IMX95_PAD_GPIO_IO36__GPIO5_IO_BIT16 0x00A0 0x02A4 0x0000 0x00 0x00 298 298 + #define IMX95_PAD_GPIO_IO36__LPUART7_TX 0x00A0 0x02A4 0x0588 0x02 0x00 299 299 + 300 300 + #define IMX95_PAD_GPIO_IO37__GPIO5_IO_BIT17 0x00A4 0x02A8 0x0000 0x00 0x00 301 301 + #define IMX95_PAD_GPIO_IO37__LPUART7_RX 0x00A4 0x02A8 0x0584 0x02 0x00 302 302 + #define IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x00A4 0x02A8 0x053C 0x04 0x00 303 303 + 304 304 + #define IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x00A8 0x02AC 0x0000 0x00 0x00 305 305 + #define IMX95_PAD_CCM_CLKO1__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x00A8 0x02AC 0x0434 0x01 0x00 306 306 + #define IMX95_PAD_CCM_CLKO1__FLEXIO1_FLEXIO_BIT26 0x00A8 0x02AC 0x0458 0x04 0x00 307 307 + #define IMX95_PAD_CCM_CLKO1__GPIO3_IO_BIT26 0x00A8 0x02AC 0x0000 0x05 0x00 308 308 + 309 309 + #define IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x00AC 0x02B0 0x0000 0x05 0x00 310 310 + #define IMX95_PAD_CCM_CLKO2__CCMSRCGPCMIX_TOP_CLKO_2 0x00AC 0x02B0 0x0000 0x00 0x00 311 311 + #define IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x00AC 0x02B0 0x0000 0x01 0x00 312 312 + #define IMX95_PAD_CCM_CLKO2__FLEXIO1_FLEXIO_BIT27 0x00AC 0x02B0 0x045C 0x04 0x00 313 313 + 314 314 + #define IMX95_PAD_CCM_CLKO3__CCMSRCGPCMIX_TOP_CLKO_3 0x00B0 0x02B4 0x0000 0x00 0x00 315 315 + #define IMX95_PAD_CCM_CLKO3__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x00B0 0x02B4 0x0438 0x01 0x00 316 316 + #define IMX95_PAD_CCM_CLKO3__CAN3_TX 0x00B0 0x02B4 0x0000 0x02 0x00 317 317 + #define IMX95_PAD_CCM_CLKO3__FLEXIO2_FLEXIO_BIT28 0x00B0 0x02B4 0x0000 0x04 0x00 318 318 + #define IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x00B0 0x02B4 0x0000 0x05 0x00 319 319 + 320 320 + #define IMX95_PAD_CCM_CLKO4__CCMSRCGPCMIX_TOP_CLKO_4 0x00B4 0x02B8 0x0000 0x00 0x00 321 321 + #define IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x00B4 0x02B8 0x0000 0x01 0x00 322 322 + #define IMX95_PAD_CCM_CLKO4__CAN3_RX 0x00B4 0x02B8 0x0448 0x02 0x00 323 323 + #define IMX95_PAD_CCM_CLKO4__FLEXIO2_FLEXIO_BIT29 0x00B4 0x02B8 0x0000 0x04 0x00 324 324 + #define IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x00B4 0x02B8 0x0000 0x05 0x00 325 325 + 326 326 + #define IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x00B8 0x02BC 0x0424 0x00 0x00 327 327 + #define IMX95_PAD_ENET1_MDC__LPUART3_DCD_B 0x00B8 0x02BC 0x0000 0x01 0x00 328 328 + #define IMX95_PAD_ENET1_MDC__I3C2_SCL 0x00B8 0x02BC 0x04F8 0x02 0x00 329 329 + #define IMX95_PAD_ENET1_MDC__HSIOMIX_TOP_USB1_OTG_ID 0x00B8 0x02BC 0x0000 0x03 0x00 330 330 + #define IMX95_PAD_ENET1_MDC__FLEXIO2_FLEXIO_BIT0 0x00B8 0x02BC 0x0000 0x04 0x00 331 331 + #define IMX95_PAD_ENET1_MDC__GPIO4_IO_BIT0 0x00B8 0x02BC 0x0000 0x05 0x00 332 332 + 333 333 + #define IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x00BC 0x02C0 0x0428 0x00 0x00 334 334 + #define IMX95_PAD_ENET1_MDIO__LPUART3_RIN_B 0x00BC 0x02C0 0x0000 0x01 0x00 335 335 + #define IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x00BC 0x02C0 0x04FC 0x02 0x00 336 336 + #define IMX95_PAD_ENET1_MDIO__HSIOMIX_TOP_USB1_OTG_PWR 0x00BC 0x02C0 0x0000 0x03 0x00 337 337 + #define IMX95_PAD_ENET1_MDIO__FLEXIO2_FLEXIO_BIT1 0x00BC 0x02C0 0x0000 0x04 0x00 338 338 + #define IMX95_PAD_ENET1_MDIO__GPIO4_IO_BIT1 0x00BC 0x02C0 0x0000 0x05 0x00 339 339 + 340 340 + #define IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x00C0 0x02C4 0x0000 0x00 0x00 341 341 + #define IMX95_PAD_ENET1_TD3__CAN2_TX 0x00C0 0x02C4 0x0000 0x02 0x00 342 342 + #define IMX95_PAD_ENET1_TD3__HSIOMIX_TOP_USB2_OTG_ID 0x00C0 0x02C4 0x0000 0x03 0x00 343 343 + #define IMX95_PAD_ENET1_TD3__FLEXIO2_FLEXIO_BIT2 0x00C0 0x02C4 0x0000 0x04 0x00 344 344 + #define IMX95_PAD_ENET1_TD3__GPIO4_IO_BIT2 0x00C0 0x02C4 0x0000 0x05 0x00 345 345 + 346 346 + #define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x00C4 0x02C8 0x0000 0x00 0x00 347 347 + #define IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RMII_REF50_CLK 0x00C4 0x02C8 0x0000 0x01 0x00 348 348 + #define IMX95_PAD_ENET1_TD2__CAN2_RX 0x00C4 0x02C8 0x0444 0x02 0x01 349 349 + #define IMX95_PAD_ENET1_TD2__HSIOMIX_TOP_USB2_OTG_OC 0x00C4 0x02C8 0x0000 0x03 0x00 350 350 + #define IMX95_PAD_ENET1_TD2__FLEXIO2_FLEXIO_BIT3 0x00C4 0x02C8 0x0000 0x04 0x00 351 351 + #define IMX95_PAD_ENET1_TD2__GPIO4_IO_BIT3 0x00C4 0x02C8 0x0000 0x05 0x00 352 352 + 353 353 + #define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x00C8 0x02CC 0x0000 0x00 0x00 354 354 + #define IMX95_PAD_ENET1_TD1__LPUART3_RTS_B 0x00C8 0x02CC 0x0000 0x01 0x00 355 355 + #define IMX95_PAD_ENET1_TD1__I3C2_PUR 0x00C8 0x02CC 0x0000 0x02 0x00 356 356 + #define IMX95_PAD_ENET1_TD1__HSIOMIX_TOP_USB1_OTG_OC 0x00C8 0x02CC 0x0000 0x03 0x00 357 357 + #define IMX95_PAD_ENET1_TD1__FLEXIO2_FLEXIO_BIT4 0x00C8 0x02CC 0x0000 0x04 0x00 358 358 + #define IMX95_PAD_ENET1_TD1__GPIO4_IO_BIT4 0x00C8 0x02CC 0x0000 0x05 0x00 359 359 + #define IMX95_PAD_ENET1_TD1__I3C2_PUR_B 0x00C8 0x02CC 0x0000 0x06 0x00 360 360 + #define IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RMII_TXD1 0x00C8 0x02CC 0x0000 0x07 0x00 361 361 + 362 362 + #define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x00CC 0x02D0 0x0000 0x00 0x00 363 363 + #define IMX95_PAD_ENET1_TD0__LPUART3_TX 0x00CC 0x02D0 0x055C 0x01 0x00 364 364 + #define IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RMII_TXD0 0x00CC 0x02D0 0x0000 0x02 0x00 365 365 + #define IMX95_PAD_ENET1_TD0__FLEXIO2_FLEXIO_BIT5 0x00CC 0x02D0 0x0000 0x04 0x00 366 366 + #define IMX95_PAD_ENET1_TD0__GPIO4_IO_BIT5 0x00CC 0x02D0 0x0000 0x05 0x00 367 367 + 368 368 + #define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x00D0 0x02D4 0x0000 0x00 0x00 369 369 + #define IMX95_PAD_ENET1_TX_CTL__LPUART3_DTR_B 0x00D0 0x02D4 0x0000 0x01 0x00 370 370 + #define IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RMII_TX_EN 0x00D0 0x02D4 0x0000 0x02 0x00 371 371 + #define IMX95_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO_BIT6 0x00D0 0x02D4 0x0000 0x04 0x00 372 372 + #define IMX95_PAD_ENET1_TX_CTL__GPIO4_IO_BIT6 0x00D0 0x02D4 0x0000 0x05 0x00 373 373 + 374 374 + #define IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x00D4 0x02D8 0x0000 0x00 0x00 375 375 + #define IMX95_PAD_ENET1_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x00D4 0x02D8 0x0000 0x01 0x00 376 376 + #define IMX95_PAD_ENET1_TXC__FLEXIO2_FLEXIO_BIT7 0x00D4 0x02D8 0x0000 0x04 0x00 377 377 + #define IMX95_PAD_ENET1_TXC__GPIO4_IO_BIT7 0x00D4 0x02D8 0x0000 0x05 0x00 378 378 + 379 379 + #define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x00D8 0x02DC 0x0000 0x00 0x00 380 380 + #define IMX95_PAD_ENET1_RX_CTL__LPUART3_DSR_B 0x00D8 0x02DC 0x0000 0x01 0x00 381 381 + #define IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RMII_CRS_DV 0x00D8 0x02DC 0x0000 0x02 0x00 382 382 + #define IMX95_PAD_ENET1_RX_CTL__HSIOMIX_TOP_USB2_OTG_PWR 0x00D8 0x02DC 0x0000 0x03 0x00 383 383 + #define IMX95_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO_BIT8 0x00D8 0x02DC 0x0000 0x04 0x00 384 384 + #define IMX95_PAD_ENET1_RX_CTL__GPIO4_IO_BIT8 0x00D8 0x02DC 0x0000 0x05 0x00 385 385 + 386 386 + #define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x00DC 0x02E0 0x0000 0x00 0x00 387 387 + #define IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00DC 0x02E0 0x042C 0x01 0x00 388 388 + #define IMX95_PAD_ENET1_RXC__FLEXIO2_FLEXIO_BIT9 0x00DC 0x02E0 0x0000 0x04 0x00 389 389 + #define IMX95_PAD_ENET1_RXC__GPIO4_IO_BIT9 0x00DC 0x02E0 0x0000 0x05 0x00 390 390 + 391 391 + #define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x00E0 0x02E4 0x0000 0x00 0x00 392 392 + #define IMX95_PAD_ENET1_RD0__LPUART3_RX 0x00E0 0x02E4 0x0558 0x01 0x00 393 393 + #define IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RMII_RXD0 0x00E0 0x02E4 0x0000 0x02 0x00 394 394 + #define IMX95_PAD_ENET1_RD0__FLEXIO2_FLEXIO_BIT10 0x00E0 0x02E4 0x0000 0x04 0x00 395 395 + #define IMX95_PAD_ENET1_RD0__GPIO4_IO_BIT10 0x00E0 0x02E4 0x0000 0x05 0x00 396 396 + 397 397 + #define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x00E4 0x02E8 0x0000 0x00 0x00 398 398 + #define IMX95_PAD_ENET1_RD1__LPUART3_CTS_B 0x00E4 0x02E8 0x0554 0x01 0x00 399 399 + #define IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RMII_RXD1 0x00E4 0x02E8 0x0000 0x02 0x00 400 400 + #define IMX95_PAD_ENET1_RD1__LPTMR2_ALT1 0x00E4 0x02E8 0x0548 0x03 0x00 401 401 + #define IMX95_PAD_ENET1_RD1__FLEXIO2_FLEXIO_BIT11 0x00E4 0x02E8 0x0000 0x04 0x00 402 402 + #define IMX95_PAD_ENET1_RD1__GPIO4_IO_BIT11 0x00E4 0x02E8 0x0000 0x05 0x00 403 403 + 404 404 + #define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x00E8 0x02EC 0x0000 0x00 0x00 405 405 + #define IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RMII_RX_ER 0x00E8 0x02EC 0x042C 0x02 0x01 406 406 + #define IMX95_PAD_ENET1_RD2__LPTMR2_ALT2 0x00E8 0x02EC 0x054C 0x03 0x00 407 407 + #define IMX95_PAD_ENET1_RD2__FLEXIO2_FLEXIO_BIT12 0x00E8 0x02EC 0x0000 0x04 0x00 408 408 + #define IMX95_PAD_ENET1_RD2__GPIO4_IO_BIT12 0x00E8 0x02EC 0x0000 0x05 0x00 409 409 + 410 410 + #define IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x00EC 0x02F0 0x0000 0x00 0x00 411 411 + #define IMX95_PAD_ENET1_RD3__LPTMR2_ALT3 0x00EC 0x02F0 0x0550 0x03 0x00 412 412 + #define IMX95_PAD_ENET1_RD3__FLEXIO2_FLEXIO_BIT13 0x00EC 0x02F0 0x0000 0x04 0x00 413 413 + #define IMX95_PAD_ENET1_RD3__GPIO4_IO_BIT13 0x00EC 0x02F0 0x0000 0x05 0x00 414 414 + 415 415 + #define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x00F0 0x02F4 0x0424 0x00 0x01 416 416 + #define IMX95_PAD_ENET2_MDC__LPUART4_DCD_B 0x00F0 0x02F4 0x0000 0x01 0x00 417 417 + #define IMX95_PAD_ENET2_MDC__NETCMIX_TOP_SAI2_RX_SYNC 0x00F0 0x02F4 0x0000 0x02 0x00 418 418 + #define IMX95_PAD_ENET2_MDC__FLEXIO2_FLEXIO_BIT14 0x00F0 0x02F4 0x0000 0x04 0x00 419 419 + #define IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x00F0 0x02F4 0x0000 0x05 0x00 420 420 + 421 421 + #define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x00F4 0x02F8 0x0428 0x00 0x01 422 422 + #define IMX95_PAD_ENET2_MDIO__LPUART4_RIN_B 0x00F4 0x02F8 0x0000 0x01 0x00 423 423 + #define IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_SAI2_RX_BCLK 0x00F4 0x02F8 0x0000 0x02 0x00 424 424 + #define IMX95_PAD_ENET2_MDIO__FLEXIO2_FLEXIO_BIT15 0x00F4 0x02F8 0x0000 0x04 0x00 425 425 + #define IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x00F4 0x02F8 0x0000 0x05 0x00 426 426 + 427 427 + #define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_SAI2_RX_DATA_BIT0 0x00F8 0x02FC 0x0000 0x02 0x00 428 428 + #define IMX95_PAD_ENET2_TD3__FLEXIO2_FLEXIO_BIT16 0x00F8 0x02FC 0x0000 0x04 0x00 429 429 + #define IMX95_PAD_ENET2_TD3__GPIO4_IO_BIT16 0x00F8 0x02FC 0x0000 0x05 0x00 430 430 + #define IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x00F8 0x02FC 0x0000 0x00 0x00 431 431 + 432 432 + #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x00FC 0x0300 0x0000 0x00 0x00 433 433 + #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RMII_REF50_CLK 0x00FC 0x0300 0x0000 0x01 0x00 434 434 + #define IMX95_PAD_ENET2_TD2__NETCMIX_TOP_SAI2_RX_DATA_BIT1 0x00FC 0x0300 0x0000 0x02 0x00 435 435 + #define IMX95_PAD_ENET2_TD2__SAI4_TX_SYNC 0x00FC 0x0300 0x05A4 0x03 0x00 436 436 + #define IMX95_PAD_ENET2_TD2__FLEXIO2_FLEXIO_BIT17 0x00FC 0x0300 0x0000 0x04 0x00 437 437 + #define IMX95_PAD_ENET2_TD2__GPIO4_IO_BIT17 0x00FC 0x0300 0x0000 0x05 0x00 438 438 + 439 439 + #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x0100 0x0304 0x0000 0x00 0x00 440 440 + #define IMX95_PAD_ENET2_TD1__LPUART4_RTS_B 0x0100 0x0304 0x0000 0x01 0x00 441 441 + #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_SAI2_RX_DATA_BIT2 0x0100 0x0304 0x0000 0x02 0x00 442 442 + #define IMX95_PAD_ENET2_TD1__SAI4_TX_BCLK 0x0100 0x0304 0x05A0 0x03 0x00 443 443 + #define IMX95_PAD_ENET2_TD1__FLEXIO2_FLEXIO_BIT18 0x0100 0x0304 0x0000 0x04 0x00 444 444 + #define IMX95_PAD_ENET2_TD1__GPIO4_IO_BIT18 0x0100 0x0304 0x0000 0x05 0x00 445 445 + #define IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RMII_TXD1 0x0100 0x0304 0x0000 0x06 0x00 446 446 + 447 447 + #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x0104 0x0308 0x0000 0x00 0x00 448 448 + #define IMX95_PAD_ENET2_TD0__LPUART4_TX 0x0104 0x0308 0x0568 0x01 0x00 449 449 + #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_SAI2_RX_DATA_BIT3 0x0104 0x0308 0x0000 0x02 0x00 450 450 + #define IMX95_PAD_ENET2_TD0__SAI4_TX_DATA_BIT0 0x0104 0x0308 0x0000 0x03 0x00 451 451 + #define IMX95_PAD_ENET2_TD0__FLEXIO2_FLEXIO_BIT19 0x0104 0x0308 0x0000 0x04 0x00 452 452 + #define IMX95_PAD_ENET2_TD0__GPIO4_IO_BIT19 0x0104 0x0308 0x0000 0x05 0x00 453 453 + #define IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RMII_TXD0 0x0104 0x0308 0x0000 0x06 0x00 454 454 + 455 455 + #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x0108 0x030C 0x0000 0x00 0x00 456 456 + #define IMX95_PAD_ENET2_TX_CTL__LPUART4_DTR_B 0x0108 0x030C 0x0000 0x01 0x00 457 457 + #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_SAI2_TX_SYNC 0x0108 0x030C 0x0000 0x02 0x00 458 458 + #define IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RMII_TX_EN 0x0108 0x030C 0x0000 0x03 0x00 459 459 + #define IMX95_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO_BIT20 0x0108 0x030C 0x0000 0x04 0x00 460 460 + #define IMX95_PAD_ENET2_TX_CTL__GPIO4_IO_BIT20 0x0108 0x030C 0x0000 0x05 0x00 461 461 + 462 462 + #define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x010C 0x0310 0x0000 0x00 0x00 463 463 + #define IMX95_PAD_ENET2_TXC__CCMSRCGPCMIX_TOP_ENET_CLK_ROOT 0x010C 0x0310 0x0000 0x01 0x00 464 464 + #define IMX95_PAD_ENET2_TXC__NETCMIX_TOP_SAI2_TX_BCLK 0x010C 0x0310 0x0000 0x02 0x00 465 465 + #define IMX95_PAD_ENET2_TXC__FLEXIO2_FLEXIO_BIT21 0x010C 0x0310 0x0000 0x04 0x00 466 466 + #define IMX95_PAD_ENET2_TXC__GPIO4_IO_BIT21 0x010C 0x0310 0x0000 0x05 0x00 467 467 + 468 468 + #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x0110 0x0314 0x0000 0x00 0x00 469 469 + #define IMX95_PAD_ENET2_RX_CTL__LPUART4_DSR_B 0x0110 0x0314 0x0000 0x01 0x00 470 470 + #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_SAI2_TX_DATA_BIT0 0x0110 0x0314 0x0000 0x02 0x00 471 471 + #define IMX95_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO_BIT22 0x0110 0x0314 0x0000 0x04 0x00 472 472 + #define IMX95_PAD_ENET2_RX_CTL__GPIO4_IO_BIT22 0x0110 0x0314 0x0000 0x05 0x00 473 473 + #define IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RMII_CRS_DV 0x0110 0x0314 0x0000 0x06 0x00 474 474 + 475 475 + #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x0114 0x0318 0x0000 0x00 0x00 476 476 + #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0114 0x0318 0x0430 0x01 0x00 477 477 + #define IMX95_PAD_ENET2_RXC__NETCMIX_TOP_SAI2_TX_DATA_BIT1 0x0114 0x0318 0x0000 0x02 0x00 478 478 + #define IMX95_PAD_ENET2_RXC__SAI4_RX_SYNC 0x0114 0x0318 0x059C 0x03 0x00 479 479 + #define IMX95_PAD_ENET2_RXC__FLEXIO2_FLEXIO_BIT23 0x0114 0x0318 0x0000 0x04 0x00 480 480 + #define IMX95_PAD_ENET2_RXC__GPIO4_IO_BIT23 0x0114 0x0318 0x0000 0x05 0x00 481 481 + 482 482 + #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x0118 0x031C 0x0000 0x00 0x00 483 483 + #define IMX95_PAD_ENET2_RD0__LPUART4_RX 0x0118 0x031C 0x0564 0x01 0x00 484 484 + #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_SAI2_TX_DATA_BIT2 0x0118 0x031C 0x0000 0x02 0x00 485 485 + #define IMX95_PAD_ENET2_RD0__SAI4_RX_BCLK 0x0118 0x031C 0x0594 0x03 0x00 486 486 + #define IMX95_PAD_ENET2_RD0__FLEXIO2_FLEXIO_BIT24 0x0118 0x031C 0x0000 0x04 0x00 487 487 + #define IMX95_PAD_ENET2_RD0__GPIO4_IO_BIT24 0x0118 0x031C 0x0000 0x05 0x00 488 488 + #define IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RMII_RXD0 0x0118 0x031C 0x0000 0x06 0x00 489 489 + 490 490 + #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x011C 0x0320 0x0000 0x00 0x00 491 491 + #define IMX95_PAD_ENET2_RD1__SPDIF_IN 0x011C 0x0320 0x0454 0x01 0x00 492 492 + #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_SAI2_TX_DATA_BIT3 0x011C 0x0320 0x0000 0x02 0x00 493 493 + #define IMX95_PAD_ENET2_RD1__SAI4_RX_DATA_BIT0 0x011C 0x0320 0x0598 0x03 0x00 494 494 + #define IMX95_PAD_ENET2_RD1__FLEXIO2_FLEXIO_BIT25 0x011C 0x0320 0x0000 0x04 0x00 495 495 + #define IMX95_PAD_ENET2_RD1__GPIO4_IO_BIT25 0x011C 0x0320 0x0000 0x05 0x00 496 496 + #define IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RMII_RXD1 0x011C 0x0320 0x0000 0x06 0x00 497 497 + 498 498 + #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x0120 0x0324 0x0000 0x00 0x00 499 499 + #define IMX95_PAD_ENET2_RD2__LPUART4_CTS_B 0x0120 0x0324 0x0560 0x01 0x00 500 500 + #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_SAI2_MCLK 0x0120 0x0324 0x0000 0x02 0x00 501 501 + #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_MQS2_RIGHT 0x0120 0x0324 0x0000 0x03 0x00 502 502 + #define IMX95_PAD_ENET2_RD2__FLEXIO2_FLEXIO_BIT26 0x0120 0x0324 0x0000 0x04 0x00 503 503 + #define IMX95_PAD_ENET2_RD2__GPIO4_IO_BIT26 0x0120 0x0324 0x0000 0x05 0x00 504 504 + #define IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RMII_RX_ER 0x0120 0x0324 0x0430 0x06 0x01 505 505 + 506 506 + #define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x0124 0x0328 0x0000 0x00 0x00 507 507 + #define IMX95_PAD_ENET2_RD3__SPDIF_OUT 0x0124 0x0328 0x0000 0x01 0x00 508 508 + #define IMX95_PAD_ENET2_RD3__SPDIF_IN 0x0124 0x0328 0x0454 0x02 0x01 509 509 + #define IMX95_PAD_ENET2_RD3__NETCMIX_TOP_MQS2_LEFT 0x0124 0x0328 0x0000 0x03 0x00 510 510 + #define IMX95_PAD_ENET2_RD3__FLEXIO2_FLEXIO_BIT27 0x0124 0x0328 0x0000 0x04 0x00 511 511 + #define IMX95_PAD_ENET2_RD3__GPIO4_IO_BIT27 0x0124 0x0328 0x0000 0x05 0x00 512 512 + 513 513 + #define IMX95_PAD_SD1_CLK__FLEXIO1_FLEXIO_BIT8 0x0128 0x032C 0x0488 0x04 0x01 514 514 + #define IMX95_PAD_SD1_CLK__GPIO3_IO_BIT8 0x0128 0x032C 0x0000 0x05 0x00 515 515 + #define IMX95_PAD_SD1_CLK__USDHC1_CLK 0x0128 0x032C 0x0000 0x00 0x00 516 516 + 517 517 + #define IMX95_PAD_SD1_CMD__USDHC1_CMD 0x012C 0x0330 0x0000 0x00 0x00 518 518 + #define IMX95_PAD_SD1_CMD__FLEXIO1_FLEXIO_BIT9 0x012C 0x0330 0x048C 0x04 0x01 519 519 + #define IMX95_PAD_SD1_CMD__GPIO3_IO_BIT9 0x012C 0x0330 0x0000 0x05 0x00 520 520 + 521 521 + #define IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x0130 0x0334 0x0000 0x00 0x00 522 522 + #define IMX95_PAD_SD1_DATA0__FLEXIO1_FLEXIO_BIT10 0x0130 0x0334 0x0490 0x04 0x01 523 523 + #define IMX95_PAD_SD1_DATA0__GPIO3_IO_BIT10 0x0130 0x0334 0x0000 0x05 0x00 524 524 + 525 525 + #define IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x0134 0x0338 0x0000 0x00 0x00 526 526 + #define IMX95_PAD_SD1_DATA1__FLEXIO1_FLEXIO_BIT11 0x0134 0x0338 0x0494 0x04 0x01 527 527 + #define IMX95_PAD_SD1_DATA1__GPIO3_IO_BIT11 0x0134 0x0338 0x0000 0x05 0x00 528 528 + 529 529 + #define IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x0138 0x033C 0x0000 0x00 0x00 530 530 + #define IMX95_PAD_SD1_DATA2__FLEXIO1_FLEXIO_BIT12 0x0138 0x033C 0x0498 0x04 0x01 531 531 + #define IMX95_PAD_SD1_DATA2__GPIO3_IO_BIT12 0x0138 0x033C 0x0000 0x05 0x00 532 532 + #define IMX95_PAD_SD1_DATA2__CCMSRCGPCMIX_TOP_PMIC_READY 0x0138 0x033C 0x0000 0x06 0x00 533 533 + 534 534 + #define IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x013C 0x0340 0x0000 0x00 0x00 535 535 + #define IMX95_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B 0x013C 0x0340 0x0000 0x01 0x00 536 536 + #define IMX95_PAD_SD1_DATA3__FLEXIO1_FLEXIO_BIT13 0x013C 0x0340 0x049C 0x04 0x01 537 537 + #define IMX95_PAD_SD1_DATA3__GPIO3_IO_BIT13 0x013C 0x0340 0x0000 0x05 0x00 538 538 + 539 539 + #define IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x0140 0x0344 0x0000 0x00 0x00 540 540 + #define IMX95_PAD_SD1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0140 0x0344 0x04E4 0x01 0x00 541 541 + #define IMX95_PAD_SD1_DATA4__FLEXIO1_FLEXIO_BIT14 0x0140 0x0344 0x04A0 0x04 0x01 542 542 + #define IMX95_PAD_SD1_DATA4__GPIO3_IO_BIT14 0x0140 0x0344 0x0000 0x05 0x00 543 543 + #define IMX95_PAD_SD1_DATA4__XSPI_DATA_BIT4 0x0140 0x0344 0x05FC 0x06 0x00 544 544 + 545 545 + #define IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x0144 0x0348 0x0000 0x00 0x00 546 546 + #define IMX95_PAD_SD1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0144 0x0348 0x04E8 0x01 0x00 547 547 + #define IMX95_PAD_SD1_DATA5__USDHC1_RESET_B 0x0144 0x0348 0x0000 0x02 0x00 548 548 + #define IMX95_PAD_SD1_DATA5__FLEXIO1_FLEXIO_BIT15 0x0144 0x0348 0x04A4 0x04 0x01 549 549 + #define IMX95_PAD_SD1_DATA5__GPIO3_IO_BIT15 0x0144 0x0348 0x0000 0x05 0x00 550 550 + #define IMX95_PAD_SD1_DATA5__XSPI_DATA_BIT5 0x0144 0x0348 0x0600 0x06 0x00 551 551 + 552 552 + #define IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x0148 0x034C 0x0000 0x00 0x00 553 553 + #define IMX95_PAD_SD1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0148 0x034C 0x04EC 0x01 0x00 554 554 + #define IMX95_PAD_SD1_DATA6__USDHC1_CD_B 0x0148 0x034C 0x0000 0x02 0x00 555 555 + #define IMX95_PAD_SD1_DATA6__FLEXIO1_FLEXIO_BIT16 0x0148 0x034C 0x04A8 0x04 0x01 556 556 + #define IMX95_PAD_SD1_DATA6__GPIO3_IO_BIT16 0x0148 0x034C 0x0000 0x05 0x00 557 557 + #define IMX95_PAD_SD1_DATA6__XSPI_DATA_BIT6 0x0148 0x034C 0x0604 0x06 0x00 558 558 + 559 559 + #define IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x014C 0x0350 0x0000 0x00 0x00 560 560 + #define IMX95_PAD_SD1_DATA7__FLEXSPI1_A_DATA_BIT7 0x014C 0x0350 0x04F0 0x01 0x00 561 561 + #define IMX95_PAD_SD1_DATA7__USDHC1_WP 0x014C 0x0350 0x0000 0x02 0x00 562 562 + #define IMX95_PAD_SD1_DATA7__FLEXIO1_FLEXIO_BIT17 0x014C 0x0350 0x04AC 0x04 0x01 563 563 + #define IMX95_PAD_SD1_DATA7__GPIO3_IO_BIT17 0x014C 0x0350 0x0000 0x05 0x00 564 564 + #define IMX95_PAD_SD1_DATA7__XSPI_DATA_BIT7 0x014C 0x0350 0x0608 0x06 0x00 565 565 + 566 566 + #define IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x0150 0x0354 0x0000 0x00 0x00 567 567 + #define IMX95_PAD_SD1_STROBE__FLEXSPI1_A_DQS 0x0150 0x0354 0x04D0 0x01 0x00 568 568 + #define IMX95_PAD_SD1_STROBE__FLEXIO1_FLEXIO_BIT18 0x0150 0x0354 0x04B0 0x04 0x01 569 569 + #define IMX95_PAD_SD1_STROBE__GPIO3_IO_BIT18 0x0150 0x0354 0x0000 0x05 0x00 570 570 + #define IMX95_PAD_SD1_STROBE__XSPI_DQS 0x0150 0x0354 0x05E4 0x06 0x00 571 571 + 572 572 + #define IMX95_PAD_SD2_VSELECT__USDHC2_VSELECT 0x0154 0x0358 0x0000 0x00 0x00 573 573 + #define IMX95_PAD_SD2_VSELECT__USDHC2_WP 0x0154 0x0358 0x0000 0x01 0x00 574 574 + #define IMX95_PAD_SD2_VSELECT__LPTMR2_ALT3 0x0154 0x0358 0x0550 0x02 0x01 575 575 + #define IMX95_PAD_SD2_VSELECT__FLEXIO1_FLEXIO_BIT19 0x0154 0x0358 0x04B4 0x04 0x01 576 576 + #define IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x0154 0x0358 0x0000 0x05 0x00 577 577 + #define IMX95_PAD_SD2_VSELECT__CCMSRCGPCMIX_TOP_EXT_CLK1 0x0154 0x0358 0x0420 0x06 0x01 578 578 + 579 579 + #define IMX95_PAD_SD3_CLK__USDHC3_CLK 0x0158 0x035C 0x05C8 0x00 0x01 580 580 + #define IMX95_PAD_SD3_CLK__FLEXSPI1_A_SCLK 0x0158 0x035C 0x04F4 0x01 0x00 581 581 + #define IMX95_PAD_SD3_CLK__SAI5_TX_DATA_BIT1 0x0158 0x035C 0x0000 0x02 0x00 582 582 + #define IMX95_PAD_SD3_CLK__SAI5_RX_DATA_BIT0 0x0158 0x035C 0x05AC 0x03 0x00 583 583 + #define IMX95_PAD_SD3_CLK__FLEXIO1_FLEXIO_BIT20 0x0158 0x035C 0x04B8 0x04 0x01 584 584 + #define IMX95_PAD_SD3_CLK__GPIO3_IO_BIT20 0x0158 0x035C 0x0000 0x05 0x00 585 585 + #define IMX95_PAD_SD3_CLK__XSPI_CLK 0x0158 0x035C 0x05E8 0x06 0x00 586 586 + 587 587 + #define IMX95_PAD_SD3_CMD__USDHC3_CMD 0x015C 0x0360 0x05CC 0x00 0x01 588 588 + #define IMX95_PAD_SD3_CMD__FLEXSPI1_A_SS0_B 0x015C 0x0360 0x0000 0x01 0x00 589 589 + #define IMX95_PAD_SD3_CMD__SAI5_TX_DATA_BIT2 0x015C 0x0360 0x0000 0x02 0x00 590 590 + #define IMX95_PAD_SD3_CMD__SAI5_RX_SYNC 0x015C 0x0360 0x05BC 0x03 0x00 591 591 + #define IMX95_PAD_SD3_CMD__FLEXIO1_FLEXIO_BIT21 0x015C 0x0360 0x04BC 0x04 0x01 592 592 + #define IMX95_PAD_SD3_CMD__GPIO3_IO_BIT21 0x015C 0x0360 0x0000 0x05 0x00 593 593 + #define IMX95_PAD_SD3_CMD__XSPI_CS 0x015C 0x0360 0x05E0 0x06 0x00 594 594 + 595 595 + #define IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x0160 0x0364 0x05D0 0x00 0x01 596 596 + #define IMX95_PAD_SD3_DATA0__FLEXSPI1_A_DATA_BIT0 0x0160 0x0364 0x04D4 0x01 0x00 597 597 + #define IMX95_PAD_SD3_DATA0__SAI5_TX_DATA_BIT3 0x0160 0x0364 0x0000 0x02 0x00 598 598 + #define IMX95_PAD_SD3_DATA0__SAI5_RX_BCLK 0x0160 0x0364 0x05A8 0x03 0x00 599 599 + #define IMX95_PAD_SD3_DATA0__FLEXIO1_FLEXIO_BIT22 0x0160 0x0364 0x04C0 0x04 0x01 600 600 + #define IMX95_PAD_SD3_DATA0__GPIO3_IO_BIT22 0x0160 0x0364 0x0000 0x05 0x00 601 601 + #define IMX95_PAD_SD3_DATA0__XSPI_DATA_BIT0 0x0160 0x0364 0x05EC 0x06 0x00 602 602 + 603 603 + #define IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x0164 0x0368 0x05D4 0x00 0x01 604 604 + #define IMX95_PAD_SD3_DATA1__FLEXSPI1_A_DATA_BIT1 0x0164 0x0368 0x04D8 0x01 0x00 605 605 + #define IMX95_PAD_SD3_DATA1__SAI5_RX_DATA_BIT1 0x0164 0x0368 0x05B0 0x02 0x00 606 606 + #define IMX95_PAD_SD3_DATA1__SAI5_TX_DATA_BIT0 0x0164 0x0368 0x0000 0x03 0x00 607 607 + #define IMX95_PAD_SD3_DATA1__FLEXIO1_FLEXIO_BIT23 0x0164 0x0368 0x04C4 0x04 0x01 608 608 + #define IMX95_PAD_SD3_DATA1__GPIO3_IO_BIT23 0x0164 0x0368 0x0000 0x05 0x00 609 609 + #define IMX95_PAD_SD3_DATA1__XSPI_DATA_BIT1 0x0164 0x0368 0x05F0 0x06 0x00 610 610 + 611 611 + #define IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x0168 0x036C 0x05D8 0x00 0x01 612 612 + #define IMX95_PAD_SD3_DATA2__FLEXSPI1_A_DATA_BIT2 0x0168 0x036C 0x04DC 0x01 0x00 613 613 + #define IMX95_PAD_SD3_DATA2__SAI5_RX_DATA_BIT2 0x0168 0x036C 0x05B4 0x02 0x00 614 614 + #define IMX95_PAD_SD3_DATA2__SAI5_TX_SYNC 0x0168 0x036C 0x05C4 0x03 0x00 615 615 + #define IMX95_PAD_SD3_DATA2__FLEXIO1_FLEXIO_BIT24 0x0168 0x036C 0x04C8 0x04 0x01 616 616 + #define IMX95_PAD_SD3_DATA2__GPIO3_IO_BIT24 0x0168 0x036C 0x0000 0x05 0x00 617 617 + #define IMX95_PAD_SD3_DATA2__XSPI_DATA_BIT2 0x0168 0x036C 0x05F4 0x06 0x00 618 618 + 619 619 + #define IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x016C 0x0370 0x05DC 0x00 0x01 620 620 + #define IMX95_PAD_SD3_DATA3__FLEXSPI1_A_DATA_BIT3 0x016C 0x0370 0x04E0 0x01 0x00 621 621 + #define IMX95_PAD_SD3_DATA3__SAI5_RX_DATA_BIT3 0x016C 0x0370 0x05B8 0x02 0x00 622 622 + #define IMX95_PAD_SD3_DATA3__SAI5_TX_BCLK 0x016C 0x0370 0x05C0 0x03 0x00 623 623 + #define IMX95_PAD_SD3_DATA3__FLEXIO1_FLEXIO_BIT25 0x016C 0x0370 0x04CC 0x04 0x01 624 624 + #define IMX95_PAD_SD3_DATA3__GPIO3_IO_BIT25 0x016C 0x0370 0x0000 0x05 0x00 625 625 + #define IMX95_PAD_SD3_DATA3__XSPI_DATA_BIT3 0x016C 0x0370 0x05F8 0x06 0x00 626 626 + 627 627 + #define IMX95_PAD_XSPI1_DATA0__FLEXSPI1_A_DATA_BIT0 0x0170 0x0374 0x04D4 0x00 0x01 628 628 + #define IMX95_PAD_XSPI1_DATA0__NETCMIX_TOP_SAI2_TX_DATA_BIT4 0x0170 0x0374 0x0000 0x01 0x00 629 629 + #define IMX95_PAD_XSPI1_DATA0__SAI4_TX_BCLK 0x0170 0x0374 0x05A0 0x02 0x01 630 630 + #define IMX95_PAD_XSPI1_DATA0__SAI4_RX_DATA_BIT1 0x0170 0x0374 0x0000 0x03 0x00 631 631 + #define IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x0170 0x0374 0x05EC 0x04 0x01 632 632 + #define IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x0170 0x0374 0x0000 0x05 0x00 633 633 + 634 634 + #define IMX95_PAD_XSPI1_DATA1__FLEXSPI1_A_DATA_BIT1 0x0174 0x0378 0x04D8 0x00 0x01 635 635 + #define IMX95_PAD_XSPI1_DATA1__NETCMIX_TOP_SAI2_TX_DATA_BIT5 0x0174 0x0378 0x0000 0x01 0x00 636 636 + #define IMX95_PAD_XSPI1_DATA1__SAI4_TX_SYNC 0x0174 0x0378 0x05A4 0x02 0x01 637 637 + #define IMX95_PAD_XSPI1_DATA1__SAI4_TX_DATA_BIT1 0x0174 0x0378 0x0000 0x03 0x00 638 638 + #define IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x0174 0x0378 0x05F0 0x04 0x01 639 639 + #define IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x0174 0x0378 0x0000 0x05 0x00 640 640 + 641 641 + #define IMX95_PAD_XSPI1_DATA2__FLEXSPI1_A_DATA_BIT2 0x0178 0x037C 0x04DC 0x00 0x01 642 642 + #define IMX95_PAD_XSPI1_DATA2__NETCMIX_TOP_SAI2_TX_DATA_BIT6 0x0178 0x037C 0x0000 0x01 0x00 643 643 + #define IMX95_PAD_XSPI1_DATA2__SAI4_TX_DATA_BIT0 0x0178 0x037C 0x0000 0x02 0x00 644 644 + #define IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x0178 0x037C 0x05F4 0x04 0x01 645 645 + #define IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x0178 0x037C 0x0000 0x05 0x00 646 646 + 647 647 + #define IMX95_PAD_XSPI1_DATA3__FLEXSPI1_A_DATA_BIT3 0x017C 0x0380 0x04E0 0x00 0x01 648 648 + #define IMX95_PAD_XSPI1_DATA3__NETCMIX_TOP_SAI2_TX_DATA_BIT7 0x017C 0x0380 0x0000 0x01 0x00 649 649 + #define IMX95_PAD_XSPI1_DATA3__SAI4_RX_DATA_BIT0 0x017C 0x0380 0x0598 0x02 0x01 650 650 + #define IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x017C 0x0380 0x05F8 0x04 0x01 651 651 + #define IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x017C 0x0380 0x0000 0x05 0x00 652 652 + 653 653 + #define IMX95_PAD_XSPI1_DATA4__FLEXSPI1_A_DATA_BIT4 0x0180 0x0384 0x04E4 0x00 0x01 654 654 + #define IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x0180 0x0384 0x0000 0x01 0x00 655 655 + #define IMX95_PAD_XSPI1_DATA4__SAI5_RX_DATA_BIT1 0x0180 0x0384 0x05B0 0x02 0x01 656 656 + #define IMX95_PAD_XSPI1_DATA4__XSPI_DATA_BIT4 0x0180 0x0384 0x05FC 0x04 0x01 657 657 + #define IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x0180 0x0384 0x0000 0x05 0x00 658 658 + 659 659 + #define IMX95_PAD_XSPI1_DATA5__FLEXSPI1_A_DATA_BIT5 0x0184 0x0388 0x04E8 0x00 0x01 660 660 + #define IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x0184 0x0388 0x05C4 0x01 0x01 661 661 + #define IMX95_PAD_XSPI1_DATA5__SAI5_RX_DATA_BIT2 0x0184 0x0388 0x05B4 0x02 0x01 662 662 + #define IMX95_PAD_XSPI1_DATA5__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0184 0x0388 0x043C 0x03 0x00 663 663 + #define IMX95_PAD_XSPI1_DATA5__XSPI_DATA_BIT5 0x0184 0x0388 0x0600 0x04 0x01 664 664 + #define IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x0184 0x0388 0x0000 0x05 0x00 665 665 + 666 666 + #define IMX95_PAD_XSPI1_DATA6__FLEXSPI1_A_DATA_BIT6 0x0188 0x038C 0x04EC 0x00 0x01 667 667 + #define IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x0188 0x038C 0x05C0 0x01 0x01 668 668 + #define IMX95_PAD_XSPI1_DATA6__SAI5_RX_DATA_BIT3 0x0188 0x038C 0x05B8 0x02 0x01 669 669 + #define IMX95_PAD_XSPI1_DATA6__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x0188 0x038C 0x0440 0x03 0x00 670 670 + #define IMX95_PAD_XSPI1_DATA6__XSPI_DATA_BIT6 0x0188 0x038C 0x0604 0x04 0x01 671 671 + #define IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x0188 0x038C 0x0000 0x05 0x00 672 672 + 673 673 + #define IMX95_PAD_XSPI1_DATA7__FLEXSPI1_A_DATA_BIT7 0x018C 0x0390 0x04F0 0x00 0x01 674 674 + #define IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x018C 0x0390 0x05AC 0x01 0x01 675 675 + #define IMX95_PAD_XSPI1_DATA7__SAI5_TX_DATA_BIT1 0x018C 0x0390 0x0000 0x02 0x00 676 676 + #define IMX95_PAD_XSPI1_DATA7__XSPI_DATA_BIT7 0x018C 0x0390 0x0608 0x04 0x01 677 677 + #define IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x018C 0x0390 0x0000 0x05 0x00 678 678 + 679 679 + #define IMX95_PAD_XSPI1_DQS__FLEXSPI1_A_DQS 0x0190 0x0394 0x04D0 0x00 0x01 680 680 + #define IMX95_PAD_XSPI1_DQS__SAI5_RX_SYNC 0x0190 0x0394 0x05BC 0x01 0x01 681 681 + #define IMX95_PAD_XSPI1_DQS__SAI5_TX_DATA_BIT2 0x0190 0x0394 0x0000 0x02 0x00 682 682 + #define IMX95_PAD_XSPI1_DQS__NETCMIX_TOP_SAI2_RX_DATA_BIT6 0x0190 0x0394 0x043C 0x03 0x01 683 683 + #define IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x0190 0x0394 0x05E4 0x04 0x01 684 684 + #define IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x0190 0x0394 0x0000 0x05 0x00 685 685 + 686 686 + #define IMX95_PAD_XSPI1_SCLK__FLEXSPI1_A_SCLK 0x0194 0x0398 0x04F4 0x00 0x01 687 687 + #define IMX95_PAD_XSPI1_SCLK__NETCMIX_TOP_SAI2_RX_DATA_BIT4 0x0194 0x0398 0x0000 0x01 0x00 688 688 + #define IMX95_PAD_XSPI1_SCLK__SAI4_RX_SYNC 0x0194 0x0398 0x059C 0x02 0x01 689 689 + #define IMX95_PAD_XSPI1_SCLK__EARC_DC_HPD_IN 0x0194 0x0398 0x0000 0x03 0x00 690 690 + #define IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x0194 0x0398 0x05E8 0x04 0x01 691 691 + #define IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x0194 0x0398 0x0000 0x05 0x00 692 692 + 693 693 + #define IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x0198 0x039C 0x0000 0x00 0x00 694 694 + #define IMX95_PAD_XSPI1_SS0_B__NETCMIX_TOP_SAI2_RX_DATA_BIT5 0x0198 0x039C 0x0000 0x01 0x00 695 695 + #define IMX95_PAD_XSPI1_SS0_B__SAI4_RX_BCLK 0x0198 0x039C 0x0594 0x02 0x01 696 696 + #define IMX95_PAD_XSPI1_SS0_B__EARC_CEC_OUT 0x0198 0x039C 0x0000 0x03 0x00 697 697 + #define IMX95_PAD_XSPI1_SS0_B__XSPI_CS 0x0198 0x039C 0x05E0 0x04 0x01 698 698 + #define IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x0198 0x039C 0x0000 0x05 0x00 699 699 + 700 700 + #define IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x019C 0x03A0 0x0000 0x00 0x00 701 701 + #define IMX95_PAD_XSPI1_SS1_B__SAI5_RX_BCLK 0x019C 0x03A0 0x05A8 0x01 0x01 702 702 + #define IMX95_PAD_XSPI1_SS1_B__SAI5_TX_DATA_BIT3 0x019C 0x03A0 0x0000 0x02 0x00 703 703 + #define IMX95_PAD_XSPI1_SS1_B__NETCMIX_TOP_SAI2_RX_DATA_BIT7 0x019C 0x03A0 0x0440 0x03 0x01 704 704 + #define IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x019C 0x03A0 0x0000 0x05 0x00 705 705 + 706 706 + #define IMX95_PAD_SD2_CD_B__USDHC2_CD_B 0x01A0 0x03A4 0x0000 0x00 0x00 707 707 + #define IMX95_PAD_SD2_CD_B__NETCMIX_TOP_NETC_TMR_1588_TRIG1 0x01A0 0x03A4 0x0434 0x01 0x01 708 708 + #define IMX95_PAD_SD2_CD_B__I3C2_SCL 0x01A0 0x03A4 0x04F8 0x02 0x01 709 709 + #define IMX95_PAD_SD2_CD_B__FLEXIO1_FLEXIO_BIT0 0x01A0 0x03A4 0x0468 0x04 0x01 710 710 + #define IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x01A0 0x03A4 0x0000 0x05 0x00 711 711 + 712 712 + #define IMX95_PAD_SD2_CLK__USDHC2_CLK 0x01A4 0x03A8 0x0000 0x00 0x00 713 713 + #define IMX95_PAD_SD2_CLK__NETCMIX_TOP_NETC_TMR_1588_PP1 0x01A4 0x03A8 0x0000 0x01 0x00 714 714 + #define IMX95_PAD_SD2_CLK__I3C2_SDA 0x01A4 0x03A8 0x04FC 0x02 0x01 715 715 + #define IMX95_PAD_SD2_CLK__FLEXIO1_FLEXIO_BIT1 0x01A4 0x03A8 0x046C 0x04 0x01 716 716 + #define IMX95_PAD_SD2_CLK__GPIO3_IO_BIT1 0x01A4 0x03A8 0x0000 0x05 0x00 717 717 + #define IMX95_PAD_SD2_CLK__CCMSRCGPCMIX_TOP_OBSERVE_0 0x01A4 0x03A8 0x0000 0x06 0x00 718 718 + 719 719 + #define IMX95_PAD_SD2_CMD__USDHC2_CMD 0x01A8 0x03AC 0x0000 0x00 0x00 720 720 + #define IMX95_PAD_SD2_CMD__NETCMIX_TOP_NETC_TMR_1588_TRIG2 0x01A8 0x03AC 0x0438 0x01 0x01 721 721 + #define IMX95_PAD_SD2_CMD__I3C2_PUR 0x01A8 0x03AC 0x0000 0x02 0x00 722 722 + #define IMX95_PAD_SD2_CMD__I3C2_PUR_B 0x01A8 0x03AC 0x0000 0x03 0x00 723 723 + #define IMX95_PAD_SD2_CMD__FLEXIO1_FLEXIO_BIT2 0x01A8 0x03AC 0x0470 0x04 0x01 724 724 + #define IMX95_PAD_SD2_CMD__GPIO3_IO_BIT2 0x01A8 0x03AC 0x0000 0x05 0x00 725 725 + #define IMX95_PAD_SD2_CMD__CCMSRCGPCMIX_TOP_OBSERVE_1 0x01A8 0x03AC 0x0000 0x06 0x00 726 726 + 727 727 + #define IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x01AC 0x03B0 0x0000 0x00 0x00 728 728 + #define IMX95_PAD_SD2_DATA0__NETCMIX_TOP_NETC_TMR_1588_PP2 0x01AC 0x03B0 0x0000 0x01 0x00 729 729 + #define IMX95_PAD_SD2_DATA0__CAN2_TX 0x01AC 0x03B0 0x0000 0x02 0x00 730 730 + #define IMX95_PAD_SD2_DATA0__FLEXIO1_FLEXIO_BIT3 0x01AC 0x03B0 0x0474 0x04 0x01 731 731 + #define IMX95_PAD_SD2_DATA0__GPIO3_IO_BIT3 0x01AC 0x03B0 0x0000 0x05 0x00 732 732 + #define IMX95_PAD_SD2_DATA0__CCMSRCGPCMIX_TOP_OBSERVE_2 0x01AC 0x03B0 0x0000 0x06 0x00 733 733 + 734 734 + #define IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x01B0 0x03B4 0x0000 0x00 0x00 735 735 + #define IMX95_PAD_SD2_DATA1__NETCMIX_TOP_NETC_TMR_1588_CLK 0x01B0 0x03B4 0x0000 0x01 0x00 736 736 + #define IMX95_PAD_SD2_DATA1__CAN2_RX 0x01B0 0x03B4 0x0444 0x02 0x03 737 737 + #define IMX95_PAD_SD2_DATA1__FLEXIO1_FLEXIO_BIT4 0x01B0 0x03B4 0x0478 0x04 0x01 738 738 + #define IMX95_PAD_SD2_DATA1__GPIO3_IO_BIT4 0x01B0 0x03B4 0x0000 0x05 0x00 739 739 + 740 740 + #define IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x01B4 0x03B8 0x0000 0x00 0x00 741 741 + #define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_NETC_TMR_1588_PP3 0x01B4 0x03B8 0x0000 0x01 0x00 742 742 + #define IMX95_PAD_SD2_DATA2__NETCMIX_TOP_MQS2_RIGHT 0x01B4 0x03B8 0x0000 0x02 0x00 743 743 + #define IMX95_PAD_SD2_DATA2__FLEXIO1_FLEXIO_BIT5 0x01B4 0x03B8 0x047C 0x04 0x01 744 744 + #define IMX95_PAD_SD2_DATA2__GPIO3_IO_BIT5 0x01B4 0x03B8 0x0000 0x05 0x00 745 745 + 746 746 + #define IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x01B8 0x03BC 0x0000 0x00 0x00 747 747 + #define IMX95_PAD_SD2_DATA3__LPTMR2_ALT1 0x01B8 0x03BC 0x0548 0x01 0x01 748 748 + #define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_MQS2_LEFT 0x01B8 0x03BC 0x0000 0x02 0x00 749 749 + #define IMX95_PAD_SD2_DATA3__NETCMIX_TOP_NETC_TMR_1588_ALARM1 0x01B8 0x03BC 0x0000 0x03 0x00 750 750 + #define IMX95_PAD_SD2_DATA3__FLEXIO1_FLEXIO_BIT6 0x01B8 0x03BC 0x0480 0x04 0x01 751 751 + #define IMX95_PAD_SD2_DATA3__GPIO3_IO_BIT6 0x01B8 0x03BC 0x0000 0x05 0x00 752 752 + 753 753 + #define IMX95_PAD_SD2_RESET_B__USDHC2_RESET_B 0x01BC 0x03C0 0x0000 0x00 0x00 754 754 + #define IMX95_PAD_SD2_RESET_B__LPTMR2_ALT2 0x01BC 0x03C0 0x054C 0x01 0x01 755 755 + #define IMX95_PAD_SD2_RESET_B__NETCMIX_TOP_NETC_TMR_1588_GCLK 0x01BC 0x03C0 0x0000 0x03 0x00 756 756 + #define IMX95_PAD_SD2_RESET_B__FLEXIO1_FLEXIO_BIT7 0x01BC 0x03C0 0x0484 0x04 0x01 757 757 + #define IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x01BC 0x03C0 0x0000 0x05 0x00 758 758 + 759 759 + #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPI2C1_SCL 0x01C0 0x03C4 0x0000 0x00 0x00 760 760 + #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_I3C1_SCL 0x01C0 0x03C4 0x0000 0x01 0x00 761 761 + #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_LPUART1_DCD_B 0x01C0 0x03C4 0x0000 0x02 0x00 762 762 + #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_TPM2_CH0 0x01C0 0x03C4 0x0000 0x03 0x00 763 763 + #define IMX95_PAD_I2C1_SCL__VPUMIX_TOP_UART_RX 0x01C0 0x03C4 0x0000 0x04 0x00 764 764 + #define IMX95_PAD_I2C1_SCL__AONMIX_TOP_GPIO1_IO_BIT0 0x01C0 0x03C4 0x0000 0x05 0x00 765 765 + 766 766 + #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPI2C1_SDA 0x01C4 0x03C8 0x0000 0x00 0x00 767 767 + #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_I3C1_SDA 0x01C4 0x03C8 0x0000 0x01 0x00 768 768 + #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_LPUART1_RIN_B 0x01C4 0x03C8 0x0000 0x02 0x00 769 769 + #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_TPM2_CH1 0x01C4 0x03C8 0x0000 0x03 0x00 770 770 + #define IMX95_PAD_I2C1_SDA__VPUMIX_TOP_UART_TX 0x01C4 0x03C8 0x0000 0x04 0x00 771 771 + #define IMX95_PAD_I2C1_SDA__AONMIX_TOP_GPIO1_IO_BIT1 0x01C4 0x03C8 0x0000 0x05 0x00 772 772 + 773 773 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x01C8 0x03CC 0x0000 0x00 0x00 774 774 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR 0x01C8 0x03CC 0x0000 0x01 0x00 775 775 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPUART2_DCD_B 0x01C8 0x03CC 0x0000 0x02 0x00 776 776 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_TPM2_CH2 0x01C8 0x03CC 0x0000 0x03 0x00 777 777 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_SAI1_RX_SYNC 0x01C8 0x03CC 0x0000 0x04 0x00 778 778 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x01C8 0x03CC 0x0000 0x05 0x00 779 779 + #define IMX95_PAD_I2C2_SCL__AONMIX_TOP_I3C1_PUR_B 0x01C8 0x03CC 0x0000 0x06 0x00 780 780 + 781 781 + #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x01CC 0x03D0 0x0000 0x00 0x00 782 782 + #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPUART2_RIN_B 0x01CC 0x03D0 0x0000 0x02 0x00 783 783 + #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_TPM2_CH3 0x01CC 0x03D0 0x0000 0x03 0x00 784 784 + #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_SAI1_RX_BCLK 0x01CC 0x03D0 0x0000 0x04 0x00 785 785 + #define IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x01CC 0x03D0 0x0000 0x05 0x00 786 786 + 787 787 + #define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x01D0 0x03D4 0x0000 0x00 0x00 788 788 + #define IMX95_PAD_UART1_RXD__S400_UART_RX 0x01D0 0x03D4 0x0000 0x01 0x00 789 789 + #define IMX95_PAD_UART1_RXD__AONMIX_TOP_LPSPI2_SIN 0x01D0 0x03D4 0x0000 0x02 0x00 790 790 + #define IMX95_PAD_UART1_RXD__AONMIX_TOP_TPM1_CH0 0x01D0 0x03D4 0x0000 0x03 0x00 791 791 + #define IMX95_PAD_UART1_RXD__AONMIX_TOP_GPIO1_IO_BIT4 0x01D0 0x03D4 0x0000 0x05 0x00 792 792 + 793 793 + #define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x01D4 0x03D8 0x0000 0x00 0x00 794 794 + #define IMX95_PAD_UART1_TXD__S400_UART_TX 0x01D4 0x03D8 0x0000 0x01 0x00 795 795 + #define IMX95_PAD_UART1_TXD__AONMIX_TOP_LPSPI2_PCS0 0x01D4 0x03D8 0x0000 0x02 0x00 796 796 + #define IMX95_PAD_UART1_TXD__AONMIX_TOP_TPM1_CH1 0x01D4 0x03D8 0x0000 0x03 0x00 797 797 + #define IMX95_PAD_UART1_TXD__AONMIX_TOP_GPIO1_IO_BIT5 0x01D4 0x03D8 0x0000 0x05 0x00 798 798 + 799 799 + #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x01D8 0x03DC 0x0000 0x00 0x00 800 800 + #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART1_CTS_B 0x01D8 0x03DC 0x0000 0x01 0x00 801 801 + #define IMX95_PAD_UART2_RXD__AONMIX_TOP_LPSPI2_SOUT 0x01D8 0x03DC 0x0000 0x02 0x00 802 802 + #define IMX95_PAD_UART2_RXD__AONMIX_TOP_TPM1_CH2 0x01D8 0x03DC 0x0000 0x03 0x00 803 803 + #define IMX95_PAD_UART2_RXD__AONMIX_TOP_SAI1_MCLK 0x01D8 0x03DC 0x041C 0x04 0x00 804 804 + #define IMX95_PAD_UART2_RXD__AONMIX_TOP_GPIO1_IO_BIT6 0x01D8 0x03DC 0x0000 0x05 0x00 805 805 + 806 806 + #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x01DC 0x03E0 0x0000 0x00 0x00 807 807 + #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART1_RTS_B 0x01DC 0x03E0 0x0000 0x01 0x00 808 808 + #define IMX95_PAD_UART2_TXD__AONMIX_TOP_LPSPI2_SCK 0x01DC 0x03E0 0x0000 0x02 0x00 809 809 + #define IMX95_PAD_UART2_TXD__AONMIX_TOP_TPM1_CH3 0x01DC 0x03E0 0x0000 0x03 0x00 810 810 + #define IMX95_PAD_UART2_TXD__AONMIX_TOP_GPIO1_IO_BIT7 0x01DC 0x03E0 0x0000 0x05 0x00 811 811 + 812 812 + #define IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x01E0 0x03E4 0x0000 0x00 0x00 813 813 + #define IMX95_PAD_PDM_CLK__AONMIX_TOP_MQS1_LEFT 0x01E0 0x03E4 0x0000 0x01 0x00 814 814 + #define IMX95_PAD_PDM_CLK__AONMIX_TOP_LPTMR1_ALT1 0x01E0 0x03E4 0x0000 0x04 0x00 815 815 + #define IMX95_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_BIT8 0x01E0 0x03E4 0x0000 0x05 0x00 816 816 + #define IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x01E0 0x03E4 0x0000 0x06 0x00 817 817 + 818 818 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_BIT0 0x01E4 0x03E8 0x040C 0x00 0x00 819 819 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_MQS1_RIGHT 0x01E4 0x03E8 0x0000 0x01 0x00 820 820 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPSPI1_PCS1 0x01E4 0x03E8 0x0000 0x02 0x00 821 821 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_TPM1_EXTCLK 0x01E4 0x03E8 0x0000 0x03 0x00 822 822 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_LPTMR1_ALT2 0x01E4 0x03E8 0x0000 0x04 0x00 823 823 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_BIT9 0x01E4 0x03E8 0x0000 0x05 0x00 824 824 + #define IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x01E4 0x03E8 0x0408 0x06 0x00 825 825 + 826 826 + #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_PDM_BIT_STREAM_BIT1 0x01E8 0x03EC 0x0410 0x00 0x00 827 827 + #define IMX95_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI 0x01E8 0x03EC 0x0000 0x01 0x00 828 828 + #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPSPI2_PCS1 0x01E8 0x03EC 0x0000 0x02 0x00 829 829 + #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_TPM2_EXTCLK 0x01E8 0x03EC 0x0000 0x03 0x00 830 830 + #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_LPTMR1_ALT3 0x01E8 0x03EC 0x0000 0x04 0x00 831 831 + #define IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x01E8 0x03EC 0x0000 0x05 0x00 832 832 + #define IMX95_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_TOP_EXT_CLK1 0x01E8 0x03EC 0x0420 0x06 0x00 833 833 + 834 834 + #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x01EC 0x03F0 0x0000 0x00 0x00 835 835 + #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_DATA_BIT1 0x01EC 0x03F0 0x0000 0x01 0x00 836 836 + #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPSPI1_PCS0 0x01EC 0x03F0 0x0000 0x02 0x00 837 837 + #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_LPUART2_DTR_B 0x01EC 0x03F0 0x0000 0x03 0x00 838 838 + #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_MQS1_LEFT 0x01EC 0x03F0 0x0000 0x04 0x00 839 839 + #define IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x01EC 0x03F0 0x0000 0x05 0x00 840 840 + 841 841 + #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x01F0 0x03F4 0x0000 0x00 0x00 842 842 + #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x01F0 0x03F4 0x0000 0x01 0x00 843 843 + #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPSPI1_SIN 0x01F0 0x03F4 0x0000 0x02 0x00 844 844 + #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART1_DSR_B 0x01F0 0x03F4 0x0000 0x03 0x00 845 845 + #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_CAN1_RX 0x01F0 0x03F4 0x0408 0x04 0x01 846 846 + #define IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x01F0 0x03F4 0x0000 0x05 0x00 847 847 + 848 848 + #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_BIT0 0x01F4 0x03F8 0x0000 0x00 0x00 849 849 + #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x01F4 0x03F8 0x0000 0x01 0x00 850 850 + #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPSPI1_SCK 0x01F4 0x03F8 0x0000 0x02 0x00 851 851 + #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART1_DTR_B 0x01F4 0x03F8 0x0000 0x03 0x00 852 852 + #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_CAN1_TX 0x01F4 0x03F8 0x0000 0x04 0x00 853 853 + #define IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x01F4 0x03F8 0x0000 0x05 0x00 854 854 + 855 855 + #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_BIT0 0x01F8 0x03FC 0x0000 0x00 0x00 856 856 + #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_MCLK 0x01F8 0x03FC 0x041C 0x01 0x01 857 857 + #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPSPI1_SOUT 0x01F8 0x03FC 0x0000 0x02 0x00 858 858 + #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_LPUART2_DSR_B 0x01F8 0x03FC 0x0000 0x03 0x00 859 859 + #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_MQS1_RIGHT 0x01F8 0x03FC 0x0000 0x04 0x00 860 860 + #define IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x01F8 0x03FC 0x0000 0x05 0x00 861 861 + 862 862 + #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_WDOG_ANY 0x01FC 0x0400 0x0000 0x00 0x00 863 863 + #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_FCCU_EOUT1 0x01FC 0x0400 0x0000 0x01 0x00 864 864 + #define IMX95_PAD_WDOG_ANY__AONMIX_TOP_GPIO1_IO_BIT15 0x01FC 0x0400 0x0000 0x05 0x00 865 865 + #endif /* __DTS_IMX95_PINFUNC_H */

+47

arch/arm64/boot/dts/freescale/imx95-power.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + #ifndef __IMX95_POWER_H__ 7 7 + #define __IMX95_POWER_H__ 8 8 + 9 9 + #define IMX95_PD_ANA 0 10 10 + #define IMX95_PD_AON 1 11 11 + #define IMX95_PD_BBSM 2 12 12 + #define IMX95_PD_CAMERA 3 13 13 + #define IMX95_PD_CCMSRCGPC 4 14 14 + #define IMX95_PD_A55C0 5 15 15 + #define IMX95_PD_A55C1 6 16 16 + #define IMX95_PD_A55C2 7 17 17 + #define IMX95_PD_A55C3 8 18 18 + #define IMX95_PD_A55C4 9 19 19 + #define IMX95_PD_A55C5 10 20 20 + #define IMX95_PD_A55P 11 21 21 + #define IMX95_PD_DDR 12 22 22 + #define IMX95_PD_DISPLAY 13 23 23 + #define IMX95_PD_GPU 14 24 24 + #define IMX95_PD_HSIO_TOP 15 25 25 + #define IMX95_PD_HSIO_WAON 16 26 26 + #define IMX95_PD_M7 17 27 27 + #define IMX95_PD_NETC 18 28 28 + #define IMX95_PD_NOC 19 29 29 + #define IMX95_PD_NPU 20 30 30 + #define IMX95_PD_VPU 21 31 31 + #define IMX95_PD_WAKEUP 22 32 32 + 33 33 + #define IMX95_PERF_ELE 0 34 34 + #define IMX95_PERF_M33 1 35 35 + #define IMX95_PERF_WAKEUP 2 36 36 + #define IMX95_PERF_M7 3 37 37 + #define IMX95_PERF_DRAM 4 38 38 + #define IMX95_PERF_HSIO 5 39 39 + #define IMX95_PERF_NPU 6 40 40 + #define IMX95_PERF_NOC 7 41 41 + #define IMX95_PERF_A55 8 42 42 + #define IMX95_PERF_GPU 9 43 43 + #define IMX95_PERF_VPU 10 44 44 + #define IMX95_PERF_CAM 11 45 45 + #define IMX95_PERF_DISP 12 46 46 + 47 47 + #endif

+1192

arch/arm64/boot/dts/freescale/imx95.dtsi

reviewed

··· 1 1 + // SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2 2 + /* 3 3 + * Copyright 2024 NXP 4 4 + */ 5 5 + 6 6 + #include <dt-bindings/gpio/gpio.h> 7 7 + #include <dt-bindings/input/input.h> 8 8 + #include <dt-bindings/interrupt-controller/arm-gic.h> 9 9 + #include <dt-bindings/thermal/thermal.h> 10 10 + 11 11 + #include "imx95-clock.h" 12 12 + #include "imx95-pinfunc.h" 13 13 + #include "imx95-power.h" 14 14 + 15 15 + / { 16 16 + interrupt-parent = <&gic>; 17 17 + #address-cells = <2>; 18 18 + #size-cells = <2>; 19 19 + 20 20 + cpus { 21 21 + #address-cells = <1>; 22 22 + #size-cells = <0>; 23 23 + 24 24 + A55_0: cpu@0 { 25 25 + device_type = "cpu"; 26 26 + compatible = "arm,cortex-a55"; 27 27 + reg = <0x0>; 28 28 + enable-method = "psci"; 29 29 + #cooling-cells = <2>; 30 30 + power-domains = <&scmi_devpd IMX95_PERF_A55>; 31 31 + power-domain-names = "perf"; 32 32 + i-cache-size = <32768>; 33 33 + i-cache-line-size = <64>; 34 34 + i-cache-sets = <128>; 35 35 + d-cache-size = <32768>; 36 36 + d-cache-line-size = <64>; 37 37 + d-cache-sets = <128>; 38 38 + next-level-cache = <&l2_cache_l0>; 39 39 + }; 40 40 + 41 41 + A55_1: cpu@100 { 42 42 + device_type = "cpu"; 43 43 + compatible = "arm,cortex-a55"; 44 44 + reg = <0x100>; 45 45 + enable-method = "psci"; 46 46 + #cooling-cells = <2>; 47 47 + power-domains = <&scmi_devpd IMX95_PERF_A55>; 48 48 + power-domain-names = "perf"; 49 49 + i-cache-size = <32768>; 50 50 + i-cache-line-size = <64>; 51 51 + i-cache-sets = <128>; 52 52 + d-cache-size = <32768>; 53 53 + d-cache-line-size = <64>; 54 54 + d-cache-sets = <128>; 55 55 + next-level-cache = <&l2_cache_l1>; 56 56 + }; 57 57 + 58 58 + A55_2: cpu@200 { 59 59 + device_type = "cpu"; 60 60 + compatible = "arm,cortex-a55"; 61 61 + reg = <0x200>; 62 62 + enable-method = "psci"; 63 63 + #cooling-cells = <2>; 64 64 + power-domains = <&scmi_devpd IMX95_PERF_A55>; 65 65 + power-domain-names = "perf"; 66 66 + i-cache-size = <32768>; 67 67 + i-cache-line-size = <64>; 68 68 + i-cache-sets = <128>; 69 69 + d-cache-size = <32768>; 70 70 + d-cache-line-size = <64>; 71 71 + d-cache-sets = <128>; 72 72 + next-level-cache = <&l2_cache_l2>; 73 73 + }; 74 74 + 75 75 + A55_3: cpu@300 { 76 76 + device_type = "cpu"; 77 77 + compatible = "arm,cortex-a55"; 78 78 + reg = <0x300>; 79 79 + enable-method = "psci"; 80 80 + #cooling-cells = <2>; 81 81 + power-domains = <&scmi_devpd IMX95_PERF_A55>; 82 82 + power-domain-names = "perf"; 83 83 + i-cache-size = <32768>; 84 84 + i-cache-line-size = <64>; 85 85 + i-cache-sets = <128>; 86 86 + d-cache-size = <32768>; 87 87 + d-cache-line-size = <64>; 88 88 + d-cache-sets = <128>; 89 89 + next-level-cache = <&l2_cache_l3>; 90 90 + }; 91 91 + 92 92 + A55_4: cpu@400 { 93 93 + device_type = "cpu"; 94 94 + compatible = "arm,cortex-a55"; 95 95 + reg = <0x400>; 96 96 + power-domains = <&scmi_devpd IMX95_PERF_A55>; 97 97 + power-domain-names = "perf"; 98 98 + enable-method = "psci"; 99 99 + #cooling-cells = <2>; 100 100 + i-cache-size = <32768>; 101 101 + i-cache-line-size = <64>; 102 102 + i-cache-sets = <128>; 103 103 + d-cache-size = <32768>; 104 104 + d-cache-line-size = <64>; 105 105 + d-cache-sets = <128>; 106 106 + next-level-cache = <&l2_cache_l4>; 107 107 + }; 108 108 + 109 109 + A55_5: cpu@500 { 110 110 + device_type = "cpu"; 111 111 + compatible = "arm,cortex-a55"; 112 112 + reg = <0x500>; 113 113 + power-domains = <&scmi_devpd IMX95_PERF_A55>; 114 114 + power-domain-names = "perf"; 115 115 + enable-method = "psci"; 116 116 + #cooling-cells = <2>; 117 117 + i-cache-size = <32768>; 118 118 + i-cache-line-size = <64>; 119 119 + i-cache-sets = <128>; 120 120 + d-cache-size = <32768>; 121 121 + d-cache-line-size = <64>; 122 122 + d-cache-sets = <128>; 123 123 + next-level-cache = <&l2_cache_l5>; 124 124 + }; 125 125 + 126 126 + l2_cache_l0: l2-cache-l0 { 127 127 + compatible = "cache"; 128 128 + cache-size = <65536>; 129 129 + cache-line-size = <64>; 130 130 + cache-sets = <256>; 131 131 + cache-level = <2>; 132 132 + cache-unified; 133 133 + next-level-cache = <&l3_cache>; 134 134 + }; 135 135 + 136 136 + l2_cache_l1: l2-cache-l1 { 137 137 + compatible = "cache"; 138 138 + cache-size = <65536>; 139 139 + cache-line-size = <64>; 140 140 + cache-sets = <256>; 141 141 + cache-level = <2>; 142 142 + cache-unified; 143 143 + next-level-cache = <&l3_cache>; 144 144 + }; 145 145 + 146 146 + l2_cache_l2: l2-cache-l2 { 147 147 + compatible = "cache"; 148 148 + cache-size = <65536>; 149 149 + cache-line-size = <64>; 150 150 + cache-sets = <256>; 151 151 + cache-level = <2>; 152 152 + cache-unified; 153 153 + next-level-cache = <&l3_cache>; 154 154 + }; 155 155 + 156 156 + l2_cache_l3: l2-cache-l3 { 157 157 + compatible = "cache"; 158 158 + cache-size = <65536>; 159 159 + cache-line-size = <64>; 160 160 + cache-sets = <256>; 161 161 + cache-level = <2>; 162 162 + cache-unified; 163 163 + next-level-cache = <&l3_cache>; 164 164 + }; 165 165 + 166 166 + l2_cache_l4: l2-cache-l4 { 167 167 + compatible = "cache"; 168 168 + cache-size = <65536>; 169 169 + cache-line-size = <64>; 170 170 + cache-sets = <256>; 171 171 + cache-level = <2>; 172 172 + cache-unified; 173 173 + next-level-cache = <&l3_cache>; 174 174 + }; 175 175 + 176 176 + l2_cache_l5: l2-cache-l5 { 177 177 + compatible = "cache"; 178 178 + cache-size = <65536>; 179 179 + cache-line-size = <64>; 180 180 + cache-sets = <256>; 181 181 + cache-level = <2>; 182 182 + cache-unified; 183 183 + next-level-cache = <&l3_cache>; 184 184 + }; 185 185 + 186 186 + l3_cache: l3-cache { 187 187 + compatible = "cache"; 188 188 + cache-size = <524288>; 189 189 + cache-line-size = <64>; 190 190 + cache-sets = <1024>; 191 191 + cache-level = <3>; 192 192 + cache-unified; 193 193 + }; 194 194 + 195 195 + cpu-map { 196 196 + cluster0 { 197 197 + core0 { 198 198 + cpu = <&A55_0>; 199 199 + }; 200 200 + 201 201 + core1 { 202 202 + cpu = <&A55_1>; 203 203 + }; 204 204 + 205 205 + core2 { 206 206 + cpu = <&A55_2>; 207 207 + }; 208 208 + 209 209 + core3 { 210 210 + cpu = <&A55_3>; 211 211 + }; 212 212 + 213 213 + core4 { 214 214 + cpu = <&A55_4>; 215 215 + }; 216 216 + 217 217 + core5 { 218 218 + cpu = <&A55_5>; 219 219 + }; 220 220 + }; 221 221 + }; 222 222 + }; 223 223 + 224 224 + clk_ext1: clock-ext1 { 225 225 + compatible = "fixed-clock"; 226 226 + #clock-cells = <0>; 227 227 + clock-frequency = <133000000>; 228 228 + clock-output-names = "clk_ext1"; 229 229 + }; 230 230 + 231 231 + sai1_mclk: clock-sai-mclk1 { 232 232 + compatible = "fixed-clock"; 233 233 + #clock-cells = <0>; 234 234 + clock-frequency= <0>; 235 235 + clock-output-names = "sai1_mclk"; 236 236 + }; 237 237 + 238 238 + sai2_mclk: clock-sai-mclk2 { 239 239 + compatible = "fixed-clock"; 240 240 + #clock-cells = <0>; 241 241 + clock-frequency= <0>; 242 242 + clock-output-names = "sai2_mclk"; 243 243 + }; 244 244 + 245 245 + sai3_mclk: clock-sai-mclk3 { 246 246 + compatible = "fixed-clock"; 247 247 + #clock-cells = <0>; 248 248 + clock-frequency= <0>; 249 249 + clock-output-names = "sai3_mclk"; 250 250 + }; 251 251 + 252 252 + sai4_mclk: clock-sai-mclk4 { 253 253 + compatible = "fixed-clock"; 254 254 + #clock-cells = <0>; 255 255 + clock-frequency= <0>; 256 256 + clock-output-names = "sai4_mclk"; 257 257 + }; 258 258 + 259 259 + sai5_mclk: clock-sai-mclk5 { 260 260 + compatible = "fixed-clock"; 261 261 + #clock-cells = <0>; 262 262 + clock-frequency= <0>; 263 263 + clock-output-names = "sai5_mclk"; 264 264 + }; 265 265 + 266 266 + osc_24m: clock-24m { 267 267 + compatible = "fixed-clock"; 268 268 + #clock-cells = <0>; 269 269 + clock-frequency = <24000000>; 270 270 + clock-output-names = "osc_24m"; 271 271 + }; 272 272 + 273 273 + sram1: sram@204c0000 { 274 274 + compatible = "mmio-sram"; 275 275 + reg = <0x0 0x204c0000 0x0 0x18000>; 276 276 + ranges = <0x0 0x0 0x204c0000 0x18000>; 277 277 + #address-cells = <1>; 278 278 + #size-cells = <1>; 279 279 + }; 280 280 + 281 281 + firmware { 282 282 + scmi { 283 283 + compatible = "arm,scmi"; 284 284 + mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>; 285 285 + shmem = <&scmi_buf0>, <&scmi_buf1>; 286 286 + #address-cells = <1>; 287 287 + #size-cells = <0>; 288 288 + 289 289 + scmi_devpd: protocol@11 { 290 290 + reg = <0x11>; 291 291 + #power-domain-cells = <1>; 292 292 + }; 293 293 + 294 294 + scmi_perf: protocol@13 { 295 295 + reg = <0x13>; 296 296 + #power-domain-cells = <1>; 297 297 + }; 298 298 + 299 299 + scmi_clk: protocol@14 { 300 300 + reg = <0x14>; 301 301 + #clock-cells = <1>; 302 302 + }; 303 303 + 304 304 + scmi_sensor: protocol@15 { 305 305 + reg = <0x15>; 306 306 + #thermal-sensor-cells = <1>; 307 307 + }; 308 308 + 309 309 + scmi_iomuxc: protocol@19 { 310 310 + reg = <0x19>; 311 311 + }; 312 312 + 313 313 + }; 314 314 + }; 315 315 + 316 316 + pmu { 317 317 + compatible = "arm,cortex-a55-pmu"; 318 318 + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 319 319 + }; 320 320 + 321 321 + thermal-zones { 322 322 + a55-thermal { 323 323 + polling-delay-passive = <250>; 324 324 + polling-delay = <2000>; 325 325 + thermal-sensors = <&scmi_sensor 1>; 326 326 + 327 327 + trips { 328 328 + cpu_alert0: trip0 { 329 329 + temperature = <85000>; 330 330 + hysteresis = <2000>; 331 331 + type = "passive"; 332 332 + }; 333 333 + 334 334 + cpu_crit0: trip1 { 335 335 + temperature = <95000>; 336 336 + hysteresis = <2000>; 337 337 + type = "critical"; 338 338 + }; 339 339 + }; 340 340 + 341 341 + cooling-maps { 342 342 + map0 { 343 343 + trip = <&cpu_alert0>; 344 344 + cooling-device = 345 345 + <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 346 346 + <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 347 347 + <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 348 348 + <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 349 349 + <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350 350 + <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 351 351 + }; 352 352 + }; 353 353 + }; 354 354 + }; 355 355 + 356 356 + psci { 357 357 + compatible = "arm,psci-1.0"; 358 358 + method = "smc"; 359 359 + }; 360 360 + 361 361 + timer { 362 362 + compatible = "arm,armv8-timer"; 363 363 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 364 364 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 365 365 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 366 366 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 367 367 + clock-frequency = <24000000>; 368 368 + arm,no-tick-in-suspend; 369 369 + interrupt-parent = <&gic>; 370 370 + }; 371 371 + 372 372 + gic: interrupt-controller@48000000 { 373 373 + compatible = "arm,gic-v3"; 374 374 + reg = <0 0x48000000 0 0x10000>, 375 375 + <0 0x48060000 0 0xc0000>; 376 376 + #address-cells = <2>; 377 377 + #size-cells = <2>; 378 378 + #interrupt-cells = <3>; 379 379 + interrupt-controller; 380 380 + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 381 381 + interrupt-parent = <&gic>; 382 382 + dma-noncoherent; 383 383 + ranges; 384 384 + 385 385 + its: msi-controller@48040000 { 386 386 + compatible = "arm,gic-v3-its"; 387 387 + reg = <0 0x48040000 0 0x20000>; 388 388 + msi-controller; 389 389 + #msi-cells = <1>; 390 390 + dma-noncoherent; 391 391 + }; 392 392 + }; 393 393 + 394 394 + soc { 395 395 + compatible = "simple-bus"; 396 396 + #address-cells = <2>; 397 397 + #size-cells = <2>; 398 398 + ranges; 399 399 + 400 400 + aips2: bus@42000000 { 401 401 + compatible = "fsl,aips-bus", "simple-bus"; 402 402 + reg = <0x0 0x42000000 0x0 0x800000>; 403 403 + ranges = <0x42000000 0x0 0x42000000 0x8000000>, 404 404 + <0x28000000 0x0 0x28000000 0x10000000>; 405 405 + #address-cells = <1>; 406 406 + #size-cells = <1>; 407 407 + 408 408 + mu7: mailbox@42430000 { 409 409 + compatible = "fsl,imx95-mu"; 410 410 + reg = <0x42430000 0x10000>; 411 411 + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 412 412 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 413 413 + #mbox-cells = <2>; 414 414 + status = "disabled"; 415 415 + }; 416 416 + 417 417 + wdog3: watchdog@42490000 { 418 418 + compatible = "fsl,imx93-wdt"; 419 419 + reg = <0x42490000 0x10000>; 420 420 + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 421 421 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 422 422 + timeout-sec = <40>; 423 423 + status = "disabled"; 424 424 + }; 425 425 + 426 426 + tpm3: pwm@424e0000 { 427 427 + compatible = "fsl,imx7ulp-pwm"; 428 428 + reg = <0x424e0000 0x1000>; 429 429 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 430 430 + #pwm-cells = <3>; 431 431 + status = "disabled"; 432 432 + }; 433 433 + 434 434 + tpm4: pwm@424f0000 { 435 435 + compatible = "fsl,imx7ulp-pwm"; 436 436 + reg = <0x424f0000 0x1000>; 437 437 + clocks = <&scmi_clk IMX95_CLK_TPM4>; 438 438 + #pwm-cells = <3>; 439 439 + status = "disabled"; 440 440 + }; 441 441 + 442 442 + tpm5: pwm@42500000 { 443 443 + compatible = "fsl,imx7ulp-pwm"; 444 444 + reg = <0x42500000 0x1000>; 445 445 + clocks = <&scmi_clk IMX95_CLK_TPM5>; 446 446 + #pwm-cells = <3>; 447 447 + status = "disabled"; 448 448 + }; 449 449 + 450 450 + tpm6: pwm@42510000 { 451 451 + compatible = "fsl,imx7ulp-pwm"; 452 452 + reg = <0x42510000 0x1000>; 453 453 + clocks = <&scmi_clk IMX95_CLK_TPM6>; 454 454 + #pwm-cells = <3>; 455 455 + status = "disabled"; 456 456 + }; 457 457 + 458 458 + lpi2c3: i2c@42530000 { 459 459 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 460 460 + reg = <0x42530000 0x10000>; 461 461 + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 462 462 + clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 463 463 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 464 464 + clock-names = "per", "ipg"; 465 465 + #address-cells = <1>; 466 466 + #size-cells = <0>; 467 467 + status = "disabled"; 468 468 + }; 469 469 + 470 470 + lpi2c4: i2c@42540000 { 471 471 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 472 472 + reg = <0x42540000 0x10000>; 473 473 + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 474 474 + clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 475 475 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 476 476 + clock-names = "per", "ipg"; 477 477 + #address-cells = <1>; 478 478 + #size-cells = <0>; 479 479 + status = "disabled"; 480 480 + }; 481 481 + 482 482 + lpspi3: spi@42550000 { 483 483 + #address-cells = <1>; 484 484 + #size-cells = <0>; 485 485 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 486 486 + reg = <0x42550000 0x10000>; 487 487 + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 488 488 + clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 489 489 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 490 490 + clock-names = "per", "ipg"; 491 491 + status = "disabled"; 492 492 + }; 493 493 + 494 494 + lpspi4: spi@42560000 { 495 495 + #address-cells = <1>; 496 496 + #size-cells = <0>; 497 497 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 498 498 + reg = <0x42560000 0x10000>; 499 499 + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 500 500 + clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 501 501 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 502 502 + clock-names = "per", "ipg"; 503 503 + status = "disabled"; 504 504 + }; 505 505 + 506 506 + lpuart3: serial@42570000 { 507 507 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 508 508 + "fsl,imx7ulp-lpuart"; 509 509 + reg = <0x42570000 0x1000>; 510 510 + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 511 511 + clocks = <&scmi_clk IMX95_CLK_LPUART3>; 512 512 + clock-names = "ipg"; 513 513 + status = "disabled"; 514 514 + }; 515 515 + 516 516 + lpuart4: serial@42580000 { 517 517 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 518 518 + "fsl,imx7ulp-lpuart"; 519 519 + reg = <0x42580000 0x1000>; 520 520 + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 521 521 + clocks = <&scmi_clk IMX95_CLK_LPUART4>; 522 522 + clock-names = "ipg"; 523 523 + status = "disabled"; 524 524 + }; 525 525 + 526 526 + lpuart5: serial@42590000 { 527 527 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 528 528 + "fsl,imx7ulp-lpuart"; 529 529 + reg = <0x42590000 0x1000>; 530 530 + interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 531 531 + clocks = <&scmi_clk IMX95_CLK_LPUART5>; 532 532 + clock-names = "ipg"; 533 533 + status = "disabled"; 534 534 + }; 535 535 + 536 536 + lpuart6: serial@425a0000 { 537 537 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 538 538 + "fsl,imx7ulp-lpuart"; 539 539 + reg = <0x425a0000 0x1000>; 540 540 + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 541 541 + clocks = <&scmi_clk IMX95_CLK_LPUART6>; 542 542 + clock-names = "ipg"; 543 543 + status = "disabled"; 544 544 + }; 545 545 + 546 546 + lpuart7: serial@42690000 { 547 547 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 548 548 + "fsl,imx7ulp-lpuart"; 549 549 + reg = <0x42690000 0x1000>; 550 550 + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 551 551 + clocks = <&scmi_clk IMX95_CLK_LPUART7>; 552 552 + clock-names = "ipg"; 553 553 + status = "disabled"; 554 554 + }; 555 555 + 556 556 + lpuart8: serial@426a0000 { 557 557 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 558 558 + "fsl,imx7ulp-lpuart"; 559 559 + reg = <0x426a0000 0x1000>; 560 560 + interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 561 561 + clocks = <&scmi_clk IMX95_CLK_LPUART8>; 562 562 + clock-names = "ipg"; 563 563 + status = "disabled"; 564 564 + }; 565 565 + 566 566 + lpi2c5: i2c@426b0000 { 567 567 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 568 568 + reg = <0x426b0000 0x10000>; 569 569 + interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 570 570 + clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 571 571 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 572 572 + clock-names = "per", "ipg"; 573 573 + #address-cells = <1>; 574 574 + #size-cells = <0>; 575 575 + status = "disabled"; 576 576 + }; 577 577 + 578 578 + lpi2c6: i2c@426c0000 { 579 579 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 580 580 + reg = <0x426c0000 0x10000>; 581 581 + interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 582 582 + clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 583 583 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 584 584 + clock-names = "per", "ipg"; 585 585 + #address-cells = <1>; 586 586 + #size-cells = <0>; 587 587 + status = "disabled"; 588 588 + }; 589 589 + 590 590 + lpi2c7: i2c@426d0000 { 591 591 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 592 592 + reg = <0x426d0000 0x10000>; 593 593 + interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 594 594 + clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 595 595 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 596 596 + clock-names = "per", "ipg"; 597 597 + #address-cells = <1>; 598 598 + #size-cells = <0>; 599 599 + status = "disabled"; 600 600 + }; 601 601 + 602 602 + lpi2c8: i2c@426e0000 { 603 603 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 604 604 + reg = <0x426e0000 0x10000>; 605 605 + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 606 606 + clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 607 607 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 608 608 + clock-names = "per", "ipg"; 609 609 + #address-cells = <1>; 610 610 + #size-cells = <0>; 611 611 + status = "disabled"; 612 612 + }; 613 613 + 614 614 + lpspi5: spi@426f0000 { 615 615 + #address-cells = <1>; 616 616 + #size-cells = <0>; 617 617 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 618 618 + reg = <0x426f0000 0x10000>; 619 619 + interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 620 620 + clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 621 621 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 622 622 + clock-names = "per", "ipg"; 623 623 + status = "disabled"; 624 624 + }; 625 625 + 626 626 + lpspi6: spi@42700000 { 627 627 + #address-cells = <1>; 628 628 + #size-cells = <0>; 629 629 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 630 630 + reg = <0x42700000 0x10000>; 631 631 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 632 632 + clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 633 633 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 634 634 + clock-names = "per", "ipg"; 635 635 + status = "disabled"; 636 636 + }; 637 637 + 638 638 + lpspi7: spi@42710000 { 639 639 + #address-cells = <1>; 640 640 + #size-cells = <0>; 641 641 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 642 642 + reg = <0x42710000 0x10000>; 643 643 + interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 644 644 + clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 645 645 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 646 646 + clock-names = "per", "ipg"; 647 647 + status = "disabled"; 648 648 + }; 649 649 + 650 650 + lpspi8: spi@42720000 { 651 651 + #address-cells = <1>; 652 652 + #size-cells = <0>; 653 653 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 654 654 + reg = <0x42720000 0x10000>; 655 655 + interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 656 656 + clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 657 657 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 658 658 + clock-names = "per", "ipg"; 659 659 + status = "disabled"; 660 660 + }; 661 661 + 662 662 + mu8: mailbox@42730000 { 663 663 + compatible = "fsl,imx95-mu"; 664 664 + reg = <0x42730000 0x10000>; 665 665 + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 666 666 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 667 667 + #mbox-cells = <2>; 668 668 + status = "disabled"; 669 669 + }; 670 670 + }; 671 671 + 672 672 + aips3: bus@42800000 { 673 673 + compatible = "fsl,aips-bus", "simple-bus"; 674 674 + reg = <0 0x42800000 0 0x800000>; 675 675 + #address-cells = <1>; 676 676 + #size-cells = <1>; 677 677 + ranges = <0x42800000 0x0 0x42800000 0x800000>; 678 678 + 679 679 + usdhc1: mmc@42850000 { 680 680 + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 681 681 + reg = <0x42850000 0x10000>; 682 682 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 683 683 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 684 684 + <&scmi_clk IMX95_CLK_WAKEUPAXI>, 685 685 + <&scmi_clk IMX95_CLK_USDHC1>; 686 686 + clock-names = "ipg", "ahb", "per"; 687 687 + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 688 688 + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 689 689 + assigned-clock-rates = <400000000>; 690 690 + bus-width = <8>; 691 691 + fsl,tuning-start-tap = <1>; 692 692 + fsl,tuning-step= <2>; 693 693 + status = "disabled"; 694 694 + }; 695 695 + 696 696 + usdhc2: mmc@42860000 { 697 697 + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 698 698 + reg = <0x42860000 0x10000>; 699 699 + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 700 700 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 701 701 + <&scmi_clk IMX95_CLK_WAKEUPAXI>, 702 702 + <&scmi_clk IMX95_CLK_USDHC2>; 703 703 + clock-names = "ipg", "ahb", "per"; 704 704 + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 705 705 + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 706 706 + assigned-clock-rates = <400000000>; 707 707 + bus-width = <4>; 708 708 + fsl,tuning-start-tap = <1>; 709 709 + fsl,tuning-step= <2>; 710 710 + status = "disabled"; 711 711 + }; 712 712 + 713 713 + usdhc3: mmc@428b0000 { 714 714 + compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 715 715 + reg = <0x428b0000 0x10000>; 716 716 + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 717 717 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 718 718 + <&scmi_clk IMX95_CLK_WAKEUPAXI>, 719 719 + <&scmi_clk IMX95_CLK_USDHC3>; 720 720 + clock-names = "ipg", "ahb", "per"; 721 721 + assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 722 722 + assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 723 723 + assigned-clock-rates = <400000000>; 724 724 + bus-width = <4>; 725 725 + fsl,tuning-start-tap = <1>; 726 726 + fsl,tuning-step= <2>; 727 727 + status = "disabled"; 728 728 + }; 729 729 + }; 730 730 + 731 731 + gpio2: gpio@43810000 { 732 732 + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 733 733 + reg = <0x0 0x43810000 0x0 0x1000>; 734 734 + gpio-controller; 735 735 + #gpio-cells = <2>; 736 736 + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 737 737 + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 738 738 + interrupt-controller; 739 739 + #interrupt-cells = <2>; 740 740 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 741 741 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 742 742 + clock-names = "gpio", "port"; 743 743 + gpio-ranges = <&scmi_iomuxc 0 4 32>; 744 744 + }; 745 745 + 746 746 + gpio3: gpio@43820000 { 747 747 + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 748 748 + reg = <0x0 0x43820000 0x0 0x1000>; 749 749 + gpio-controller; 750 750 + #gpio-cells = <2>; 751 751 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 752 752 + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 753 753 + interrupt-controller; 754 754 + #interrupt-cells = <2>; 755 755 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 756 756 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 757 757 + clock-names = "gpio", "port"; 758 758 + gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 759 759 + <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 760 760 + }; 761 761 + 762 762 + gpio4: gpio@43840000 { 763 763 + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 764 764 + reg = <0x0 0x43840000 0x0 0x1000>; 765 765 + gpio-controller; 766 766 + #gpio-cells = <2>; 767 767 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 768 768 + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 769 769 + interrupt-controller; 770 770 + #interrupt-cells = <2>; 771 771 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 772 772 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 773 773 + clock-names = "gpio", "port"; 774 774 + gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 775 775 + }; 776 776 + 777 777 + gpio5: gpio@43850000 { 778 778 + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 779 779 + reg = <0x0 0x43850000 0x0 0x1000>; 780 780 + gpio-controller; 781 781 + #gpio-cells = <2>; 782 782 + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 783 783 + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 784 784 + interrupt-controller; 785 785 + #interrupt-cells = <2>; 786 786 + clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 787 787 + <&scmi_clk IMX95_CLK_BUSWAKEUP>; 788 788 + clock-names = "gpio", "port"; 789 789 + gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 790 790 + }; 791 791 + 792 792 + aips1: bus@44000000 { 793 793 + compatible = "fsl,aips-bus", "simple-bus"; 794 794 + reg = <0x0 0x44000000 0x0 0x800000>; 795 795 + ranges = <0x44000000 0x0 0x44000000 0x800000>; 796 796 + #address-cells = <1>; 797 797 + #size-cells = <1>; 798 798 + 799 799 + mu1: mailbox@44220000 { 800 800 + compatible = "fsl,imx95-mu"; 801 801 + reg = <0x44220000 0x10000>; 802 802 + interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 803 803 + clocks = <&scmi_clk IMX95_CLK_BUSAON>; 804 804 + #mbox-cells = <2>; 805 805 + status = "disabled"; 806 806 + }; 807 807 + 808 808 + tpm1: pwm@44310000 { 809 809 + compatible = "fsl,imx7ulp-pwm"; 810 810 + reg = <0x44310000 0x1000>; 811 811 + clocks = <&scmi_clk IMX95_CLK_BUSAON>; 812 812 + #pwm-cells = <3>; 813 813 + status = "disabled"; 814 814 + }; 815 815 + 816 816 + tpm2: pwm@44320000 { 817 817 + compatible = "fsl,imx7ulp-pwm"; 818 818 + reg = <0x44320000 0x1000>; 819 819 + clocks = <&scmi_clk IMX95_CLK_TPM2>; 820 820 + #pwm-cells = <3>; 821 821 + status = "disabled"; 822 822 + }; 823 823 + 824 824 + lpi2c1: i2c@44340000 { 825 825 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 826 826 + reg = <0x44340000 0x10000>; 827 827 + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 828 828 + clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 829 829 + <&scmi_clk IMX95_CLK_BUSAON>; 830 830 + clock-names = "per", "ipg"; 831 831 + #address-cells = <1>; 832 832 + #size-cells = <0>; 833 833 + status = "disabled"; 834 834 + }; 835 835 + 836 836 + lpi2c2: i2c@44350000 { 837 837 + compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 838 838 + reg = <0x44350000 0x10000>; 839 839 + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 840 840 + clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 841 841 + <&scmi_clk IMX95_CLK_BUSAON>; 842 842 + clock-names = "per", "ipg"; 843 843 + #address-cells = <1>; 844 844 + #size-cells = <0>; 845 845 + status = "disabled"; 846 846 + }; 847 847 + 848 848 + lpspi1: spi@44360000 { 849 849 + #address-cells = <1>; 850 850 + #size-cells = <0>; 851 851 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 852 852 + reg = <0x44360000 0x10000>; 853 853 + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 854 854 + clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 855 855 + <&scmi_clk IMX95_CLK_BUSAON>; 856 856 + clock-names = "per", "ipg"; 857 857 + status = "disabled"; 858 858 + }; 859 859 + 860 860 + lpspi2: spi@44370000 { 861 861 + #address-cells = <1>; 862 862 + #size-cells = <0>; 863 863 + compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 864 864 + reg = <0x44370000 0x10000>; 865 865 + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 866 866 + clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 867 867 + <&scmi_clk IMX95_CLK_BUSAON>; 868 868 + clock-names = "per", "ipg"; 869 869 + status = "disabled"; 870 870 + }; 871 871 + 872 872 + lpuart1: serial@44380000 { 873 873 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 874 874 + "fsl,imx7ulp-lpuart"; 875 875 + reg = <0x44380000 0x1000>; 876 876 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 877 877 + clocks = <&scmi_clk IMX95_CLK_LPUART1>; 878 878 + clock-names = "ipg"; 879 879 + status = "disabled"; 880 880 + }; 881 881 + 882 882 + lpuart2: serial@44390000 { 883 883 + compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 884 884 + "fsl,imx7ulp-lpuart"; 885 885 + reg = <0x44390000 0x1000>; 886 886 + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 887 887 + clocks = <&scmi_clk IMX95_CLK_LPUART2>; 888 888 + clock-names = "ipg"; 889 889 + status = "disabled"; 890 890 + }; 891 891 + 892 892 + adc1: adc@44530000 { 893 893 + compatible = "nxp,imx93-adc"; 894 894 + reg = <0x44530000 0x10000>; 895 895 + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 896 896 + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 897 897 + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 898 898 + clocks = <&scmi_clk IMX95_CLK_ADC>; 899 899 + clock-names = "ipg"; 900 900 + status = "disabled"; 901 901 + }; 902 902 + 903 903 + mu2: mailbox@445b0000 { 904 904 + compatible = "fsl,imx95-mu"; 905 905 + reg = <0x445b0000 0x1000>; 906 906 + ranges; 907 907 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 908 908 + #address-cells = <1>; 909 909 + #size-cells = <1>; 910 910 + #mbox-cells = <2>; 911 911 + 912 912 + sram0: sram@445b1000 { 913 913 + compatible = "mmio-sram"; 914 914 + reg = <0x445b1000 0x400>; 915 915 + ranges = <0x0 0x445b1000 0x400>; 916 916 + #address-cells = <1>; 917 917 + #size-cells = <1>; 918 918 + 919 919 + scmi_buf0: scmi-sram-section@0 { 920 920 + compatible = "arm,scmi-shmem"; 921 921 + reg = <0x0 0x80>; 922 922 + }; 923 923 + 924 924 + scmi_buf1: scmi-sram-section@80 { 925 925 + compatible = "arm,scmi-shmem"; 926 926 + reg = <0x80 0x80>; 927 927 + }; 928 928 + }; 929 929 + 930 930 + }; 931 931 + 932 932 + mu3: mailbox@445d0000 { 933 933 + compatible = "fsl,imx95-mu"; 934 934 + reg = <0x445d0000 0x10000>; 935 935 + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 936 936 + clocks = <&scmi_clk IMX95_CLK_BUSAON>; 937 937 + #mbox-cells = <2>; 938 938 + status = "disabled"; 939 939 + }; 940 940 + 941 941 + mu4: mailbox@445f0000 { 942 942 + compatible = "fsl,imx95-mu"; 943 943 + reg = <0x445f0000 0x10000>; 944 944 + interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 945 945 + clocks = <&scmi_clk IMX95_CLK_BUSAON>; 946 946 + #mbox-cells = <2>; 947 947 + status = "disabled"; 948 948 + }; 949 949 + 950 950 + mu6: mailbox@44630000 { 951 951 + compatible = "fsl,imx95-mu"; 952 952 + reg = <0x44630000 0x10000>; 953 953 + interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 954 954 + clocks = <&scmi_clk IMX95_CLK_BUSAON>; 955 955 + #mbox-cells = <2>; 956 956 + status = "disabled"; 957 957 + }; 958 958 + }; 959 959 + 960 960 + mailbox@47320000 { 961 961 + compatible = "fsl,imx95-mu-v2x"; 962 962 + reg = <0x0 0x47320000 0x0 0x10000>; 963 963 + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 964 964 + #mbox-cells = <2>; 965 965 + }; 966 966 + 967 967 + mailbox@47350000 { 968 968 + compatible = "fsl,imx95-mu-v2x"; 969 969 + reg = <0x0 0x47350000 0x0 0x10000>; 970 970 + interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 971 971 + #mbox-cells = <2>; 972 972 + }; 973 973 + 974 974 + /* GPIO1 is under exclusive control of System Manager */ 975 975 + gpio1: gpio@47400000 { 976 976 + compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 977 977 + reg = <0x0 0x47400000 0x0 0x1000>; 978 978 + gpio-controller; 979 979 + #gpio-cells = <2>; 980 980 + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 981 981 + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 982 982 + interrupt-controller; 983 983 + #interrupt-cells = <2>; 984 984 + clocks = <&scmi_clk IMX95_CLK_M33>, 985 985 + <&scmi_clk IMX95_CLK_M33>; 986 986 + clock-names = "gpio", "port"; 987 987 + gpio-ranges = <&scmi_iomuxc 0 112 16>; 988 988 + status = "disabled"; 989 989 + }; 990 990 + 991 991 + elemu0: mailbox@47520000 { 992 992 + compatible = "fsl,imx95-mu-ele"; 993 993 + reg = <0x0 0x47520000 0x0 0x10000>; 994 994 + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 995 995 + #mbox-cells = <2>; 996 996 + status = "disabled"; 997 997 + }; 998 998 + 999 999 + elemu1: mailbox@47530000 { 1000 1000 + compatible = "fsl,imx95-mu-ele"; 1001 1001 + reg = <0x0 0x47530000 0x0 0x10000>; 1002 1002 + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1003 1003 + #mbox-cells = <2>; 1004 1004 + status = "disabled"; 1005 1005 + }; 1006 1006 + 1007 1007 + elemu2: mailbox@47540000 { 1008 1008 + compatible = "fsl,imx95-mu-ele"; 1009 1009 + reg = <0x0 0x47540000 0x0 0x10000>; 1010 1010 + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1011 1011 + #mbox-cells = <2>; 1012 1012 + status = "disabled"; 1013 1013 + }; 1014 1014 + 1015 1015 + elemu3: mailbox@47550000 { 1016 1016 + compatible = "fsl,imx95-mu-ele"; 1017 1017 + reg = <0x0 0x47550000 0x0 0x10000>; 1018 1018 + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1019 1019 + #mbox-cells = <2>; 1020 1020 + }; 1021 1021 + 1022 1022 + elemu4: mailbox@47560000 { 1023 1023 + compatible = "fsl,imx95-mu-ele"; 1024 1024 + reg = <0x0 0x47560000 0x0 0x10000>; 1025 1025 + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1026 1026 + #mbox-cells = <2>; 1027 1027 + status = "disabled"; 1028 1028 + }; 1029 1029 + 1030 1030 + elemu5: mailbox@47570000 { 1031 1031 + compatible = "fsl,imx95-mu-ele"; 1032 1032 + reg = <0x0 0x47570000 0x0 0x10000>; 1033 1033 + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1034 1034 + #mbox-cells = <2>; 1035 1035 + status = "disabled"; 1036 1036 + }; 1037 1037 + 1038 1038 + aips4: bus@49000000 { 1039 1039 + compatible = "fsl,aips-bus", "simple-bus"; 1040 1040 + reg = <0x0 0x49000000 0x0 0x800000>; 1041 1041 + ranges = <0x49000000 0x0 0x49000000 0x800000>; 1042 1042 + #address-cells = <1>; 1043 1043 + #size-cells = <1>; 1044 1044 + 1045 1045 + smmu: iommu@490d0000 { 1046 1046 + compatible = "arm,smmu-v3"; 1047 1047 + reg = <0x490d0000 0x100000>; 1048 1048 + interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1049 1049 + <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1050 1050 + <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1051 1051 + <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1052 1052 + interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1053 1053 + #iommu-cells = <1>; 1054 1054 + status = "disabled"; 1055 1055 + }; 1056 1056 + }; 1057 1057 + 1058 1058 + pcie0: pcie@4c300000 { 1059 1059 + compatible = "fsl,imx95-pcie"; 1060 1060 + reg = <0 0x4c300000 0 0x10000>, 1061 1061 + <0 0x60100000 0 0xfe00000>, 1062 1062 + <0 0x4c360000 0 0x10000>, 1063 1063 + <0 0x4c340000 0 0x2000>; 1064 1064 + reg-names = "dbi", "config", "atu", "app"; 1065 1065 + ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1066 1066 + <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1067 1067 + #address-cells = <3>; 1068 1068 + #size-cells = <2>; 1069 1069 + device_type = "pci"; 1070 1070 + linux,pci-domain = <0>; 1071 1071 + bus-range = <0x00 0xff>; 1072 1072 + num-lanes = <1>; 1073 1073 + num-viewport = <8>; 1074 1074 + interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1075 1075 + interrupt-names = "msi"; 1076 1076 + #interrupt-cells = <1>; 1077 1077 + interrupt-map-mask = <0 0 0 0x7>; 1078 1078 + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1079 1079 + <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1080 1080 + <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1081 1081 + <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1082 1082 + clocks = <&scmi_clk IMX95_CLK_HSIO>, 1083 1083 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1084 1084 + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1085 1085 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1086 1086 + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1087 1087 + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1088 1088 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1089 1089 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1090 1090 + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1091 1091 + assigned-clock-parents = <0>, <0>, 1092 1092 + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1093 1093 + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1094 1094 + fsl,max-link-speed = <3>; 1095 1095 + status = "disabled"; 1096 1096 + }; 1097 1097 + 1098 1098 + pcie0_ep: pcie-ep@4c300000 { 1099 1099 + compatible = "fsl,imx95-pcie-ep"; 1100 1100 + reg = <0 0x4c300000 0 0x10000>, 1101 1101 + <0 0x4c360000 0 0x1000>, 1102 1102 + <0 0x4c320000 0 0x1000>, 1103 1103 + <0 0x4c340000 0 0x2000>, 1104 1104 + <0 0x4c370000 0 0x10000>, 1105 1105 + <0x9 0 1 0>; 1106 1106 + reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1107 1107 + num-lanes = <1>; 1108 1108 + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1109 1109 + interrupt-names = "dma"; 1110 1110 + clocks = <&scmi_clk IMX95_CLK_HSIO>, 1111 1111 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1112 1112 + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1113 1113 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1114 1114 + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1115 1115 + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1116 1116 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1117 1117 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1118 1118 + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1119 1119 + assigned-clock-parents = <0>, <0>, 1120 1120 + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1121 1121 + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1122 1122 + status = "disabled"; 1123 1123 + }; 1124 1124 + 1125 1125 + pcie1: pcie@4c380000 { 1126 1126 + compatible = "fsl,imx95-pcie"; 1127 1127 + reg = <0 0x4c380000 0 0x10000>, 1128 1128 + <8 0x80100000 0 0xfe00000>, 1129 1129 + <0 0x4c3e0000 0 0x10000>, 1130 1130 + <0 0x4c3c0000 0 0x2000>; 1131 1131 + reg-names = "dbi", "config", "atu", "app"; 1132 1132 + ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1133 1133 + <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1134 1134 + #address-cells = <3>; 1135 1135 + #size-cells = <2>; 1136 1136 + device_type = "pci"; 1137 1137 + linux,pci-domain = <1>; 1138 1138 + bus-range = <0x00 0xff>; 1139 1139 + num-lanes = <1>; 1140 1140 + num-viewport = <8>; 1141 1141 + interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1142 1142 + interrupt-names = "msi"; 1143 1143 + #interrupt-cells = <1>; 1144 1144 + interrupt-map-mask = <0 0 0 0x7>; 1145 1145 + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1146 1146 + <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1147 1147 + <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1148 1148 + <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1149 1149 + clocks = <&scmi_clk IMX95_CLK_HSIO>, 1150 1150 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1151 1151 + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1152 1152 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1153 1153 + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1154 1154 + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1155 1155 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1156 1156 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1157 1157 + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1158 1158 + assigned-clock-parents = <0>, <0>, 1159 1159 + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1160 1160 + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1161 1161 + fsl,max-link-speed = <3>; 1162 1162 + status = "disabled"; 1163 1163 + }; 1164 1164 + 1165 1165 + pcie1_ep: pcie-ep@4c380000 { 1166 1166 + compatible = "fsl,imx95-pcie-ep"; 1167 1167 + reg = <0 0x4c380000 0 0x10000>, 1168 1168 + <0 0x4c3e0000 0 0x1000>, 1169 1169 + <0 0x4c3a0000 0 0x1000>, 1170 1170 + <0 0x4c3c0000 0 0x2000>, 1171 1171 + <0 0x4c3f0000 0 0x10000>, 1172 1172 + <0xa 0 1 0>; 1173 1173 + reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1174 1174 + num-lanes = <1>; 1175 1175 + interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1176 1176 + interrupt-names = "dma"; 1177 1177 + clocks = <&scmi_clk IMX95_CLK_HSIO>, 1178 1178 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1179 1179 + <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1180 1180 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1181 1181 + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1182 1182 + assigned-clocks =<&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1183 1183 + <&scmi_clk IMX95_CLK_HSIOPLL>, 1184 1184 + <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1185 1185 + assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1186 1186 + assigned-clock-parents = <0>, <0>, 1187 1187 + <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1188 1188 + power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1189 1189 + status = "disabled"; 1190 1190 + }; 1191 1191 + }; 1192 1192 + };

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi

reviewed

··· 32 32 mdio@f1000 { 33 33 #address-cells = <1>; 34 34 #size-cells = <0>; 35 35 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 35 35 + compatible = "fsl,fman-memac-mdio"; 36 36 reg = <0xf1000 0x1000>; 37 37 38 38 pcsphy6: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi

reviewed

··· 32 32 mdio@f3000 { 33 33 #address-cells = <1>; 34 34 #size-cells = <0>; 35 35 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 35 35 + compatible = "fsl,fman-memac-mdio"; 36 36 reg = <0xf3000 0x1000>; 37 37 38 38 pcsphy7: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi

reviewed

··· 31 31 mdio@e1000 { 32 32 #address-cells = <1>; 33 33 #size-cells = <0>; 34 34 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 34 34 + compatible = "fsl,fman-memac-mdio"; 35 35 reg = <0xe1000 0x1000>; 36 36 37 37 pcsphy0: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi

reviewed

··· 31 31 mdio@e3000 { 32 32 #address-cells = <1>; 33 33 #size-cells = <0>; 34 34 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 34 34 + compatible = "fsl,fman-memac-mdio"; 35 35 reg = <0xe3000 0x1000>; 36 36 37 37 pcsphy1: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi

reviewed

··· 31 31 mdio@e5000 { 32 32 #address-cells = <1>; 33 33 #size-cells = <0>; 34 34 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 34 34 + compatible = "fsl,fman-memac-mdio"; 35 35 reg = <0xe5000 0x1000>; 36 36 37 37 pcsphy2: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi

reviewed

··· 31 31 mdio@e7000 { 32 32 #address-cells = <1>; 33 33 #size-cells = <0>; 34 34 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 34 34 + compatible = "fsl,fman-memac-mdio"; 35 35 reg = <0xe7000 0x1000>; 36 36 37 37 pcsphy3: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi

reviewed

··· 31 31 mdio@e9000 { 32 32 #address-cells = <1>; 33 33 #size-cells = <0>; 34 34 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 34 34 + compatible = "fsl,fman-memac-mdio"; 35 35 reg = <0xe9000 0x1000>; 36 36 37 37 pcsphy4: ethernet-phy@0 {

+1 -1

arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi

reviewed

··· 31 31 mdio@eb000 { 32 32 #address-cells = <1>; 33 33 #size-cells = <0>; 34 34 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 34 34 + compatible = "fsl,fman-memac-mdio"; 35 35 reg = <0xeb000 0x1000>; 36 36 37 37 pcsphy5: ethernet-phy@0 {

+2 -2

arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi

reviewed

··· 67 67 mdio0: mdio@fc000 { 68 68 #address-cells = <1>; 69 69 #size-cells = <0>; 70 70 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 70 70 + compatible = "fsl,fman-memac-mdio"; 71 71 reg = <0xfc000 0x1000>; 72 72 }; 73 73 74 74 xmdio0: mdio@fd000 { 75 75 #address-cells = <1>; 76 76 #size-cells = <0>; 77 77 - compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; 77 77 + compatible = "fsl,fman-memac-mdio"; 78 78 reg = <0xfd000 0x1000>; 79 79 }; 80 80 };

+6 -2

arch/arm64/boot/dts/freescale/tqma8xx.dtsi

reviewed

··· 61 61 62 62 flash0: flash@0 { 63 63 reg = <0>; 64 64 - #address-cells = <1>; 65 65 - #size-cells = <1>; 66 64 compatible = "jedec,spi-nor"; 67 65 spi-max-frequency = <66000000>; 68 66 spi-tx-bus-width = <1>; 69 67 spi-rx-bus-width = <4>; 68 68 + 69 69 + partitions { 70 70 + compatible = "fixed-partitions"; 71 71 + #address-cells = <1>; 72 72 + #size-cells = <1>; 73 73 + }; 70 74 }; 71 75 }; 72 76