clk: qcom: gcc-msm8994: Add missing clocks

+143

2 changed files

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drivers

clk

qcom

gcc-msm8994.c

include

dt-bindings

clock

qcom,gcc-msm8994.h

+134

drivers/clk/qcom/gcc-msm8994.c

··· 2319 2319 }, 2320 2320 }; 2321 2321 2322 + static struct clk_branch gcc_usb3_phy_pipe_clk = { 2323 + .halt_reg = 0x140c, 2324 + .halt_check = BRANCH_HALT_SKIP, 2325 + .clkr = { 2326 + .enable_reg = 0x140c, 2327 + .enable_mask = BIT(0), 2328 + .hw.init = &(struct clk_init_data){ 2329 + .name = "gcc_usb3_phy_pipe_clk", 2330 + .ops = &clk_branch2_ops, 2331 + }, 2332 + }, 2333 + }; 2334 + 2322 2335 static struct clk_branch gcc_usb_hs_ahb_clk = { 2323 2336 .halt_reg = 0x0488, 2324 2337 .clkr = { ··· 2368 2355 .enable_mask = BIT(0), 2369 2356 .hw.init = &(struct clk_init_data){ 2370 2357 .name = "gcc_usb_phy_cfg_ahb2phy_clk", 2358 + .ops = &clk_branch2_ops, 2359 + }, 2360 + }, 2361 + }; 2362 + 2363 + static struct clk_branch gpll0_out_mmsscc = { 2364 + .halt_check = BRANCH_HALT_DELAY, 2365 + .clkr = { 2366 + .enable_reg = 0x1484, 2367 + .enable_mask = BIT(26), 2368 + .hw.init = &(struct clk_init_data){ 2369 + .name = "gpll0_out_mmsscc", 2370 + .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2371 + .num_parents = 1, 2372 + .ops = &clk_branch2_ops, 2373 + }, 2374 + }, 2375 + }; 2376 + 2377 + static struct clk_branch gpll0_out_msscc = { 2378 + .halt_check = BRANCH_HALT_DELAY, 2379 + .clkr = { 2380 + .enable_reg = 0x1484, 2381 + .enable_mask = BIT(27), 2382 + .hw.init = &(struct clk_init_data){ 2383 + .name = "gpll0_out_msscc", 2384 + .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw }, 2385 + .num_parents = 1, 2386 + .ops = &clk_branch2_ops, 2387 + }, 2388 + }, 2389 + }; 2390 + 2391 + static struct clk_branch pcie_0_phy_ldo = { 2392 + .halt_reg = 0x1e00, 2393 + .halt_check = BRANCH_HALT_SKIP, 2394 + .clkr = { 2395 + .enable_reg = 0x1E00, 2396 + .enable_mask = BIT(0), 2397 + .hw.init = &(struct clk_init_data){ 2398 + .name = "pcie_0_phy_ldo", 2399 + .ops = &clk_branch2_ops, 2400 + }, 2401 + }, 2402 + }; 2403 + 2404 + static struct clk_branch pcie_1_phy_ldo = { 2405 + .halt_reg = 0x1e04, 2406 + .halt_check = BRANCH_HALT_SKIP, 2407 + .clkr = { 2408 + .enable_reg = 0x1E04, 2409 + .enable_mask = BIT(0), 2410 + .hw.init = &(struct clk_init_data){ 2411 + .name = "pcie_1_phy_ldo", 2412 + .ops = &clk_branch2_ops, 2413 + }, 2414 + }, 2415 + }; 2416 + 2417 + static struct clk_branch ufs_phy_ldo = { 2418 + .halt_reg = 0x1e0c, 2419 + .halt_check = BRANCH_HALT_SKIP, 2420 + .clkr = { 2421 + .enable_reg = 0x1E0C, 2422 + .enable_mask = BIT(0), 2423 + .hw.init = &(struct clk_init_data){ 2424 + .name = "ufs_phy_ldo", 2425 + .ops = &clk_branch2_ops, 2426 + }, 2427 + }, 2428 + }; 2429 + 2430 + static struct clk_branch usb_ss_phy_ldo = { 2431 + .halt_reg = 0x1e08, 2432 + .halt_check = BRANCH_HALT_SKIP, 2433 + .clkr = { 2434 + .enable_reg = 0x1E08, 2435 + .enable_mask = BIT(0), 2436 + .hw.init = &(struct clk_init_data){ 2437 + .name = "usb_ss_phy_ldo", 2438 + .ops = &clk_branch2_ops, 2439 + }, 2440 + }, 2441 + }; 2442 + 2443 + static struct clk_branch gcc_boot_rom_ahb_clk = { 2444 + .halt_reg = 0x0e04, 2445 + .halt_check = BRANCH_HALT_VOTED, 2446 + .hwcg_reg = 0x0e04, 2447 + .hwcg_bit = 1, 2448 + .clkr = { 2449 + .enable_reg = 0x1484, 2450 + .enable_mask = BIT(10), 2451 + .hw.init = &(struct clk_init_data){ 2452 + .name = "gcc_boot_rom_ahb_clk", 2453 + .parent_hws = (const struct clk_hw *[]){ &config_noc_clk_src.clkr.hw }, 2454 + .num_parents = 1, 2455 + .ops = &clk_branch2_ops, 2456 + }, 2457 + }, 2458 + }; 2459 + 2460 + static struct clk_branch gcc_prng_ahb_clk = { 2461 + .halt_reg = 0x0d04, 2462 + .halt_check = BRANCH_HALT_VOTED, 2463 + .clkr = { 2464 + .enable_reg = 0x1484, 2465 + .enable_mask = BIT(13), 2466 + .hw.init = &(struct clk_init_data){ 2467 + .name = "gcc_prng_ahb_clk", 2468 + .parent_hws = (const struct clk_hw *[]){ &periph_noc_clk_src.clkr.hw }, 2469 + .num_parents = 1, 2371 2470 .ops = &clk_branch2_ops, 2372 2471 }, 2373 2472 }, ··· 2667 2542 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr, 2668 2543 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr, 2669 2544 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr, 2545 + [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr, 2670 2546 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2671 2547 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2672 2548 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr, 2549 + [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr, 2550 + [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr, 2551 + [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr, 2552 + [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr, 2553 + [UFS_PHY_LDO] = &ufs_phy_ldo.clkr, 2554 + [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr, 2555 + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2556 + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2673 2557 }; 2674 2558 2675 2559 static struct gdsc *gcc_msm8994_gdscs[] = {

include/dt-bindings/clock/qcom,gcc-msm8994.h

··· 151 151 #define CONFIG_NOC_CLK_SRC 141 152 152 #define PERIPH_NOC_CLK_SRC 142 153 153 #define SYSTEM_NOC_CLK_SRC 143 154 + #define GPLL0_OUT_MMSSCC 144 155 + #define GPLL0_OUT_MSSCC 145 156 + #define PCIE_0_PHY_LDO 146 157 + #define PCIE_1_PHY_LDO 147 158 + #define UFS_PHY_LDO 148 159 + #define USB_SS_PHY_LDO 149 160 + #define GCC_BOOT_ROM_AHB_CLK 150 161 + #define GCC_PRNG_AHB_CLK 151 162 + #define GCC_USB3_PHY_PIPE_CLK 152 154 163 155 164 /* GDSCs */ 156 165 #define PCIE_GDSC 0

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