Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'dmaengine-fix-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine fixes from Vinod Koul:
- tegra210 div_u64 divison and max page fixes
- revert Qualcomm unavailable register workaround which is causing
regression, fixes have been proposed but still gaps are present so
revert this for now
* tag 'dmaengine-fix-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine:
dmaengine: Revert "dmaengine: qcom: bam_dma: Avoid writing unavailable register"
dmaengine: tegra210-adma: check for adma max page
dmaengine: tegra210-adma: Use div_u64 for 64 bit division
+13
-16
+8
-16
drivers/dma/qcom/bam_dma.c
+8
-16
drivers/dma/qcom/bam_dma.c
···
59
59
#define DESC_FLAG_NWD BIT(12)
60
60
#define DESC_FLAG_CMD BIT(11)
61
61
62
-
#define BAM_NDP_REVISION_START 0x20
63
-
#define BAM_NDP_REVISION_END 0x27
64
-
65
62
struct bam_async_desc {
66
63
struct virt_dma_desc vd;
67
64
···
398
401
399
402
/* dma start transaction tasklet */
400
403
struct tasklet_struct task;
401
-
u32 bam_revision;
402
404
};
403
405
404
406
/**
···
441
445
writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
442
446
443
447
/* set descriptor threshold, start with 4 bytes */
444
-
if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,
445
-
BAM_NDP_REVISION_END))
446
-
writel_relaxed(DEFAULT_CNT_THRSHLD,
447
-
bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
448
+
writel_relaxed(DEFAULT_CNT_THRSHLD,
449
+
bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
448
450
449
451
/* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
450
452
writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
···
1000
1006
maxburst = bchan->slave.src_maxburst;
1001
1007
else
1002
1008
maxburst = bchan->slave.dst_maxburst;
1003
-
if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,
1004
-
BAM_NDP_REVISION_END))
1005
-
writel_relaxed(maxburst,
1006
-
bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
1009
+
1010
+
writel_relaxed(maxburst,
1011
+
bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
1007
1012
}
1008
1013
1009
1014
bchan->reconfigure = 0;
···
1192
1199
u32 val;
1193
1200
1194
1201
/* read revision and configuration information */
1195
-
val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
1196
-
if (!bdev->num_ees)
1202
+
if (!bdev->num_ees) {
1203
+
val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
1197
1204
bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;
1198
-
1199
-
bdev->bam_revision = val & REVISION_MASK;
1205
+
}
1200
1206
1201
1207
/* check that configured EE is within range */
1202
1208
if (bdev->ee >= bdev->num_ees)
+5
drivers/dma/tegra210-adma.c
+5
drivers/dma/tegra210-adma.c
···
83
83
* @nr_channels: Number of DMA channels available.
84
84
* @ch_fifo_size_mask: Mask for FIFO size field.
85
85
* @sreq_index_offset: Slave channel index offset.
86
+
* @max_page: Maximum ADMA Channel Page.
86
87
* @has_outstanding_reqs: If DMA channel can have outstanding requests.
88
+
* @set_global_pg_config: Global page programming.
87
89
*/
88
90
struct tegra_adma_chip_data {
89
91
unsigned int (*adma_get_burst_config)(unsigned int burst_size);
···
101
99
unsigned int nr_channels;
102
100
unsigned int ch_fifo_size_mask;
103
101
unsigned int sreq_index_offset;
102
+
unsigned int max_page;
104
103
bool has_outstanding_reqs;
105
104
void (*set_global_pg_config)(struct tegra_adma *tdma);
106
105
};
···
857
854
.nr_channels = 22,
858
855
.ch_fifo_size_mask = 0xf,
859
856
.sreq_index_offset = 2,
857
+
.max_page = 0,
860
858
.has_outstanding_reqs = false,
861
859
.set_global_pg_config = NULL,
862
860
};
···
875
871
.nr_channels = 32,
876
872
.ch_fifo_size_mask = 0x1f,
877
873
.sreq_index_offset = 4,
874
+
.max_page = 4,
878
875
.has_outstanding_reqs = true,
879
876
.set_global_pg_config = tegra186_adma_global_page_config,
880
877
};