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Merge branch 'net-phy-bcm54811-phy-initialization'

says:

====================
net: phy: bcm54811: PHY initialization

Proper bcm54811 PHY driver initialization for MII-Lite.

The bcm54811 PHY in MLP package must be setup for MII-Lite interface
mode by software. Normally, the PHY to MAC interface is selected in
hardware by setting the bootstrap pins of the PHY. However, MII and
MII-Lite share the same hardware setup and must be distinguished by
software, setting appropriate bit in a configuration register.
The MII-Lite interface mode is non-standard one, defined by Broadcom
for some of their PHYs. The MII-Lite lightness consist in omitting
RXER, TXER, CRS and COL signals of the standard MII interface.
Absence of COL them makes half-duplex links modes impossible but
does not interfere with Broadcom's BroadR-Reach link modes, because
they are full-duplex only.
To do it in a clean way, MII-Lite must be introduced first, including
its limitation to link modes (no half-duplex), because it is a
prerequisite for the patch #3 of this series. The patch #4 does not
depend on MII-Lite directly but both #3 and #4 are necessary for
bcm54811 to work properly without additional configuration steps to be
done - for example in the bootloader, before the kernel starts.

PATCH 1 - Add MII-Lite PHY interface mode as defined by Broadcom for
their two-wire PHYs. It can be used with most Ethernet controllers
under certain limitations (no half-duplex link modes etc.).

PATCH 2 - Add MII-Lite PHY interface type

PATCH 3 - Activation of MII-Lite interface mode on Broadcom bcm5481x
PHYs

PATCH 4 - Initialize the BCM54811 PHY properly so that it conforms
to the datasheet regarding a reserved bit in the LRE Control
register, which must be written to zero after every device reset.
Ignore the LDS capability bit in LRE Status register on bcm54811.
====================

Link: https://patch.msgid.link/20250708090140.61355-1-kamilh@axis.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

+58 -5
+1
Documentation/devicetree/bindings/net/ethernet-controller.yaml
··· 39 39 # MAC. 40 40 - internal 41 41 - mii 42 + - mii-lite 42 43 - gmii 43 44 - sgmii 44 45 - psgmii
+7
Documentation/networking/phy.rst
··· 333 333 SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved 334 334 through symbol replication. The PCS expects the standard USXGMII code word. 335 335 336 + ``PHY_INTERFACE_MODE_MIILITE`` 337 + Non-standard, simplified MII mode, without TXER, RXER, CRS and COL signals 338 + as defined for the MII. The absence of COL signal makes half-duplex link 339 + modes impossible but does not interfere with BroadR-Reach link modes on 340 + Broadcom (and other two-wire Ethernet) PHYs, because they are full-duplex 341 + only. 342 + 336 343 Pause frames / flow control 337 344 =========================== 338 345
+34 -5
drivers/net/phy/broadcom.c
··· 407 407 static int bcm54811_config_init(struct phy_device *phydev) 408 408 { 409 409 struct bcm54xx_phy_priv *priv = phydev->priv; 410 - int err, reg; 410 + int err, reg, exp_sync_ethernet; 411 411 412 412 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */ 413 413 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) { ··· 423 423 /* With BCM54811, BroadR-Reach implies no autoneg */ 424 424 if (priv->brr_mode) 425 425 phydev->autoneg = 0; 426 + 427 + /* Enable MII Lite (No TXER, RXER, CRS, COL) if configured */ 428 + if (phydev->interface == PHY_INTERFACE_MODE_MIILITE) 429 + exp_sync_ethernet = BCM_EXP_SYNC_ETHERNET_MII_LITE; 430 + else 431 + exp_sync_ethernet = 0; 432 + 433 + err = bcm_phy_modify_exp(phydev, BCM_EXP_SYNC_ETHERNET, 434 + BCM_EXP_SYNC_ETHERNET_MII_LITE, 435 + exp_sync_ethernet); 436 + if (err < 0) 437 + return err; 426 438 427 439 return bcm5481x_set_brrmode(phydev, priv->brr_mode); 428 440 } ··· 667 655 { 668 656 struct device_node *np = phydev->mdio.dev.of_node; 669 657 struct bcm54xx_phy_priv *priv = phydev->priv; 670 - int i, val, err; 658 + int i, val, err, aneg; 671 659 672 660 for (i = 0; i < ARRAY_SIZE(bcm54811_linkmodes); i++) 673 661 linkmode_clear_bit(bcm54811_linkmodes[i], phydev->supported); ··· 688 676 if (val < 0) 689 677 return val; 690 678 679 + /* BCM54811 is not capable of LDS but the corresponding bit 680 + * in LRESR is set to 1 and marked "Ignore" in the datasheet. 681 + * So we must read the bcm54811 as unable to auto-negotiate 682 + * in BroadR-Reach mode. 683 + */ 684 + if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811) 685 + aneg = 0; 686 + else 687 + aneg = val & LRESR_LDSABILITY; 688 + 691 689 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 692 690 phydev->supported, 693 - val & LRESR_LDSABILITY); 691 + aneg); 694 692 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT1_Full_BIT, 695 693 phydev->supported, 696 694 val & LRESR_100_1PAIR); ··· 757 735 758 736 /* Aneg firstly. */ 759 737 if (priv->brr_mode) { 760 - /* BCM54811 is only capable of autonegotiation in IEEE mode */ 761 - phydev->autoneg = 0; 738 + /* BCM54811 is only capable of autonegotiation in IEEE mode. 739 + * In BroadR-Reach mode, disable the Long Distance Signaling, 740 + * the BRR mode autoneg as supported in other Broadcom PHYs. 741 + * This bit is marked as "Reserved" and "Default 1, must be 742 + * written to 0 after every device reset" in the datasheet. 743 + */ 744 + ret = phy_modify(phydev, MII_BCM54XX_LRECR, LRECR_LDSEN, 0); 745 + if (ret < 0) 746 + return ret; 762 747 ret = bcm_config_lre_aneg(phydev, false); 763 748 } else { 764 749 ret = genphy_config_aneg(phydev);
+1
drivers/net/phy/phy-core.c
··· 115 115 return 0; 116 116 case PHY_INTERFACE_MODE_INTERNAL: 117 117 case PHY_INTERFACE_MODE_MII: 118 + case PHY_INTERFACE_MODE_MIILITE: 118 119 case PHY_INTERFACE_MODE_GMII: 119 120 case PHY_INTERFACE_MODE_TBI: 120 121 case PHY_INTERFACE_MODE_REVMII:
+4
drivers/net/phy/phy_caps.c
··· 316 316 link_caps |= BIT(LINK_CAPA_100HD) | BIT(LINK_CAPA_100FD); 317 317 break; 318 318 319 + case PHY_INTERFACE_MODE_MIILITE: 320 + link_caps |= BIT(LINK_CAPA_10FD) | BIT(LINK_CAPA_100FD); 321 + break; 322 + 319 323 case PHY_INTERFACE_MODE_TBI: 320 324 case PHY_INTERFACE_MODE_MOCA: 321 325 case PHY_INTERFACE_MODE_RTBI:
+1
drivers/net/phy/phylink.c
··· 237 237 case PHY_INTERFACE_MODE_SMII: 238 238 case PHY_INTERFACE_MODE_REVMII: 239 239 case PHY_INTERFACE_MODE_MII: 240 + case PHY_INTERFACE_MODE_MIILITE: 240 241 return SPEED_100; 241 242 242 243 case PHY_INTERFACE_MODE_TBI:
+6
include/linux/brcmphy.h
··· 183 183 #define BCM_LED_MULTICOLOR_PROGRAM 0xa 184 184 185 185 /* 186 + * Broadcom Synchronous Ethernet Controls (expansion register 0x0E) 187 + */ 188 + #define BCM_EXP_SYNC_ETHERNET (MII_BCM54XX_EXP_SEL_ER + 0x0E) 189 + #define BCM_EXP_SYNC_ETHERNET_MII_LITE BIT(11) 190 + 191 + /* 186 192 * BCM5482: Shadow registers 187 193 * Shadow values go into bits [14:10] of register 0x1c to select a shadow 188 194 * register to access.
+4
include/linux/phy.h
··· 106 106 * @PHY_INTERFACE_MODE_50GBASER: 50GBase-R - with Clause 134 FEC 107 107 * @PHY_INTERFACE_MODE_LAUI: 50 Gigabit Attachment Unit Interface 108 108 * @PHY_INTERFACE_MODE_100GBASEP: 100GBase-P - with Clause 134 FEC 109 + * @PHY_INTERFACE_MODE_MIILITE: MII-Lite - MII without RXER TXER CRS COL 109 110 * @PHY_INTERFACE_MODE_MAX: Book keeping 110 111 * 111 112 * Describes the interface between the MAC and PHY. ··· 151 150 PHY_INTERFACE_MODE_50GBASER, 152 151 PHY_INTERFACE_MODE_LAUI, 153 152 PHY_INTERFACE_MODE_100GBASEP, 153 + PHY_INTERFACE_MODE_MIILITE, 154 154 PHY_INTERFACE_MODE_MAX, 155 155 } phy_interface_t; 156 156 ··· 274 272 return "laui"; 275 273 case PHY_INTERFACE_MODE_100GBASEP: 276 274 return "100gbase-p"; 275 + case PHY_INTERFACE_MODE_MIILITE: 276 + return "mii-lite"; 277 277 default: 278 278 return "unknown"; 279 279 }