Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Bluetooth: btintel_pcie: Read hardware exception data
On hardware error, controller writes hardware error event and optional
vendor specific hci events in device memory in TLV format and raises
MSIX interrupt. Driver reads the device memory and passes the events to
the stack for further processing.
Co-developed-by: Vijay Satija <vijay.satija@intel.com>
Signed-off-by: Vijay Satija <vijay.satija@intel.com>
Signed-off-by: Kiran K <kiran.k@intel.com>
Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
authored by
Kiran K
and committed by
Luiz Augusto von Dentz
b9465e66
6ed83047
+247
-1
+1
drivers/bluetooth/btintel.h
+1
drivers/bluetooth/btintel.h
+223
-1
drivers/bluetooth/btintel_pcie.c
+223
-1
drivers/bluetooth/btintel_pcie.c
···
51
51
52
52
#define BTINTEL_PCIE_MAGIC_NUM 0xA5A5A5A5
53
53
54
+
#define BTINTEL_PCIE_BLZR_HWEXP_SIZE 1024
55
+
#define BTINTEL_PCIE_BLZR_HWEXP_DMP_ADDR 0xB00A7C00
56
+
57
+
#define BTINTEL_PCIE_SCP_HWEXP_SIZE 4096
58
+
#define BTINTEL_PCIE_SCP_HWEXP_DMP_ADDR 0xB030F800
59
+
60
+
#define BTINTEL_PCIE_MAGIC_NUM 0xA5A5A5A5
61
+
54
62
/* Alive interrupt context */
55
63
enum {
56
64
BTINTEL_PCIE_ROM,
···
361
353
return reg == 0 ? 0 : -ENODEV;
362
354
}
363
355
356
+
static void btintel_pcie_mac_init(struct btintel_pcie_data *data)
357
+
{
358
+
u32 reg;
359
+
360
+
/* Set MAC_INIT bit to start primary bootloader */
361
+
reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG);
362
+
reg &= ~(BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT |
363
+
BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON |
364
+
BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET);
365
+
reg |= (BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_ENA |
366
+
BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT);
367
+
btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg);
368
+
}
369
+
370
+
static int btintel_pcie_get_mac_access(struct btintel_pcie_data *data)
371
+
{
372
+
u32 reg;
373
+
int retry = 15;
374
+
375
+
reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG);
376
+
377
+
reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS;
378
+
reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ;
379
+
if ((reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS) == 0)
380
+
reg |= BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ;
381
+
382
+
btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg);
383
+
384
+
do {
385
+
reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG);
386
+
if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS)
387
+
return 0;
388
+
/* Need delay here for Target Access harwdware to settle down*/
389
+
usleep_range(1000, 1200);
390
+
391
+
} while (--retry > 0);
392
+
393
+
return -ETIME;
394
+
}
395
+
396
+
static void btintel_pcie_release_mac_access(struct btintel_pcie_data *data)
397
+
{
398
+
u32 reg;
399
+
400
+
reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG);
401
+
402
+
if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ)
403
+
reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ;
404
+
405
+
if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS)
406
+
reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS;
407
+
408
+
if (reg & BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ)
409
+
reg &= ~BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ;
410
+
411
+
btintel_pcie_wr_reg32(data, BTINTEL_PCIE_CSR_FUNC_CTRL_REG, reg);
412
+
}
413
+
364
414
/* This function enables BT function by setting BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT bit in
365
415
* BTINTEL_PCIE_CSR_FUNC_CTRL_REG register and wait for MSI-X with
366
416
* BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0.
···
537
471
default:
538
472
return "unknown";
539
473
}
474
+
}
475
+
476
+
static int btintel_pcie_read_device_mem(struct btintel_pcie_data *data,
477
+
void *buf, u32 dev_addr, int len)
478
+
{
479
+
int err;
480
+
u32 *val = buf;
481
+
482
+
/* Get device mac access */
483
+
err = btintel_pcie_get_mac_access(data);
484
+
if (err) {
485
+
bt_dev_err(data->hdev, "Failed to get mac access %d", err);
486
+
return err;
487
+
}
488
+
489
+
for (; len > 0; len -= 4, dev_addr += 4, val++)
490
+
*val = btintel_pcie_rd_dev_mem(data, dev_addr);
491
+
492
+
btintel_pcie_release_mac_access(data);
493
+
494
+
return 0;
540
495
}
541
496
542
497
/* This function handles the MSI-X interrupt for gp0 cause (bit 0 in
···
881
794
return ret;
882
795
}
883
796
797
+
static void btintel_pcie_read_hwexp(struct btintel_pcie_data *data)
798
+
{
799
+
struct btintel_data *intel_data = hci_get_priv(data->hdev);
800
+
int len, err, offset, pending;
801
+
struct sk_buff *skb;
802
+
u8 *buf, prefix[64];
803
+
u32 addr, val;
804
+
u16 pkt_len;
805
+
806
+
struct tlv {
807
+
u8 type;
808
+
__le16 len;
809
+
u8 val[];
810
+
} __packed;
811
+
812
+
struct tlv *tlv;
813
+
814
+
switch (intel_data->cnvi_top & 0xfff) {
815
+
case BTINTEL_CNVI_BLAZARI:
816
+
case BTINTEL_CNVI_BLAZARIW:
817
+
/* only from step B0 onwards */
818
+
if (INTEL_CNVX_TOP_STEP(intel_data->cnvi_top) != 0x01)
819
+
return;
820
+
len = BTINTEL_PCIE_BLZR_HWEXP_SIZE; /* exception data length */
821
+
addr = BTINTEL_PCIE_BLZR_HWEXP_DMP_ADDR;
822
+
break;
823
+
case BTINTEL_CNVI_SCP:
824
+
len = BTINTEL_PCIE_SCP_HWEXP_SIZE;
825
+
addr = BTINTEL_PCIE_SCP_HWEXP_DMP_ADDR;
826
+
break;
827
+
default:
828
+
bt_dev_err(data->hdev, "Unsupported cnvi 0x%8.8x", intel_data->cnvi_top);
829
+
return;
830
+
}
831
+
832
+
buf = kzalloc(len, GFP_KERNEL);
833
+
if (!buf)
834
+
goto exit_on_error;
835
+
836
+
btintel_pcie_mac_init(data);
837
+
838
+
err = btintel_pcie_read_device_mem(data, buf, addr, len);
839
+
if (err)
840
+
goto exit_on_error;
841
+
842
+
val = get_unaligned_le32(buf);
843
+
if (val != BTINTEL_PCIE_MAGIC_NUM) {
844
+
bt_dev_err(data->hdev, "Invalid exception dump signature: 0x%8.8x",
845
+
val);
846
+
goto exit_on_error;
847
+
}
848
+
849
+
snprintf(prefix, sizeof(prefix), "Bluetooth: %s: ", bt_dev_name(data->hdev));
850
+
851
+
offset = 4;
852
+
do {
853
+
pending = len - offset;
854
+
if (pending < sizeof(*tlv))
855
+
break;
856
+
tlv = (struct tlv *)(buf + offset);
857
+
858
+
/* If type == 0, then there are no more TLVs to be parsed */
859
+
if (!tlv->type) {
860
+
bt_dev_dbg(data->hdev, "Invalid TLV type 0");
861
+
break;
862
+
}
863
+
pkt_len = le16_to_cpu(tlv->len);
864
+
offset += sizeof(*tlv);
865
+
pending = len - offset;
866
+
if (pkt_len > pending)
867
+
break;
868
+
869
+
offset += pkt_len;
870
+
871
+
/* Only TLVs of type == 1 are HCI events, no need to process other
872
+
* TLVs
873
+
*/
874
+
if (tlv->type != 1)
875
+
continue;
876
+
877
+
bt_dev_dbg(data->hdev, "TLV packet length: %u", pkt_len);
878
+
if (pkt_len > HCI_MAX_EVENT_SIZE)
879
+
break;
880
+
skb = bt_skb_alloc(pkt_len, GFP_KERNEL);
881
+
if (!skb)
882
+
goto exit_on_error;
883
+
hci_skb_pkt_type(skb) = HCI_EVENT_PKT;
884
+
skb_put_data(skb, tlv->val, pkt_len);
885
+
886
+
/* copy Intel specific pcie packet type */
887
+
val = BTINTEL_PCIE_HCI_EVT_PKT;
888
+
memcpy(skb_push(skb, BTINTEL_PCIE_HCI_TYPE_LEN), &val,
889
+
BTINTEL_PCIE_HCI_TYPE_LEN);
890
+
891
+
print_hex_dump(KERN_DEBUG, prefix, DUMP_PREFIX_OFFSET, 16, 1,
892
+
tlv->val, pkt_len, false);
893
+
894
+
btintel_pcie_recv_frame(data, skb);
895
+
} while (offset < len);
896
+
897
+
exit_on_error:
898
+
kfree(buf);
899
+
}
900
+
901
+
static void btintel_pcie_msix_hw_exp_handler(struct btintel_pcie_data *data)
902
+
{
903
+
bt_dev_err(data->hdev, "Received hw exception interrupt");
904
+
905
+
if (test_and_set_bit(BTINTEL_PCIE_CORE_HALTED, &data->flags))
906
+
return;
907
+
908
+
if (test_and_set_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags))
909
+
return;
910
+
queue_work(data->workqueue, &data->rx_work);
911
+
}
912
+
884
913
static void btintel_pcie_rx_work(struct work_struct *work)
885
914
{
886
915
struct btintel_pcie_data *data = container_of(work,
···
1004
801
struct sk_buff *skb;
1005
802
int err;
1006
803
struct hci_dev *hdev = data->hdev;
804
+
805
+
if (test_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags)) {
806
+
/* Unlike usb products, controller will not send hardware
807
+
* exception event on exception. Instead controller writes the
808
+
* hardware event to device memory along with optional debug
809
+
* events, raises MSIX and halts. Driver shall read the
810
+
* exception event from device memory and passes it stack for
811
+
* further processing.
812
+
*/
813
+
btintel_pcie_read_hwexp(data);
814
+
clear_bit(BTINTEL_PCIE_HWEXP_INPROGRESS, &data->flags);
815
+
}
1007
816
1008
817
/* Process the sk_buf in queue and send to the HCI layer */
1009
818
while ((skb = skb_dequeue(&data->rx_skb_q))) {
···
1135
920
return IRQ_NONE;
1136
921
}
1137
922
923
+
/* This interrupt is raised when there is an hardware exception */
924
+
if (intr_hw & BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP)
925
+
btintel_pcie_msix_hw_exp_handler(data);
926
+
1138
927
/* This interrupt is triggered by the firmware after updating
1139
928
* boot_stage register and image_response register
1140
929
*/
···
1219
1000
static struct btintel_pcie_causes_list causes_list[] = {
1220
1001
{ BTINTEL_PCIE_MSIX_FH_INT_CAUSES_0, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK, 0x00 },
1221
1002
{ BTINTEL_PCIE_MSIX_FH_INT_CAUSES_1, BTINTEL_PCIE_CSR_MSIX_FH_INT_MASK, 0x01 },
1222
-
{ BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, 0x20 },
1003
+
{ BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, 0x20 },
1004
+
{ BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP, BTINTEL_PCIE_CSR_MSIX_HW_INT_MASK, 0x23 },
1223
1005
};
1224
1006
1225
1007
/* This function configures the interrupt masks for both HW_INT_CAUSES and
···
1702
1482
1703
1483
static int btintel_pcie_setup_internal(struct hci_dev *hdev)
1704
1484
{
1485
+
struct btintel_data *data = hci_get_priv(hdev);
1705
1486
const u8 param[1] = { 0xFF };
1706
1487
struct intel_version_tlv ver_tlv;
1707
1488
struct sk_buff *skb;
···
1741
1520
goto exit_error;
1742
1521
}
1743
1522
1523
+
data->cnvi_top = ver_tlv.cnvi_top;
1744
1524
switch (INTEL_HW_PLATFORM(ver_tlv.cnvi_bt)) {
1745
1525
case 0x37:
1746
1526
break;
+23
drivers/bluetooth/btintel_pcie.h
+23
drivers/bluetooth/btintel_pcie.h
···
16
16
#define BTINTEL_PCIE_CSR_CI_ADDR_LSB_REG (BTINTEL_PCIE_CSR_BASE + 0x118)
17
17
#define BTINTEL_PCIE_CSR_CI_ADDR_MSB_REG (BTINTEL_PCIE_CSR_BASE + 0x11C)
18
18
#define BTINTEL_PCIE_CSR_IMG_RESPONSE_REG (BTINTEL_PCIE_CSR_BASE + 0x12C)
19
+
#define BTINTEL_PCIE_PRPH_DEV_ADDR_REG (BTINTEL_PCIE_CSR_BASE + 0x440)
20
+
#define BTINTEL_PCIE_PRPH_DEV_RD_REG (BTINTEL_PCIE_CSR_BASE + 0x458)
19
21
#define BTINTEL_PCIE_CSR_HBUS_TARG_WRPTR (BTINTEL_PCIE_CSR_BASE + 0x460)
20
22
21
23
/* BTINTEL_PCIE_CSR Function Control Register */
···
25
23
#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_INIT (BIT(6))
26
24
#define BTINTEL_PCIE_CSR_FUNC_CTRL_FUNC_INIT (BIT(7))
27
25
#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_STS (BIT(20))
26
+
27
+
#define BTINTEL_PCIE_CSR_FUNC_CTRL_MAC_ACCESS_REQ (BIT(21))
28
+
/* Stop MAC Access disconnection request */
29
+
#define BTINTEL_PCIE_CSR_FUNC_CTRL_STOP_MAC_ACCESS_DIS (BIT(22))
30
+
#define BTINTEL_PCIE_CSR_FUNC_CTRL_XTAL_CLK_REQ (BIT(23))
31
+
28
32
#define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_STS (BIT(28))
29
33
#define BTINTEL_PCIE_CSR_FUNC_CTRL_BUS_MASTER_DISCON (BIT(29))
30
34
#define BTINTEL_PCIE_CSR_FUNC_CTRL_SW_RESET (BIT(31))
···
80
72
/* Causes for the HW register interrupts */
81
73
enum msix_hw_int_causes {
82
74
BTINTEL_PCIE_MSIX_HW_INT_CAUSES_GP0 = BIT(0), /* cause 32 */
75
+
BTINTEL_PCIE_MSIX_HW_INT_CAUSES_HWEXP = BIT(3), /* cause 35 */
83
76
};
84
77
85
78
/* PCIe device states
···
93
84
BTINTEL_PCIE_STATE_D3_HOT = 2,
94
85
BTINTEL_PCIE_STATE_D3_COLD = 3,
95
86
};
87
+
88
+
enum {
89
+
BTINTEL_PCIE_CORE_HALTED,
90
+
BTINTEL_PCIE_HWEXP_INPROGRESS,
91
+
};
92
+
96
93
#define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE BIT(7)
97
94
98
95
/* Minimum and Maximum number of MSI-X Vector
···
491
476
r &= ~bits;
492
477
iowrite32(r, data->base_addr + offset);
493
478
}
479
+
480
+
static inline u32 btintel_pcie_rd_dev_mem(struct btintel_pcie_data *data,
481
+
u32 addr)
482
+
{
483
+
btintel_pcie_wr_reg32(data, BTINTEL_PCIE_PRPH_DEV_ADDR_REG, addr);
484
+
return btintel_pcie_rd_reg32(data, BTINTEL_PCIE_PRPH_DEV_RD_REG);
485
+
}
486
+