tjh.dev / kernel
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phy: qcom-qmp: qserdes-com: Add some more v8 register offsets

Some qserdes-com register offsets for the v8 PHY were previously omitted,
as they were not needed by earlier v8 PHY initialization sequences. Add
these missing v8 register offsets now required to support PCIe QMP PHY on
Kaanapali platform.

Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20251124-kaanapali-pcie-phy-v4-4-d04ee9cca83b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Qiang Yu and committed by
Vinod Koul ba13ff85 ecc12453

+11
+11
drivers/phy/qualcomm/phy-qcom-qmp-qserdes-com-v8.h
··· 33 33 #define QSERDES_V8_COM_CP_CTRL_MODE0 0x070 34 34 #define QSERDES_V8_COM_PLL_RCTRL_MODE0 0x074 35 35 #define QSERDES_V8_COM_PLL_CCTRL_MODE0 0x078 36 + #define QSERDES_V8_COM_CORECLK_DIV_MODE0 0x07c 36 37 #define QSERDES_V8_COM_LOCK_CMP1_MODE0 0x080 37 38 #define QSERDES_V8_COM_LOCK_CMP2_MODE0 0x084 38 39 #define QSERDES_V8_COM_DEC_START_MODE0 0x088 ··· 41 40 #define QSERDES_V8_COM_DIV_FRAC_START1_MODE0 0x090 42 41 #define QSERDES_V8_COM_DIV_FRAC_START2_MODE0 0x094 43 42 #define QSERDES_V8_COM_DIV_FRAC_START3_MODE0 0x098 43 + #define QSERDES_V8_COM_HSCLK_HS_SWITCH_SEL_1 0x09c 44 44 #define QSERDES_V8_COM_VCO_TUNE1_MODE0 0x0a8 45 45 #define QSERDES_V8_COM_VCO_TUNE2_MODE0 0x0ac 46 46 #define QSERDES_V8_COM_BG_TIMER 0x0bc ··· 49 47 #define QSERDES_V8_COM_SSC_PER1 0x0cc 50 48 #define QSERDES_V8_COM_SSC_PER2 0x0d0 51 49 #define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN 0x0dc 50 + #define QSERDES_V8_COM_CLK_ENABLE1 0x0e0 51 + #define QSERDES_V8_COM_SYS_CLK_CTRL 0x0e4 52 + #define QSERDES_V8_COM_PLL_IVCO 0x0f4 52 53 #define QSERDES_V8_COM_SYSCLK_BUF_ENABLE 0x0e8 53 54 #define QSERDES_V8_COM_SYSCLK_EN_SEL 0x110 54 55 #define QSERDES_V8_COM_RESETSM_CNTRL 0x118 56 + #define QSERDES_V8_COM_LOCK_CMP_EN 0x120 55 57 #define QSERDES_V8_COM_LOCK_CMP_CFG 0x124 56 58 #define QSERDES_V8_COM_VCO_TUNE_MAP 0x140 59 + #define QSERDES_V8_COM_CLK_SELECT 0x164 57 60 #define QSERDES_V8_COM_CORE_CLK_EN 0x170 58 61 #define QSERDES_V8_COM_CMN_CONFIG_1 0x174 62 + #define QSERDES_V8_COM_CMN_MISC_1 0x184 63 + #define QSERDES_V8_COM_CMN_MODE 0x188 64 + #define QSERDES_V8_COM_VCO_DC_LEVEL_CTRL 0x198 65 + #define QSERDES_V8_COM_PLL_SPARE_FOR_ECO 0x2b4 59 66 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1 0x1a4 60 67 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2 0x1a8 61 68 #define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3 0x1ac