Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux into soc/dt
RISC-V SpacemiT DT changes for 6.16
- Add clock driver, fix for pinctrl/uart
- Add gpio support, enable LED heartbeat
* tag 'spacemit-dt-for-6.16-1' of https://github.com/spacemit-com/linux:
riscv: dts: spacemit: add gpio LED for system heartbeat
riscv: dts: spacemit: add gpio support for K1 SoC
riscv: dts: spacemit: Acquire clocks for UART
riscv: dts: spacemit: Acquire clocks for pinctrl
riscv: dts: spacemit: Add clock tree for SpacemiT K1
dt-bindings: clock: spacemit: Add spacemit,k1-pll
dt-bindings: soc: spacemit: Add spacemit,k1-syscon
Link: https://lore.kernel.org/r/20250514044841-GYA524674@gentoo
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+514
-9
+50
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
+50
Documentation/devicetree/bindings/clock/spacemit,k1-pll.yaml
···
1
+
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/clock/spacemit,k1-pll.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SpacemiT K1 PLL
8
+
9
+
maintainers:
10
+
- Haylen Chu <heylenay@4d2.org>
11
+
12
+
properties:
13
+
compatible:
14
+
const: spacemit,k1-pll
15
+
16
+
reg:
17
+
maxItems: 1
18
+
19
+
clocks:
20
+
description: External 24MHz oscillator
21
+
22
+
spacemit,mpmu:
23
+
$ref: /schemas/types.yaml#/definitions/phandle
24
+
description:
25
+
Phandle to the "Main PMU (MPMU)" syscon. It is used to check PLL
26
+
lock status.
27
+
28
+
"#clock-cells":
29
+
const: 1
30
+
description:
31
+
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
32
+
33
+
required:
34
+
- compatible
35
+
- reg
36
+
- clocks
37
+
- spacemit,mpmu
38
+
- "#clock-cells"
39
+
40
+
additionalProperties: false
41
+
42
+
examples:
43
+
- |
44
+
clock-controller@d4090000 {
45
+
compatible = "spacemit,k1-pll";
46
+
reg = <0xd4090000 0x1000>;
47
+
clocks = <&vctcxo_24m>;
48
+
spacemit,mpmu = <&sysctl_mpmu>;
49
+
#clock-cells = <1>;
50
+
};
+80
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
+80
Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml
···
1
+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
%YAML 1.2
3
+
---
4
+
$id: http://devicetree.org/schemas/soc/spacemit/spacemit,k1-syscon.yaml#
5
+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6
+
7
+
title: SpacemiT K1 SoC System Controller
8
+
9
+
maintainers:
10
+
- Haylen Chu <heylenay@4d2.org>
11
+
12
+
description:
13
+
System controllers found on SpacemiT K1 SoC, which are capable of
14
+
clock, reset and power-management functions.
15
+
16
+
properties:
17
+
compatible:
18
+
enum:
19
+
- spacemit,k1-syscon-apbc
20
+
- spacemit,k1-syscon-apmu
21
+
- spacemit,k1-syscon-mpmu
22
+
23
+
reg:
24
+
maxItems: 1
25
+
26
+
clocks:
27
+
maxItems: 4
28
+
29
+
clock-names:
30
+
items:
31
+
- const: osc
32
+
- const: vctcxo_1m
33
+
- const: vctcxo_3m
34
+
- const: vctcxo_24m
35
+
36
+
"#clock-cells":
37
+
const: 1
38
+
description:
39
+
See <dt-bindings/clock/spacemit,k1-syscon.h> for valid indices.
40
+
41
+
"#power-domain-cells":
42
+
const: 1
43
+
44
+
"#reset-cells":
45
+
const: 1
46
+
47
+
required:
48
+
- compatible
49
+
- reg
50
+
- clocks
51
+
- clock-names
52
+
- "#clock-cells"
53
+
- "#reset-cells"
54
+
55
+
allOf:
56
+
- if:
57
+
properties:
58
+
compatible:
59
+
contains:
60
+
const: spacemit,k1-syscon-apbc
61
+
then:
62
+
properties:
63
+
"#power-domain-cells": false
64
+
else:
65
+
required:
66
+
- "#power-domain-cells"
67
+
68
+
additionalProperties: false
69
+
70
+
examples:
71
+
- |
72
+
system-controller@d4050000 {
73
+
compatible = "spacemit,k1-syscon-mpmu";
74
+
reg = <0xd4050000 0x209c>;
75
+
clocks = <&osc>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>;
76
+
clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m";
77
+
#clock-cells = <1>;
78
+
#power-domain-cells = <1>;
79
+
#reset-cells = <1>;
80
+
};
+11
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+11
arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
···
17
17
chosen {
18
18
stdout-path = "serial0";
19
19
};
20
+
21
+
leds {
22
+
compatible = "gpio-leds";
23
+
24
+
led1 {
25
+
label = "sys-led";
26
+
gpios = <&gpio K1_GPIO(96) GPIO_ACTIVE_HIGH>;
27
+
linux,default-trigger = "heartbeat";
28
+
default-state = "on";
29
+
};
30
+
};
20
31
};
21
32
22
33
&uart0 {
+3
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+3
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+123
-9
arch/riscv/boot/dts/spacemit/k1.dtsi
+123
-9
arch/riscv/boot/dts/spacemit/k1.dtsi
···
3
3
* Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
4
4
*/
5
5
6
+
#include <dt-bindings/clock/spacemit,k1-syscon.h>
7
+
6
8
/dts-v1/;
7
9
/ {
8
10
#address-cells = <2>;
···
308
306
};
309
307
};
310
308
309
+
clocks {
310
+
vctcxo_1m: clock-1m {
311
+
compatible = "fixed-clock";
312
+
clock-frequency = <1000000>;
313
+
clock-output-names = "vctcxo_1m";
314
+
#clock-cells = <0>;
315
+
};
316
+
317
+
vctcxo_24m: clock-24m {
318
+
compatible = "fixed-clock";
319
+
clock-frequency = <24000000>;
320
+
clock-output-names = "vctcxo_24m";
321
+
#clock-cells = <0>;
322
+
};
323
+
324
+
vctcxo_3m: clock-3m {
325
+
compatible = "fixed-clock";
326
+
clock-frequency = <3000000>;
327
+
clock-output-names = "vctcxo_3m";
328
+
#clock-cells = <0>;
329
+
};
330
+
331
+
osc_32k: clock-32k {
332
+
compatible = "fixed-clock";
333
+
clock-frequency = <32000>;
334
+
clock-output-names = "osc_32k";
335
+
#clock-cells = <0>;
336
+
};
337
+
};
338
+
311
339
soc {
312
340
compatible = "simple-bus";
313
341
interrupt-parent = <&plic>;
···
346
314
dma-noncoherent;
347
315
ranges;
348
316
317
+
syscon_apbc: system-controller@d4015000 {
318
+
compatible = "spacemit,k1-syscon-apbc";
319
+
reg = <0x0 0xd4015000 0x0 0x1000>;
320
+
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
321
+
<&vctcxo_24m>;
322
+
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
323
+
"vctcxo_24m";
324
+
#clock-cells = <1>;
325
+
#reset-cells = <1>;
326
+
};
327
+
349
328
uart0: serial@d4017000 {
350
329
compatible = "spacemit,k1-uart", "intel,xscale-uart";
351
330
reg = <0x0 0xd4017000 0x0 0x100>;
331
+
clocks = <&syscon_apbc CLK_UART0>,
332
+
<&syscon_apbc CLK_UART0_BUS>;
333
+
clock-names = "core", "bus";
352
334
interrupts = <42>;
353
-
clock-frequency = <14857000>;
354
335
reg-shift = <2>;
355
336
reg-io-width = <4>;
356
337
status = "disabled";
···
372
327
uart2: serial@d4017100 {
373
328
compatible = "spacemit,k1-uart", "intel,xscale-uart";
374
329
reg = <0x0 0xd4017100 0x0 0x100>;
330
+
clocks = <&syscon_apbc CLK_UART2>,
331
+
<&syscon_apbc CLK_UART2_BUS>;
332
+
clock-names = "core", "bus";
375
333
interrupts = <44>;
376
-
clock-frequency = <14857000>;
377
334
reg-shift = <2>;
378
335
reg-io-width = <4>;
379
336
status = "disabled";
···
384
337
uart3: serial@d4017200 {
385
338
compatible = "spacemit,k1-uart", "intel,xscale-uart";
386
339
reg = <0x0 0xd4017200 0x0 0x100>;
340
+
clocks = <&syscon_apbc CLK_UART3>,
341
+
<&syscon_apbc CLK_UART3_BUS>;
342
+
clock-names = "core", "bus";
387
343
interrupts = <45>;
388
-
clock-frequency = <14857000>;
389
344
reg-shift = <2>;
390
345
reg-io-width = <4>;
391
346
status = "disabled";
···
396
347
uart4: serial@d4017300 {
397
348
compatible = "spacemit,k1-uart", "intel,xscale-uart";
398
349
reg = <0x0 0xd4017300 0x0 0x100>;
350
+
clocks = <&syscon_apbc CLK_UART4>,
351
+
<&syscon_apbc CLK_UART4_BUS>;
352
+
clock-names = "core", "bus";
399
353
interrupts = <46>;
400
-
clock-frequency = <14857000>;
401
354
reg-shift = <2>;
402
355
reg-io-width = <4>;
403
356
status = "disabled";
···
408
357
uart5: serial@d4017400 {
409
358
compatible = "spacemit,k1-uart", "intel,xscale-uart";
410
359
reg = <0x0 0xd4017400 0x0 0x100>;
360
+
clocks = <&syscon_apbc CLK_UART5>,
361
+
<&syscon_apbc CLK_UART5_BUS>;
362
+
clock-names = "core", "bus";
411
363
interrupts = <47>;
412
-
clock-frequency = <14857000>;
413
364
reg-shift = <2>;
414
365
reg-io-width = <4>;
415
366
status = "disabled";
···
420
367
uart6: serial@d4017500 {
421
368
compatible = "spacemit,k1-uart", "intel,xscale-uart";
422
369
reg = <0x0 0xd4017500 0x0 0x100>;
370
+
clocks = <&syscon_apbc CLK_UART6>,
371
+
<&syscon_apbc CLK_UART6_BUS>;
372
+
clock-names = "core", "bus";
423
373
interrupts = <48>;
424
-
clock-frequency = <14857000>;
425
374
reg-shift = <2>;
426
375
reg-io-width = <4>;
427
376
status = "disabled";
···
432
377
uart7: serial@d4017600 {
433
378
compatible = "spacemit,k1-uart", "intel,xscale-uart";
434
379
reg = <0x0 0xd4017600 0x0 0x100>;
380
+
clocks = <&syscon_apbc CLK_UART7>,
381
+
<&syscon_apbc CLK_UART7_BUS>;
382
+
clock-names = "core", "bus";
435
383
interrupts = <49>;
436
-
clock-frequency = <14857000>;
437
384
reg-shift = <2>;
438
385
reg-io-width = <4>;
439
386
status = "disabled";
···
444
387
uart8: serial@d4017700 {
445
388
compatible = "spacemit,k1-uart", "intel,xscale-uart";
446
389
reg = <0x0 0xd4017700 0x0 0x100>;
390
+
clocks = <&syscon_apbc CLK_UART8>,
391
+
<&syscon_apbc CLK_UART8_BUS>;
392
+
clock-names = "core", "bus";
447
393
interrupts = <50>;
448
-
clock-frequency = <14857000>;
449
394
reg-shift = <2>;
450
395
reg-io-width = <4>;
451
396
status = "disabled";
···
456
397
uart9: serial@d4017800 {
457
398
compatible = "spacemit,k1-uart", "intel,xscale-uart";
458
399
reg = <0x0 0xd4017800 0x0 0x100>;
400
+
clocks = <&syscon_apbc CLK_UART9>,
401
+
<&syscon_apbc CLK_UART9_BUS>;
402
+
clock-names = "core", "bus";
459
403
interrupts = <51>;
460
-
clock-frequency = <14857000>;
461
404
reg-shift = <2>;
462
405
reg-io-width = <4>;
463
406
status = "disabled";
464
407
};
465
408
409
+
gpio: gpio@d4019000 {
410
+
compatible = "spacemit,k1-gpio";
411
+
reg = <0x0 0xd4019000 0x0 0x100>;
412
+
clocks = <&syscon_apbc CLK_GPIO>,
413
+
<&syscon_apbc CLK_GPIO_BUS>;
414
+
clock-names = "core", "bus";
415
+
gpio-controller;
416
+
#gpio-cells = <3>;
417
+
interrupts = <58>;
418
+
interrupt-parent = <&plic>;
419
+
interrupt-controller;
420
+
#interrupt-cells = <3>;
421
+
gpio-ranges = <&pinctrl 0 0 0 32>,
422
+
<&pinctrl 1 0 32 32>,
423
+
<&pinctrl 2 0 64 32>,
424
+
<&pinctrl 3 0 96 32>;
425
+
};
426
+
466
427
pinctrl: pinctrl@d401e000 {
467
428
compatible = "spacemit,k1-pinctrl";
468
429
reg = <0x0 0xd401e000 0x0 0x400>;
430
+
clocks = <&syscon_apbc CLK_AIB>,
431
+
<&syscon_apbc CLK_AIB_BUS>;
432
+
clock-names = "func", "bus";
433
+
};
434
+
435
+
syscon_mpmu: system-controller@d4050000 {
436
+
compatible = "spacemit,k1-syscon-mpmu";
437
+
reg = <0x0 0xd4050000 0x0 0x209c>;
438
+
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
439
+
<&vctcxo_24m>;
440
+
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
441
+
"vctcxo_24m";
442
+
#clock-cells = <1>;
443
+
#power-domain-cells = <1>;
444
+
#reset-cells = <1>;
445
+
};
446
+
447
+
pll: clock-controller@d4090000 {
448
+
compatible = "spacemit,k1-pll";
449
+
reg = <0x0 0xd4090000 0x0 0x1000>;
450
+
clocks = <&vctcxo_24m>;
451
+
spacemit,mpmu = <&syscon_mpmu>;
452
+
#clock-cells = <1>;
453
+
};
454
+
455
+
syscon_apmu: system-controller@d4282800 {
456
+
compatible = "spacemit,k1-syscon-apmu";
457
+
reg = <0x0 0xd4282800 0x0 0x400>;
458
+
clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>,
459
+
<&vctcxo_24m>;
460
+
clock-names = "osc", "vctcxo_1m", "vctcxo_3m",
461
+
"vctcxo_24m";
462
+
#clock-cells = <1>;
463
+
#power-domain-cells = <1>;
464
+
#reset-cells = <1>;
469
465
};
470
466
471
467
plic: interrupt-controller@e0000000 {
+247
include/dt-bindings/clock/spacemit,k1-syscon.h
+247
include/dt-bindings/clock/spacemit,k1-syscon.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2
+
/*
3
+
* Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>
4
+
*/
5
+
6
+
#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_
7
+
#define _DT_BINDINGS_SPACEMIT_CCU_H_
8
+
9
+
/* APBS (PLL) clocks */
10
+
#define CLK_PLL1 0
11
+
#define CLK_PLL2 1
12
+
#define CLK_PLL3 2
13
+
#define CLK_PLL1_D2 3
14
+
#define CLK_PLL1_D3 4
15
+
#define CLK_PLL1_D4 5
16
+
#define CLK_PLL1_D5 6
17
+
#define CLK_PLL1_D6 7
18
+
#define CLK_PLL1_D7 8
19
+
#define CLK_PLL1_D8 9
20
+
#define CLK_PLL1_D11 10
21
+
#define CLK_PLL1_D13 11
22
+
#define CLK_PLL1_D23 12
23
+
#define CLK_PLL1_D64 13
24
+
#define CLK_PLL1_D10_AUD 14
25
+
#define CLK_PLL1_D100_AUD 15
26
+
#define CLK_PLL2_D1 16
27
+
#define CLK_PLL2_D2 17
28
+
#define CLK_PLL2_D3 18
29
+
#define CLK_PLL2_D4 19
30
+
#define CLK_PLL2_D5 20
31
+
#define CLK_PLL2_D6 21
32
+
#define CLK_PLL2_D7 22
33
+
#define CLK_PLL2_D8 23
34
+
#define CLK_PLL3_D1 24
35
+
#define CLK_PLL3_D2 25
36
+
#define CLK_PLL3_D3 26
37
+
#define CLK_PLL3_D4 27
38
+
#define CLK_PLL3_D5 28
39
+
#define CLK_PLL3_D6 29
40
+
#define CLK_PLL3_D7 30
41
+
#define CLK_PLL3_D8 31
42
+
#define CLK_PLL3_80 32
43
+
#define CLK_PLL3_40 33
44
+
#define CLK_PLL3_20 34
45
+
46
+
/* MPMU clocks */
47
+
#define CLK_PLL1_307P2 0
48
+
#define CLK_PLL1_76P8 1
49
+
#define CLK_PLL1_61P44 2
50
+
#define CLK_PLL1_153P6 3
51
+
#define CLK_PLL1_102P4 4
52
+
#define CLK_PLL1_51P2 5
53
+
#define CLK_PLL1_51P2_AP 6
54
+
#define CLK_PLL1_57P6 7
55
+
#define CLK_PLL1_25P6 8
56
+
#define CLK_PLL1_12P8 9
57
+
#define CLK_PLL1_12P8_WDT 10
58
+
#define CLK_PLL1_6P4 11
59
+
#define CLK_PLL1_3P2 12
60
+
#define CLK_PLL1_1P6 13
61
+
#define CLK_PLL1_0P8 14
62
+
#define CLK_PLL1_409P6 15
63
+
#define CLK_PLL1_204P8 16
64
+
#define CLK_PLL1_491 17
65
+
#define CLK_PLL1_245P76 18
66
+
#define CLK_PLL1_614 19
67
+
#define CLK_PLL1_47P26 20
68
+
#define CLK_PLL1_31P5 21
69
+
#define CLK_PLL1_819 22
70
+
#define CLK_PLL1_1228 23
71
+
#define CLK_SLOW_UART 24
72
+
#define CLK_SLOW_UART1 25
73
+
#define CLK_SLOW_UART2 26
74
+
#define CLK_WDT 27
75
+
#define CLK_RIPC 28
76
+
#define CLK_I2S_SYSCLK 29
77
+
#define CLK_I2S_BCLK 30
78
+
#define CLK_APB 31
79
+
#define CLK_WDT_BUS 32
80
+
81
+
/* APBC clocks */
82
+
#define CLK_UART0 0
83
+
#define CLK_UART2 1
84
+
#define CLK_UART3 2
85
+
#define CLK_UART4 3
86
+
#define CLK_UART5 4
87
+
#define CLK_UART6 5
88
+
#define CLK_UART7 6
89
+
#define CLK_UART8 7
90
+
#define CLK_UART9 8
91
+
#define CLK_GPIO 9
92
+
#define CLK_PWM0 10
93
+
#define CLK_PWM1 11
94
+
#define CLK_PWM2 12
95
+
#define CLK_PWM3 13
96
+
#define CLK_PWM4 14
97
+
#define CLK_PWM5 15
98
+
#define CLK_PWM6 16
99
+
#define CLK_PWM7 17
100
+
#define CLK_PWM8 18
101
+
#define CLK_PWM9 19
102
+
#define CLK_PWM10 20
103
+
#define CLK_PWM11 21
104
+
#define CLK_PWM12 22
105
+
#define CLK_PWM13 23
106
+
#define CLK_PWM14 24
107
+
#define CLK_PWM15 25
108
+
#define CLK_PWM16 26
109
+
#define CLK_PWM17 27
110
+
#define CLK_PWM18 28
111
+
#define CLK_PWM19 29
112
+
#define CLK_SSP3 30
113
+
#define CLK_RTC 31
114
+
#define CLK_TWSI0 32
115
+
#define CLK_TWSI1 33
116
+
#define CLK_TWSI2 34
117
+
#define CLK_TWSI4 35
118
+
#define CLK_TWSI5 36
119
+
#define CLK_TWSI6 37
120
+
#define CLK_TWSI7 38
121
+
#define CLK_TWSI8 39
122
+
#define CLK_TIMERS1 40
123
+
#define CLK_TIMERS2 41
124
+
#define CLK_AIB 42
125
+
#define CLK_ONEWIRE 43
126
+
#define CLK_SSPA0 44
127
+
#define CLK_SSPA1 45
128
+
#define CLK_DRO 46
129
+
#define CLK_IR 47
130
+
#define CLK_TSEN 48
131
+
#define CLK_IPC_AP2AUD 49
132
+
#define CLK_CAN0 50
133
+
#define CLK_CAN0_BUS 51
134
+
#define CLK_UART0_BUS 52
135
+
#define CLK_UART2_BUS 53
136
+
#define CLK_UART3_BUS 54
137
+
#define CLK_UART4_BUS 55
138
+
#define CLK_UART5_BUS 56
139
+
#define CLK_UART6_BUS 57
140
+
#define CLK_UART7_BUS 58
141
+
#define CLK_UART8_BUS 59
142
+
#define CLK_UART9_BUS 60
143
+
#define CLK_GPIO_BUS 61
144
+
#define CLK_PWM0_BUS 62
145
+
#define CLK_PWM1_BUS 63
146
+
#define CLK_PWM2_BUS 64
147
+
#define CLK_PWM3_BUS 65
148
+
#define CLK_PWM4_BUS 66
149
+
#define CLK_PWM5_BUS 67
150
+
#define CLK_PWM6_BUS 68
151
+
#define CLK_PWM7_BUS 69
152
+
#define CLK_PWM8_BUS 70
153
+
#define CLK_PWM9_BUS 71
154
+
#define CLK_PWM10_BUS 72
155
+
#define CLK_PWM11_BUS 73
156
+
#define CLK_PWM12_BUS 74
157
+
#define CLK_PWM13_BUS 75
158
+
#define CLK_PWM14_BUS 76
159
+
#define CLK_PWM15_BUS 77
160
+
#define CLK_PWM16_BUS 78
161
+
#define CLK_PWM17_BUS 79
162
+
#define CLK_PWM18_BUS 80
163
+
#define CLK_PWM19_BUS 81
164
+
#define CLK_SSP3_BUS 82
165
+
#define CLK_RTC_BUS 83
166
+
#define CLK_TWSI0_BUS 84
167
+
#define CLK_TWSI1_BUS 85
168
+
#define CLK_TWSI2_BUS 86
169
+
#define CLK_TWSI4_BUS 87
170
+
#define CLK_TWSI5_BUS 88
171
+
#define CLK_TWSI6_BUS 89
172
+
#define CLK_TWSI7_BUS 90
173
+
#define CLK_TWSI8_BUS 91
174
+
#define CLK_TIMERS1_BUS 92
175
+
#define CLK_TIMERS2_BUS 93
176
+
#define CLK_AIB_BUS 94
177
+
#define CLK_ONEWIRE_BUS 95
178
+
#define CLK_SSPA0_BUS 96
179
+
#define CLK_SSPA1_BUS 97
180
+
#define CLK_TSEN_BUS 98
181
+
#define CLK_IPC_AP2AUD_BUS 99
182
+
183
+
/* APMU clocks */
184
+
#define CLK_CCI550 0
185
+
#define CLK_CPU_C0_HI 1
186
+
#define CLK_CPU_C0_CORE 2
187
+
#define CLK_CPU_C0_ACE 3
188
+
#define CLK_CPU_C0_TCM 4
189
+
#define CLK_CPU_C1_HI 5
190
+
#define CLK_CPU_C1_CORE 6
191
+
#define CLK_CPU_C1_ACE 7
192
+
#define CLK_CCIC_4X 8
193
+
#define CLK_CCIC1PHY 9
194
+
#define CLK_SDH_AXI 10
195
+
#define CLK_SDH0 11
196
+
#define CLK_SDH1 12
197
+
#define CLK_SDH2 13
198
+
#define CLK_USB_P1 14
199
+
#define CLK_USB_AXI 15
200
+
#define CLK_USB30 16
201
+
#define CLK_QSPI 17
202
+
#define CLK_QSPI_BUS 18
203
+
#define CLK_DMA 19
204
+
#define CLK_AES 20
205
+
#define CLK_VPU 21
206
+
#define CLK_GPU 22
207
+
#define CLK_EMMC 23
208
+
#define CLK_EMMC_X 24
209
+
#define CLK_AUDIO 25
210
+
#define CLK_HDMI 26
211
+
#define CLK_PMUA_ACLK 27
212
+
#define CLK_PCIE0_MASTER 28
213
+
#define CLK_PCIE0_SLAVE 29
214
+
#define CLK_PCIE0_DBI 30
215
+
#define CLK_PCIE1_MASTER 31
216
+
#define CLK_PCIE1_SLAVE 32
217
+
#define CLK_PCIE1_DBI 33
218
+
#define CLK_PCIE2_MASTER 34
219
+
#define CLK_PCIE2_SLAVE 35
220
+
#define CLK_PCIE2_DBI 36
221
+
#define CLK_EMAC0_BUS 37
222
+
#define CLK_EMAC0_PTP 38
223
+
#define CLK_EMAC1_BUS 39
224
+
#define CLK_EMAC1_PTP 40
225
+
#define CLK_JPG 41
226
+
#define CLK_CCIC2PHY 42
227
+
#define CLK_CCIC3PHY 43
228
+
#define CLK_CSI 44
229
+
#define CLK_CAMM0 45
230
+
#define CLK_CAMM1 46
231
+
#define CLK_CAMM2 47
232
+
#define CLK_ISP_CPP 48
233
+
#define CLK_ISP_BUS 49
234
+
#define CLK_ISP 50
235
+
#define CLK_DPU_MCLK 51
236
+
#define CLK_DPU_ESC 52
237
+
#define CLK_DPU_BIT 53
238
+
#define CLK_DPU_PXCLK 54
239
+
#define CLK_DPU_HCLK 55
240
+
#define CLK_DPU_SPI 56
241
+
#define CLK_DPU_SPI_HBUS 57
242
+
#define CLK_DPU_SPIBUS 58
243
+
#define CLK_DPU_SPI_ACLK 59
244
+
#define CLK_V2D 60
245
+
#define CLK_EMMC_BUS 61
246
+
247
+
#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */