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drm/amd/amdgpu: Fix SMUIO/PWR Confusion (v2)

The PWR block was merged into the SMUIO block by revision 12 so we add
that to the smuio_12_0_0 headers.

(v2): Drop nonsensical smuio_10_0_0 header

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

Tom St Denis and committed by
Alex Deucher ba56657d 6c33a6f4

+8
+3
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_offset.h
··· 24 24 #define mmSMUIO_GFX_MISC_CNTL 0x00c8 25 25 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0 26 26 27 + #define mmPWR_MISC_CNTL_STATUS 0x0183 28 + #define mmPWR_MISC_CNTL_STATUS_BASE_IDX 1 29 + 27 30 #endif
+5
drivers/gpu/drm/amd/include/asic_reg/smuio/smuio_12_0_0_sh_mask.h
··· 24 24 //SMUIO_GFX_MISC_CNTL 25 25 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L 26 26 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1 27 + //PWR_MISC_CNTL_STATUS 28 + #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT 0x0 29 + #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT 0x1 30 + #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK 0x00000001L 31 + #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK 0x00000006L 27 32 28 33 #endif