Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
riscv: hwprobe: Add MIPS vendor extension probing
Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" which allows
userspace to probe for the new xmipsexectl vendor extension.
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20250724-p8700-pause-v5-4-a6cbbe1c3412@htecgroup.com
[pjw@kernel.org: fixed some checkpatch issues]
Signed-off-by: Paul Walmsley <pjw@kernel.org>
authored by
Aleksa Paunovic
and committed by
Paul Walmsley
bb4b0f8a
1d4ce63e
+56
-1
+2
-1
arch/riscv/include/asm/hwprobe.h
+2
-1
arch/riscv/include/asm/hwprobe.h
···
8
8
9
9
#include <uapi/asm/hwprobe.h>
10
10
11
-
#define RISCV_HWPROBE_MAX_KEY 13
11
+
#define RISCV_HWPROBE_MAX_KEY 14
12
12
13
13
static inline bool riscv_hwprobe_key_is_valid(__s64 key)
14
14
{
···
22
22
case RISCV_HWPROBE_KEY_IMA_EXT_0:
23
23
case RISCV_HWPROBE_KEY_CPUPERF_0:
24
24
case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
25
+
case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
25
26
case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
26
27
return true;
27
28
}
+22
arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
+22
arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
···
1
+
/* SPDX-License-Identifier: GPL-2.0-only */
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
7
+
#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
8
+
9
+
#include <linux/cpumask.h>
10
+
#include <uapi/asm/hwprobe.h>
11
+
12
+
#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
13
+
void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
14
+
#else
15
+
static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
16
+
const struct cpumask *cpus)
17
+
{
18
+
pair->value = 0;
19
+
}
20
+
#endif
21
+
22
+
#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
+1
arch/riscv/include/uapi/asm/hwprobe.h
+1
arch/riscv/include/uapi/asm/hwprobe.h
···
106
106
#define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0 11
107
107
#define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE 12
108
108
#define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0 13
109
+
#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0 14
109
110
/* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
110
111
111
112
/* Flags */
+3
arch/riscv/include/uapi/asm/vendor/mips.h
+3
arch/riscv/include/uapi/asm/vendor/mips.h
+4
arch/riscv/kernel/sys_hwprobe.c
+4
arch/riscv/kernel/sys_hwprobe.c
···
15
15
#include <asm/uaccess.h>
16
16
#include <asm/unistd.h>
17
17
#include <asm/vector.h>
18
+
#include <asm/vendor_extensions/mips_hwprobe.h>
18
19
#include <asm/vendor_extensions/sifive_hwprobe.h>
19
20
#include <asm/vendor_extensions/thead_hwprobe.h>
20
21
#include <vdso/vsyscall.h>
···
307
306
308
307
case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
309
308
hwprobe_isa_vendor_ext_thead_0(pair, cpus);
309
+
break;
310
+
case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
311
+
hwprobe_isa_vendor_ext_mips_0(pair, cpus);
310
312
break;
311
313
312
314
/*
+1
arch/riscv/kernel/vendor_extensions/Makefile
+1
arch/riscv/kernel/vendor_extensions/Makefile
···
2
2
3
3
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES) += andes.o
4
4
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) += mips.o
5
+
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS) += mips_hwprobe.o
5
6
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive.o
6
7
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE) += sifive_hwprobe.o
7
8
obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD) += thead.o
+23
arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
+23
arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-only
2
+
/*
3
+
* Copyright (C) 2025 MIPS.
4
+
*/
5
+
6
+
#include <asm/vendor_extensions.h>
7
+
#include <asm/vendor_extensions/mips.h>
8
+
#include <asm/vendor_extensions/mips_hwprobe.h>
9
+
#include <asm/vendor_extensions/vendor_hwprobe.h>
10
+
11
+
#include <linux/cpumask.h>
12
+
#include <linux/types.h>
13
+
14
+
#include <uapi/asm/hwprobe.h>
15
+
#include <uapi/asm/vendor/mips.h>
16
+
17
+
void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
18
+
const struct cpumask *cpus)
19
+
{
20
+
VENDOR_EXTENSION_SUPPORTED(pair, cpus,
21
+
riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap,
22
+
{ VENDOR_EXT_KEY(XMIPSEXECTL); });
23
+
}