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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: renesas: rzv2h: Add support for RZ/G3E SoC
The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
are present only on the RZ/G3E SoC.
Add minimal clock and reset entries required to boot the Renesas RZ/G3E
SMARC EVK and binds it with the RZ/V2H CPG core driver.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
authored by
Biju Das
and committed by
Geert Uytterhoeven
bb6a9aaf
6b4a095c
+116
-1
+6
-1
drivers/clk/renesas/Kconfig
+6
-1
drivers/clk/renesas/Kconfig
···
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select CLK_R9A07G054 if ARCH_R9A07G054
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select CLK_R9A08G045 if ARCH_R9A08G045
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select CLK_R9A09G011 if ARCH_R9A09G011
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+
select CLK_R9A09G047 if ARCH_R9A09G047
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select CLK_R9A09G057 if ARCH_R9A09G057
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select CLK_SH73A0 if ARCH_SH73A0
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···
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bool "RZ/V2M clock support" if COMPILE_TEST
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select CLK_RZG2L
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config CLK_R9A09G047
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bool "RZ/G3E clock support" if COMPILE_TEST
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select CLK_RZV2H
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config CLK_R9A09G057
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bool "RZ/V2H(P) clock support" if COMPILE_TEST
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select CLK_RZV2H
···
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select RESET_CONTROLLER
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config CLK_RZV2H
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bool "RZ/V2H(P) family clock support" if COMPILE_TEST
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bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
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select RESET_CONTROLLER
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config CLK_RENESAS_VBATTB
+1
drivers/clk/renesas/Makefile
+1
drivers/clk/renesas/Makefile
···
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obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o
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obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o
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obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o
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obj-$(CONFIG_CLK_R9A09G047) += r9a09g047-cpg.o
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obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o
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obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o
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+102
drivers/clk/renesas/r9a09g047-cpg.c
+102
drivers/clk/renesas/r9a09g047-cpg.c
···
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+
// SPDX-License-Identifier: GPL-2.0
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/*
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* Renesas RZ/G3E CPG driver
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#include <linux/clk-provider.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
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#include "rzv2h-cpg.h"
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A09G047_IOTOP_0_SHCLK,
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+
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/* External Input Clocks */
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CLK_AUDIO_EXTAL,
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CLK_RTXIN,
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CLK_QEXTAL,
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+
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/* PLL Clocks */
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CLK_PLLCM33,
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CLK_PLLDTY,
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CLK_PLLCA55,
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/* Internal Core Clocks */
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CLK_PLLCM33_DIV16,
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CLK_PLLDTY_ACPU,
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CLK_PLLDTY_ACPU_DIV4,
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/* Module Clocks */
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MOD_CLK_BASE,
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};
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static const struct clk_div_table dtable_2_64[] = {
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{0, 2},
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{1, 4},
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{2, 8},
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{3, 16},
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{4, 64},
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{0, 0},
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};
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static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
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/* External Clock Inputs */
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DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL),
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DEF_INPUT("rtxin", CLK_RTXIN),
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DEF_INPUT("qextal", CLK_QEXTAL),
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/* PLL Clocks */
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DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3),
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DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3),
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DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)),
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/* Internal Core Clocks */
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DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16),
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DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64),
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DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4),
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/* Core Clocks */
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DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
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DEF_FIXED("iotop_0_shclk", R9A09G047_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1),
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};
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static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
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DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
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BUS_MSTOP(3, BIT(5))),
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DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15,
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BUS_MSTOP(3, BIT(14))),
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};
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static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
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DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */
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DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */
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DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */
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DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */
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};
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const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
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/* Core Clocks */
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.core_clks = r9a09g047_core_clks,
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.num_core_clks = ARRAY_SIZE(r9a09g047_core_clks),
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.last_dt_core_clk = LAST_DT_CORE_CLK,
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.num_total_core_clks = MOD_CLK_BASE,
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/* Module Clocks */
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.mod_clks = r9a09g047_mod_clks,
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.num_mod_clks = ARRAY_SIZE(r9a09g047_mod_clks),
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.num_hw_mod_clks = 28 * 16,
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/* Resets */
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.resets = r9a09g047_resets,
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.num_resets = ARRAY_SIZE(r9a09g047_resets),
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.num_mstop_bits = 208,
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};
+6
drivers/clk/renesas/rzv2h-cpg.c
+6
drivers/clk/renesas/rzv2h-cpg.c