tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'mtd/fixes-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux

Pull MTD fixes from Miquel Raynal:
"There has been OTP support improvements in the NVMEM subsystem, and
later also improvements of OTP support in the NAND subsystem. This
lead to situations that we currently cannot handle, so better prevent
this situation from happening in order to avoid canceling device's
probe.

In the raw NAND subsystem, two runtime fixes have been shared, one
fixing two important commands in the Qcom driver since it got reworked
and a NULL pointer dereference happening on STB chips.

Arnd also fixed a UBSAN link failure on diskonchip"

* tag 'mtd/fixes-for-6.9-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux:
mtd: limit OTP NVMEM cell parse to non-NAND devices
mtd: diskonchip: work around ubsan link failure
mtd: rawnand: qcom: Fix broken OP_RESET_DEVICE command in qcom_misc_cmd_type_exec()
mtd: rawnand: brcmnand: Fix data access violation for STB chip

Linus Torvalds bbacf717 3022bf37

+7 -8
+1 -1
drivers/mtd/mtdcore.c
··· 900 900 config.name = compatible; 901 901 config.id = NVMEM_DEVID_AUTO; 902 902 config.owner = THIS_MODULE; 903 - config.add_legacy_fixed_of_cells = true; 903 + config.add_legacy_fixed_of_cells = !mtd_type_is_nand(mtd); 904 904 config.type = NVMEM_TYPE_OTP; 905 905 config.root_only = true; 906 906 config.ignore_wp = true;
+1 -1
drivers/mtd/nand/raw/brcmnand/brcmnand.c
··· 857 857 struct brcmnand_soc *soc = ctrl->soc; 858 858 int i; 859 859 860 - if (soc->read_data_bus) { 860 + if (soc && soc->read_data_bus) { 861 861 soc->read_data_bus(soc, flash_cache, buffer, fc_words); 862 862 } else { 863 863 for (i = 0; i < fc_words; i++)
+2 -2
drivers/mtd/nand/raw/diskonchip.c
··· 53 53 0xe8000, 0xea000, 0xec000, 0xee000, 54 54 #endif 55 55 #endif 56 - 0xffffffff }; 56 + }; 57 57 58 58 static struct mtd_info *doclist = NULL; 59 59 ··· 1554 1554 if (ret < 0) 1555 1555 return ret; 1556 1556 } else { 1557 - for (i = 0; (doc_locations[i] != 0xffffffff); i++) { 1557 + for (i = 0; i < ARRAY_SIZE(doc_locations); i++) { 1558 1558 doc_probe(doc_locations[i]); 1559 1559 } 1560 1560 }
+3 -4
drivers/mtd/nand/raw/qcom_nandc.c
··· 2815 2815 host->cfg0_raw & ~(7 << CW_PER_PAGE)); 2816 2816 nandc_set_reg(chip, NAND_DEV0_CFG1, host->cfg1_raw); 2817 2817 instrs = 3; 2818 - } else { 2818 + } else if (q_op.cmd_reg != OP_RESET_DEVICE) { 2819 2819 return 0; 2820 2820 } 2821 2821 ··· 2830 2830 nandc_set_reg(chip, NAND_EXEC_CMD, 1); 2831 2831 2832 2832 write_reg_dma(nandc, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); 2833 - (q_op.cmd_reg == OP_BLOCK_ERASE) ? write_reg_dma(nandc, NAND_DEV0_CFG0, 2834 - 2, NAND_BAM_NEXT_SGL) : read_reg_dma(nandc, 2835 - NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); 2833 + if (q_op.cmd_reg == OP_BLOCK_ERASE) 2834 + write_reg_dma(nandc, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); 2836 2835 2837 2836 write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 2838 2837 read_reg_dma(nandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);