clk: qcom: gcc-sa8775p: Update the GDSC wait_val fields and flags

Update the GDSC wait_val fields as per the default hardware values as
otherwise they would lead to GDSC FSM state to be stuck and causing
failures to power on/off. Also add the GDSC flags as applicable and
add support to control PCIE GDSC's using collapse vote registers.

Fixes: 08c51ceb12f7 ("clk: qcom: add the GCC driver for sa8775p")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-2-adcc756a23df@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

authored by

Taniya Das and committed by

Bjorn Andersson 2 years ago be208c0c d3b33848

+40

1 changed file

expand all

drivers

clk

qcom

gcc-sa8775p.c

+40

drivers/clk/qcom/gcc-sa8775p.c

··· 4203 4203 4204 4204 static struct gdsc pcie_0_gdsc = { 4205 4205 .gdscr = 0xa9004, 4206 + .collapse_ctrl = 0x4b104, 4207 + .collapse_mask = BIT(0), 4208 + .en_rest_wait_val = 0x2, 4209 + .en_few_wait_val = 0x2, 4210 + .clk_dis_wait_val = 0xf, 4206 4211 .pd = { 4207 4212 .name = "pcie_0_gdsc", 4208 4213 }, 4209 4214 .pwrsts = PWRSTS_OFF_ON, 4215 + .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4210 4216 }; 4211 4217 4212 4218 static struct gdsc pcie_1_gdsc = { 4213 4219 .gdscr = 0x77004, 4220 + .collapse_ctrl = 0x4b104, 4221 + .collapse_mask = BIT(1), 4222 + .en_rest_wait_val = 0x2, 4223 + .en_few_wait_val = 0x2, 4224 + .clk_dis_wait_val = 0xf, 4214 4225 .pd = { 4215 4226 .name = "pcie_1_gdsc", 4216 4227 }, 4217 4228 .pwrsts = PWRSTS_OFF_ON, 4229 + .flags = VOTABLE | RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4218 4230 }; 4219 4231 4220 4232 static struct gdsc ufs_card_gdsc = { 4221 4233 .gdscr = 0x81004, 4234 + .en_rest_wait_val = 0x2, 4235 + .en_few_wait_val = 0x2, 4236 + .clk_dis_wait_val = 0xf, 4222 4237 .pd = { 4223 4238 .name = "ufs_card_gdsc", 4224 4239 }, 4225 4240 .pwrsts = PWRSTS_OFF_ON, 4241 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4226 4242 }; 4227 4243 4228 4244 static struct gdsc ufs_phy_gdsc = { 4229 4245 .gdscr = 0x83004, 4246 + .en_rest_wait_val = 0x2, 4247 + .en_few_wait_val = 0x2, 4248 + .clk_dis_wait_val = 0xf, 4230 4249 .pd = { 4231 4250 .name = "ufs_phy_gdsc", 4232 4251 }, 4233 4252 .pwrsts = PWRSTS_OFF_ON, 4253 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4234 4254 }; 4235 4255 4236 4256 static struct gdsc usb20_prim_gdsc = { 4237 4257 .gdscr = 0x1c004, 4258 + .en_rest_wait_val = 0x2, 4259 + .en_few_wait_val = 0x2, 4260 + .clk_dis_wait_val = 0xf, 4238 4261 .pd = { 4239 4262 .name = "usb20_prim_gdsc", 4240 4263 }, 4241 4264 .pwrsts = PWRSTS_OFF_ON, 4265 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4242 4266 }; 4243 4267 4244 4268 static struct gdsc usb30_prim_gdsc = { 4245 4269 .gdscr = 0x1b004, 4270 + .en_rest_wait_val = 0x2, 4271 + .en_few_wait_val = 0x2, 4272 + .clk_dis_wait_val = 0xf, 4246 4273 .pd = { 4247 4274 .name = "usb30_prim_gdsc", 4248 4275 }, 4249 4276 .pwrsts = PWRSTS_OFF_ON, 4277 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4250 4278 }; 4251 4279 4252 4280 static struct gdsc usb30_sec_gdsc = { 4253 4281 .gdscr = 0x2f004, 4282 + .en_rest_wait_val = 0x2, 4283 + .en_few_wait_val = 0x2, 4284 + .clk_dis_wait_val = 0xf, 4254 4285 .pd = { 4255 4286 .name = "usb30_sec_gdsc", 4256 4287 }, 4257 4288 .pwrsts = PWRSTS_OFF_ON, 4289 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4258 4290 }; 4259 4291 4260 4292 static struct gdsc emac0_gdsc = { 4261 4293 .gdscr = 0xb6004, 4294 + .en_rest_wait_val = 0x2, 4295 + .en_few_wait_val = 0x2, 4296 + .clk_dis_wait_val = 0xf, 4262 4297 .pd = { 4263 4298 .name = "emac0_gdsc", 4264 4299 }, 4265 4300 .pwrsts = PWRSTS_OFF_ON, 4301 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4266 4302 }; 4267 4303 4268 4304 static struct gdsc emac1_gdsc = { 4269 4305 .gdscr = 0xb4004, 4306 + .en_rest_wait_val = 0x2, 4307 + .en_few_wait_val = 0x2, 4308 + .clk_dis_wait_val = 0xf, 4270 4309 .pd = { 4271 4310 .name = "emac1_gdsc", 4272 4311 }, 4273 4312 .pwrsts = PWRSTS_OFF_ON, 4313 + .flags = RETAIN_FF_ENABLE | POLL_CFG_GDSCR, 4274 4314 }; 4275 4315 4276 4316 static struct clk_regmap *gcc_sa8775p_clocks[] = {

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