Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
clk: qcom: gcc-sa8775p: Remove support for UFS hw ctl clocks
The UFS hw ctl clocks are not used by any consumers on SA8775P,
and these clocks are not using the correct clock ops to manage the
hw ctl of the branch clock, hence remove these clocks.
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20240612-sa8775p-v2-gcc-gpucc-fixes-v2-1-adcc756a23df@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
authored by
Taniya Das
and committed by
Bjorn Andersson
d3b33848
313e2909
+2
-109
+2
-109
drivers/clk/qcom/gcc-sa8775p.c
+2
-109
drivers/clk/qcom/gcc-sa8775p.c
···
1
1
// SPDX-License-Identifier: GPL-2.0-only
2
2
/*
3
-
* Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
3
+
* Copyright (c) 2021-2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2023, Linaro Limited
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5
*/
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-
#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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+
#include <linux/mod_devicetable.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
···
1725
1727
.enable_mask = BIT(0),
1726
1728
.hw.init = &(const struct clk_init_data){
1727
1729
.name = "gcc_aggre_ufs_phy_axi_clk",
1728
-
.parent_hws = (const struct clk_hw*[]){
1729
-
&gcc_ufs_phy_axi_clk_src.clkr.hw,
1730
-
},
1731
-
.num_parents = 1,
1732
-
.flags = CLK_SET_RATE_PARENT,
1733
-
.ops = &clk_branch2_ops,
1734
-
},
1735
-
},
1736
-
};
1737
-
1738
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static struct clk_branch gcc_aggre_ufs_phy_axi_hw_ctl_clk = {
1739
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.halt_reg = 0x830d4,
1740
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.halt_check = BRANCH_HALT_VOTED,
1741
-
.hwcg_reg = 0x830d4,
1742
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.hwcg_bit = 1,
1743
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.clkr = {
1744
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.enable_reg = 0x830d4,
1745
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.enable_mask = BIT(1),
1746
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.hw.init = &(const struct clk_init_data){
1747
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.name = "gcc_aggre_ufs_phy_axi_hw_ctl_clk",
1748
1730
.parent_hws = (const struct clk_hw*[]){
1749
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&gcc_ufs_phy_axi_clk_src.clkr.hw,
1750
1732
},
···
3787
3809
},
3788
3810
};
3789
3811
3790
-
static struct clk_branch gcc_ufs_phy_axi_hw_ctl_clk = {
3791
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.halt_reg = 0x83018,
3792
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.halt_check = BRANCH_HALT_VOTED,
3793
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.hwcg_reg = 0x83018,
3794
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.hwcg_bit = 1,
3795
-
.clkr = {
3796
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.enable_reg = 0x83018,
3797
-
.enable_mask = BIT(1),
3798
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.hw.init = &(const struct clk_init_data){
3799
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.name = "gcc_ufs_phy_axi_hw_ctl_clk",
3800
-
.parent_hws = (const struct clk_hw*[]){
3801
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&gcc_ufs_phy_axi_clk_src.clkr.hw,
3802
-
},
3803
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.num_parents = 1,
3804
-
.flags = CLK_SET_RATE_PARENT,
3805
-
.ops = &clk_branch2_ops,
3806
-
},
3807
-
},
3808
-
};
3809
-
3810
3812
static struct clk_branch gcc_ufs_phy_ice_core_clk = {
3811
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.halt_reg = 0x8306c,
3812
3814
.halt_check = BRANCH_HALT_VOTED,
···
3807
3849
},
3808
3850
};
3809
3851
3810
-
static struct clk_branch gcc_ufs_phy_ice_core_hw_ctl_clk = {
3811
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.halt_reg = 0x8306c,
3812
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.halt_check = BRANCH_HALT_VOTED,
3813
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.hwcg_reg = 0x8306c,
3814
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.hwcg_bit = 1,
3815
-
.clkr = {
3816
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.enable_reg = 0x8306c,
3817
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.enable_mask = BIT(1),
3818
-
.hw.init = &(const struct clk_init_data){
3819
-
.name = "gcc_ufs_phy_ice_core_hw_ctl_clk",
3820
-
.parent_hws = (const struct clk_hw*[]){
3821
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&gcc_ufs_phy_ice_core_clk_src.clkr.hw,
3822
-
},
3823
-
.num_parents = 1,
3824
-
.flags = CLK_SET_RATE_PARENT,
3825
-
.ops = &clk_branch2_ops,
3826
-
},
3827
-
},
3828
-
};
3829
-
3830
3852
static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
3831
3853
.halt_reg = 0x830a4,
3832
3854
.halt_check = BRANCH_HALT_VOTED,
···
3817
3879
.enable_mask = BIT(0),
3818
3880
.hw.init = &(const struct clk_init_data){
3819
3881
.name = "gcc_ufs_phy_phy_aux_clk",
3820
-
.parent_hws = (const struct clk_hw*[]){
3821
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&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3822
-
},
3823
-
.num_parents = 1,
3824
-
.flags = CLK_SET_RATE_PARENT,
3825
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.ops = &clk_branch2_ops,
3826
-
},
3827
-
},
3828
-
};
3829
-
3830
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static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
3831
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.halt_reg = 0x830a4,
3832
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.halt_check = BRANCH_HALT_VOTED,
3833
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.hwcg_reg = 0x830a4,
3834
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.hwcg_bit = 1,
3835
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.clkr = {
3836
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.enable_reg = 0x830a4,
3837
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.enable_mask = BIT(1),
3838
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.hw.init = &(const struct clk_init_data){
3839
-
.name = "gcc_ufs_phy_phy_aux_hw_ctl_clk",
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3882
.parent_hws = (const struct clk_hw*[]){
3841
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&gcc_ufs_phy_phy_aux_clk_src.clkr.hw,
3842
3884
},
···
3891
3973
.enable_mask = BIT(0),
3892
3974
.hw.init = &(const struct clk_init_data){
3893
3975
.name = "gcc_ufs_phy_unipro_core_clk",
3894
-
.parent_hws = (const struct clk_hw*[]){
3895
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&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3896
-
},
3897
-
.num_parents = 1,
3898
-
.flags = CLK_SET_RATE_PARENT,
3899
-
.ops = &clk_branch2_ops,
3900
-
},
3901
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},
3902
-
};
3903
-
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static struct clk_branch gcc_ufs_phy_unipro_core_hw_ctl_clk = {
3905
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.halt_reg = 0x83064,
3906
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.halt_check = BRANCH_HALT_VOTED,
3907
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.hwcg_reg = 0x83064,
3908
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.hwcg_bit = 1,
3909
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.clkr = {
3910
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.enable_reg = 0x83064,
3911
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.enable_mask = BIT(1),
3912
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.hw.init = &(const struct clk_init_data){
3913
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.name = "gcc_ufs_phy_unipro_core_hw_ctl_clk",
3914
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.parent_hws = (const struct clk_hw*[]){
3915
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&gcc_ufs_phy_unipro_core_clk_src.clkr.hw,
3916
3978
},
···
4277
4379
[GCC_AGGRE_NOC_QUPV3_AXI_CLK] = &gcc_aggre_noc_qupv3_axi_clk.clkr,
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4380
[GCC_AGGRE_UFS_CARD_AXI_CLK] = &gcc_aggre_ufs_card_axi_clk.clkr,
4279
4381
[GCC_AGGRE_UFS_PHY_AXI_CLK] = &gcc_aggre_ufs_phy_axi_clk.clkr,
4280
-
[GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_aggre_ufs_phy_axi_hw_ctl_clk.clkr,
4281
4382
[GCC_AGGRE_USB2_PRIM_AXI_CLK] = &gcc_aggre_usb2_prim_axi_clk.clkr,
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4383
[GCC_AGGRE_USB3_PRIM_AXI_CLK] = &gcc_aggre_usb3_prim_axi_clk.clkr,
4283
4384
[GCC_AGGRE_USB3_SEC_AXI_CLK] = &gcc_aggre_usb3_sec_axi_clk.clkr,
···
4466
4569
[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
4467
4570
[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
4468
4571
[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,
4469
-
[GCC_UFS_PHY_AXI_HW_CTL_CLK] = &gcc_ufs_phy_axi_hw_ctl_clk.clkr,
4470
4572
[GCC_UFS_PHY_ICE_CORE_CLK] = &gcc_ufs_phy_ice_core_clk.clkr,
4471
4573
[GCC_UFS_PHY_ICE_CORE_CLK_SRC] = &gcc_ufs_phy_ice_core_clk_src.clkr,
4472
-
[GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK] = &gcc_ufs_phy_ice_core_hw_ctl_clk.clkr,
4473
4574
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
4474
4575
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
4475
-
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
4476
4576
[GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
4477
4577
[GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_rx_symbol_0_clk_src.clkr,
4478
4578
[GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
···
4478
4584
[GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC] = &gcc_ufs_phy_tx_symbol_0_clk_src.clkr,
4479
4585
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
4480
4586
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
4481
-
[GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK] = &gcc_ufs_phy_unipro_core_hw_ctl_clk.clkr,
4482
4587
[GCC_USB20_MASTER_CLK] = &gcc_usb20_master_clk.clkr,
4483
4588
[GCC_USB20_MASTER_CLK_SRC] = &gcc_usb20_master_clk_src.clkr,
4484
4589
[GCC_USB20_MOCK_UTMI_CLK] = &gcc_usb20_mock_utmi_clk.clkr,