Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: move queue_bitmap to an independent structure (v3)
To allocate independent queue_bitmap for each XCD,
then the old bitmap policy can be continued to use
with a clear logic.
Use mec_bitmap[0] as default for all non-GC 9.4.3 IPs.
v2: squash commits to avoid breaking the build
v3: unify naming style
Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Le Ma
and committed by
Alex Deucher
be697aa3
277bd337
+47
-32
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
···
778
778
* Iterate through the shader engines and arrays of the device
779
779
* to get number of waves in flight
780
780
*/
781
-
bitmap_complement(cp_queue_bitmap, adev->gfx.mec.queue_bitmap,
781
+
bitmap_complement(cp_queue_bitmap, adev->gfx.mec_bitmap[0].queue_bitmap,
782
782
KGD_MAX_QUEUES);
783
783
max_queue_cnt = adev->gfx.mec.num_pipe_per_mec *
784
784
adev->gfx.mec.num_queue_per_pipe;
+24
-15
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+24
-15
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
···
63
63
}
64
64
65
65
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev,
66
-
int mec, int pipe, int queue)
66
+
int xcc_id, int mec, int pipe, int queue)
67
67
{
68
68
return test_bit(amdgpu_gfx_mec_queue_to_bit(adev, mec, pipe, queue),
69
-
adev->gfx.mec.queue_bitmap);
69
+
adev->gfx.mec_bitmap[xcc_id].queue_bitmap);
70
70
}
71
71
72
72
int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev,
···
204
204
205
205
void amdgpu_gfx_compute_queue_acquire(struct amdgpu_device *adev)
206
206
{
207
-
int i, queue, pipe;
207
+
int i, j, queue, pipe;
208
208
bool multipipe_policy = amdgpu_gfx_is_compute_multipipe_capable(adev);
209
209
int max_queues_per_mec = min(adev->gfx.mec.num_pipe_per_mec *
210
210
adev->gfx.mec.num_queue_per_pipe,
211
211
adev->gfx.num_compute_rings);
212
+
int num_xcd = (adev->gfx.num_xcd > 1) ? adev->gfx.num_xcd : 1;
212
213
213
214
if (multipipe_policy) {
214
-
/* policy: make queues evenly cross all pipes on MEC1 only */
215
-
for (i = 0; i < max_queues_per_mec; i++) {
216
-
pipe = i % adev->gfx.mec.num_pipe_per_mec;
217
-
queue = (i / adev->gfx.mec.num_pipe_per_mec) %
218
-
adev->gfx.mec.num_queue_per_pipe;
215
+
/* policy: make queues evenly cross all pipes on MEC1 only
216
+
* for multiple xcc, just use the original policy for simplicity */
217
+
for (j = 0; j < num_xcd; j++) {
218
+
for (i = 0; i < max_queues_per_mec; i++) {
219
+
pipe = i % adev->gfx.mec.num_pipe_per_mec;
220
+
queue = (i / adev->gfx.mec.num_pipe_per_mec) %
221
+
adev->gfx.mec.num_queue_per_pipe;
219
222
220
-
set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
221
-
adev->gfx.mec.queue_bitmap);
223
+
set_bit(pipe * adev->gfx.mec.num_queue_per_pipe + queue,
224
+
adev->gfx.mec_bitmap[j].queue_bitmap);
225
+
}
222
226
}
223
227
} else {
224
228
/* policy: amdgpu owns all queues in the given pipe */
225
-
for (i = 0; i < max_queues_per_mec; ++i)
226
-
set_bit(i, adev->gfx.mec.queue_bitmap);
229
+
for (j = 0; j < num_xcd; j++) {
230
+
for (i = 0; i < max_queues_per_mec; ++i)
231
+
set_bit(i, adev->gfx.mec_bitmap[j].queue_bitmap);
232
+
}
227
233
}
228
234
229
-
dev_dbg(adev->dev, "mec queue bitmap weight=%d\n", bitmap_weight(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
235
+
for (j = 0; j < num_xcd; j++) {
236
+
dev_dbg(adev->dev, "mec queue bitmap weight=%d\n",
237
+
bitmap_weight(adev->gfx.mec_bitmap[j].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES));
238
+
}
230
239
}
231
240
232
241
void amdgpu_gfx_graphics_queue_acquire(struct amdgpu_device *adev)
···
277
268
* adev->gfx.mec.num_queue_per_pipe;
278
269
279
270
while (--queue_bit >= 0) {
280
-
if (test_bit(queue_bit, adev->gfx.mec.queue_bitmap))
271
+
if (test_bit(queue_bit, adev->gfx.mec_bitmap[0].queue_bitmap))
281
272
continue;
282
273
283
274
amdgpu_queue_mask_bit_to_mec_queue(adev, queue_bit, &mec, &pipe, &queue);
···
525
516
return -EINVAL;
526
517
527
518
for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
528
-
if (!test_bit(i, adev->gfx.mec.queue_bitmap))
519
+
if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))
529
520
continue;
530
521
531
522
/* This situation may be hit in the future if a new HW
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
+5
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
···
76
76
u32 num_pipe_per_mec;
77
77
u32 num_queue_per_pipe;
78
78
void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
79
+
};
79
80
81
+
struct amdgpu_mec_bitmap {
80
82
/* These are the resources for which amdgpu takes ownership */
81
83
DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
82
84
};
···
298
296
struct amdgpu_ce ce;
299
297
struct amdgpu_me me;
300
298
struct amdgpu_mec mec;
299
+
struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES];
301
300
struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES];
302
301
struct amdgpu_imu imu;
303
302
bool rs64_enable; /* firmware format */
···
428
425
int pipe, int queue);
429
426
void amdgpu_queue_mask_bit_to_mec_queue(struct amdgpu_device *adev, int bit,
430
427
int *mec, int *pipe, int *queue);
431
-
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int mec,
432
-
int pipe, int queue);
428
+
bool amdgpu_gfx_is_mec_queue_enabled(struct amdgpu_device *adev, int inst,
429
+
int mec, int pipe, int queue);
433
430
bool amdgpu_gfx_is_high_priority_compute_queue(struct amdgpu_device *adev,
434
431
struct amdgpu_ring *ring);
435
432
bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev,
+3
-3
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+3
-3
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
···
4219
4219
4220
4220
const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4221
4221
4222
-
bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4222
+
bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4223
4223
4224
4224
/* take ownership of the relevant compute queues */
4225
4225
amdgpu_gfx_compute_queue_acquire(adev);
···
4614
4614
for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4615
4615
for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4616
4616
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4617
-
if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4618
-
j))
4617
+
if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4618
+
k, j))
4619
4619
continue;
4620
4620
4621
4621
r = gfx_v10_0_compute_ring_init(adev, ring_id,
+3
-3
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+3
-3
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
···
699
699
u32 *hpd;
700
700
size_t mec_hpd_size;
701
701
702
-
bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
702
+
bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
703
703
704
704
/* take ownership of the relevant compute queues */
705
705
amdgpu_gfx_compute_queue_acquire(adev);
···
1374
1374
for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1375
1375
for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1376
1376
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1377
-
if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
1378
-
j))
1377
+
if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
1378
+
k, j))
1379
1379
continue;
1380
1380
1381
1381
r = gfx_v11_0_compute_ring_init(adev, ring_id,
+3
-2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+3
-2
drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
···
2728
2728
u32 *hpd;
2729
2729
size_t mec_hpd_size;
2730
2730
2731
-
bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2731
+
bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
2732
2732
2733
2733
/* take ownership of the relevant compute queues */
2734
2734
amdgpu_gfx_compute_queue_acquire(adev);
···
4456
4456
for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4457
4457
for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4458
4458
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4459
-
if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
4459
+
if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
4460
+
k, j))
4460
4461
continue;
4461
4462
4462
4463
r = gfx_v7_0_compute_ring_init(adev,
+4
-3
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+4
-3
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
···
1304
1304
u32 *hpd;
1305
1305
size_t mec_hpd_size;
1306
1306
1307
-
bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1307
+
bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1308
1308
1309
1309
/* take ownership of the relevant compute queues */
1310
1310
amdgpu_gfx_compute_queue_acquire(adev);
···
2001
2001
for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2002
2002
for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2003
2003
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2004
-
if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2004
+
if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
2005
+
k, j))
2005
2006
continue;
2006
2007
2007
2008
r = gfx_v8_0_compute_ring_init(adev,
···
4320
4319
int r, i;
4321
4320
4322
4321
for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
4323
-
if (!test_bit(i, adev->gfx.mec.queue_bitmap))
4322
+
if (!test_bit(i, adev->gfx.mec_bitmap[0].queue_bitmap))
4324
4323
continue;
4325
4324
4326
4325
/* This situation may be hit in the future if a new HW
+3
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+3
-2
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
···
1713
1713
1714
1714
const struct gfx_firmware_header_v1_0 *mec_hdr;
1715
1715
1716
-
bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1716
+
bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1717
1717
1718
1718
/* take ownership of the relevant compute queues */
1719
1719
amdgpu_gfx_compute_queue_acquire(adev);
···
2154
2154
for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
2155
2155
for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
2156
2156
for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
2157
-
if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
2157
+
if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
2158
+
k, j))
2158
2159
continue;
2159
2160
2160
2161
r = gfx_v9_0_compute_ring_init(adev,