clk: qcom: Add driver for MSM8909 GCC · tjh.dev/kernel@bf37a05

+8

drivers/clk/qcom/Kconfig

··· 180 180 Say Y if you want to use peripheral devices such as UART, SPI, 181 181 i2c, USB, SD/eMMC, etc. 182 182 183 + config MSM_GCC_8909 184 + tristate "MSM8909 Global Clock Controller" 185 + select QCOM_GDSC 186 + help 187 + Support for the global clock controller on msm8909 devices. 188 + Say Y if you want to use devices such as UART, SPI, I2C, USB, 189 + SD/eMMC, display, graphics, camera etc. 190 + 183 191 config MSM_GCC_8916 184 192 tristate "MSM8916 Global Clock Controller" 185 193 select QCOM_GDSC

+1

drivers/clk/qcom/Makefile

··· 32 32 obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o 33 33 obj-$(CONFIG_MDM_LCC_9615) += lcc-mdm9615.o 34 34 obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o 35 + obj-$(CONFIG_MSM_GCC_8909) += gcc-msm8909.o 35 36 obj-$(CONFIG_MSM_GCC_8916) += gcc-msm8916.o 36 37 obj-$(CONFIG_MSM_GCC_8939) += gcc-msm8939.o 37 38 obj-$(CONFIG_MSM_GCC_8953) += gcc-msm8953.o

+2731

drivers/clk/qcom/gcc-msm8909.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * Copyright (C) 2022 Kernkonzept GmbH. 4 + * 5 + * Based on gcc-msm8916.c: 6 + * Copyright 2015 Linaro Limited 7 + * adapted with data from clock-gcc-8909.c in Qualcomm's msm-3.18 release: 8 + * Copyright (c) 2014-2016, The Linux Foundation. All rights reserved. 9 + */ 10 + 11 + #include <linux/bitops.h> 12 + #include <linux/clk-provider.h> 13 + #include <linux/err.h> 14 + #include <linux/kernel.h> 15 + #include <linux/module.h> 16 + #include <linux/of.h> 17 + #include <linux/of_device.h> 18 + #include <linux/platform_device.h> 19 + #include <linux/regmap.h> 20 + #include <linux/reset-controller.h> 21 + 22 + #include <dt-bindings/clock/qcom,gcc-msm8909.h> 23 + 24 + #include "clk-alpha-pll.h" 25 + #include "clk-branch.h" 26 + #include "clk-pll.h" 27 + #include "clk-rcg.h" 28 + #include "clk-regmap.h" 29 + #include "common.h" 30 + #include "gdsc.h" 31 + #include "reset.h" 32 + 33 + /* Need to match the order of clocks in DT binding */ 34 + enum { 35 + DT_XO, 36 + DT_SLEEP_CLK, 37 + DT_DSI0PLL, 38 + DT_DSI0PLL_BYTE, 39 + }; 40 + 41 + enum { 42 + P_XO, 43 + P_SLEEP_CLK, 44 + P_GPLL0, 45 + P_GPLL1, 46 + P_GPLL2, 47 + P_BIMC, 48 + P_DSI0PLL, 49 + P_DSI0PLL_BYTE, 50 + }; 51 + 52 + static const struct parent_map gcc_xo_map[] = { 53 + { P_XO, 0 }, 54 + }; 55 + 56 + static const struct clk_parent_data gcc_xo_data[] = { 57 + { .index = DT_XO }, 58 + }; 59 + 60 + static const struct clk_parent_data gcc_sleep_clk_data[] = { 61 + { .index = DT_SLEEP_CLK }, 62 + }; 63 + 64 + static struct clk_alpha_pll gpll0_early = { 65 + .offset = 0x21000, 66 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 67 + .clkr = { 68 + .enable_reg = 0x45000, 69 + .enable_mask = BIT(0), 70 + .hw.init = &(struct clk_init_data) { 71 + .name = "gpll0_early", 72 + .parent_data = gcc_xo_data, 73 + .num_parents = ARRAY_SIZE(gcc_xo_data), 74 + /* Avoid rate changes for shared clock */ 75 + .ops = &clk_alpha_pll_fixed_ops, 76 + }, 77 + }, 78 + }; 79 + 80 + static struct clk_alpha_pll_postdiv gpll0 = { 81 + .offset = 0x21000, 82 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 83 + .clkr.hw.init = &(struct clk_init_data) { 84 + .name = "gpll0", 85 + .parent_hws = (const struct clk_hw*[]) { 86 + &gpll0_early.clkr.hw, 87 + }, 88 + .num_parents = 1, 89 + /* Avoid rate changes for shared clock */ 90 + .ops = &clk_alpha_pll_postdiv_ro_ops, 91 + }, 92 + }; 93 + 94 + static struct clk_pll gpll1 = { 95 + .l_reg = 0x20004, 96 + .m_reg = 0x20008, 97 + .n_reg = 0x2000c, 98 + .config_reg = 0x20010, 99 + .mode_reg = 0x20000, 100 + .status_reg = 0x2001c, 101 + .status_bit = 17, 102 + .clkr.hw.init = &(struct clk_init_data) { 103 + .name = "gpll1", 104 + .parent_data = gcc_xo_data, 105 + .num_parents = ARRAY_SIZE(gcc_xo_data), 106 + .ops = &clk_pll_ops, 107 + }, 108 + }; 109 + 110 + static struct clk_regmap gpll1_vote = { 111 + .enable_reg = 0x45000, 112 + .enable_mask = BIT(1), 113 + .hw.init = &(struct clk_init_data) { 114 + .name = "gpll1_vote", 115 + .parent_hws = (const struct clk_hw*[]) { 116 + &gpll1.clkr.hw, 117 + }, 118 + .num_parents = 1, 119 + .ops = &clk_pll_vote_ops, 120 + }, 121 + }; 122 + 123 + static struct clk_alpha_pll gpll2_early = { 124 + .offset = 0x25000, 125 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 126 + .clkr = { 127 + .enable_reg = 0x45000, 128 + .enable_mask = BIT(3), 129 + .hw.init = &(struct clk_init_data) { 130 + .name = "gpll2_early", 131 + .parent_data = gcc_xo_data, 132 + .num_parents = ARRAY_SIZE(gcc_xo_data), 133 + /* Avoid rate changes for shared clock */ 134 + .ops = &clk_alpha_pll_fixed_ops, 135 + }, 136 + }, 137 + }; 138 + 139 + static struct clk_alpha_pll_postdiv gpll2 = { 140 + .offset = 0x25000, 141 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 142 + .clkr.hw.init = &(struct clk_init_data) { 143 + .name = "gpll2", 144 + .parent_hws = (const struct clk_hw*[]) { 145 + &gpll2_early.clkr.hw, 146 + }, 147 + .num_parents = 1, 148 + /* Avoid rate changes for shared clock */ 149 + .ops = &clk_alpha_pll_postdiv_ro_ops, 150 + }, 151 + }; 152 + 153 + static struct clk_alpha_pll bimc_pll_early = { 154 + .offset = 0x23000, 155 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 156 + .clkr = { 157 + .enable_reg = 0x45000, 158 + .enable_mask = BIT(2), 159 + .hw.init = &(struct clk_init_data) { 160 + .name = "bimc_pll_early", 161 + .parent_data = gcc_xo_data, 162 + .num_parents = ARRAY_SIZE(gcc_xo_data), 163 + /* Avoid rate changes for shared clock */ 164 + .ops = &clk_alpha_pll_fixed_ops, 165 + }, 166 + }, 167 + }; 168 + 169 + static struct clk_alpha_pll_postdiv bimc_pll = { 170 + .offset = 0x23000, 171 + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT], 172 + .clkr.hw.init = &(struct clk_init_data) { 173 + .name = "bimc_pll", 174 + .parent_hws = (const struct clk_hw*[]) { 175 + &bimc_pll_early.clkr.hw, 176 + }, 177 + .num_parents = 1, 178 + /* Avoid rate changes for shared clock */ 179 + .ops = &clk_alpha_pll_postdiv_ro_ops, 180 + }, 181 + }; 182 + 183 + static const struct parent_map gcc_xo_gpll0_map[] = { 184 + { P_XO, 0 }, 185 + { P_GPLL0, 1 }, 186 + }; 187 + 188 + static const struct clk_parent_data gcc_xo_gpll0_data[] = { 189 + { .index = DT_XO }, 190 + { .hw = &gpll0.clkr.hw }, 191 + }; 192 + 193 + static const struct parent_map gcc_xo_gpll0_bimc_map[] = { 194 + { P_XO, 0 }, 195 + { P_GPLL0, 1 }, 196 + { P_BIMC, 2 }, 197 + }; 198 + 199 + static const struct clk_parent_data gcc_xo_gpll0_bimc_data[] = { 200 + { .index = DT_XO }, 201 + { .hw = &gpll0.clkr.hw }, 202 + { .hw = &bimc_pll.clkr.hw }, 203 + }; 204 + 205 + static const struct freq_tbl ftbl_apss_ahb_clk_src[] = { 206 + F(19200000, P_XO, 1, 0, 0), 207 + F(50000000, P_GPLL0, 16, 0, 0), 208 + F(100000000, P_GPLL0, 8, 0, 0), 209 + { } 210 + }; 211 + 212 + static struct clk_rcg2 apss_ahb_clk_src = { 213 + .cmd_rcgr = 0x46000, 214 + .hid_width = 5, 215 + .freq_tbl = ftbl_apss_ahb_clk_src, 216 + .parent_map = gcc_xo_gpll0_map, 217 + .clkr.hw.init = &(struct clk_init_data) { 218 + .name = "apss_ahb_clk_src", 219 + .parent_data = gcc_xo_gpll0_data, 220 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 221 + .ops = &clk_rcg2_ops, 222 + } 223 + }; 224 + 225 + static struct clk_rcg2 bimc_ddr_clk_src = { 226 + .cmd_rcgr = 0x32004, 227 + .hid_width = 5, 228 + .parent_map = gcc_xo_gpll0_bimc_map, 229 + .clkr.hw.init = &(struct clk_init_data) { 230 + .name = "bimc_ddr_clk_src", 231 + .parent_data = gcc_xo_gpll0_bimc_data, 232 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data), 233 + .ops = &clk_rcg2_ops, 234 + .flags = CLK_GET_RATE_NOCACHE, 235 + }, 236 + }; 237 + 238 + static struct clk_rcg2 bimc_gpu_clk_src = { 239 + .cmd_rcgr = 0x31028, 240 + .hid_width = 5, 241 + .parent_map = gcc_xo_gpll0_bimc_map, 242 + .clkr.hw.init = &(struct clk_init_data) { 243 + .name = "bimc_gpu_clk_src", 244 + .parent_data = gcc_xo_gpll0_bimc_data, 245 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data), 246 + .ops = &clk_rcg2_ops, 247 + .flags = CLK_GET_RATE_NOCACHE, 248 + }, 249 + }; 250 + 251 + static const struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = { 252 + F(19200000, P_XO, 1, 0, 0), 253 + F(50000000, P_GPLL0, 16, 0, 0), 254 + { } 255 + }; 256 + 257 + static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = { 258 + .cmd_rcgr = 0x0200c, 259 + .hid_width = 5, 260 + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 261 + .parent_map = gcc_xo_gpll0_map, 262 + .clkr.hw.init = &(struct clk_init_data) { 263 + .name = "blsp1_qup1_i2c_apps_clk_src", 264 + .parent_data = gcc_xo_gpll0_data, 265 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 266 + .ops = &clk_rcg2_ops, 267 + } 268 + }; 269 + 270 + static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = { 271 + .cmd_rcgr = 0x03000, 272 + .hid_width = 5, 273 + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 274 + .parent_map = gcc_xo_gpll0_map, 275 + .clkr.hw.init = &(struct clk_init_data) { 276 + .name = "blsp1_qup2_i2c_apps_clk_src", 277 + .parent_data = gcc_xo_gpll0_data, 278 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 279 + .ops = &clk_rcg2_ops, 280 + } 281 + }; 282 + 283 + static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = { 284 + .cmd_rcgr = 0x04000, 285 + .hid_width = 5, 286 + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 287 + .parent_map = gcc_xo_gpll0_map, 288 + .clkr.hw.init = &(struct clk_init_data) { 289 + .name = "blsp1_qup3_i2c_apps_clk_src", 290 + .parent_data = gcc_xo_gpll0_data, 291 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 292 + .ops = &clk_rcg2_ops, 293 + } 294 + }; 295 + 296 + static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = { 297 + .cmd_rcgr = 0x05000, 298 + .hid_width = 5, 299 + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 300 + .parent_map = gcc_xo_gpll0_map, 301 + .clkr.hw.init = &(struct clk_init_data) { 302 + .name = "blsp1_qup4_i2c_apps_clk_src", 303 + .parent_data = gcc_xo_gpll0_data, 304 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 305 + .ops = &clk_rcg2_ops, 306 + } 307 + }; 308 + 309 + static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = { 310 + .cmd_rcgr = 0x06000, 311 + .hid_width = 5, 312 + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 313 + .parent_map = gcc_xo_gpll0_map, 314 + .clkr.hw.init = &(struct clk_init_data) { 315 + .name = "blsp1_qup5_i2c_apps_clk_src", 316 + .parent_data = gcc_xo_gpll0_data, 317 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 318 + .ops = &clk_rcg2_ops, 319 + } 320 + }; 321 + 322 + static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = { 323 + .cmd_rcgr = 0x07000, 324 + .hid_width = 5, 325 + .freq_tbl = ftbl_blsp_i2c_apps_clk_src, 326 + .parent_map = gcc_xo_gpll0_map, 327 + .clkr.hw.init = &(struct clk_init_data) { 328 + .name = "blsp1_qup6_i2c_apps_clk_src", 329 + .parent_data = gcc_xo_gpll0_data, 330 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 331 + .ops = &clk_rcg2_ops, 332 + } 333 + }; 334 + 335 + static const struct freq_tbl ftbl_blsp_spi_apps_clk_src[] = { 336 + F(960000, P_XO, 10, 1, 2), 337 + F(4800000, P_XO, 4, 0, 0), 338 + F(9600000, P_XO, 2, 0, 0), 339 + F(16000000, P_GPLL0, 10, 1, 5), 340 + F(19200000, P_XO, 1, 0, 0), 341 + F(25000000, P_GPLL0, 16, 1, 2), 342 + F(50000000, P_GPLL0, 16, 0, 0), 343 + { } 344 + }; 345 + 346 + static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = { 347 + .cmd_rcgr = 0x02024, 348 + .hid_width = 5, 349 + .mnd_width = 8, 350 + .freq_tbl = ftbl_blsp_spi_apps_clk_src, 351 + .parent_map = gcc_xo_gpll0_map, 352 + .clkr.hw.init = &(struct clk_init_data) { 353 + .name = "blsp1_qup1_spi_apps_clk_src", 354 + .parent_data = gcc_xo_gpll0_data, 355 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 356 + .ops = &clk_rcg2_ops, 357 + } 358 + }; 359 + 360 + static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = { 361 + .cmd_rcgr = 0x03014, 362 + .hid_width = 5, 363 + .mnd_width = 8, 364 + .freq_tbl = ftbl_blsp_spi_apps_clk_src, 365 + .parent_map = gcc_xo_gpll0_map, 366 + .clkr.hw.init = &(struct clk_init_data) { 367 + .name = "blsp1_qup2_spi_apps_clk_src", 368 + .parent_data = gcc_xo_gpll0_data, 369 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 370 + .ops = &clk_rcg2_ops, 371 + } 372 + }; 373 + 374 + static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = { 375 + .cmd_rcgr = 0x04024, 376 + .hid_width = 5, 377 + .mnd_width = 8, 378 + .freq_tbl = ftbl_blsp_spi_apps_clk_src, 379 + .parent_map = gcc_xo_gpll0_map, 380 + .clkr.hw.init = &(struct clk_init_data) { 381 + .name = "blsp1_qup3_spi_apps_clk_src", 382 + .parent_data = gcc_xo_gpll0_data, 383 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 384 + .ops = &clk_rcg2_ops, 385 + } 386 + }; 387 + 388 + static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = { 389 + .cmd_rcgr = 0x05024, 390 + .hid_width = 5, 391 + .mnd_width = 8, 392 + .freq_tbl = ftbl_blsp_spi_apps_clk_src, 393 + .parent_map = gcc_xo_gpll0_map, 394 + .clkr.hw.init = &(struct clk_init_data) { 395 + .name = "blsp1_qup4_spi_apps_clk_src", 396 + .parent_data = gcc_xo_gpll0_data, 397 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 398 + .ops = &clk_rcg2_ops, 399 + } 400 + }; 401 + 402 + static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = { 403 + .cmd_rcgr = 0x06024, 404 + .hid_width = 5, 405 + .mnd_width = 8, 406 + .freq_tbl = ftbl_blsp_spi_apps_clk_src, 407 + .parent_map = gcc_xo_gpll0_map, 408 + .clkr.hw.init = &(struct clk_init_data) { 409 + .name = "blsp1_qup5_spi_apps_clk_src", 410 + .parent_data = gcc_xo_gpll0_data, 411 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 412 + .ops = &clk_rcg2_ops, 413 + } 414 + }; 415 + 416 + static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = { 417 + .cmd_rcgr = 0x07024, 418 + .hid_width = 5, 419 + .mnd_width = 8, 420 + .freq_tbl = ftbl_blsp_spi_apps_clk_src, 421 + .parent_map = gcc_xo_gpll0_map, 422 + .clkr.hw.init = &(struct clk_init_data) { 423 + .name = "blsp1_qup6_spi_apps_clk_src", 424 + .parent_data = gcc_xo_gpll0_data, 425 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 426 + .ops = &clk_rcg2_ops, 427 + } 428 + }; 429 + 430 + static const struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = { 431 + F(3686400, P_GPLL0, 1, 72, 15625), 432 + F(7372800, P_GPLL0, 1, 144, 15625), 433 + F(14745600, P_GPLL0, 1, 288, 15625), 434 + F(16000000, P_GPLL0, 10, 1, 5), 435 + F(19200000, P_XO, 1, 0, 0), 436 + F(24000000, P_GPLL0, 1, 3, 100), 437 + F(25000000, P_GPLL0, 16, 1, 2), 438 + F(32000000, P_GPLL0, 1, 1, 25), 439 + F(40000000, P_GPLL0, 1, 1, 20), 440 + F(46400000, P_GPLL0, 1, 29, 500), 441 + F(48000000, P_GPLL0, 1, 3, 50), 442 + F(51200000, P_GPLL0, 1, 8, 125), 443 + F(56000000, P_GPLL0, 1, 7, 100), 444 + F(58982400, P_GPLL0, 1, 1152, 15625), 445 + F(60000000, P_GPLL0, 1, 3, 40), 446 + { } 447 + }; 448 + 449 + static struct clk_rcg2 blsp1_uart1_apps_clk_src = { 450 + .cmd_rcgr = 0x02044, 451 + .hid_width = 5, 452 + .mnd_width = 16, 453 + .freq_tbl = ftbl_blsp_uart_apps_clk_src, 454 + .parent_map = gcc_xo_gpll0_map, 455 + .clkr.hw.init = &(struct clk_init_data) { 456 + .name = "blsp1_uart1_apps_clk_src", 457 + .parent_data = gcc_xo_gpll0_data, 458 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 459 + .ops = &clk_rcg2_ops, 460 + } 461 + }; 462 + 463 + static struct clk_rcg2 blsp1_uart2_apps_clk_src = { 464 + .cmd_rcgr = 0x03034, 465 + .hid_width = 5, 466 + .mnd_width = 16, 467 + .freq_tbl = ftbl_blsp_uart_apps_clk_src, 468 + .parent_map = gcc_xo_gpll0_map, 469 + .clkr.hw.init = &(struct clk_init_data) { 470 + .name = "blsp1_uart2_apps_clk_src", 471 + .parent_data = gcc_xo_gpll0_data, 472 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 473 + .ops = &clk_rcg2_ops, 474 + } 475 + }; 476 + 477 + static const struct parent_map gcc_byte0_map[] = { 478 + { P_XO, 0 }, 479 + { P_DSI0PLL_BYTE, 1 }, 480 + }; 481 + 482 + static const struct clk_parent_data gcc_byte_data[] = { 483 + { .index = DT_XO }, 484 + { .index = DT_DSI0PLL_BYTE }, 485 + }; 486 + 487 + static struct clk_rcg2 byte0_clk_src = { 488 + .cmd_rcgr = 0x4d044, 489 + .hid_width = 5, 490 + .parent_map = gcc_byte0_map, 491 + .clkr.hw.init = &(struct clk_init_data) { 492 + .name = "byte0_clk_src", 493 + .parent_data = gcc_byte_data, 494 + .num_parents = ARRAY_SIZE(gcc_byte_data), 495 + .ops = &clk_byte2_ops, 496 + .flags = CLK_SET_RATE_PARENT, 497 + } 498 + }; 499 + 500 + static const struct freq_tbl ftbl_camss_gp_clk_src[] = { 501 + F(100000000, P_GPLL0, 8, 0, 0), 502 + F(200000000, P_GPLL0, 4, 0, 0), 503 + { } 504 + }; 505 + 506 + static struct clk_rcg2 camss_gp0_clk_src = { 507 + .cmd_rcgr = 0x54000, 508 + .hid_width = 5, 509 + .mnd_width = 8, 510 + .freq_tbl = ftbl_camss_gp_clk_src, 511 + .parent_map = gcc_xo_gpll0_map, 512 + .clkr.hw.init = &(struct clk_init_data) { 513 + .name = "camss_gp0_clk_src", 514 + .parent_data = gcc_xo_gpll0_data, 515 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 516 + .ops = &clk_rcg2_ops, 517 + } 518 + }; 519 + 520 + static struct clk_rcg2 camss_gp1_clk_src = { 521 + .cmd_rcgr = 0x55000, 522 + .hid_width = 5, 523 + .mnd_width = 8, 524 + .freq_tbl = ftbl_camss_gp_clk_src, 525 + .parent_map = gcc_xo_gpll0_map, 526 + .clkr.hw.init = &(struct clk_init_data) { 527 + .name = "camss_gp1_clk_src", 528 + .parent_data = gcc_xo_gpll0_data, 529 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 530 + .ops = &clk_rcg2_ops, 531 + } 532 + }; 533 + 534 + static const struct freq_tbl ftbl_camss_top_ahb_clk_src[] = { 535 + F(40000000, P_GPLL0, 10, 1, 2), 536 + F(80000000, P_GPLL0, 10, 0, 0), 537 + { } 538 + }; 539 + 540 + static struct clk_rcg2 camss_top_ahb_clk_src = { 541 + .cmd_rcgr = 0x5a000, 542 + .hid_width = 5, 543 + .mnd_width = 8, 544 + .freq_tbl = ftbl_camss_top_ahb_clk_src, 545 + .parent_map = gcc_xo_gpll0_map, 546 + .clkr.hw.init = &(struct clk_init_data) { 547 + .name = "camss_top_ahb_clk_src", 548 + .parent_data = gcc_xo_gpll0_data, 549 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 550 + .ops = &clk_rcg2_ops, 551 + } 552 + }; 553 + 554 + static const struct freq_tbl ftbl_crypto_clk_src[] = { 555 + F(50000000, P_GPLL0, 16, 0, 0), 556 + F(80000000, P_GPLL0, 10, 0, 0), 557 + F(100000000, P_GPLL0, 8, 0, 0), 558 + F(160000000, P_GPLL0, 5, 0, 0), 559 + { } 560 + }; 561 + 562 + static struct clk_rcg2 crypto_clk_src = { 563 + .cmd_rcgr = 0x16004, 564 + .hid_width = 5, 565 + .freq_tbl = ftbl_crypto_clk_src, 566 + .parent_map = gcc_xo_gpll0_map, 567 + .clkr.hw.init = &(struct clk_init_data) { 568 + .name = "crypto_clk_src", 569 + .parent_data = gcc_xo_gpll0_data, 570 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 571 + .ops = &clk_rcg2_ops, 572 + } 573 + }; 574 + 575 + static const struct freq_tbl ftbl_csi_clk_src[] = { 576 + F(100000000, P_GPLL0, 8, 0, 0), 577 + F(200000000, P_GPLL0, 4, 0, 0), 578 + { } 579 + }; 580 + 581 + static struct clk_rcg2 csi0_clk_src = { 582 + .cmd_rcgr = 0x4e020, 583 + .hid_width = 5, 584 + .freq_tbl = ftbl_csi_clk_src, 585 + .parent_map = gcc_xo_gpll0_map, 586 + .clkr.hw.init = &(struct clk_init_data) { 587 + .name = "csi0_clk_src", 588 + .parent_data = gcc_xo_gpll0_data, 589 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_map), 590 + .ops = &clk_rcg2_ops, 591 + } 592 + }; 593 + 594 + static struct clk_rcg2 csi1_clk_src = { 595 + .cmd_rcgr = 0x4f020, 596 + .hid_width = 5, 597 + .freq_tbl = ftbl_csi_clk_src, 598 + .parent_map = gcc_xo_gpll0_map, 599 + .clkr.hw.init = &(struct clk_init_data) { 600 + .name = "csi1_clk_src", 601 + .parent_data = gcc_xo_gpll0_data, 602 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 603 + .ops = &clk_rcg2_ops, 604 + } 605 + }; 606 + 607 + static const struct freq_tbl ftbl_csi_phytimer_clk_src[] = { 608 + F(100000000, P_GPLL0, 8, 0, 0), 609 + F(200000000, P_GPLL0, 4, 0, 0), 610 + { } 611 + }; 612 + 613 + static struct clk_rcg2 csi0phytimer_clk_src = { 614 + .cmd_rcgr = 0x4e000, 615 + .hid_width = 5, 616 + .freq_tbl = ftbl_csi_phytimer_clk_src, 617 + .parent_map = gcc_xo_gpll0_map, 618 + .clkr.hw.init = &(struct clk_init_data) { 619 + .name = "csi0phytimer_clk_src", 620 + .parent_data = gcc_xo_gpll0_data, 621 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 622 + .ops = &clk_rcg2_ops, 623 + } 624 + }; 625 + 626 + static const struct freq_tbl ftbl_esc0_clk_src[] = { 627 + F(19200000, P_XO, 1, 0, 0), 628 + { } 629 + }; 630 + 631 + static struct clk_rcg2 esc0_clk_src = { 632 + .cmd_rcgr = 0x4d05c, 633 + .hid_width = 5, 634 + .freq_tbl = ftbl_esc0_clk_src, 635 + .parent_map = gcc_xo_map, 636 + .clkr.hw.init = &(struct clk_init_data) { 637 + .name = "esc0_clk_src", 638 + .parent_data = gcc_xo_data, 639 + .num_parents = ARRAY_SIZE(gcc_xo_data), 640 + .ops = &clk_rcg2_ops, 641 + } 642 + }; 643 + 644 + static const struct parent_map gcc_gfx3d_map[] = { 645 + { P_XO, 0 }, 646 + { P_GPLL0, 1 }, 647 + { P_GPLL1, 2 }, 648 + }; 649 + 650 + static const struct clk_parent_data gcc_gfx3d_data[] = { 651 + { .index = DT_XO }, 652 + { .hw = &gpll0.clkr.hw }, 653 + { .hw = &gpll1_vote.hw }, 654 + }; 655 + 656 + static const struct freq_tbl ftbl_gfx3d_clk_src[] = { 657 + F(19200000, P_XO, 1, 0, 0), 658 + F(50000000, P_GPLL0, 16, 0, 0), 659 + F(80000000, P_GPLL0, 10, 0, 0), 660 + F(100000000, P_GPLL0, 8, 0, 0), 661 + F(160000000, P_GPLL0, 5, 0, 0), 662 + F(177780000, P_GPLL0, 4.5, 0, 0), 663 + F(200000000, P_GPLL0, 4, 0, 0), 664 + F(266670000, P_GPLL0, 3, 0, 0), 665 + F(307200000, P_GPLL1, 4, 0, 0), 666 + F(409600000, P_GPLL1, 3, 0, 0), 667 + { } 668 + }; 669 + 670 + static struct clk_rcg2 gfx3d_clk_src = { 671 + .cmd_rcgr = 0x59000, 672 + .hid_width = 5, 673 + .freq_tbl = ftbl_gfx3d_clk_src, 674 + .parent_map = gcc_gfx3d_map, 675 + .clkr.hw.init = &(struct clk_init_data) { 676 + .name = "gfx3d_clk_src", 677 + .parent_data = gcc_gfx3d_data, 678 + .num_parents = ARRAY_SIZE(gcc_gfx3d_data), 679 + .ops = &clk_rcg2_ops, 680 + } 681 + }; 682 + 683 + static const struct freq_tbl ftbl_gp_clk_src[] = { 684 + F(150000, P_XO, 1, 1, 128), 685 + F(19200000, P_XO, 1, 0, 0), 686 + { } 687 + }; 688 + 689 + static struct clk_rcg2 gp1_clk_src = { 690 + .cmd_rcgr = 0x08004, 691 + .hid_width = 5, 692 + .mnd_width = 8, 693 + .freq_tbl = ftbl_gp_clk_src, 694 + .parent_map = gcc_xo_map, 695 + .clkr.hw.init = &(struct clk_init_data) { 696 + .name = "gp1_clk_src", 697 + .parent_data = gcc_xo_data, 698 + .num_parents = ARRAY_SIZE(gcc_xo_data), 699 + .ops = &clk_rcg2_ops, 700 + } 701 + }; 702 + 703 + static struct clk_rcg2 gp2_clk_src = { 704 + .cmd_rcgr = 0x09004, 705 + .hid_width = 5, 706 + .mnd_width = 8, 707 + .freq_tbl = ftbl_gp_clk_src, 708 + .parent_map = gcc_xo_map, 709 + .clkr.hw.init = &(struct clk_init_data) { 710 + .name = "gp2_clk_src", 711 + .parent_data = gcc_xo_data, 712 + .num_parents = ARRAY_SIZE(gcc_xo_data), 713 + .ops = &clk_rcg2_ops, 714 + } 715 + }; 716 + 717 + static struct clk_rcg2 gp3_clk_src = { 718 + .cmd_rcgr = 0x0a004, 719 + .hid_width = 5, 720 + .mnd_width = 8, 721 + .freq_tbl = ftbl_gp_clk_src, 722 + .parent_map = gcc_xo_map, 723 + .clkr.hw.init = &(struct clk_init_data) { 724 + .name = "gp3_clk_src", 725 + .parent_data = gcc_xo_data, 726 + .num_parents = ARRAY_SIZE(gcc_xo_data), 727 + .ops = &clk_rcg2_ops, 728 + } 729 + }; 730 + 731 + static const struct parent_map gcc_mclk_map[] = { 732 + { P_XO, 0 }, 733 + { P_GPLL0, 1 }, 734 + { P_GPLL2, 3 }, 735 + }; 736 + 737 + static const struct clk_parent_data gcc_mclk_data[] = { 738 + { .index = DT_XO }, 739 + { .hw = &gpll0.clkr.hw }, 740 + { .hw = &gpll2.clkr.hw }, 741 + }; 742 + 743 + static const struct freq_tbl ftbl_mclk_clk_src[] = { 744 + F(24000000, P_GPLL2, 1, 1, 33), 745 + F(66667000, P_GPLL0, 12, 0, 0), 746 + { } 747 + }; 748 + 749 + static struct clk_rcg2 mclk0_clk_src = { 750 + .cmd_rcgr = 0x52000, 751 + .hid_width = 5, 752 + .mnd_width = 8, 753 + .freq_tbl = ftbl_mclk_clk_src, 754 + .parent_map = gcc_mclk_map, 755 + .clkr.hw.init = &(struct clk_init_data) { 756 + .name = "mclk0_clk_src", 757 + .parent_data = gcc_mclk_data, 758 + .num_parents = ARRAY_SIZE(gcc_mclk_data), 759 + .ops = &clk_rcg2_ops, 760 + } 761 + }; 762 + 763 + static struct clk_rcg2 mclk1_clk_src = { 764 + .cmd_rcgr = 0x53000, 765 + .hid_width = 5, 766 + .mnd_width = 8, 767 + .freq_tbl = ftbl_mclk_clk_src, 768 + .parent_map = gcc_mclk_map, 769 + .clkr.hw.init = &(struct clk_init_data) { 770 + .name = "mclk1_clk_src", 771 + .parent_data = gcc_mclk_data, 772 + .num_parents = ARRAY_SIZE(gcc_mclk_data), 773 + .ops = &clk_rcg2_ops, 774 + } 775 + }; 776 + 777 + static const struct parent_map gcc_mdp_map[] = { 778 + { P_XO, 0 }, 779 + { P_GPLL0, 1 }, 780 + { P_GPLL1, 3 }, 781 + }; 782 + 783 + static const struct clk_parent_data gcc_mdp_data[] = { 784 + { .index = DT_XO }, 785 + { .hw = &gpll0.clkr.hw }, 786 + { .hw = &gpll1_vote.hw }, 787 + }; 788 + 789 + static const struct freq_tbl ftbl_mdp_clk_src[] = { 790 + F(50000000, P_GPLL0, 16, 0, 0), 791 + F(80000000, P_GPLL0, 10, 0, 0), 792 + F(100000000, P_GPLL0, 8, 0, 0), 793 + F(160000000, P_GPLL0, 5, 0, 0), 794 + F(177780000, P_GPLL0, 4.5, 0, 0), 795 + F(200000000, P_GPLL0, 4, 0, 0), 796 + F(266670000, P_GPLL0, 3, 0, 0), 797 + F(307200000, P_GPLL1, 4, 0, 0), 798 + { } 799 + }; 800 + 801 + static struct clk_rcg2 mdp_clk_src = { 802 + .cmd_rcgr = 0x4d014, 803 + .hid_width = 5, 804 + .freq_tbl = ftbl_mdp_clk_src, 805 + .parent_map = gcc_mdp_map, 806 + .clkr.hw.init = &(struct clk_init_data) { 807 + .name = "mdp_clk_src", 808 + .parent_data = gcc_mdp_data, 809 + .num_parents = ARRAY_SIZE(gcc_mdp_data), 810 + .ops = &clk_rcg2_ops, 811 + } 812 + }; 813 + 814 + static const struct parent_map gcc_pclk0_map[] = { 815 + { P_XO, 0 }, 816 + { P_DSI0PLL, 1 }, 817 + }; 818 + 819 + static const struct clk_parent_data gcc_pclk_data[] = { 820 + { .index = DT_XO }, 821 + { .index = DT_DSI0PLL }, 822 + }; 823 + 824 + static struct clk_rcg2 pclk0_clk_src = { 825 + .cmd_rcgr = 0x4d000, 826 + .hid_width = 5, 827 + .mnd_width = 8, 828 + .parent_map = gcc_pclk0_map, 829 + .clkr.hw.init = &(struct clk_init_data) { 830 + .name = "pclk0_clk_src", 831 + .parent_data = gcc_pclk_data, 832 + .num_parents = ARRAY_SIZE(gcc_pclk_data), 833 + .ops = &clk_pixel_ops, 834 + .flags = CLK_SET_RATE_PARENT, 835 + } 836 + }; 837 + 838 + static struct clk_rcg2 pcnoc_bfdcd_clk_src = { 839 + .cmd_rcgr = 0x27000, 840 + .hid_width = 5, 841 + .parent_map = gcc_xo_gpll0_bimc_map, 842 + .clkr.hw.init = &(struct clk_init_data) { 843 + .name = "pcnoc_bfdcd_clk_src", 844 + .parent_data = gcc_xo_gpll0_bimc_data, 845 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data), 846 + .ops = &clk_rcg2_ops, 847 + }, 848 + }; 849 + 850 + static const struct freq_tbl ftbl_pdm2_clk_src[] = { 851 + F(64000000, P_GPLL0, 12.5, 0, 0), 852 + { } 853 + }; 854 + 855 + static struct clk_rcg2 pdm2_clk_src = { 856 + .cmd_rcgr = 0x44010, 857 + .hid_width = 5, 858 + .freq_tbl = ftbl_pdm2_clk_src, 859 + .parent_map = gcc_xo_gpll0_map, 860 + .clkr.hw.init = &(struct clk_init_data) { 861 + .name = "pdm2_clk_src", 862 + .parent_data = gcc_xo_gpll0_data, 863 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 864 + .ops = &clk_rcg2_ops, 865 + } 866 + }; 867 + 868 + static const struct freq_tbl ftbl_gcc_sdcc1_2_apps_clk[] = { 869 + F(144000, P_XO, 16, 3, 25), 870 + F(400000, P_XO, 12, 1, 4), 871 + F(20000000, P_GPLL0, 10, 1, 4), 872 + F(25000000, P_GPLL0, 16, 1, 2), 873 + F(50000000, P_GPLL0, 16, 0, 0), 874 + F(100000000, P_GPLL0, 8, 0, 0), 875 + F(177770000, P_GPLL0, 4.5, 0, 0), 876 + F(200000000, P_GPLL0, 4, 0, 0), 877 + { } 878 + }; 879 + 880 + static struct clk_rcg2 sdcc1_apps_clk_src = { 881 + .cmd_rcgr = 0x42004, 882 + .hid_width = 5, 883 + .mnd_width = 8, 884 + .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, 885 + .parent_map = gcc_xo_gpll0_map, 886 + .clkr.hw.init = &(struct clk_init_data) { 887 + .name = "sdcc1_apps_clk_src", 888 + .parent_data = gcc_xo_gpll0_data, 889 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 890 + .ops = &clk_rcg2_floor_ops, 891 + } 892 + }; 893 + 894 + static struct clk_rcg2 sdcc2_apps_clk_src = { 895 + .cmd_rcgr = 0x43004, 896 + .hid_width = 5, 897 + .mnd_width = 8, 898 + .freq_tbl = ftbl_gcc_sdcc1_2_apps_clk, 899 + .parent_map = gcc_xo_gpll0_map, 900 + .clkr.hw.init = &(struct clk_init_data) { 901 + .name = "sdcc2_apps_clk_src", 902 + .parent_data = gcc_xo_gpll0_data, 903 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 904 + .ops = &clk_rcg2_floor_ops, 905 + } 906 + }; 907 + 908 + static struct clk_rcg2 system_noc_bfdcd_clk_src = { 909 + .cmd_rcgr = 0x26004, 910 + .hid_width = 5, 911 + .parent_map = gcc_xo_gpll0_bimc_map, 912 + .clkr.hw.init = &(struct clk_init_data) { 913 + .name = "system_noc_bfdcd_clk_src", 914 + .parent_data = gcc_xo_gpll0_bimc_data, 915 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_bimc_data), 916 + .ops = &clk_rcg2_ops, 917 + }, 918 + }; 919 + 920 + static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { 921 + F(57140000, P_GPLL0, 14, 0, 0), 922 + F(80000000, P_GPLL0, 10, 0, 0), 923 + F(100000000, P_GPLL0, 8, 0, 0), 924 + { } 925 + }; 926 + 927 + static struct clk_rcg2 usb_hs_system_clk_src = { 928 + .cmd_rcgr = 0x41010, 929 + .hid_width = 5, 930 + .freq_tbl = ftbl_gcc_usb_hs_system_clk, 931 + .parent_map = gcc_xo_gpll0_map, 932 + .clkr.hw.init = &(struct clk_init_data) { 933 + .name = "usb_hs_system_clk_src", 934 + .parent_data = gcc_xo_gpll0_data, 935 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 936 + .ops = &clk_rcg2_ops, 937 + } 938 + }; 939 + 940 + static const struct parent_map gcc_vcodec0_map[] = { 941 + { P_XO, 0 }, 942 + { P_GPLL0, 1 }, 943 + { P_GPLL1, 3 }, 944 + }; 945 + 946 + static const struct clk_parent_data gcc_vcodec0_data[] = { 947 + { .index = DT_XO }, 948 + { .hw = &gpll0.clkr.hw }, 949 + { .hw = &gpll1_vote.hw }, 950 + }; 951 + 952 + static const struct freq_tbl ftbl_vcodec0_clk_src[] = { 953 + F(133330000, P_GPLL0, 6, 0, 0), 954 + F(266670000, P_GPLL0, 3, 0, 0), 955 + F(307200000, P_GPLL1, 4, 0, 0), 956 + { } 957 + }; 958 + 959 + static struct clk_rcg2 vcodec0_clk_src = { 960 + .cmd_rcgr = 0x4c000, 961 + .hid_width = 5, 962 + .mnd_width = 8, 963 + .freq_tbl = ftbl_vcodec0_clk_src, 964 + .parent_map = gcc_vcodec0_map, 965 + .clkr.hw.init = &(struct clk_init_data) { 966 + .name = "vcodec0_clk_src", 967 + .parent_data = gcc_vcodec0_data, 968 + .num_parents = ARRAY_SIZE(gcc_vcodec0_data), 969 + .ops = &clk_rcg2_ops, 970 + } 971 + }; 972 + 973 + static const struct freq_tbl ftbl_gcc_camss_vfe0_clk[] = { 974 + F(50000000, P_GPLL0, 16, 0, 0), 975 + F(80000000, P_GPLL0, 10, 0, 0), 976 + F(100000000, P_GPLL0, 8, 0, 0), 977 + F(133330000, P_GPLL0, 6, 0, 0), 978 + F(160000000, P_GPLL0, 5, 0, 0), 979 + F(177780000, P_GPLL0, 4.5, 0, 0), 980 + F(200000000, P_GPLL0, 4, 0, 0), 981 + F(266670000, P_GPLL0, 3, 0, 0), 982 + F(320000000, P_GPLL0, 2.5, 0, 0), 983 + { } 984 + }; 985 + 986 + static struct clk_rcg2 vfe0_clk_src = { 987 + .cmd_rcgr = 0x58000, 988 + .hid_width = 5, 989 + .freq_tbl = ftbl_gcc_camss_vfe0_clk, 990 + .parent_map = gcc_xo_gpll0_map, 991 + .clkr.hw.init = &(struct clk_init_data) { 992 + .name = "vfe0_clk_src", 993 + .parent_data = gcc_xo_gpll0_data, 994 + .num_parents = ARRAY_SIZE(gcc_xo_gpll0_data), 995 + .ops = &clk_rcg2_ops, 996 + } 997 + }; 998 + 999 + static const struct freq_tbl ftbl_vsync_clk_src[] = { 1000 + F(19200000, P_XO, 1, 0, 0), 1001 + { } 1002 + }; 1003 + 1004 + static struct clk_rcg2 vsync_clk_src = { 1005 + .cmd_rcgr = 0x4d02c, 1006 + .hid_width = 5, 1007 + .freq_tbl = ftbl_vsync_clk_src, 1008 + .parent_map = gcc_xo_map, 1009 + .clkr.hw.init = &(struct clk_init_data) { 1010 + .name = "vsync_clk_src", 1011 + .parent_data = gcc_xo_data, 1012 + .num_parents = ARRAY_SIZE(gcc_xo_data), 1013 + .ops = &clk_rcg2_ops, 1014 + } 1015 + }; 1016 + 1017 + static struct clk_branch gcc_apss_tcu_clk = { 1018 + .halt_reg = 0x12018, 1019 + .halt_check = BRANCH_HALT_VOTED, 1020 + .clkr = { 1021 + .enable_reg = 0x4500c, 1022 + .enable_mask = BIT(1), 1023 + .hw.init = &(struct clk_init_data) { 1024 + .name = "gcc_apss_tcu_clk", 1025 + .parent_hws = (const struct clk_hw*[]) { 1026 + &bimc_ddr_clk_src.clkr.hw, 1027 + }, 1028 + .num_parents = 1, 1029 + .ops = &clk_branch2_ops, 1030 + } 1031 + } 1032 + }; 1033 + 1034 + static struct clk_branch gcc_blsp1_ahb_clk = { 1035 + .halt_reg = 0x01008, 1036 + .halt_check = BRANCH_HALT_VOTED, 1037 + .clkr = { 1038 + .enable_reg = 0x45004, 1039 + .enable_mask = BIT(10), 1040 + .hw.init = &(struct clk_init_data) { 1041 + .name = "gcc_blsp1_ahb_clk", 1042 + .parent_hws = (const struct clk_hw*[]) { 1043 + &pcnoc_bfdcd_clk_src.clkr.hw, 1044 + }, 1045 + .num_parents = 1, 1046 + .ops = &clk_branch2_ops, 1047 + } 1048 + } 1049 + }; 1050 + 1051 + static struct clk_branch gcc_blsp1_sleep_clk = { 1052 + .halt_reg = 0x01004, 1053 + .halt_check = BRANCH_HALT_VOTED, 1054 + .clkr = { 1055 + .enable_reg = 0x45004, 1056 + .enable_mask = BIT(9), 1057 + .hw.init = &(struct clk_init_data) { 1058 + .name = "gcc_blsp1_sleep_clk", 1059 + .parent_data = gcc_sleep_clk_data, 1060 + .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), 1061 + .ops = &clk_branch2_ops, 1062 + } 1063 + } 1064 + }; 1065 + 1066 + static struct clk_branch gcc_boot_rom_ahb_clk = { 1067 + .halt_reg = 0x1300c, 1068 + .halt_check = BRANCH_HALT_VOTED, 1069 + .clkr = { 1070 + .enable_reg = 0x45004, 1071 + .enable_mask = BIT(7), 1072 + .hw.init = &(struct clk_init_data) { 1073 + .name = "gcc_boot_rom_ahb_clk", 1074 + .parent_hws = (const struct clk_hw*[]) { 1075 + &pcnoc_bfdcd_clk_src.clkr.hw, 1076 + }, 1077 + .num_parents = 1, 1078 + .ops = &clk_branch2_ops, 1079 + } 1080 + } 1081 + }; 1082 + 1083 + static struct clk_branch gcc_crypto_clk = { 1084 + .halt_reg = 0x1601c, 1085 + .halt_check = BRANCH_HALT_VOTED, 1086 + .clkr = { 1087 + .enable_reg = 0x45004, 1088 + .enable_mask = BIT(2), 1089 + .hw.init = &(struct clk_init_data) { 1090 + .name = "gcc_crypto_clk", 1091 + .parent_hws = (const struct clk_hw*[]) { 1092 + &crypto_clk_src.clkr.hw, 1093 + }, 1094 + .num_parents = 1, 1095 + .ops = &clk_branch2_ops, 1096 + .flags = CLK_SET_RATE_PARENT, 1097 + } 1098 + } 1099 + }; 1100 + 1101 + static struct clk_branch gcc_crypto_ahb_clk = { 1102 + .halt_reg = 0x16024, 1103 + .halt_check = BRANCH_HALT_VOTED, 1104 + .clkr = { 1105 + .enable_reg = 0x45004, 1106 + .enable_mask = BIT(0), 1107 + .hw.init = &(struct clk_init_data) { 1108 + .name = "gcc_crypto_ahb_clk", 1109 + .parent_hws = (const struct clk_hw*[]) { 1110 + &pcnoc_bfdcd_clk_src.clkr.hw, 1111 + }, 1112 + .num_parents = 1, 1113 + .ops = &clk_branch2_ops, 1114 + } 1115 + } 1116 + }; 1117 + 1118 + static struct clk_branch gcc_crypto_axi_clk = { 1119 + .halt_reg = 0x16020, 1120 + .halt_check = BRANCH_HALT_VOTED, 1121 + .clkr = { 1122 + .enable_reg = 0x45004, 1123 + .enable_mask = BIT(1), 1124 + .hw.init = &(struct clk_init_data) { 1125 + .name = "gcc_crypto_axi_clk", 1126 + .parent_hws = (const struct clk_hw*[]) { 1127 + &pcnoc_bfdcd_clk_src.clkr.hw, 1128 + }, 1129 + .num_parents = 1, 1130 + .ops = &clk_branch2_ops, 1131 + } 1132 + } 1133 + }; 1134 + 1135 + static struct clk_branch gcc_gfx_tbu_clk = { 1136 + .halt_reg = 0x12010, 1137 + .halt_check = BRANCH_HALT_VOTED, 1138 + .clkr = { 1139 + .enable_reg = 0x4500c, 1140 + .enable_mask = BIT(3), 1141 + .hw.init = &(struct clk_init_data) { 1142 + .name = "gcc_gfx_tbu_clk", 1143 + .parent_hws = (const struct clk_hw*[]) { 1144 + &bimc_ddr_clk_src.clkr.hw, 1145 + }, 1146 + .num_parents = 1, 1147 + .ops = &clk_branch2_ops, 1148 + } 1149 + } 1150 + }; 1151 + 1152 + static struct clk_branch gcc_gfx_tcu_clk = { 1153 + .halt_reg = 0x12020, 1154 + .halt_check = BRANCH_HALT_VOTED, 1155 + .clkr = { 1156 + .enable_reg = 0x4500c, 1157 + .enable_mask = BIT(2), 1158 + .hw.init = &(struct clk_init_data) { 1159 + .name = "gcc_gfx_tcu_clk", 1160 + .parent_hws = (const struct clk_hw*[]) { 1161 + &bimc_ddr_clk_src.clkr.hw, 1162 + }, 1163 + .num_parents = 1, 1164 + .ops = &clk_branch2_ops, 1165 + } 1166 + } 1167 + }; 1168 + 1169 + static struct clk_branch gcc_gtcu_ahb_clk = { 1170 + .halt_reg = 0x12044, 1171 + .halt_check = BRANCH_HALT_VOTED, 1172 + .clkr = { 1173 + .enable_reg = 0x4500c, 1174 + .enable_mask = BIT(13), 1175 + .hw.init = &(struct clk_init_data) { 1176 + .name = "gcc_gtcu_ahb_clk", 1177 + .parent_hws = (const struct clk_hw*[]) { 1178 + &pcnoc_bfdcd_clk_src.clkr.hw, 1179 + }, 1180 + .num_parents = 1, 1181 + .ops = &clk_branch2_ops, 1182 + } 1183 + } 1184 + }; 1185 + 1186 + static struct clk_branch gcc_mdp_tbu_clk = { 1187 + .halt_reg = 0x1201c, 1188 + .halt_check = BRANCH_HALT_VOTED, 1189 + .clkr = { 1190 + .enable_reg = 0x4500c, 1191 + .enable_mask = BIT(4), 1192 + .hw.init = &(struct clk_init_data) { 1193 + .name = "gcc_mdp_tbu_clk", 1194 + .parent_hws = (const struct clk_hw*[]) { 1195 + &system_noc_bfdcd_clk_src.clkr.hw, 1196 + }, 1197 + .num_parents = 1, 1198 + .ops = &clk_branch2_ops, 1199 + } 1200 + } 1201 + }; 1202 + 1203 + static struct clk_branch gcc_prng_ahb_clk = { 1204 + .halt_reg = 0x13004, 1205 + .halt_check = BRANCH_HALT_VOTED, 1206 + .clkr = { 1207 + .enable_reg = 0x45004, 1208 + .enable_mask = BIT(8), 1209 + .hw.init = &(struct clk_init_data) { 1210 + .name = "gcc_prng_ahb_clk", 1211 + .parent_hws = (const struct clk_hw*[]) { 1212 + &pcnoc_bfdcd_clk_src.clkr.hw, 1213 + }, 1214 + .num_parents = 1, 1215 + .ops = &clk_branch2_ops, 1216 + } 1217 + } 1218 + }; 1219 + 1220 + static struct clk_branch gcc_smmu_cfg_clk = { 1221 + .halt_reg = 0x12038, 1222 + .halt_check = BRANCH_HALT_VOTED, 1223 + .clkr = { 1224 + .enable_reg = 0x4500c, 1225 + .enable_mask = BIT(12), 1226 + .hw.init = &(struct clk_init_data) { 1227 + .name = "gcc_smmu_cfg_clk", 1228 + .parent_hws = (const struct clk_hw*[]) { 1229 + &pcnoc_bfdcd_clk_src.clkr.hw, 1230 + }, 1231 + .num_parents = 1, 1232 + .ops = &clk_branch2_ops, 1233 + } 1234 + } 1235 + }; 1236 + 1237 + static struct clk_branch gcc_venus_tbu_clk = { 1238 + .halt_reg = 0x12014, 1239 + .halt_check = BRANCH_HALT_VOTED, 1240 + .clkr = { 1241 + .enable_reg = 0x4500c, 1242 + .enable_mask = BIT(5), 1243 + .hw.init = &(struct clk_init_data) { 1244 + .name = "gcc_venus_tbu_clk", 1245 + .parent_hws = (const struct clk_hw*[]) { 1246 + &system_noc_bfdcd_clk_src.clkr.hw, 1247 + }, 1248 + .num_parents = 1, 1249 + .ops = &clk_branch2_ops, 1250 + } 1251 + } 1252 + }; 1253 + 1254 + static struct clk_branch gcc_vfe_tbu_clk = { 1255 + .halt_reg = 0x1203c, 1256 + .halt_check = BRANCH_HALT_VOTED, 1257 + .clkr = { 1258 + .enable_reg = 0x4500c, 1259 + .enable_mask = BIT(9), 1260 + .hw.init = &(struct clk_init_data) { 1261 + .name = "gcc_vfe_tbu_clk", 1262 + .parent_hws = (const struct clk_hw*[]) { 1263 + &system_noc_bfdcd_clk_src.clkr.hw, 1264 + }, 1265 + .num_parents = 1, 1266 + .ops = &clk_branch2_ops, 1267 + } 1268 + } 1269 + }; 1270 + 1271 + static struct clk_branch gcc_bimc_gfx_clk = { 1272 + .halt_reg = 0x31024, 1273 + .halt_check = BRANCH_HALT, 1274 + .clkr = { 1275 + .enable_reg = 0x31024, 1276 + .enable_mask = BIT(0), 1277 + .hw.init = &(struct clk_init_data) { 1278 + .name = "gcc_bimc_gfx_clk", 1279 + .parent_hws = (const struct clk_hw*[]) { 1280 + &bimc_gpu_clk_src.clkr.hw, 1281 + }, 1282 + .num_parents = 1, 1283 + .ops = &clk_branch2_ops, 1284 + } 1285 + } 1286 + }; 1287 + 1288 + static struct clk_branch gcc_bimc_gpu_clk = { 1289 + .halt_reg = 0x31040, 1290 + .halt_check = BRANCH_HALT, 1291 + .clkr = { 1292 + .enable_reg = 0x31040, 1293 + .enable_mask = BIT(0), 1294 + .hw.init = &(struct clk_init_data) { 1295 + .name = "gcc_bimc_gpu_clk", 1296 + .parent_hws = (const struct clk_hw*[]) { 1297 + &bimc_gpu_clk_src.clkr.hw, 1298 + }, 1299 + .num_parents = 1, 1300 + .ops = &clk_branch2_ops, 1301 + } 1302 + } 1303 + }; 1304 + 1305 + static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = { 1306 + .halt_reg = 0x02008, 1307 + .halt_check = BRANCH_HALT, 1308 + .clkr = { 1309 + .enable_reg = 0x02008, 1310 + .enable_mask = BIT(0), 1311 + .hw.init = &(struct clk_init_data) { 1312 + .name = "gcc_blsp1_qup1_i2c_apps_clk", 1313 + .parent_hws = (const struct clk_hw*[]) { 1314 + &blsp1_qup1_i2c_apps_clk_src.clkr.hw, 1315 + }, 1316 + .num_parents = 1, 1317 + .ops = &clk_branch2_ops, 1318 + .flags = CLK_SET_RATE_PARENT, 1319 + } 1320 + } 1321 + }; 1322 + 1323 + static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = { 1324 + .halt_reg = 0x03010, 1325 + .halt_check = BRANCH_HALT, 1326 + .clkr = { 1327 + .enable_reg = 0x03010, 1328 + .enable_mask = BIT(0), 1329 + .hw.init = &(struct clk_init_data) { 1330 + .name = "gcc_blsp1_qup2_i2c_apps_clk", 1331 + .parent_hws = (const struct clk_hw*[]) { 1332 + &blsp1_qup2_i2c_apps_clk_src.clkr.hw, 1333 + }, 1334 + .num_parents = 1, 1335 + .ops = &clk_branch2_ops, 1336 + .flags = CLK_SET_RATE_PARENT, 1337 + } 1338 + } 1339 + }; 1340 + 1341 + static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = { 1342 + .halt_reg = 0x04020, 1343 + .halt_check = BRANCH_HALT, 1344 + .clkr = { 1345 + .enable_reg = 0x04020, 1346 + .enable_mask = BIT(0), 1347 + .hw.init = &(struct clk_init_data) { 1348 + .name = "gcc_blsp1_qup3_i2c_apps_clk", 1349 + .parent_hws = (const struct clk_hw*[]) { 1350 + &blsp1_qup3_i2c_apps_clk_src.clkr.hw, 1351 + }, 1352 + .num_parents = 1, 1353 + .ops = &clk_branch2_ops, 1354 + .flags = CLK_SET_RATE_PARENT, 1355 + } 1356 + } 1357 + }; 1358 + 1359 + static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = { 1360 + .halt_reg = 0x05020, 1361 + .halt_check = BRANCH_HALT, 1362 + .clkr = { 1363 + .enable_reg = 0x05020, 1364 + .enable_mask = BIT(0), 1365 + .hw.init = &(struct clk_init_data) { 1366 + .name = "gcc_blsp1_qup4_i2c_apps_clk", 1367 + .parent_hws = (const struct clk_hw*[]) { 1368 + &blsp1_qup4_i2c_apps_clk_src.clkr.hw, 1369 + }, 1370 + .num_parents = 1, 1371 + .ops = &clk_branch2_ops, 1372 + .flags = CLK_SET_RATE_PARENT, 1373 + } 1374 + } 1375 + }; 1376 + 1377 + static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = { 1378 + .halt_reg = 0x06020, 1379 + .halt_check = BRANCH_HALT, 1380 + .clkr = { 1381 + .enable_reg = 0x06020, 1382 + .enable_mask = BIT(0), 1383 + .hw.init = &(struct clk_init_data) { 1384 + .name = "gcc_blsp1_qup5_i2c_apps_clk", 1385 + .parent_hws = (const struct clk_hw*[]) { 1386 + &blsp1_qup5_i2c_apps_clk_src.clkr.hw, 1387 + }, 1388 + .num_parents = 1, 1389 + .ops = &clk_branch2_ops, 1390 + .flags = CLK_SET_RATE_PARENT, 1391 + } 1392 + } 1393 + }; 1394 + 1395 + static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = { 1396 + .halt_reg = 0x07020, 1397 + .halt_check = BRANCH_HALT, 1398 + .clkr = { 1399 + .enable_reg = 0x07020, 1400 + .enable_mask = BIT(0), 1401 + .hw.init = &(struct clk_init_data) { 1402 + .name = "gcc_blsp1_qup6_i2c_apps_clk", 1403 + .parent_hws = (const struct clk_hw*[]) { 1404 + &blsp1_qup6_i2c_apps_clk_src.clkr.hw, 1405 + }, 1406 + .num_parents = 1, 1407 + .ops = &clk_branch2_ops, 1408 + .flags = CLK_SET_RATE_PARENT, 1409 + } 1410 + } 1411 + }; 1412 + 1413 + static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = { 1414 + .halt_reg = 0x02004, 1415 + .halt_check = BRANCH_HALT, 1416 + .clkr = { 1417 + .enable_reg = 0x02004, 1418 + .enable_mask = BIT(0), 1419 + .hw.init = &(struct clk_init_data) { 1420 + .name = "gcc_blsp1_qup1_spi_apps_clk", 1421 + .parent_hws = (const struct clk_hw*[]) { 1422 + &blsp1_qup1_spi_apps_clk_src.clkr.hw, 1423 + }, 1424 + .num_parents = 1, 1425 + .ops = &clk_branch2_ops, 1426 + .flags = CLK_SET_RATE_PARENT, 1427 + } 1428 + } 1429 + }; 1430 + 1431 + static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = { 1432 + .halt_reg = 0x0300c, 1433 + .halt_check = BRANCH_HALT, 1434 + .clkr = { 1435 + .enable_reg = 0x0300c, 1436 + .enable_mask = BIT(0), 1437 + .hw.init = &(struct clk_init_data) { 1438 + .name = "gcc_blsp1_qup2_spi_apps_clk", 1439 + .parent_hws = (const struct clk_hw*[]) { 1440 + &blsp1_qup2_spi_apps_clk_src.clkr.hw, 1441 + }, 1442 + .num_parents = 1, 1443 + .ops = &clk_branch2_ops, 1444 + .flags = CLK_SET_RATE_PARENT, 1445 + } 1446 + } 1447 + }; 1448 + 1449 + static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = { 1450 + .halt_reg = 0x0401c, 1451 + .halt_check = BRANCH_HALT, 1452 + .clkr = { 1453 + .enable_reg = 0x0401c, 1454 + .enable_mask = BIT(0), 1455 + .hw.init = &(struct clk_init_data) { 1456 + .name = "gcc_blsp1_qup3_spi_apps_clk", 1457 + .parent_hws = (const struct clk_hw*[]) { 1458 + &blsp1_qup3_spi_apps_clk_src.clkr.hw, 1459 + }, 1460 + .num_parents = 1, 1461 + .ops = &clk_branch2_ops, 1462 + .flags = CLK_SET_RATE_PARENT, 1463 + } 1464 + } 1465 + }; 1466 + 1467 + static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = { 1468 + .halt_reg = 0x0501c, 1469 + .halt_check = BRANCH_HALT, 1470 + .clkr = { 1471 + .enable_reg = 0x0501c, 1472 + .enable_mask = BIT(0), 1473 + .hw.init = &(struct clk_init_data) { 1474 + .name = "gcc_blsp1_qup4_spi_apps_clk", 1475 + .parent_hws = (const struct clk_hw*[]) { 1476 + &blsp1_qup4_spi_apps_clk_src.clkr.hw, 1477 + }, 1478 + .num_parents = 1, 1479 + .ops = &clk_branch2_ops, 1480 + .flags = CLK_SET_RATE_PARENT, 1481 + } 1482 + } 1483 + }; 1484 + 1485 + static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = { 1486 + .halt_reg = 0x0601c, 1487 + .halt_check = BRANCH_HALT, 1488 + .clkr = { 1489 + .enable_reg = 0x0601c, 1490 + .enable_mask = BIT(0), 1491 + .hw.init = &(struct clk_init_data) { 1492 + .name = "gcc_blsp1_qup5_spi_apps_clk", 1493 + .parent_hws = (const struct clk_hw*[]) { 1494 + &blsp1_qup5_spi_apps_clk_src.clkr.hw, 1495 + }, 1496 + .num_parents = 1, 1497 + .ops = &clk_branch2_ops, 1498 + .flags = CLK_SET_RATE_PARENT, 1499 + } 1500 + } 1501 + }; 1502 + 1503 + static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = { 1504 + .halt_reg = 0x0701c, 1505 + .halt_check = BRANCH_HALT, 1506 + .clkr = { 1507 + .enable_reg = 0x0701c, 1508 + .enable_mask = BIT(0), 1509 + .hw.init = &(struct clk_init_data) { 1510 + .name = "gcc_blsp1_qup6_spi_apps_clk", 1511 + .parent_hws = (const struct clk_hw*[]) { 1512 + &blsp1_qup6_spi_apps_clk_src.clkr.hw, 1513 + }, 1514 + .num_parents = 1, 1515 + .ops = &clk_branch2_ops, 1516 + .flags = CLK_SET_RATE_PARENT, 1517 + } 1518 + } 1519 + }; 1520 + 1521 + static struct clk_branch gcc_blsp1_uart1_apps_clk = { 1522 + .halt_reg = 0x0203c, 1523 + .halt_check = BRANCH_HALT, 1524 + .clkr = { 1525 + .enable_reg = 0x0203c, 1526 + .enable_mask = BIT(0), 1527 + .hw.init = &(struct clk_init_data) { 1528 + .name = "gcc_blsp1_uart1_apps_clk", 1529 + .parent_hws = (const struct clk_hw*[]) { 1530 + &blsp1_uart1_apps_clk_src.clkr.hw, 1531 + }, 1532 + .num_parents = 1, 1533 + .ops = &clk_branch2_ops, 1534 + .flags = CLK_SET_RATE_PARENT, 1535 + } 1536 + } 1537 + }; 1538 + 1539 + static struct clk_branch gcc_blsp1_uart2_apps_clk = { 1540 + .halt_reg = 0x0302c, 1541 + .halt_check = BRANCH_HALT, 1542 + .clkr = { 1543 + .enable_reg = 0x0302c, 1544 + .enable_mask = BIT(0), 1545 + .hw.init = &(struct clk_init_data) { 1546 + .name = "gcc_blsp1_uart2_apps_clk", 1547 + .parent_hws = (const struct clk_hw*[]) { 1548 + &blsp1_uart2_apps_clk_src.clkr.hw, 1549 + }, 1550 + .num_parents = 1, 1551 + .ops = &clk_branch2_ops, 1552 + .flags = CLK_SET_RATE_PARENT, 1553 + } 1554 + } 1555 + }; 1556 + 1557 + static struct clk_branch gcc_camss_ahb_clk = { 1558 + .halt_reg = 0x5a014, 1559 + .halt_check = BRANCH_HALT, 1560 + .clkr = { 1561 + .enable_reg = 0x5a014, 1562 + .enable_mask = BIT(0), 1563 + .hw.init = &(struct clk_init_data) { 1564 + .name = "gcc_camss_ahb_clk", 1565 + .parent_hws = (const struct clk_hw*[]) { 1566 + &pcnoc_bfdcd_clk_src.clkr.hw, 1567 + }, 1568 + .num_parents = 1, 1569 + .ops = &clk_branch2_ops, 1570 + } 1571 + } 1572 + }; 1573 + 1574 + static struct clk_branch gcc_camss_csi0_clk = { 1575 + .halt_reg = 0x4e03c, 1576 + .halt_check = BRANCH_HALT, 1577 + .clkr = { 1578 + .enable_reg = 0x4e03c, 1579 + .enable_mask = BIT(0), 1580 + .hw.init = &(struct clk_init_data) { 1581 + .name = "gcc_camss_csi0_clk", 1582 + .parent_hws = (const struct clk_hw*[]) { 1583 + &csi0_clk_src.clkr.hw, 1584 + }, 1585 + .num_parents = 1, 1586 + .ops = &clk_branch2_ops, 1587 + .flags = CLK_SET_RATE_PARENT, 1588 + } 1589 + } 1590 + }; 1591 + 1592 + static struct clk_branch gcc_camss_csi0_ahb_clk = { 1593 + .halt_reg = 0x4e040, 1594 + .halt_check = BRANCH_HALT, 1595 + .clkr = { 1596 + .enable_reg = 0x4e040, 1597 + .enable_mask = BIT(0), 1598 + .hw.init = &(struct clk_init_data) { 1599 + .name = "gcc_camss_csi0_ahb_clk", 1600 + .parent_hws = (const struct clk_hw*[]) { 1601 + &camss_top_ahb_clk_src.clkr.hw, 1602 + }, 1603 + .num_parents = 1, 1604 + .ops = &clk_branch2_ops, 1605 + .flags = CLK_SET_RATE_PARENT, 1606 + } 1607 + } 1608 + }; 1609 + 1610 + static struct clk_branch gcc_camss_csi0phy_clk = { 1611 + .halt_reg = 0x4e048, 1612 + .halt_check = BRANCH_HALT, 1613 + .clkr = { 1614 + .enable_reg = 0x4e048, 1615 + .enable_mask = BIT(0), 1616 + .hw.init = &(struct clk_init_data) { 1617 + .name = "gcc_camss_csi0phy_clk", 1618 + .parent_hws = (const struct clk_hw*[]) { 1619 + &csi0_clk_src.clkr.hw, 1620 + }, 1621 + .num_parents = 1, 1622 + .ops = &clk_branch2_ops, 1623 + .flags = CLK_SET_RATE_PARENT, 1624 + } 1625 + } 1626 + }; 1627 + 1628 + static struct clk_branch gcc_camss_csi0phytimer_clk = { 1629 + .halt_reg = 0x4e01c, 1630 + .halt_check = BRANCH_HALT, 1631 + .clkr = { 1632 + .enable_reg = 0x4e01c, 1633 + .enable_mask = BIT(0), 1634 + .hw.init = &(struct clk_init_data) { 1635 + .name = "gcc_camss_csi0phytimer_clk", 1636 + .parent_hws = (const struct clk_hw*[]) { 1637 + &csi0phytimer_clk_src.clkr.hw, 1638 + }, 1639 + .num_parents = 1, 1640 + .ops = &clk_branch2_ops, 1641 + .flags = CLK_SET_RATE_PARENT, 1642 + } 1643 + } 1644 + }; 1645 + 1646 + static struct clk_branch gcc_camss_csi0pix_clk = { 1647 + .halt_reg = 0x4e058, 1648 + .halt_check = BRANCH_HALT, 1649 + .clkr = { 1650 + .enable_reg = 0x4e058, 1651 + .enable_mask = BIT(0), 1652 + .hw.init = &(struct clk_init_data) { 1653 + .name = "gcc_camss_csi0pix_clk", 1654 + .parent_hws = (const struct clk_hw*[]) { 1655 + &csi0_clk_src.clkr.hw, 1656 + }, 1657 + .num_parents = 1, 1658 + .ops = &clk_branch2_ops, 1659 + .flags = CLK_SET_RATE_PARENT, 1660 + } 1661 + } 1662 + }; 1663 + 1664 + static struct clk_branch gcc_camss_csi0rdi_clk = { 1665 + .halt_reg = 0x4e050, 1666 + .halt_check = BRANCH_HALT, 1667 + .clkr = { 1668 + .enable_reg = 0x4e050, 1669 + .enable_mask = BIT(0), 1670 + .hw.init = &(struct clk_init_data) { 1671 + .name = "gcc_camss_csi0rdi_clk", 1672 + .parent_hws = (const struct clk_hw*[]) { 1673 + &csi0_clk_src.clkr.hw, 1674 + }, 1675 + .num_parents = 1, 1676 + .ops = &clk_branch2_ops, 1677 + .flags = CLK_SET_RATE_PARENT, 1678 + } 1679 + } 1680 + }; 1681 + 1682 + static struct clk_branch gcc_camss_csi1_clk = { 1683 + .halt_reg = 0x4f03c, 1684 + .halt_check = BRANCH_HALT, 1685 + .clkr = { 1686 + .enable_reg = 0x4f03c, 1687 + .enable_mask = BIT(0), 1688 + .hw.init = &(struct clk_init_data) { 1689 + .name = "gcc_camss_csi1_clk", 1690 + .parent_hws = (const struct clk_hw*[]) { 1691 + &csi1_clk_src.clkr.hw, 1692 + }, 1693 + .num_parents = 1, 1694 + .ops = &clk_branch2_ops, 1695 + .flags = CLK_SET_RATE_PARENT, 1696 + } 1697 + } 1698 + }; 1699 + 1700 + static struct clk_branch gcc_camss_csi1_ahb_clk = { 1701 + .halt_reg = 0x4f040, 1702 + .halt_check = BRANCH_HALT, 1703 + .clkr = { 1704 + .enable_reg = 0x4f040, 1705 + .enable_mask = BIT(0), 1706 + .hw.init = &(struct clk_init_data) { 1707 + .name = "gcc_camss_csi1_ahb_clk", 1708 + .parent_hws = (const struct clk_hw*[]) { 1709 + &camss_top_ahb_clk_src.clkr.hw, 1710 + }, 1711 + .num_parents = 1, 1712 + .ops = &clk_branch2_ops, 1713 + .flags = CLK_SET_RATE_PARENT, 1714 + } 1715 + } 1716 + }; 1717 + 1718 + static struct clk_branch gcc_camss_csi1phy_clk = { 1719 + .halt_reg = 0x4f048, 1720 + .halt_check = BRANCH_HALT, 1721 + .clkr = { 1722 + .enable_reg = 0x4f048, 1723 + .enable_mask = BIT(0), 1724 + .hw.init = &(struct clk_init_data) { 1725 + .name = "gcc_camss_csi1phy_clk", 1726 + .parent_hws = (const struct clk_hw*[]) { 1727 + &csi1_clk_src.clkr.hw, 1728 + }, 1729 + .num_parents = 1, 1730 + .ops = &clk_branch2_ops, 1731 + .flags = CLK_SET_RATE_PARENT, 1732 + } 1733 + } 1734 + }; 1735 + 1736 + static struct clk_branch gcc_camss_csi1pix_clk = { 1737 + .halt_reg = 0x4f058, 1738 + .halt_check = BRANCH_HALT, 1739 + .clkr = { 1740 + .enable_reg = 0x4f058, 1741 + .enable_mask = BIT(0), 1742 + .hw.init = &(struct clk_init_data) { 1743 + .name = "gcc_camss_csi1pix_clk", 1744 + .parent_hws = (const struct clk_hw*[]) { 1745 + &csi1_clk_src.clkr.hw, 1746 + }, 1747 + .num_parents = 1, 1748 + .ops = &clk_branch2_ops, 1749 + .flags = CLK_SET_RATE_PARENT, 1750 + } 1751 + } 1752 + }; 1753 + 1754 + static struct clk_branch gcc_camss_csi1rdi_clk = { 1755 + .halt_reg = 0x4f050, 1756 + .halt_check = BRANCH_HALT, 1757 + .clkr = { 1758 + .enable_reg = 0x4f050, 1759 + .enable_mask = BIT(0), 1760 + .hw.init = &(struct clk_init_data) { 1761 + .name = "gcc_camss_csi1rdi_clk", 1762 + .parent_hws = (const struct clk_hw*[]) { 1763 + &csi1_clk_src.clkr.hw, 1764 + }, 1765 + .num_parents = 1, 1766 + .ops = &clk_branch2_ops, 1767 + .flags = CLK_SET_RATE_PARENT, 1768 + } 1769 + } 1770 + }; 1771 + 1772 + static struct clk_branch gcc_camss_csi_vfe0_clk = { 1773 + .halt_reg = 0x58050, 1774 + .halt_check = BRANCH_HALT, 1775 + .clkr = { 1776 + .enable_reg = 0x58050, 1777 + .enable_mask = BIT(0), 1778 + .hw.init = &(struct clk_init_data) { 1779 + .name = "gcc_camss_csi_vfe0_clk", 1780 + .parent_hws = (const struct clk_hw*[]) { 1781 + &vfe0_clk_src.clkr.hw, 1782 + }, 1783 + .num_parents = 1, 1784 + .ops = &clk_branch2_ops, 1785 + .flags = CLK_SET_RATE_PARENT, 1786 + } 1787 + } 1788 + }; 1789 + 1790 + static struct clk_branch gcc_camss_gp0_clk = { 1791 + .halt_reg = 0x54018, 1792 + .halt_check = BRANCH_HALT, 1793 + .clkr = { 1794 + .enable_reg = 0x54018, 1795 + .enable_mask = BIT(0), 1796 + .hw.init = &(struct clk_init_data) { 1797 + .name = "gcc_camss_gp0_clk", 1798 + .parent_hws = (const struct clk_hw*[]) { 1799 + &camss_gp0_clk_src.clkr.hw, 1800 + }, 1801 + .num_parents = 1, 1802 + .ops = &clk_branch2_ops, 1803 + .flags = CLK_SET_RATE_PARENT, 1804 + } 1805 + } 1806 + }; 1807 + 1808 + static struct clk_branch gcc_camss_gp1_clk = { 1809 + .halt_reg = 0x55018, 1810 + .halt_check = BRANCH_HALT, 1811 + .clkr = { 1812 + .enable_reg = 0x55018, 1813 + .enable_mask = BIT(0), 1814 + .hw.init = &(struct clk_init_data) { 1815 + .name = "gcc_camss_gp1_clk", 1816 + .parent_hws = (const struct clk_hw*[]) { 1817 + &camss_gp1_clk_src.clkr.hw, 1818 + }, 1819 + .num_parents = 1, 1820 + .ops = &clk_branch2_ops, 1821 + .flags = CLK_SET_RATE_PARENT, 1822 + } 1823 + } 1824 + }; 1825 + 1826 + static struct clk_branch gcc_camss_ispif_ahb_clk = { 1827 + .halt_reg = 0x50004, 1828 + .halt_check = BRANCH_HALT, 1829 + .clkr = { 1830 + .enable_reg = 0x50004, 1831 + .enable_mask = BIT(0), 1832 + .hw.init = &(struct clk_init_data) { 1833 + .name = "gcc_camss_ispif_ahb_clk", 1834 + .parent_hws = (const struct clk_hw*[]) { 1835 + &camss_top_ahb_clk_src.clkr.hw, 1836 + }, 1837 + .num_parents = 1, 1838 + .ops = &clk_branch2_ops, 1839 + .flags = CLK_SET_RATE_PARENT, 1840 + } 1841 + } 1842 + }; 1843 + 1844 + static struct clk_branch gcc_camss_mclk0_clk = { 1845 + .halt_reg = 0x52018, 1846 + .halt_check = BRANCH_HALT, 1847 + .clkr = { 1848 + .enable_reg = 0x52018, 1849 + .enable_mask = BIT(0), 1850 + .hw.init = &(struct clk_init_data) { 1851 + .name = "gcc_camss_mclk0_clk", 1852 + .parent_hws = (const struct clk_hw*[]) { 1853 + &mclk0_clk_src.clkr.hw, 1854 + }, 1855 + .num_parents = 1, 1856 + .ops = &clk_branch2_ops, 1857 + .flags = CLK_SET_RATE_PARENT, 1858 + } 1859 + } 1860 + }; 1861 + 1862 + static struct clk_branch gcc_camss_mclk1_clk = { 1863 + .halt_reg = 0x53018, 1864 + .halt_check = BRANCH_HALT, 1865 + .clkr = { 1866 + .enable_reg = 0x53018, 1867 + .enable_mask = BIT(0), 1868 + .hw.init = &(struct clk_init_data) { 1869 + .name = "gcc_camss_mclk1_clk", 1870 + .parent_hws = (const struct clk_hw*[]) { 1871 + &mclk1_clk_src.clkr.hw, 1872 + }, 1873 + .num_parents = 1, 1874 + .ops = &clk_branch2_ops, 1875 + .flags = CLK_SET_RATE_PARENT, 1876 + } 1877 + } 1878 + }; 1879 + 1880 + static struct clk_branch gcc_camss_top_ahb_clk = { 1881 + .halt_reg = 0x56004, 1882 + .halt_check = BRANCH_HALT, 1883 + .clkr = { 1884 + .enable_reg = 0x56004, 1885 + .enable_mask = BIT(0), 1886 + .hw.init = &(struct clk_init_data) { 1887 + .name = "gcc_camss_top_ahb_clk", 1888 + .parent_hws = (const struct clk_hw*[]) { 1889 + &camss_top_ahb_clk_src.clkr.hw, 1890 + }, 1891 + .num_parents = 1, 1892 + .ops = &clk_branch2_ops, 1893 + .flags = CLK_SET_RATE_PARENT, 1894 + } 1895 + } 1896 + }; 1897 + 1898 + static struct clk_branch gcc_camss_vfe0_clk = { 1899 + .halt_reg = 0x58038, 1900 + .halt_check = BRANCH_HALT, 1901 + .clkr = { 1902 + .enable_reg = 0x58038, 1903 + .enable_mask = BIT(0), 1904 + .hw.init = &(struct clk_init_data) { 1905 + .name = "gcc_camss_vfe0_clk", 1906 + .parent_hws = (const struct clk_hw*[]) { 1907 + &vfe0_clk_src.clkr.hw, 1908 + }, 1909 + .num_parents = 1, 1910 + .ops = &clk_branch2_ops, 1911 + .flags = CLK_SET_RATE_PARENT, 1912 + } 1913 + } 1914 + }; 1915 + 1916 + static struct clk_branch gcc_camss_vfe_ahb_clk = { 1917 + .halt_reg = 0x58044, 1918 + .halt_check = BRANCH_HALT, 1919 + .clkr = { 1920 + .enable_reg = 0x58044, 1921 + .enable_mask = BIT(0), 1922 + .hw.init = &(struct clk_init_data) { 1923 + .name = "gcc_camss_vfe_ahb_clk", 1924 + .parent_hws = (const struct clk_hw*[]) { 1925 + &camss_top_ahb_clk_src.clkr.hw, 1926 + }, 1927 + .num_parents = 1, 1928 + .ops = &clk_branch2_ops, 1929 + .flags = CLK_SET_RATE_PARENT, 1930 + } 1931 + } 1932 + }; 1933 + 1934 + static struct clk_branch gcc_camss_vfe_axi_clk = { 1935 + .halt_reg = 0x58048, 1936 + .halt_check = BRANCH_HALT, 1937 + .clkr = { 1938 + .enable_reg = 0x58048, 1939 + .enable_mask = BIT(0), 1940 + .hw.init = &(struct clk_init_data) { 1941 + .name = "gcc_camss_vfe_axi_clk", 1942 + .parent_hws = (const struct clk_hw*[]) { 1943 + &system_noc_bfdcd_clk_src.clkr.hw, 1944 + }, 1945 + .num_parents = 1, 1946 + .ops = &clk_branch2_ops, 1947 + } 1948 + } 1949 + }; 1950 + 1951 + static struct clk_branch gcc_gp1_clk = { 1952 + .halt_reg = 0x08000, 1953 + .halt_check = BRANCH_HALT, 1954 + .clkr = { 1955 + .enable_reg = 0x08000, 1956 + .enable_mask = BIT(0), 1957 + .hw.init = &(struct clk_init_data) { 1958 + .name = "gcc_gp1_clk", 1959 + .parent_hws = (const struct clk_hw*[]) { 1960 + &gp1_clk_src.clkr.hw, 1961 + }, 1962 + .num_parents = 1, 1963 + .ops = &clk_branch2_ops, 1964 + .flags = CLK_SET_RATE_PARENT, 1965 + } 1966 + } 1967 + }; 1968 + 1969 + static struct clk_branch gcc_gp2_clk = { 1970 + .halt_reg = 0x09000, 1971 + .halt_check = BRANCH_HALT, 1972 + .clkr = { 1973 + .enable_reg = 0x09000, 1974 + .enable_mask = BIT(0), 1975 + .hw.init = &(struct clk_init_data) { 1976 + .name = "gcc_gp2_clk", 1977 + .parent_hws = (const struct clk_hw*[]) { 1978 + &gp2_clk_src.clkr.hw, 1979 + }, 1980 + .num_parents = 1, 1981 + .ops = &clk_branch2_ops, 1982 + .flags = CLK_SET_RATE_PARENT, 1983 + } 1984 + } 1985 + }; 1986 + 1987 + static struct clk_branch gcc_gp3_clk = { 1988 + .halt_reg = 0x0a000, 1989 + .halt_check = BRANCH_HALT, 1990 + .clkr = { 1991 + .enable_reg = 0x0a000, 1992 + .enable_mask = BIT(0), 1993 + .hw.init = &(struct clk_init_data) { 1994 + .name = "gcc_gp3_clk", 1995 + .parent_hws = (const struct clk_hw*[]) { 1996 + &gp3_clk_src.clkr.hw, 1997 + }, 1998 + .num_parents = 1, 1999 + .ops = &clk_branch2_ops, 2000 + .flags = CLK_SET_RATE_PARENT, 2001 + } 2002 + } 2003 + }; 2004 + 2005 + static struct clk_branch gcc_mdss_ahb_clk = { 2006 + .halt_reg = 0x4d07c, 2007 + .halt_check = BRANCH_HALT, 2008 + .clkr = { 2009 + .enable_reg = 0x4d07c, 2010 + .enable_mask = BIT(0), 2011 + .hw.init = &(struct clk_init_data) { 2012 + .name = "gcc_mdss_ahb_clk", 2013 + .parent_hws = (const struct clk_hw*[]) { 2014 + &pcnoc_bfdcd_clk_src.clkr.hw, 2015 + }, 2016 + .num_parents = 1, 2017 + .ops = &clk_branch2_ops, 2018 + } 2019 + } 2020 + }; 2021 + 2022 + static struct clk_branch gcc_mdss_axi_clk = { 2023 + .halt_reg = 0x4d080, 2024 + .halt_check = BRANCH_HALT, 2025 + .clkr = { 2026 + .enable_reg = 0x4d080, 2027 + .enable_mask = BIT(0), 2028 + .hw.init = &(struct clk_init_data) { 2029 + .name = "gcc_mdss_axi_clk", 2030 + .parent_hws = (const struct clk_hw*[]) { 2031 + &system_noc_bfdcd_clk_src.clkr.hw, 2032 + }, 2033 + .num_parents = 1, 2034 + .ops = &clk_branch2_ops, 2035 + } 2036 + } 2037 + }; 2038 + 2039 + static struct clk_branch gcc_mdss_byte0_clk = { 2040 + .halt_reg = 0x4d094, 2041 + .halt_check = BRANCH_HALT, 2042 + .clkr = { 2043 + .enable_reg = 0x4d094, 2044 + .enable_mask = BIT(0), 2045 + .hw.init = &(struct clk_init_data) { 2046 + .name = "gcc_mdss_byte0_clk", 2047 + .parent_hws = (const struct clk_hw*[]) { 2048 + &byte0_clk_src.clkr.hw, 2049 + }, 2050 + .num_parents = 1, 2051 + .ops = &clk_branch2_ops, 2052 + .flags = CLK_SET_RATE_PARENT, 2053 + } 2054 + } 2055 + }; 2056 + 2057 + static struct clk_branch gcc_mdss_esc0_clk = { 2058 + .halt_reg = 0x4d098, 2059 + .halt_check = BRANCH_HALT, 2060 + .clkr = { 2061 + .enable_reg = 0x4d098, 2062 + .enable_mask = BIT(0), 2063 + .hw.init = &(struct clk_init_data) { 2064 + .name = "gcc_mdss_esc0_clk", 2065 + .parent_hws = (const struct clk_hw*[]) { 2066 + &esc0_clk_src.clkr.hw, 2067 + }, 2068 + .num_parents = 1, 2069 + .ops = &clk_branch2_ops, 2070 + .flags = CLK_SET_RATE_PARENT, 2071 + } 2072 + } 2073 + }; 2074 + 2075 + static struct clk_branch gcc_mdss_mdp_clk = { 2076 + .halt_reg = 0x4d088, 2077 + .halt_check = BRANCH_HALT, 2078 + .clkr = { 2079 + .enable_reg = 0x4d088, 2080 + .enable_mask = BIT(0), 2081 + .hw.init = &(struct clk_init_data) { 2082 + .name = "gcc_mdss_mdp_clk", 2083 + .parent_hws = (const struct clk_hw*[]) { 2084 + &mdp_clk_src.clkr.hw, 2085 + }, 2086 + .num_parents = 1, 2087 + .ops = &clk_branch2_ops, 2088 + .flags = CLK_SET_RATE_PARENT, 2089 + } 2090 + } 2091 + }; 2092 + 2093 + static struct clk_branch gcc_mdss_pclk0_clk = { 2094 + .halt_reg = 0x4d084, 2095 + .halt_check = BRANCH_HALT, 2096 + .clkr = { 2097 + .enable_reg = 0x4d084, 2098 + .enable_mask = BIT(0), 2099 + .hw.init = &(struct clk_init_data) { 2100 + .name = "gcc_mdss_pclk0_clk", 2101 + .parent_hws = (const struct clk_hw*[]) { 2102 + &pclk0_clk_src.clkr.hw, 2103 + }, 2104 + .num_parents = 1, 2105 + .ops = &clk_branch2_ops, 2106 + .flags = CLK_SET_RATE_PARENT, 2107 + } 2108 + } 2109 + }; 2110 + 2111 + static struct clk_branch gcc_mdss_vsync_clk = { 2112 + .halt_reg = 0x4d090, 2113 + .halt_check = BRANCH_HALT, 2114 + .clkr = { 2115 + .enable_reg = 0x4d090, 2116 + .enable_mask = BIT(0), 2117 + .hw.init = &(struct clk_init_data) { 2118 + .name = "gcc_mdss_vsync_clk", 2119 + .parent_hws = (const struct clk_hw*[]) { 2120 + &vsync_clk_src.clkr.hw, 2121 + }, 2122 + .num_parents = 1, 2123 + .ops = &clk_branch2_ops, 2124 + .flags = CLK_SET_RATE_PARENT, 2125 + } 2126 + } 2127 + }; 2128 + 2129 + static struct clk_branch gcc_mss_cfg_ahb_clk = { 2130 + .halt_reg = 0x49000, 2131 + .halt_check = BRANCH_HALT, 2132 + .clkr = { 2133 + .enable_reg = 0x49000, 2134 + .enable_mask = BIT(0), 2135 + .hw.init = &(struct clk_init_data) { 2136 + .name = "gcc_mss_cfg_ahb_clk", 2137 + .parent_hws = (const struct clk_hw*[]) { 2138 + &pcnoc_bfdcd_clk_src.clkr.hw, 2139 + }, 2140 + .num_parents = 1, 2141 + .ops = &clk_branch2_ops, 2142 + } 2143 + } 2144 + }; 2145 + 2146 + static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 2147 + .halt_reg = 0x49004, 2148 + .halt_check = BRANCH_HALT, 2149 + .clkr = { 2150 + .enable_reg = 0x49004, 2151 + .enable_mask = BIT(0), 2152 + .hw.init = &(struct clk_init_data) { 2153 + .name = "gcc_mss_q6_bimc_axi_clk", 2154 + .parent_hws = (const struct clk_hw*[]) { 2155 + &bimc_ddr_clk_src.clkr.hw, 2156 + }, 2157 + .num_parents = 1, 2158 + .ops = &clk_branch2_ops, 2159 + } 2160 + } 2161 + }; 2162 + 2163 + static struct clk_branch gcc_oxili_ahb_clk = { 2164 + .halt_reg = 0x59028, 2165 + .halt_check = BRANCH_HALT, 2166 + .clkr = { 2167 + .enable_reg = 0x59028, 2168 + .enable_mask = BIT(0), 2169 + .hw.init = &(struct clk_init_data) { 2170 + .name = "gcc_oxili_ahb_clk", 2171 + .parent_hws = (const struct clk_hw*[]) { 2172 + &pcnoc_bfdcd_clk_src.clkr.hw, 2173 + }, 2174 + .num_parents = 1, 2175 + .ops = &clk_branch2_ops, 2176 + } 2177 + } 2178 + }; 2179 + 2180 + static struct clk_branch gcc_oxili_gfx3d_clk = { 2181 + .halt_reg = 0x59020, 2182 + .halt_check = BRANCH_HALT, 2183 + .clkr = { 2184 + .enable_reg = 0x59020, 2185 + .enable_mask = BIT(0), 2186 + .hw.init = &(struct clk_init_data) { 2187 + .name = "gcc_oxili_gfx3d_clk", 2188 + .parent_hws = (const struct clk_hw*[]) { 2189 + &gfx3d_clk_src.clkr.hw, 2190 + }, 2191 + .num_parents = 1, 2192 + .ops = &clk_branch2_ops, 2193 + .flags = CLK_SET_RATE_PARENT, 2194 + } 2195 + } 2196 + }; 2197 + 2198 + static struct clk_branch gcc_pdm2_clk = { 2199 + .halt_reg = 0x4400c, 2200 + .halt_check = BRANCH_HALT, 2201 + .clkr = { 2202 + .enable_reg = 0x4400c, 2203 + .enable_mask = BIT(0), 2204 + .hw.init = &(struct clk_init_data) { 2205 + .name = "gcc_pdm2_clk", 2206 + .parent_hws = (const struct clk_hw*[]) { 2207 + &pdm2_clk_src.clkr.hw, 2208 + }, 2209 + .num_parents = 1, 2210 + .ops = &clk_branch2_ops, 2211 + .flags = CLK_SET_RATE_PARENT, 2212 + } 2213 + } 2214 + }; 2215 + 2216 + static struct clk_branch gcc_pdm_ahb_clk = { 2217 + .halt_reg = 0x44004, 2218 + .halt_check = BRANCH_HALT, 2219 + .clkr = { 2220 + .enable_reg = 0x44004, 2221 + .enable_mask = BIT(0), 2222 + .hw.init = &(struct clk_init_data) { 2223 + .name = "gcc_pdm_ahb_clk", 2224 + .parent_hws = (const struct clk_hw*[]) { 2225 + &pcnoc_bfdcd_clk_src.clkr.hw, 2226 + }, 2227 + .num_parents = 1, 2228 + .ops = &clk_branch2_ops, 2229 + } 2230 + } 2231 + }; 2232 + 2233 + static struct clk_branch gcc_sdcc1_ahb_clk = { 2234 + .halt_reg = 0x4201c, 2235 + .halt_check = BRANCH_HALT, 2236 + .clkr = { 2237 + .enable_reg = 0x4201c, 2238 + .enable_mask = BIT(0), 2239 + .hw.init = &(struct clk_init_data) { 2240 + .name = "gcc_sdcc1_ahb_clk", 2241 + .parent_hws = (const struct clk_hw*[]) { 2242 + &pcnoc_bfdcd_clk_src.clkr.hw, 2243 + }, 2244 + .num_parents = 1, 2245 + .ops = &clk_branch2_ops, 2246 + } 2247 + } 2248 + }; 2249 + 2250 + static struct clk_branch gcc_sdcc1_apps_clk = { 2251 + .halt_reg = 0x42018, 2252 + .halt_check = BRANCH_HALT, 2253 + .clkr = { 2254 + .enable_reg = 0x42018, 2255 + .enable_mask = BIT(0), 2256 + .hw.init = &(struct clk_init_data) { 2257 + .name = "gcc_sdcc1_apps_clk", 2258 + .parent_hws = (const struct clk_hw*[]) { 2259 + &sdcc1_apps_clk_src.clkr.hw, 2260 + }, 2261 + .num_parents = 1, 2262 + .ops = &clk_branch2_ops, 2263 + .flags = CLK_SET_RATE_PARENT, 2264 + } 2265 + } 2266 + }; 2267 + 2268 + static struct clk_branch gcc_sdcc2_ahb_clk = { 2269 + .halt_reg = 0x4301c, 2270 + .halt_check = BRANCH_HALT, 2271 + .clkr = { 2272 + .enable_reg = 0x4301c, 2273 + .enable_mask = BIT(0), 2274 + .hw.init = &(struct clk_init_data) { 2275 + .name = "gcc_sdcc2_ahb_clk", 2276 + .parent_hws = (const struct clk_hw*[]) { 2277 + &pcnoc_bfdcd_clk_src.clkr.hw, 2278 + }, 2279 + .num_parents = 1, 2280 + .ops = &clk_branch2_ops, 2281 + } 2282 + } 2283 + }; 2284 + 2285 + static struct clk_branch gcc_sdcc2_apps_clk = { 2286 + .halt_reg = 0x43018, 2287 + .halt_check = BRANCH_HALT, 2288 + .clkr = { 2289 + .enable_reg = 0x43018, 2290 + .enable_mask = BIT(0), 2291 + .hw.init = &(struct clk_init_data) { 2292 + .name = "gcc_sdcc2_apps_clk", 2293 + .parent_hws = (const struct clk_hw*[]) { 2294 + &sdcc2_apps_clk_src.clkr.hw, 2295 + }, 2296 + .num_parents = 1, 2297 + .ops = &clk_branch2_ops, 2298 + .flags = CLK_SET_RATE_PARENT, 2299 + } 2300 + } 2301 + }; 2302 + 2303 + static struct clk_branch gcc_usb2a_phy_sleep_clk = { 2304 + .halt_reg = 0x4102c, 2305 + .halt_check = BRANCH_HALT, 2306 + .clkr = { 2307 + .enable_reg = 0x4102c, 2308 + .enable_mask = BIT(0), 2309 + .hw.init = &(struct clk_init_data) { 2310 + .name = "gcc_usb2a_phy_sleep_clk", 2311 + .parent_data = gcc_sleep_clk_data, 2312 + .num_parents = ARRAY_SIZE(gcc_sleep_clk_data), 2313 + .ops = &clk_branch2_ops, 2314 + } 2315 + } 2316 + }; 2317 + 2318 + static struct clk_branch gcc_usb_hs_ahb_clk = { 2319 + .halt_reg = 0x41008, 2320 + .halt_check = BRANCH_HALT, 2321 + .clkr = { 2322 + .enable_reg = 0x41008, 2323 + .enable_mask = BIT(0), 2324 + .hw.init = &(struct clk_init_data) { 2325 + .name = "gcc_usb_hs_ahb_clk", 2326 + .parent_hws = (const struct clk_hw*[]) { 2327 + &pcnoc_bfdcd_clk_src.clkr.hw, 2328 + }, 2329 + .num_parents = 1, 2330 + .ops = &clk_branch2_ops, 2331 + } 2332 + } 2333 + }; 2334 + 2335 + static struct clk_branch gcc_usb_hs_phy_cfg_ahb_clk = { 2336 + .halt_reg = 0x41030, 2337 + .halt_check = BRANCH_HALT, 2338 + .clkr = { 2339 + .enable_reg = 0x41030, 2340 + .enable_mask = BIT(0), 2341 + .hw.init = &(struct clk_init_data) { 2342 + .name = "gcc_usb_hs_phy_cfg_ahb_clk", 2343 + .parent_hws = (const struct clk_hw*[]) { 2344 + &pcnoc_bfdcd_clk_src.clkr.hw, 2345 + }, 2346 + .num_parents = 1, 2347 + .ops = &clk_branch2_ops, 2348 + } 2349 + } 2350 + }; 2351 + 2352 + static struct clk_branch gcc_usb_hs_system_clk = { 2353 + .halt_reg = 0x41004, 2354 + .halt_check = BRANCH_HALT, 2355 + .clkr = { 2356 + .enable_reg = 0x41004, 2357 + .enable_mask = BIT(0), 2358 + .hw.init = &(struct clk_init_data) { 2359 + .name = "gcc_usb_hs_system_clk", 2360 + .parent_hws = (const struct clk_hw*[]) { 2361 + &usb_hs_system_clk_src.clkr.hw, 2362 + }, 2363 + .num_parents = 1, 2364 + .ops = &clk_branch2_ops, 2365 + .flags = CLK_SET_RATE_PARENT, 2366 + } 2367 + } 2368 + }; 2369 + 2370 + static struct clk_branch gcc_venus0_ahb_clk = { 2371 + .halt_reg = 0x4c020, 2372 + .halt_check = BRANCH_HALT, 2373 + .clkr = { 2374 + .enable_reg = 0x4c020, 2375 + .enable_mask = BIT(0), 2376 + .hw.init = &(struct clk_init_data) { 2377 + .name = "gcc_venus0_ahb_clk", 2378 + .parent_hws = (const struct clk_hw*[]) { 2379 + &pcnoc_bfdcd_clk_src.clkr.hw, 2380 + }, 2381 + .num_parents = 1, 2382 + .ops = &clk_branch2_ops, 2383 + } 2384 + } 2385 + }; 2386 + 2387 + static struct clk_branch gcc_venus0_axi_clk = { 2388 + .halt_reg = 0x4c024, 2389 + .halt_check = BRANCH_HALT, 2390 + .clkr = { 2391 + .enable_reg = 0x4c024, 2392 + .enable_mask = BIT(0), 2393 + .hw.init = &(struct clk_init_data) { 2394 + .name = "gcc_venus0_axi_clk", 2395 + .parent_hws = (const struct clk_hw*[]) { 2396 + &system_noc_bfdcd_clk_src.clkr.hw, 2397 + }, 2398 + .num_parents = 1, 2399 + .ops = &clk_branch2_ops, 2400 + } 2401 + } 2402 + }; 2403 + 2404 + static struct clk_branch gcc_venus0_core0_vcodec0_clk = { 2405 + .halt_reg = 0x4c02c, 2406 + .halt_check = BRANCH_HALT, 2407 + .clkr = { 2408 + .enable_reg = 0x4c02c, 2409 + .enable_mask = BIT(0), 2410 + .hw.init = &(struct clk_init_data) { 2411 + .name = "gcc_venus0_core0_vcodec0_clk", 2412 + .parent_hws = (const struct clk_hw*[]) { 2413 + &vcodec0_clk_src.clkr.hw, 2414 + }, 2415 + .num_parents = 1, 2416 + .ops = &clk_branch2_ops, 2417 + .flags = CLK_SET_RATE_PARENT, 2418 + } 2419 + } 2420 + }; 2421 + 2422 + static struct clk_branch gcc_venus0_vcodec0_clk = { 2423 + .halt_reg = 0x4c01c, 2424 + .halt_check = BRANCH_HALT, 2425 + .clkr = { 2426 + .enable_reg = 0x4c01c, 2427 + .enable_mask = BIT(0), 2428 + .hw.init = &(struct clk_init_data) { 2429 + .name = "gcc_venus0_vcodec0_clk", 2430 + .parent_hws = (const struct clk_hw*[]) { 2431 + &vcodec0_clk_src.clkr.hw, 2432 + }, 2433 + .num_parents = 1, 2434 + .ops = &clk_branch2_ops, 2435 + .flags = CLK_SET_RATE_PARENT, 2436 + } 2437 + } 2438 + }; 2439 + 2440 + static struct gdsc mdss_gdsc = { 2441 + .gdscr = 0x4d078, 2442 + .cxcs = (unsigned int []) { 0x4d080, 0x4d088 }, 2443 + .cxc_count = 2, 2444 + .pd = { 2445 + .name = "mdss_gdsc", 2446 + }, 2447 + .pwrsts = PWRSTS_OFF_ON, 2448 + }; 2449 + 2450 + static struct gdsc oxili_gdsc = { 2451 + .gdscr = 0x5901c, 2452 + .cxcs = (unsigned int []) { 0x59020 }, 2453 + .cxc_count = 1, 2454 + .pd = { 2455 + .name = "oxili_gdsc", 2456 + }, 2457 + .pwrsts = PWRSTS_OFF_ON, 2458 + }; 2459 + 2460 + static struct gdsc venus_gdsc = { 2461 + .gdscr = 0x4c018, 2462 + .cxcs = (unsigned int []) { 0x4c024, 0x4c01c }, 2463 + .cxc_count = 2, 2464 + .pd = { 2465 + .name = "venus_gdsc", 2466 + }, 2467 + .pwrsts = PWRSTS_OFF_ON, 2468 + }; 2469 + 2470 + static struct gdsc venus_core0_gdsc = { 2471 + .gdscr = 0x4c028, 2472 + .cxcs = (unsigned int []) { 0x4c02c }, 2473 + .cxc_count = 1, 2474 + .pd = { 2475 + .name = "venus_core0_gdsc", 2476 + }, 2477 + .flags = HW_CTRL, 2478 + .pwrsts = PWRSTS_OFF_ON, 2479 + }; 2480 + 2481 + static struct gdsc vfe_gdsc = { 2482 + .gdscr = 0x58034, 2483 + .cxcs = (unsigned int []) { 0x58038, 0x58048, 0x58050 }, 2484 + .cxc_count = 3, 2485 + .pd = { 2486 + .name = "vfe_gdsc", 2487 + }, 2488 + .pwrsts = PWRSTS_OFF_ON, 2489 + }; 2490 + 2491 + static struct clk_regmap *gcc_msm8909_clocks[] = { 2492 + [GPLL0_EARLY] = &gpll0_early.clkr, 2493 + [GPLL0] = &gpll0.clkr, 2494 + [GPLL1] = &gpll1.clkr, 2495 + [GPLL1_VOTE] = &gpll1_vote, 2496 + [GPLL2_EARLY] = &gpll2_early.clkr, 2497 + [GPLL2] = &gpll2.clkr, 2498 + [BIMC_PLL_EARLY] = &bimc_pll_early.clkr, 2499 + [BIMC_PLL] = &bimc_pll.clkr, 2500 + [APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr, 2501 + [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr, 2502 + [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr, 2503 + [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr, 2504 + [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr, 2505 + [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr, 2506 + [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr, 2507 + [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr, 2508 + [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr, 2509 + [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr, 2510 + [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr, 2511 + [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr, 2512 + [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr, 2513 + [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr, 2514 + [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr, 2515 + [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr, 2516 + [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr, 2517 + [BYTE0_CLK_SRC] = &byte0_clk_src.clkr, 2518 + [CAMSS_GP0_CLK_SRC] = &camss_gp0_clk_src.clkr, 2519 + [CAMSS_GP1_CLK_SRC] = &camss_gp1_clk_src.clkr, 2520 + [CAMSS_TOP_AHB_CLK_SRC] = &camss_top_ahb_clk_src.clkr, 2521 + [CRYPTO_CLK_SRC] = &crypto_clk_src.clkr, 2522 + [CSI0_CLK_SRC] = &csi0_clk_src.clkr, 2523 + [CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr, 2524 + [CSI1_CLK_SRC] = &csi1_clk_src.clkr, 2525 + [ESC0_CLK_SRC] = &esc0_clk_src.clkr, 2526 + [GFX3D_CLK_SRC] = &gfx3d_clk_src.clkr, 2527 + [GP1_CLK_SRC] = &gp1_clk_src.clkr, 2528 + [GP2_CLK_SRC] = &gp2_clk_src.clkr, 2529 + [GP3_CLK_SRC] = &gp3_clk_src.clkr, 2530 + [MCLK0_CLK_SRC] = &mclk0_clk_src.clkr, 2531 + [MCLK1_CLK_SRC] = &mclk1_clk_src.clkr, 2532 + [MDP_CLK_SRC] = &mdp_clk_src.clkr, 2533 + [PCLK0_CLK_SRC] = &pclk0_clk_src.clkr, 2534 + [PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr, 2535 + [PDM2_CLK_SRC] = &pdm2_clk_src.clkr, 2536 + [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr, 2537 + [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr, 2538 + [SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr, 2539 + [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr, 2540 + [VCODEC0_CLK_SRC] = &vcodec0_clk_src.clkr, 2541 + [VFE0_CLK_SRC] = &vfe0_clk_src.clkr, 2542 + [VSYNC_CLK_SRC] = &vsync_clk_src.clkr, 2543 + [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr, 2544 + [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr, 2545 + [GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr, 2546 + [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr, 2547 + [GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr, 2548 + [GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr, 2549 + [GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr, 2550 + [GCC_GFX_TBU_CLK] = &gcc_gfx_tbu_clk.clkr, 2551 + [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr, 2552 + [GCC_GTCU_AHB_CLK] = &gcc_gtcu_ahb_clk.clkr, 2553 + [GCC_MDP_TBU_CLK] = &gcc_mdp_tbu_clk.clkr, 2554 + [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr, 2555 + [GCC_SMMU_CFG_CLK] = &gcc_smmu_cfg_clk.clkr, 2556 + [GCC_VENUS_TBU_CLK] = &gcc_venus_tbu_clk.clkr, 2557 + [GCC_VFE_TBU_CLK] = &gcc_vfe_tbu_clk.clkr, 2558 + [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr, 2559 + [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr, 2560 + [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr, 2561 + [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr, 2562 + [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr, 2563 + [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr, 2564 + [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr, 2565 + [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr, 2566 + [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr, 2567 + [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr, 2568 + [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr, 2569 + [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr, 2570 + [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr, 2571 + [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr, 2572 + [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr, 2573 + [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr, 2574 + [GCC_CAMSS_AHB_CLK] = &gcc_camss_ahb_clk.clkr, 2575 + [GCC_CAMSS_CSI0_CLK] = &gcc_camss_csi0_clk.clkr, 2576 + [GCC_CAMSS_CSI0_AHB_CLK] = &gcc_camss_csi0_ahb_clk.clkr, 2577 + [GCC_CAMSS_CSI0PHY_CLK] = &gcc_camss_csi0phy_clk.clkr, 2578 + [GCC_CAMSS_CSI0PHYTIMER_CLK] = &gcc_camss_csi0phytimer_clk.clkr, 2579 + [GCC_CAMSS_CSI0PIX_CLK] = &gcc_camss_csi0pix_clk.clkr, 2580 + [GCC_CAMSS_CSI0RDI_CLK] = &gcc_camss_csi0rdi_clk.clkr, 2581 + [GCC_CAMSS_CSI1_CLK] = &gcc_camss_csi1_clk.clkr, 2582 + [GCC_CAMSS_CSI1_AHB_CLK] = &gcc_camss_csi1_ahb_clk.clkr, 2583 + [GCC_CAMSS_CSI1PHY_CLK] = &gcc_camss_csi1phy_clk.clkr, 2584 + [GCC_CAMSS_CSI1PIX_CLK] = &gcc_camss_csi1pix_clk.clkr, 2585 + [GCC_CAMSS_CSI1RDI_CLK] = &gcc_camss_csi1rdi_clk.clkr, 2586 + [GCC_CAMSS_CSI_VFE0_CLK] = &gcc_camss_csi_vfe0_clk.clkr, 2587 + [GCC_CAMSS_GP0_CLK] = &gcc_camss_gp0_clk.clkr, 2588 + [GCC_CAMSS_GP1_CLK] = &gcc_camss_gp1_clk.clkr, 2589 + [GCC_CAMSS_ISPIF_AHB_CLK] = &gcc_camss_ispif_ahb_clk.clkr, 2590 + [GCC_CAMSS_MCLK0_CLK] = &gcc_camss_mclk0_clk.clkr, 2591 + [GCC_CAMSS_MCLK1_CLK] = &gcc_camss_mclk1_clk.clkr, 2592 + [GCC_CAMSS_TOP_AHB_CLK] = &gcc_camss_top_ahb_clk.clkr, 2593 + [GCC_CAMSS_VFE0_CLK] = &gcc_camss_vfe0_clk.clkr, 2594 + [GCC_CAMSS_VFE_AHB_CLK] = &gcc_camss_vfe_ahb_clk.clkr, 2595 + [GCC_CAMSS_VFE_AXI_CLK] = &gcc_camss_vfe_axi_clk.clkr, 2596 + [GCC_GP1_CLK] = &gcc_gp1_clk.clkr, 2597 + [GCC_GP2_CLK] = &gcc_gp2_clk.clkr, 2598 + [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, 2599 + [GCC_MDSS_AHB_CLK] = &gcc_mdss_ahb_clk.clkr, 2600 + [GCC_MDSS_AXI_CLK] = &gcc_mdss_axi_clk.clkr, 2601 + [GCC_MDSS_BYTE0_CLK] = &gcc_mdss_byte0_clk.clkr, 2602 + [GCC_MDSS_ESC0_CLK] = &gcc_mdss_esc0_clk.clkr, 2603 + [GCC_MDSS_MDP_CLK] = &gcc_mdss_mdp_clk.clkr, 2604 + [GCC_MDSS_PCLK0_CLK] = &gcc_mdss_pclk0_clk.clkr, 2605 + [GCC_MDSS_VSYNC_CLK] = &gcc_mdss_vsync_clk.clkr, 2606 + [GCC_MSS_CFG_AHB_CLK] = &gcc_mss_cfg_ahb_clk.clkr, 2607 + [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr, 2608 + [GCC_OXILI_AHB_CLK] = &gcc_oxili_ahb_clk.clkr, 2609 + [GCC_OXILI_GFX3D_CLK] = &gcc_oxili_gfx3d_clk.clkr, 2610 + [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr, 2611 + [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr, 2612 + [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr, 2613 + [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr, 2614 + [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr, 2615 + [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr, 2616 + [GCC_USB2A_PHY_SLEEP_CLK] = &gcc_usb2a_phy_sleep_clk.clkr, 2617 + [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr, 2618 + [GCC_USB_HS_PHY_CFG_AHB_CLK] = &gcc_usb_hs_phy_cfg_ahb_clk.clkr, 2619 + [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr, 2620 + [GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr, 2621 + [GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr, 2622 + [GCC_VENUS0_CORE0_VCODEC0_CLK] = &gcc_venus0_core0_vcodec0_clk.clkr, 2623 + [GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr, 2624 + }; 2625 + 2626 + static struct gdsc *gcc_msm8909_gdscs[] = { 2627 + [MDSS_GDSC] = &mdss_gdsc, 2628 + [OXILI_GDSC] = &oxili_gdsc, 2629 + [VENUS_GDSC] = &venus_gdsc, 2630 + [VENUS_CORE0_GDSC] = &venus_core0_gdsc, 2631 + [VFE_GDSC] = &vfe_gdsc, 2632 + }; 2633 + 2634 + static const struct qcom_reset_map gcc_msm8909_resets[] = { 2635 + [GCC_AUDIO_CORE_BCR] = { 0x1c008 }, 2636 + [GCC_BLSP1_BCR] = { 0x01000 }, 2637 + [GCC_BLSP1_QUP1_BCR] = { 0x02000 }, 2638 + [GCC_BLSP1_QUP2_BCR] = { 0x03008 }, 2639 + [GCC_BLSP1_QUP3_BCR] = { 0x04018 }, 2640 + [GCC_BLSP1_QUP4_BCR] = { 0x05018 }, 2641 + [GCC_BLSP1_QUP5_BCR] = { 0x06018 }, 2642 + [GCC_BLSP1_QUP6_BCR] = { 0x07018 }, 2643 + [GCC_BLSP1_UART1_BCR] = { 0x02038 }, 2644 + [GCC_BLSP1_UART2_BCR] = { 0x03028 }, 2645 + [GCC_CAMSS_CSI0_BCR] = { 0x4e038 }, 2646 + [GCC_CAMSS_CSI0PHY_BCR] = { 0x4e044 }, 2647 + [GCC_CAMSS_CSI0PIX_BCR] = { 0x4e054 }, 2648 + [GCC_CAMSS_CSI0RDI_BCR] = { 0x4e04c }, 2649 + [GCC_CAMSS_CSI1_BCR] = { 0x4f038 }, 2650 + [GCC_CAMSS_CSI1PHY_BCR] = { 0x4f044 }, 2651 + [GCC_CAMSS_CSI1PIX_BCR] = { 0x4f054 }, 2652 + [GCC_CAMSS_CSI1RDI_BCR] = { 0x4f04c }, 2653 + [GCC_CAMSS_CSI_VFE0_BCR] = { 0x5804c }, 2654 + [GCC_CAMSS_GP0_BCR] = { 0x54014 }, 2655 + [GCC_CAMSS_GP1_BCR] = { 0x55014 }, 2656 + [GCC_CAMSS_ISPIF_BCR] = { 0x50000 }, 2657 + [GCC_CAMSS_MCLK0_BCR] = { 0x52014 }, 2658 + [GCC_CAMSS_MCLK1_BCR] = { 0x53014 }, 2659 + [GCC_CAMSS_PHY0_BCR] = { 0x4e018 }, 2660 + [GCC_CAMSS_TOP_BCR] = { 0x56000 }, 2661 + [GCC_CAMSS_TOP_AHB_BCR] = { 0x5a018 }, 2662 + [GCC_CAMSS_VFE_BCR] = { 0x58030 }, 2663 + [GCC_CRYPTO_BCR] = { 0x16000 }, 2664 + [GCC_MDSS_BCR] = { 0x4d074 }, 2665 + [GCC_OXILI_BCR] = { 0x59018 }, 2666 + [GCC_PDM_BCR] = { 0x44000 }, 2667 + [GCC_PRNG_BCR] = { 0x13000 }, 2668 + [GCC_QUSB2_PHY_BCR] = { 0x4103c }, 2669 + [GCC_SDCC1_BCR] = { 0x42000 }, 2670 + [GCC_SDCC2_BCR] = { 0x43000 }, 2671 + [GCC_ULT_AUDIO_BCR] = { 0x1c0b4 }, 2672 + [GCC_USB2A_PHY_BCR] = { 0x41028 }, 2673 + [GCC_USB2_HS_PHY_ONLY_BCR] = { 0x41034 }, 2674 + [GCC_USB_HS_BCR] = { 0x41000 }, 2675 + [GCC_VENUS0_BCR] = { 0x4c014 }, 2676 + /* Subsystem Restart */ 2677 + [GCC_MSS_RESTART] = { 0x3e000 }, 2678 + }; 2679 + 2680 + static const struct regmap_config gcc_msm8909_regmap_config = { 2681 + .reg_bits = 32, 2682 + .reg_stride = 4, 2683 + .val_bits = 32, 2684 + .max_register = 0x80000, 2685 + .fast_io = true, 2686 + }; 2687 + 2688 + static const struct qcom_cc_desc gcc_msm8909_desc = { 2689 + .config = &gcc_msm8909_regmap_config, 2690 + .clks = gcc_msm8909_clocks, 2691 + .num_clks = ARRAY_SIZE(gcc_msm8909_clocks), 2692 + .resets = gcc_msm8909_resets, 2693 + .num_resets = ARRAY_SIZE(gcc_msm8909_resets), 2694 + .gdscs = gcc_msm8909_gdscs, 2695 + .num_gdscs = ARRAY_SIZE(gcc_msm8909_gdscs), 2696 + }; 2697 + 2698 + static const struct of_device_id gcc_msm8909_match_table[] = { 2699 + { .compatible = "qcom,gcc-msm8909" }, 2700 + { } 2701 + }; 2702 + MODULE_DEVICE_TABLE(of, gcc_msm8909_match_table); 2703 + 2704 + static int gcc_msm8909_probe(struct platform_device *pdev) 2705 + { 2706 + return qcom_cc_probe(pdev, &gcc_msm8909_desc); 2707 + } 2708 + 2709 + static struct platform_driver gcc_msm8909_driver = { 2710 + .probe = gcc_msm8909_probe, 2711 + .driver = { 2712 + .name = "gcc-msm8909", 2713 + .of_match_table = gcc_msm8909_match_table, 2714 + }, 2715 + }; 2716 + 2717 + static int __init gcc_msm8909_init(void) 2718 + { 2719 + return platform_driver_register(&gcc_msm8909_driver); 2720 + } 2721 + core_initcall(gcc_msm8909_init); 2722 + 2723 + static void __exit gcc_msm8909_exit(void) 2724 + { 2725 + platform_driver_unregister(&gcc_msm8909_driver); 2726 + } 2727 + module_exit(gcc_msm8909_exit); 2728 + 2729 + MODULE_DESCRIPTION("Qualcomm GCC MSM8909 Driver"); 2730 + MODULE_LICENSE("GPL"); 2731 + MODULE_ALIAS("platform:gcc-msm8909");

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