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dt-bindings: clock: Add schema for MSM8909 GCC

The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks,
resets and power domains for the various hardware blocks in the SoC.
Add a DT schema to describe it, similar to other Qualcomm SoCs.

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20220706134132.3623415-2-stephan.gerhold@kernkonzept.com

authored by

Stephan Gerhold and committed by
Bjorn Andersson c4066804 c3ddc184

+276
+58
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm Global Clock & Reset Controller Binding for MSM8909 8 + 9 + maintainers: 10 + - Stephan Gerhold <stephan@gerhold.net> 11 + 12 + description: | 13 + Qualcomm global clock control module which supports the clocks, resets and 14 + power domains on MSM8909. 15 + 16 + See also: 17 + - dt-bindings/clock/qcom,gcc-msm8909.h 18 + 19 + properties: 20 + compatible: 21 + const: qcom,gcc-msm8909 22 + 23 + clocks: 24 + items: 25 + - description: XO source 26 + - description: Sleep clock source 27 + - description: DSI phy instance 0 dsi clock 28 + - description: DSI phy instance 0 byte clock 29 + 30 + clock-names: 31 + items: 32 + - const: xo 33 + - const: sleep_clk 34 + - const: dsi0pll 35 + - const: dsi0pllbyte 36 + 37 + required: 38 + - compatible 39 + - clocks 40 + - clock-names 41 + 42 + allOf: 43 + - $ref: qcom,gcc.yaml# 44 + 45 + unevaluatedProperties: false 46 + 47 + examples: 48 + - | 49 + gcc: clock-controller@1800000 { 50 + compatible = "qcom,gcc-msm8909"; 51 + reg = <0x01800000 0x80000>; 52 + #clock-cells = <1>; 53 + #reset-cells = <1>; 54 + #power-domain-cells = <1>; 55 + clocks = <&xo_board>, <&sleep_clk>, <&dsi0_phy 1>, <&dsi0_phy 0>; 56 + clock-names = "xo", "sleep_clk", "dsi0pll", "dsi0pllbyte"; 57 + }; 58 + ...
+218
include/dt-bindings/clock/qcom,gcc-msm8909.h
··· 1 + /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 + /* 3 + * Copyright (C) 2022 Kernkonzept GmbH. 4 + */ 5 + 6 + #ifndef _DT_BINDINGS_CLK_QCOM_GCC_8909_H 7 + #define _DT_BINDINGS_CLK_QCOM_GCC_8909_H 8 + 9 + /* PLLs */ 10 + #define GPLL0_EARLY 0 11 + #define GPLL0 1 12 + #define GPLL1 2 13 + #define GPLL1_VOTE 3 14 + #define GPLL2_EARLY 4 15 + #define GPLL2 5 16 + #define BIMC_PLL_EARLY 6 17 + #define BIMC_PLL 7 18 + 19 + /* RCGs */ 20 + #define APSS_AHB_CLK_SRC 8 21 + #define BIMC_DDR_CLK_SRC 9 22 + #define BIMC_GPU_CLK_SRC 10 23 + #define BLSP1_QUP1_I2C_APPS_CLK_SRC 11 24 + #define BLSP1_QUP1_SPI_APPS_CLK_SRC 12 25 + #define BLSP1_QUP2_I2C_APPS_CLK_SRC 13 26 + #define BLSP1_QUP2_SPI_APPS_CLK_SRC 14 27 + #define BLSP1_QUP3_I2C_APPS_CLK_SRC 15 28 + #define BLSP1_QUP3_SPI_APPS_CLK_SRC 16 29 + #define BLSP1_QUP4_I2C_APPS_CLK_SRC 17 30 + #define BLSP1_QUP4_SPI_APPS_CLK_SRC 18 31 + #define BLSP1_QUP5_I2C_APPS_CLK_SRC 19 32 + #define BLSP1_QUP5_SPI_APPS_CLK_SRC 20 33 + #define BLSP1_QUP6_I2C_APPS_CLK_SRC 21 34 + #define BLSP1_QUP6_SPI_APPS_CLK_SRC 22 35 + #define BLSP1_UART1_APPS_CLK_SRC 23 36 + #define BLSP1_UART2_APPS_CLK_SRC 24 37 + #define BYTE0_CLK_SRC 25 38 + #define CAMSS_GP0_CLK_SRC 26 39 + #define CAMSS_GP1_CLK_SRC 27 40 + #define CAMSS_TOP_AHB_CLK_SRC 28 41 + #define CODEC_DIGCODEC_CLK_SRC 29 42 + #define CRYPTO_CLK_SRC 30 43 + #define CSI0_CLK_SRC 31 44 + #define CSI0PHYTIMER_CLK_SRC 32 45 + #define CSI1_CLK_SRC 33 46 + #define ESC0_CLK_SRC 34 47 + #define GFX3D_CLK_SRC 35 48 + #define GP1_CLK_SRC 36 49 + #define GP2_CLK_SRC 37 50 + #define GP3_CLK_SRC 38 51 + #define MCLK0_CLK_SRC 39 52 + #define MCLK1_CLK_SRC 40 53 + #define MDP_CLK_SRC 41 54 + #define PCLK0_CLK_SRC 42 55 + #define PCNOC_BFDCD_CLK_SRC 43 56 + #define PDM2_CLK_SRC 44 57 + #define SDCC1_APPS_CLK_SRC 45 58 + #define SDCC2_APPS_CLK_SRC 46 59 + #define SYSTEM_NOC_BFDCD_CLK_SRC 47 60 + #define ULTAUDIO_AHBFABRIC_CLK_SRC 48 61 + #define ULTAUDIO_LPAIF_AUX_I2S_CLK_SRC 49 62 + #define ULTAUDIO_LPAIF_PRI_I2S_CLK_SRC 50 63 + #define ULTAUDIO_LPAIF_SEC_I2S_CLK_SRC 51 64 + #define ULTAUDIO_XO_CLK_SRC 52 65 + #define USB_HS_SYSTEM_CLK_SRC 53 66 + #define VCODEC0_CLK_SRC 54 67 + #define VFE0_CLK_SRC 55 68 + #define VSYNC_CLK_SRC 56 69 + 70 + /* Voteable Clocks */ 71 + #define GCC_APSS_TCU_CLK 57 72 + #define GCC_BLSP1_AHB_CLK 58 73 + #define GCC_BLSP1_SLEEP_CLK 59 74 + #define GCC_BOOT_ROM_AHB_CLK 60 75 + #define GCC_CRYPTO_CLK 61 76 + #define GCC_CRYPTO_AHB_CLK 62 77 + #define GCC_CRYPTO_AXI_CLK 63 78 + #define GCC_GFX_TBU_CLK 64 79 + #define GCC_GFX_TCU_CLK 65 80 + #define GCC_GTCU_AHB_CLK 66 81 + #define GCC_MDP_TBU_CLK 67 82 + #define GCC_PRNG_AHB_CLK 68 83 + #define GCC_SMMU_CFG_CLK 69 84 + #define GCC_VENUS_TBU_CLK 70 85 + #define GCC_VFE_TBU_CLK 71 86 + 87 + /* Branches */ 88 + #define GCC_BIMC_GFX_CLK 72 89 + #define GCC_BIMC_GPU_CLK 73 90 + #define GCC_BLSP1_QUP1_I2C_APPS_CLK 74 91 + #define GCC_BLSP1_QUP1_SPI_APPS_CLK 75 92 + #define GCC_BLSP1_QUP2_I2C_APPS_CLK 76 93 + #define GCC_BLSP1_QUP2_SPI_APPS_CLK 77 94 + #define GCC_BLSP1_QUP3_I2C_APPS_CLK 78 95 + #define GCC_BLSP1_QUP3_SPI_APPS_CLK 79 96 + #define GCC_BLSP1_QUP4_I2C_APPS_CLK 80 97 + #define GCC_BLSP1_QUP4_SPI_APPS_CLK 81 98 + #define GCC_BLSP1_QUP5_I2C_APPS_CLK 82 99 + #define GCC_BLSP1_QUP5_SPI_APPS_CLK 83 100 + #define GCC_BLSP1_QUP6_I2C_APPS_CLK 84 101 + #define GCC_BLSP1_QUP6_SPI_APPS_CLK 85 102 + #define GCC_BLSP1_UART1_APPS_CLK 86 103 + #define GCC_BLSP1_UART2_APPS_CLK 87 104 + #define GCC_CAMSS_AHB_CLK 88 105 + #define GCC_CAMSS_CSI0_CLK 89 106 + #define GCC_CAMSS_CSI0_AHB_CLK 90 107 + #define GCC_CAMSS_CSI0PHY_CLK 91 108 + #define GCC_CAMSS_CSI0PHYTIMER_CLK 92 109 + #define GCC_CAMSS_CSI0PIX_CLK 93 110 + #define GCC_CAMSS_CSI0RDI_CLK 94 111 + #define GCC_CAMSS_CSI1_CLK 95 112 + #define GCC_CAMSS_CSI1_AHB_CLK 96 113 + #define GCC_CAMSS_CSI1PHY_CLK 97 114 + #define GCC_CAMSS_CSI1PIX_CLK 98 115 + #define GCC_CAMSS_CSI1RDI_CLK 99 116 + #define GCC_CAMSS_CSI_VFE0_CLK 100 117 + #define GCC_CAMSS_GP0_CLK 101 118 + #define GCC_CAMSS_GP1_CLK 102 119 + #define GCC_CAMSS_ISPIF_AHB_CLK 103 120 + #define GCC_CAMSS_MCLK0_CLK 104 121 + #define GCC_CAMSS_MCLK1_CLK 105 122 + #define GCC_CAMSS_TOP_AHB_CLK 106 123 + #define GCC_CAMSS_VFE0_CLK 107 124 + #define GCC_CAMSS_VFE_AHB_CLK 108 125 + #define GCC_CAMSS_VFE_AXI_CLK 109 126 + #define GCC_CODEC_DIGCODEC_CLK 110 127 + #define GCC_GP1_CLK 111 128 + #define GCC_GP2_CLK 112 129 + #define GCC_GP3_CLK 113 130 + #define GCC_MDSS_AHB_CLK 114 131 + #define GCC_MDSS_AXI_CLK 115 132 + #define GCC_MDSS_BYTE0_CLK 116 133 + #define GCC_MDSS_ESC0_CLK 117 134 + #define GCC_MDSS_MDP_CLK 118 135 + #define GCC_MDSS_PCLK0_CLK 119 136 + #define GCC_MDSS_VSYNC_CLK 120 137 + #define GCC_MSS_CFG_AHB_CLK 121 138 + #define GCC_MSS_Q6_BIMC_AXI_CLK 122 139 + #define GCC_OXILI_AHB_CLK 123 140 + #define GCC_OXILI_GFX3D_CLK 124 141 + #define GCC_PDM2_CLK 125 142 + #define GCC_PDM_AHB_CLK 126 143 + #define GCC_SDCC1_AHB_CLK 127 144 + #define GCC_SDCC1_APPS_CLK 128 145 + #define GCC_SDCC2_AHB_CLK 129 146 + #define GCC_SDCC2_APPS_CLK 130 147 + #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK 131 148 + #define GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_LPM_CLK 132 149 + #define GCC_ULTAUDIO_AVSYNC_XO_CLK 133 150 + #define GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK 134 151 + #define GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK 135 152 + #define GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK 136 153 + #define GCC_ULTAUDIO_PCNOC_MPORT_CLK 137 154 + #define GCC_ULTAUDIO_PCNOC_SWAY_CLK 138 155 + #define GCC_ULTAUDIO_STC_XO_CLK 139 156 + #define GCC_USB2A_PHY_SLEEP_CLK 140 157 + #define GCC_USB_HS_AHB_CLK 141 158 + #define GCC_USB_HS_PHY_CFG_AHB_CLK 142 159 + #define GCC_USB_HS_SYSTEM_CLK 143 160 + #define GCC_VENUS0_AHB_CLK 144 161 + #define GCC_VENUS0_AXI_CLK 145 162 + #define GCC_VENUS0_CORE0_VCODEC0_CLK 146 163 + #define GCC_VENUS0_VCODEC0_CLK 147 164 + 165 + /* Resets */ 166 + #define GCC_AUDIO_CORE_BCR 0 167 + #define GCC_BLSP1_BCR 1 168 + #define GCC_BLSP1_QUP1_BCR 2 169 + #define GCC_BLSP1_QUP2_BCR 3 170 + #define GCC_BLSP1_QUP3_BCR 4 171 + #define GCC_BLSP1_QUP4_BCR 5 172 + #define GCC_BLSP1_QUP5_BCR 6 173 + #define GCC_BLSP1_QUP6_BCR 7 174 + #define GCC_BLSP1_UART1_BCR 8 175 + #define GCC_BLSP1_UART2_BCR 9 176 + #define GCC_CAMSS_CSI0_BCR 10 177 + #define GCC_CAMSS_CSI0PHY_BCR 11 178 + #define GCC_CAMSS_CSI0PIX_BCR 12 179 + #define GCC_CAMSS_CSI0RDI_BCR 13 180 + #define GCC_CAMSS_CSI1_BCR 14 181 + #define GCC_CAMSS_CSI1PHY_BCR 15 182 + #define GCC_CAMSS_CSI1PIX_BCR 16 183 + #define GCC_CAMSS_CSI1RDI_BCR 17 184 + #define GCC_CAMSS_CSI_VFE0_BCR 18 185 + #define GCC_CAMSS_GP0_BCR 19 186 + #define GCC_CAMSS_GP1_BCR 20 187 + #define GCC_CAMSS_ISPIF_BCR 21 188 + #define GCC_CAMSS_MCLK0_BCR 22 189 + #define GCC_CAMSS_MCLK1_BCR 23 190 + #define GCC_CAMSS_PHY0_BCR 24 191 + #define GCC_CAMSS_TOP_BCR 25 192 + #define GCC_CAMSS_TOP_AHB_BCR 26 193 + #define GCC_CAMSS_VFE_BCR 27 194 + #define GCC_CRYPTO_BCR 28 195 + #define GCC_MDSS_BCR 29 196 + #define GCC_OXILI_BCR 30 197 + #define GCC_PDM_BCR 31 198 + #define GCC_PRNG_BCR 32 199 + #define GCC_QUSB2_PHY_BCR 33 200 + #define GCC_SDCC1_BCR 34 201 + #define GCC_SDCC2_BCR 35 202 + #define GCC_ULT_AUDIO_BCR 36 203 + #define GCC_USB2A_PHY_BCR 37 204 + #define GCC_USB2_HS_PHY_ONLY_BCR 38 205 + #define GCC_USB_HS_BCR 39 206 + #define GCC_VENUS0_BCR 40 207 + 208 + /* Subsystem Restart */ 209 + #define GCC_MSS_RESTART 41 210 + 211 + /* Power Domains */ 212 + #define MDSS_GDSC 0 213 + #define OXILI_GDSC 1 214 + #define VENUS_GDSC 2 215 + #define VENUS_CORE0_GDSC 3 216 + #define VFE_GDSC 4 217 + 218 + #endif