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clk: qcom: gcc-sc7180: get rid of test clock

The test clock apparently it's not used by anyone upstream. Remove it.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228185237.3111988-11-dmitry.baryshkov@linaro.org

authored by

Dmitry Baryshkov and committed by
Bjorn Andersson
bfa78833 32bde50f

-16
-16
drivers/clk/qcom/gcc-sc7180.c
··· 23 23 24 24 enum { 25 25 P_BI_TCXO, 26 - P_CORE_BI_PLL_TEST_SE, 27 26 P_GPLL0_OUT_EVEN, 28 27 P_GPLL0_OUT_MAIN, 29 28 P_GPLL1_OUT_MAIN, ··· 161 162 { P_BI_TCXO, 0 }, 162 163 { P_GPLL0_OUT_MAIN, 1 }, 163 164 { P_GPLL0_OUT_EVEN, 6 }, 164 - { P_CORE_BI_PLL_TEST_SE, 7 }, 165 165 }; 166 166 167 167 static const struct clk_parent_data gcc_parent_data_0[] = { 168 168 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 169 169 { .hw = &gpll0.clkr.hw }, 170 170 { .hw = &gpll0_out_even.clkr.hw }, 171 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 172 171 }; 173 172 174 173 static const struct clk_parent_data gcc_parent_data_0_ao[] = { 175 174 { .fw_name = "bi_tcxo_ao", .name = "bi_tcxo_ao" }, 176 175 { .hw = &gpll0.clkr.hw }, 177 176 { .hw = &gpll0_out_even.clkr.hw }, 178 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 179 177 }; 180 178 181 179 static const struct parent_map gcc_parent_map_1[] = { ··· 180 184 { P_GPLL0_OUT_MAIN, 1 }, 181 185 { P_GPLL6_OUT_MAIN, 2 }, 182 186 { P_GPLL0_OUT_EVEN, 6 }, 183 - { P_CORE_BI_PLL_TEST_SE, 7 }, 184 187 }; 185 188 186 189 static const struct clk_parent_data gcc_parent_data_1[] = { ··· 187 192 { .hw = &gpll0.clkr.hw }, 188 193 { .hw = &gpll6.clkr.hw }, 189 194 { .hw = &gpll0_out_even.clkr.hw }, 190 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 191 195 }; 192 196 193 197 static const struct parent_map gcc_parent_map_2[] = { ··· 195 201 { P_GPLL1_OUT_MAIN, 4 }, 196 202 { P_GPLL4_OUT_MAIN, 5 }, 197 203 { P_GPLL0_OUT_EVEN, 6 }, 198 - { P_CORE_BI_PLL_TEST_SE, 7 }, 199 204 }; 200 205 201 206 static const struct clk_parent_data gcc_parent_data_2[] = { ··· 203 210 { .hw = &gpll1.clkr.hw }, 204 211 { .hw = &gpll4.clkr.hw }, 205 212 { .hw = &gpll0_out_even.clkr.hw }, 206 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 207 213 }; 208 214 209 215 static const struct parent_map gcc_parent_map_3[] = { 210 216 { P_BI_TCXO, 0 }, 211 217 { P_GPLL0_OUT_MAIN, 1 }, 212 - { P_CORE_BI_PLL_TEST_SE, 7 }, 213 218 }; 214 219 215 220 static const struct clk_parent_data gcc_parent_data_3[] = { 216 221 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 217 222 { .hw = &gpll0.clkr.hw }, 218 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 219 223 }; 220 224 221 225 static const struct parent_map gcc_parent_map_4[] = { ··· 220 230 { P_GPLL0_OUT_MAIN, 1 }, 221 231 { P_SLEEP_CLK, 5 }, 222 232 { P_GPLL0_OUT_EVEN, 6 }, 223 - { P_CORE_BI_PLL_TEST_SE, 7 }, 224 233 }; 225 234 226 235 static const struct clk_parent_data gcc_parent_data_4[] = { ··· 227 238 { .hw = &gpll0.clkr.hw }, 228 239 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 229 240 { .hw = &gpll0_out_even.clkr.hw }, 230 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 231 241 }; 232 242 233 243 static const struct parent_map gcc_parent_map_5[] = { ··· 234 246 { P_GPLL0_OUT_MAIN, 1 }, 235 247 { P_GPLL7_OUT_MAIN, 3 }, 236 248 { P_GPLL0_OUT_EVEN, 6 }, 237 - { P_CORE_BI_PLL_TEST_SE, 7 }, 238 249 }; 239 250 240 251 static const struct clk_parent_data gcc_parent_data_5[] = { ··· 241 254 { .hw = &gpll0.clkr.hw }, 242 255 { .hw = &gpll7.clkr.hw }, 243 256 { .hw = &gpll0_out_even.clkr.hw }, 244 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 245 257 }; 246 258 247 259 static const struct parent_map gcc_parent_map_6[] = { 248 260 { P_BI_TCXO, 0 }, 249 261 { P_GPLL0_OUT_MAIN, 1 }, 250 262 { P_SLEEP_CLK, 5 }, 251 - { P_CORE_BI_PLL_TEST_SE, 7 }, 252 263 }; 253 264 254 265 static const struct clk_parent_data gcc_parent_data_6[] = { 255 266 { .fw_name = "bi_tcxo", .name = "bi_tcxo" }, 256 267 { .hw = &gpll0.clkr.hw }, 257 268 { .fw_name = "sleep_clk", .name = "sleep_clk" }, 258 - { .fw_name = "core_bi_pll_test_se", .name = "core_bi_pll_test_se" }, 259 269 }; 260 270 261 271 static const struct freq_tbl ftbl_gcc_cpuss_ahb_clk_src[] = {